Graphics processor cache for data from multiple memory spaces

A unified data cache with a tiered banking configuration addresses the challenge of managing data from multiple memory spaces in graphics processors, achieving efficient parallel access and improved cache management.

WO2025048990A1PCT designated stage expired Publication Date: 2025-03-06APPLE INC
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Patent Information

Application Number
PCT/US2024/038696
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-02-21
Filing Date
2024-07-19
Publication Date
2025-03-06

AI Technical Summary

Technical Problem

Existing graphics processors face challenges in efficiently managing data from multiple memory spaces, leading to complex memory access requests and data networks.

Method used

A unified data cache with tiered multiple banking configuration, including multiple tag banks, scheduler banks, data banks, and data subbanks, is implemented to cache data from various memory spaces, allowing for parallel tag checks, invalidations, and occupancy management.

Benefits of technology

This solution simplifies and consolidates memory access request and data networks, enabling efficient parallel access to multiple memory spaces, improved cache occupancy management, and increased throughput.

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Abstract

In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.
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Citation Information

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