Vertical silicon carbide metal oxide semiconductor gate junction field effect transistors

Abstract

Vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs) are presented herein. An epitaxial region (104) is grown on a substrate layer to form a vertical structure. A vertical JFET is formed within the vertical structure and includes a source region (108) at a device surface, a deep gate (106) formed below the surface, and a drain (102) formed by a substrate layer. A MOS gate (123) is formed above a sub-surface channel implant region to improve pinch-off behavior and specific on-resistance. Pinch-off voltage is determined, at least in part, by a gate dielectric thickness, a dimension of the JFET neck, and a doping concentration of the sub-surface channel implant region.

Description

VERTICAL SILICON CARBIDE METAL OXIDE SEMICONDUCTOR GATE JUNCTIONFIELD EFFECT TRANSISTORSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application 63 / 579,972, filed on September 1, 2023, herein incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates generally to semiconductor devices, and more specifically to vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs).BACKGROUND INFORMATION

[0003] Silicon carbide (SiC) was first discovered in 1891 by Edward Acheson as he attempted to find a way to produce artificial diamonds, by heating clay (aluminium silicate) and carbon. He referred to the shiny hexagonal crystals as carborundum. Since that time SiC has evolved into a superior material for fabricating semiconductor devices.

[0004] Compared to Silicon (Si), Silicon carbide (SiC) has a higher bandgap and avails superior breakdown strength, thermal conductivity, and maximum current density. Silicon carbide can take on many crystalline forms, one of which, 4H-SiC (a hexagonal crystal structure) is often the polytype of choice for high power devices; and silicon carbide may be doped n-type or p-type. Some n-type dopants include nitrogen and phosphorus; and some p-type dopants include beryllium, boron, aluminum, or gallium.

[0005] A junction field effect transistor (JFET) is a gate controlled device whereby electric current is controlled by means of a semiconducting channel between a source and a drain. A JFET usually operates in the on-state (conducts current) when there is no voltage between its gate and source. By applying a reverse bias voltage to a gate terminal, the channel becomes "pinched", whereby electric current is impeded or switched off completely.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs) are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] FIG. 1 illustrates a cell device cross section for an active region of a vertical SiC MOS gate JFET according to an embodiment.

[0008] FIG. 2 illustrates a cell device cross section for an active region of a vertical SiC MOS gate JFET according to an embodiment.

[0009] FIG. 3A illustrates a cell device cross section and carrier concentration scale corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0010] FIG. 3B illustrates a cell device cross section and carrier concentration scale corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0011] FIG. 3C illustrates a cell device cross section and carrier concentration scale corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0012] FIG. 4 illustrates source potential as a function of drain potential corresponding to embodiments of vertical SiC MOS gate JFETs.

[0013] FIG. 5A illustrates a cell device cross section and carrier concentration scale corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0014] FIG. 5B illustrates a cell device cross section corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0015] FIG. 5C illustrates a cell device cross section corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0016] FIG. 5D illustrates a cell device cross section corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment.

[0017] FIG. 6 illustrates electric field and potential as a function of position corresponding with embodiments of vertical SiC MOS gate JFETs.

[0018] FIG. 7A illustrates stripe layouts corresponding with vertical SiC MOS gate JFETs.

[0019] FIG. 7B illustrates stripe layouts corresponding with vertical SiC MOS gate JFETs according to an embodiment.

[0020] FIG. 7C illustrates closed-cell layouts corresponding with vertical SiC MOS gate JFETs according to an embodiment.

[0021] FIG. 8 illustrates a cell device cross section for a termination region of a vertical SiC MOS gate JFET according to an embodiment.

[0022] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements inthe figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements and layers in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the teachings herein. Also, common but well-understood elements, layers, and / or process steps that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs). DETAILED DESCRIPTION

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of vertical SiC MOS gate JFETs. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0024] Reference throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" means that a particular feature, structure, method, process, and / or characteristic described in connection with the embodiment or example is included in at least one embodiment of vertical SiC MOS gate JFETs. Thus, appearances of the phrases "in one embodiment", "in an embodiment", "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, methods, processes and / or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0025] In the context of the present application, SiC may refer to various polytypes of SiC including, but not limited to, 4H-SiC. Also, terms commonly used in the field of semiconductors and semiconductor device fabrication may be relied upon to describe features of vertical SiC MOS gate JFETs. For instance, the terms “shallow” and “deep” may refer to depth of a junction and / or an implanted dopant region; and support for the definition of “shallow” and “deep” is conveyed by the drawings showing (cell) device cross sections for embodiments of vertical SiC MOS gate JFETs.

[0026] Further, when a transistor is in an “off-state” or “off’ the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an “on-state” or “on” the transistor is able to substantially conduct current. Also, for purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential againstwhich all other voltages or potentials of an electronic circuit, device, or Integrated circuit (IC) are defined or measured.

[0027] Throughout the specification there may be reference to semiconductor device and / or process simulations using technology computer aided design (TCAD). “TCAD simulations” or “TCAD device simulations” or “Synopsys Sentaurus TCAD device and process simulations” refers to simulations using SYNOPSYS® tools. (SYNOPSYS® is a trademark of Synopsys, Inc., 690 East Middlefield Road, Mountain View, CA 94043)

[0028] As described above, SiC may be used as a semiconductor device material for fabricating semiconductor devices. The crystalline structure of SiC can be 4H-SiC polytype; however, other types may be possible (e.g., a 6H-SiC polytype). These polytypes of SiC have opened areas of research in the high power device arena; and there is an ongoing need to develop new SiC junction field effect transistors suitable for high voltage operation.

[0029] Vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistors (JFETs) are presented herein. An epitaxial region is grown on a substrate layer to form a vertical structure. A vertical JFET is formed within the vertical structure and includes a source region at a device surface, a deep gate formed below the surface, and a drain formed by a substrate layer. A MOS gate is formed above a sub-surface channel implant region to improve pinch-off behavior and specific on-resistance. Pinch-off voltage is determined, at least in part, by a gate dielectric thickness, a dimension of the JFET neck, and a doping concentration of the sub-surface channel implant region.

[0030] FIG. 1 illustrates a cell device cross section 150 for an active region of a vertical SiC MOS gate JFET according to an embodiment. In the following description, the cell device cross section 150 may also be referred to as an active cell 150. The cell device cross section 150 includes a substrate layer 102, an epitaxial (Epi) layer 104, a deep gate 106, an oxide 110 (i.e., an oxide layer 110), a metal (Ml) pattern 112, a source region 108, a thin film gate 123, and a gate shield region 131. In forming a vertical SiC MOS gate JFET, the substrate layer 102, the epitaxial layer 104, and the source region 108 may be of the same doping type, opposite to that of the deep gate 106 and gate shield region 131.

[0031] Also, as illustrated, a MOS gate of gate dielectric thickness tox may be formed by the thin film gate 123 and oxide 110. As illustrated the thin film gate 123 extends laterally by a gate lateral distance LX and may be comprised of either polysilicon or metal aluminum.

[0032] Additionally, although the MOS gate is illustrated as being isolated from SiC by oxide 110, other dielectrics are possible. For instance, instead of oxide 110, other dielectrics include, but are not limited to nitride and / or oxynitride.

[0033] FIG. 2 illustrates a cell device cross section 150 for an active region of a vertical SiC MOS gate JFET according to an embodiment of FIG. 1. For ease of presentation and simulation purposes, some elements, including the substrate layer 102, are not illustrated. The epitaxial layer 104 is a SiC n-type (N) epitaxial layer 104. The source region 108 is heavily doped n-type (N+); and the oxide 110 comprises silicon dioxide (SiO2) which may be formed by a thermal and / or chemical vapor deposition (CVD) process step. In other embodiments alternative materials may be included and / or substituted for those described herein. For instance, the oxide 110 may comprise aluminum oxide (A12O3).

[0034] As illustrated, the deep gate 106 is p-type and may extend to the surface of the epitaxial layer 104 by virtue of a deep well 243. As one of ordinary skill in the art may appreciate, a deep gate 106 may be formed by one or more process steps including, but not limited to, ion implantation, deep well implantation and / or diffusion, and ohmic contact formation.

[0035] The cell device cross section 150 further includes a sub-surface channel region 242, which may be an implant region below the device surface. As illustrated, the sub-surface channel region 242 may be implanted below the device surface and above the deep gate 106. In the embodiment of FIG. 2, the deep gate 106 and gate shield region 131 may be p-type and the sub-surface channel region 242 may be n-type. Also, as illustrated, the deep gate 106 forms a JFET neck of length LCH1 below the gate shield region 131; and the sub-surface channel region 242 may be in diffusive contact with the source region 108.

[0036] Additionally, the thin film gate 123 may be poly silicon, and as illustrated, may be electrically connected (z.e., coupled) to the gate shield region 131.

[0037] According to semiconductor device physics, JFET behavior, including pinch-off, may be determined, in part, by the JFET neck length LCH1.

[0038] According to the teachings herein, JFET operation and pinch-off may be further determined by the presence of the thin film gate 123, the gate shield region 131, and the subsurface channel region 242. For instance, the thin film gate 123 and gate shield region 131 may enhance depletion and electric field strength. This may, in turn, reduce drain-induced barrier lowering and / or reduce drain current sensitivity as a function of applied drain voltage. Additionally, the sub-surface channel region 242 may improve (z.e., reduce) channel resistance thereby reducing specific on-resistance.

[0039] Also, according to the physics of junction field effect transistors and the teachings herein, during an on-state, current may flow from source region 108 to the substrate 102 whereby the substrate 102 may function as a drain on the device bottom. During pinch off,carriers (e.g., electrons) may be depleted due to an applied voltage at the thin film gate 123 and by P / N junctions formed between deep P-gate(s) 106 and epitaxial layer 104.

[0040] FIGs. 3A-3C illustrate cell device cross sections 350a-c corresponding with Synopsys Sentaurus TCAD device simulations of a vertical SiC MOS gate JFET. The cell device cross sections 350a-c are similar except the gate dielectric thickness tox are varied. In FIG. 3 A the gate dielectric thickness is five hundred angstroms (500A). In FIG. 3B the gate dielectric thickness is eight hundred angstroms (800A); and in FIG. 3C the gate dielectric thickness one-thousand two-hundred angstroms (1200A).

[0041] FIG. 4 illustrates waveforms 401-403 of source potential as a function of drain potential corresponding with the cell device cross sections 350a-c, respectively. Waveform 401 corresponds with cell device cross section 350a. Waveform 402 corresponds with cell device cross section 350b; and waveform 403 corresponds with cell device cross section 350c.

[0042] FIG. 5A illustrates a cell device cross section 550a and carrier concentration scale corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment. Also as illustrated, a simulation cut line 510 is selected below the device surface. The cut line 510 extends through the gate shield region 131 and source region 108.

[0043] FIG. 5B illustrates a cell device cross section 550b corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment. The cell device cross section 550b illustrates electric field profile when the gate dielectric thickness tox equals five hundred angstroms (500A).

[0044] FIG. 5C illustrates a cell device cross section 550c corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment. The cell device cross section 550c illustrates electric field profile when the gate dielectric thickness tox equals eight hundred angstroms (800A).

[0045] FIG. 5D illustrates a cell device cross section 550d corresponding with a Synopsys Sentaurus TCAD device simulation of a vertical SiC MOS gate JFET according to an embodiment. The cell device cross section 550d illustrates electric field profile when the gate dielectric thickness tox equals eight hundred angstroms (1200A).

[0046] FIG. 6 illustrates waveforms 611-613 of electric field and waveforms 601-603 of potential as a function of position corresponding with the cell device cross sections 550b-d, respectively. Waveform 601 illustrates potential along cut line 510 when the gate dielectric thickness is 500A. Waveform 602 illustrates potential along the cut line 510 when the gate dielectric thickness is 800A; and waveform 603 illustrates potential along cut line 510 when the gate dielectric thickness is 1200A. Waveform 611 illustrates electric field along cut line 510when the gate dielectric thickness is 500A. Waveform 612 illustrates electric field along the cut line 510 when the gate dielectric thickness is 800A; and waveform 613 illustrates electric field along cut line 510 when the gate dielectric thickness is 1200A.

[0047] FIG. 7A illustrates stripe layouts 700, 701 corresponding with vertical SiC MOS gate JFETs. The stripe layouts 700, 701 may include patterns of thin film gate 123 (e.g., polysilicon) and the heavily doped regions (e.g., gate shield region 131 and source region 108). Additionally, stripe patterns 71 la-b may correspond with a stripe gate-shield of mask dimension LD11; and stripe patterns 712a-b may correspond with an island gate-shield of mask dimension LD12. According to the practice of microelectronics, the gate lateral distance LX, as discussed above with regards to FIG. 1, may be determined, at least in part, by the mask dimensions LD11, LD12.

[0048] FIG. 7B illustrates stripe layouts 702, 703 corresponding with vertical SiC MOS gate JFETs. The stripe layouts 702, 703 may include patterns of thin film gate 123 (e.g., polysilicon) and the heavily doped regions (e.g., gate shield region 131 and source region 108). Additionally, stripe patterns 713a-b may correspond with an island gate-shield of mask dimension LD13; and stripe patterns 714a-b may correspond with a stripe gate-shield of mask dimension LD14. According to the practice of microelectronics, the gate lateral distance LX, as discussed above with regards to FIG. 1, may also be determined, at least in part, by the mask dimensions LD13, LD14.

[0049] FIG. 7C illustrates closed cell layouts 704, 705 corresponding with vertical SiC MOS gate JFETs. The closed cell layouts 704, 705 may include patterns of thin film gate 123 (e.g., polysilicon) and the heavily doped regions (e.g., gate shield region 131 and source region 108). Additionally, closed cell patterns 715 may correspond with an island gate-shield of mask dimension LD15; and closed cell patterns 716 may correspond with a stripe gate-shield of mask dimension LD16. According to the practice of microelectronics, the gate lateral distance LX, as discussed above with regards to FIG. 1, may also be determined, at least in part, by the mask dimensions LD15, LD16.

[0050] In one aspect a vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistor (JFET) comprises an active cell (e.g., cell device cross sections 150). The active cell comprises an epitaxial layer (e.g., epitaxial layer 104), a source region (e.g., source region 108), a sub-surface channel region (e.g., sub-surface channel region 242), a gate shield region (e.g., shield region 131), a deep gate (e.g., deep gate 106), a deep well (e.g., deep well 243), and a metal oxide semiconductor (MOS) gate (e.g., a MOS gate of gate dielectric thickness tox formed by the thin film gate 123 and oxide 110).

[0051] The source region may be implanted at a surface of the epitaxial layer. The subsurface channel may be in electrical contact (e.g., electrically coupled) with the source region. The shield region may be laterally separated from the source region. The deep gate may be formed below the sub-surface channel region so as to create a JFET neck. The deep well may be in electrical contact with the deep gate; and the MOS gate may be formed above the sub-surface channel region.

[0052] According to the teachings herein, a pinch off voltage of the vertical SiC MOS gate JFET may be based, at least in part, upon a gate dielectric thickness of the MOS gate (e.g., the gate dielectric thickness tox), a dimension of the JFET neck (e.g., JFET neck length LCH1), and a doping concentration of the sub-surface channel region.

[0053] The epitaxial layer may comprise n-type doping with concentration between lel4 and lel6 inverse cubic centimeters. The deep gate may comprise aluminum. The shallow source may comprise nitrogen.

[0054] FIG. 8 illustrates a cell device cross 800 for a termination region of a vertical SiC MOS gate JFET according to an embodiment. The cell device cross section 800 includes the substrate layer 102, epitaxial (Epi) layer 104, deep gate 106, which may extend to the surface of the epitaxial layer 104 by virtue of deep well 243.

[0055] As one of ordinary skill in the art may appreciate, a termination pattern may be formed by one or more rings at the edge of die in order to spread electric fields and improve breakdown voltage. A termination (i.e., a termination region) may advantageously improve breakdown voltage by forming an equipotential guard ring at the die edge without adding additional process steps or complexity. Spacing of junctions formed by deep gate 106 and / or metal field plates may be selected so as to reduce peak electric fields.

[0056] The above description of illustrated examples of the present disclosure, including what is described in the Abstract, are not intended to be exhaustive or to be a limitation to the precise forms disclosed. While specific embodiments of vertical SiC MOS gate JFETs are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example device cross sections are provided for explanation purposes and that other embodiments may also be employed in accordance with the teachings herein.

[0057] Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.

Claims

CLAIMSWhat is claimed is:

1. A vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistor (JFET) comprising: a source region implanted at a surface of an epitaxial layer; a sub-surface channel region in electrical contact with the source region; a shield region laterally separated from the source region; a deep gate formed below the sub-surface channel region so as to create a JFET neck; a deep well in electrical contact with the deep gate; and a metal oxide semiconductor (MOS) gate formed above the sub-surface channel region, wherein a pinch-off voltage of the vertical SIC MOS gate JFET is based, at least in part, upon a gate dielectric thickness, a dimension of the JFET neck, and a doping concentration of the subsurface channel region.

2. The vertical SiC MOS gate JFET of claim 1, wherein a specific on-resistance of the vertical SIC MOS gate JFET is based, at least in part, upon the gate dielectric thickness, the dimension of the JFET neck, and the doping concentration of the sub-surface channel region.

3. The vertical SiC MOS gate JFET of claim 1, wherein the MOS gate comprises: a first dielectric deposited on the surface of the epitaxial layer; and a thin film deposited over the first dielectric.

4. The vertical SiC MOS gate JFET of claim 3, wherein the thin film comprises a stripe pattern.

5. The vertical SiC MOS gate JFET of claim 3, wherein the thin film comprises a closed-cell pattern.

6. The vertical SiC MOS gate JFET of claim 3, wherein the thin film comprises polysilicon.

7. The vertical SiC MOS gate JFET of claim 3, wherein a length of the MOS gate is determined, at least in part, by a mask dimension of the thin film.

8. The vertical SiC MOS gate JFET of claim 7, wherein the pinch-off voltage is determined, at least in part, by the mask dimension of the thin film.

9. The vertical SiC MOS gate JFET of claim 7, wherein a specific on-resistance is determined, at least in part, by the mask dimension of the thin film.

10. A vertical silicon carbide (SiC) metal oxide semiconductor (MOS) gate junction field effect transistor (JFET) comprising: an active cell comprising: a substrate layer; an epitaxial layer formed on the substrate layer; a source region implanted at a surface of the epitaxial layer; a sub-surface channel region formed below a surface of the epitaxial layer and in electrical contact with source region; a shield region implanted at the surface of the epitaxial layer and laterally separated from the source region; a deep gate implanted below the sub-surface channel region so as to create a JFET neck within the epitaxial layer; a deep well implanted into the epitaxial layer and in electrical contact with the deep gate; and a metal oxide semiconductor (MOS) gate formed above the sub-surface channel region and comprising a gate dielectric thickness, wherein a pinch-off voltage of the of the SIC MOS gate JFET is based, at least in part, upon a dimension of the JFET neck, a gate dielectric thickness of the MOS gate, and a doping concentration of the sub-surface channel region.

11. The vertical SiC MOS gate JFET of claim 10, wherein the active cell comprises a stripe pattern.

12. The vertical SiC MOS gate JFET of claim 10, wherein the active cell comprises a closed-cell pattern.

13. The vertical SiC MOS gate JFET of claim 10, wherein the JFET neck comprises a lateral dimension between one-half a micron and two microns.

14. The vertical SiC MOS gate JFET of claim 10, wherein the epitaxial layer comprises an n-type doping of concentration between lel4 and lei 6 inverse cubic centimeters.

15. The vertical SiC MOS gate JFET of claim 10, wherein the deep gate comprises aluminum.

16. The vertical SiC MOS gate JFET of claim 10, wherein the sub-surface channel region comprises nitrogen.

17. The vertical SiC MOS gate JFET of claim 10 further comprising: a termination region comprising: the substrate layer; the epitaxial layer; and a deep well implanted into the epitaxial layer.

18. The vertical SiC MOS gate JFET of claim 17, wherein the deep well and the deep gate are p-type.

19. The vertical SiC MOS gate JFET of claim 10, wherein the epitaxial layer and the sub-surface channel region are n-type.

20. The vertical SiC MOS gate JFET of claim 10, wherein the MOS gate comprises: a first dielectric deposited on the surface of the epitaxial layer; and a thin film deposited over the first dielectric.

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