Adder circuit structure and processor

Abstract

An adder circuit structure and a processor, which are used for realizing an addition operation of 2^n bits of data, n being a positive integer greater than or equal to 3. The adder circuit structure comprises 2^n input ends for the input of 2^n bits, and at least 2^n output ends, wherein one or more circuit structures for logic computation are provided on each path between the input ends and the output ends; and among every eight adjacent longitudinal paths, an input end of the fourth circuit structure in the eighth longitudinal path and an input end of the third circuit structure in the sixth longitudinal path are both connected to an output end of the third circuit structure in the fourth longitudinal path, and the longitudinal path is a path from an ith input end to an (i+1)th output end.

Description

Adder circuit structure and processor Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of computer technology, and in particular to an adder circuit structure and a processor. Background Art

[0002] Adders, as the most basic logical unit, are widely used in various types of processors. In circuit systems, adders are primarily responsible for calculations, indexing, and other functions. They are also crucial components of other hardware logical units, such as multipliers and subtractors. Adders can be categorized based on their circuit topology. Common adder topologies include ripple carry and carry-lookahead. Adders of different topologies vary in area and speed. Processor cores currently require high operating frequencies and low power consumption.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides an adder circuit structure, including: for implementing an addition operation of 2^n bits of data, where n is a positive integer greater than or equal to 3, the adder including: at least 2^n first-class circuit structures, at least 2 second-class circuit structures, at least 2^n-2 third-class circuit structures, and at least 2^n-1 fourth-class circuit structures, wherein:

[0006] The circuit structure is configured to receive the i-th bit of the input first data and the i-th bit of the second data, 0≥i≥2^n, and output the G logic result and the P logic result of the i-th bit;

[0007] The second type of circuit structure is configured to receive the G logic result and the P logic result, and output a G logic result sub-combination and a P logic result sub-combination;

[0008] The three types of circuit structures are configured to receive the G logic result and the P logic result or receive the G logic result sub-combination and the P logic result sub-combination, and output a new G logic result sub-combination;

[0009] The four types of circuit structures are configured to receive the P logic result and the G logic result or receive a sub-combination of the P logic result and the new G logic result, and output a sum value;

[0010] In the adder circuit structure, two or more of the second-type circuit structures reuse the calculation result of one second-type circuit structure, or two or more of the three-type circuit structures reuse the calculation result of one three-type circuit structure.

[0011] In a second aspect, an embodiment of the present disclosure provides an adder circuit structure, comprising: a circuit structure for implementing an addition operation of 2^n-bit data, where n is a positive integer greater than or equal to 3, the adder circuit structure comprising 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, and one or more circuit structures for logical calculation being provided on each path from the input terminal to the output terminal;

[0012] In every eight adjacent vertical paths, an input end of the fourth circuit structure in the eighth vertical path and an input end of the third circuit structure in the sixth vertical path are both connected to the output end of the third circuit structure in the fourth vertical path. The vertical path is a path from the i-th input end to the i+1-th output end, 0≤i≤2^n.

[0013] In a third aspect, an embodiment of the present disclosure provides a processor, comprising: the adder circuit structure as described above.

[0014] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the solutions described in the description, claims and drawings.

[0015] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0016] Summary of the Figures

[0017] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0018] FIG1A is a circuit diagram of a circuit structure S01;

[0019] FIG1B is a symbolic diagram of a circuit structure S01;

[0020] FIG2A is a circuit diagram of a second type of circuit structure S02;

[0021] FIG2B is a symbolic diagram of the second type of circuit structure S02;

[0022] FIG3A is a circuit diagram of three types of circuit structures S03;

[0023] FIG3B is a symbolic diagram of three types of circuit structures S03;

[0024] FIG4A is a circuit diagram of four types of circuit structures S04;

[0025] FIG4B is a symbolic diagram of four types of circuit structures S04;

[0026] Figure 5 is a topological diagram of an 8-bit unsigned integer adder without carry;

[0027] Figure 6 is a topological diagram of an 8-bit unsigned integer adder with carry;

[0028] Figure 7 is a topological diagram of a 16-bit unsigned integer adder without carry;

[0029] Figure 8 is a topological diagram of a 16-bit unsigned integer adder with carry;

[0030] Figure 9 is a topological diagram of a 32-bit unsigned integer adder without carry;

[0031] Figure 10 is a topological diagram of a 32-bit unsigned integer adder with carry;

[0032] FIG11A is a partial topological diagram of a 64-bit unsigned integer adder without carry;

[0033] FIG11B is a topological diagram of another part of a 64-bit unsigned integer adder without carry;

[0034] FIG12A is a partial topological diagram of a 64-bit unsigned integer adder with carry;

[0035] FIG12B is another topological structure diagram of a 64-bit unsigned integer adder with carry.

[0036] Details

[0037] The present disclosure describes a number of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0038] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0039] The terms "first" and "second" and the like in the specification and drawings of the present disclosure are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein.

[0040] In the description of the present disclosure, unless otherwise specified, “plurality” means two or more, and “two or more” herein includes two.

[0041] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0042] The following describes four circuit structures (or circuit units) used in the embodiments of the present disclosure, which are represented by circuit structures S01, S02, S03 and S04. The four circuit structures are all composed of logic gates.

[0043] Figure 1A is a circuit diagram of circuit structure S01, and Figure 1B is a symbolic diagram of circuit structure S01. The circuit structure S01 consists of logic gates: an AND gate (and) and an XOR gate (xor). The input of circuit structure S01 is a i and b i , indicating the a and b of the i-th position, the output is G i and P i , represents the G (Generate, carry generation) logic result and P (Propagate, carry propagation) logic result of the i-th bit. G, P and a i 、b i The logical relationship is: G i =a i b i Formula 1

[0044] Figure 2A is a circuit diagram of circuit structure S02, and Figure 2B is a symbolic diagram of circuit structure S02. The circuit structure S02 consists of logic gates: an AND gate and an AND-OR gate (abbreviated as Ao gate). The input of circuit structure S02 is P i:k , G i:k 、P k-1:j and G k-1:j , the output is G i:j and P i:j , that is, the logical result sub-combination of G and the logical result sub-combination of P, the relationship between i, j, k is: i>k>k-1>j. In some cases, i=k, or k=j, or k-1=j may appear. The logical relationship between P and G is: P i:j =P i:k ·P k-1:j Formula 3 G i:j =(P i:k ·G k-1:j )|G i:k Formula 4

[0045] When j=i-1, P i:i-1 =P i:i ·P i-1:i-1 =P i ·P i-1 Type 5G i:i-1 =(P i:i ·G i-1:i-1 )|G i:i =(P i ·G i-1 )|G i Formula 6

[0046] For example: If i=5, k=3, j=1, then P 5:1 =P 5:3 ·P 2:1 , G 5:1 =(P 5:3 ·G 2:1 )|G 5:3

[0047] Among them, P 5:3 =P 5:4 ·P 3:3 , G 5:3 =(P 5:4 ·G 3:3 )|G 5:4 , P 3:3That is, P3, which can be obtained by the above formula 2, G 3:3 That is, G3, which can be obtained by the above formula 1, then P 5:3 =P 5:4 P3, G 5:3 =(P 5:4 ·G3)|G 5:4 Among them, P 5:4 =P 5:5 ·P 4:4 , G 5:4 =(P 5:5 ·G 4:4 )|G 5:5 , P 5:5 That is, P5, P 4:4 That is, P4, G 5:5 That is G5, G 4:4 That is, G4, then P 5:4 =P5·P4,G 5:4 =(P5·G4)|G5; where P 2:1 =P 2:2 ·P 1:1 , G 2:1 =(P 2:2 ·G 1:1 )|G 2:2 , P 2:2 That is, P2, P 1:1 That is, P1, G 2:2 That is, G2, G 1:1 That is, G1, then P 2:1 =P2·P1,G 2:1 =(P2·G1)|G2.

[0048] Figure 3A is a circuit diagram of circuit structure S03, and Figure 3B is a symbolic diagram of circuit structure S03. Circuit structure S03 consists of a logic gate: an ao gate. Compared with circuit structure S02, it has one less AND gate. The input of circuit structure S03 is P i:k , G i:k and G k-1:j , the output is G i:j , that is, the new G logical result sub-combination, the relationship between i, j, k is: i>k>k-1>j. In some cases, i=k, or k=j, or k-1=j may appear. The logical relationship between P and G is as follows, the same as formula 4: G i:j =(P i:k ·G k-1:j )|G i:k Formula 7 (same as Formula 4)

[0049] Figure 4A is a circuit diagram of the circuit structure S04, and Figure 4B is a symbolic diagram of the circuit structure S04. The circuit structure S04 consists of a logic gate: an exclusive OR gate (xor). The input of the circuit structure S04 is P i and G i-1:0 , the output is S i , S i Represents S (sum, sum value) of the i-th position. The logical relationship between them is: S i =P i ·G i-1:0 Formula 8

[0050] In the examples herein, the circuit structure S01 is represented by a hexagon, the circuit structure S02 is represented by a square, the circuit structure S03 is represented by a circle, and the circuit structure S04 is represented by a triangle. These are merely examples and are not intended to limit the present application.

[0051] Logic gate circuits include transistors. When building an adder, the fewer logic gate circuits (circuit structures) used, the smaller the area occupied by the adder circuit topology structure. Moreover, since fewer transistors are used, the overall power consumption is lower.

[0052] An embodiment of the present disclosure provides an adder circuit structure for implementing an addition operation on 2^n-bit data, where n is a positive integer greater than or equal to 3. The adder includes: at least 2^n first-class circuit structures (i.e., the aforementioned circuit structure S01), at least two second-class circuit structures (i.e., the aforementioned circuit structure S02), at least 2^n-2 third-class circuit structures (i.e., the aforementioned circuit structure S03), and at least 2^n-1 fourth-class circuit structures (i.e., the aforementioned circuit structure S04), wherein:

[0053] The circuit structure includes an AND gate and an XOR gate, which is configured to receive the i-th bit of the first data and the i-th bit of the second data, 0≥i≥2^n, and output the carry of the i-th bit to generate a G logic result (G i ) and carry propagate P logical result (P i );

[0054] The second type of circuit structure includes an AND gate and an AND-OR gate, which are configured to receive the G logic result and the P logic result and output a G logic result sub-combination (G i:j ) and P logical result subcombination (P i:j );

[0055] The three types of circuit structures include an AND-OR gate configured to receive a G logic result and a P logic result or a G logic result sub-combination and a P logic result sub-combination, and output a new G logic result sub-combination (G i:0 );

[0056] The four types of circuit structures include an XOR gate, which is configured to receive a P logic result and a G logic result or a sub-combination of a P logic result and a new G logic result, and the output logic result is a sum value S.

[0057] The adder circuit structure provided in the embodiment of the present disclosure utilizes the above four circuit structures to construct an adder. Through reasonable design, the number of circuit structures used can be reduced, the power consumption of the adder can be reduced, and the area occupied by the overall topology structure can be reduced.

[0058] The reasonable design includes any one or more of the following:

[0059] ●The adder circuit structure includes at least 2^n vertical paths, and the vertical path is used to receive the i-th bit of the first data and the second data, and output the sum value of the i+1th bit. For example, the first vertical path receives the 0th bit of data and outputs the sum value of the 1st bit. The vertical path that receives the k-th bit of the first data and the second data includes a first-class circuit structure, a third-class circuit structure and a fourth-class circuit structure, k is an even number other than 0 in i, and the first-class circuit structure is used to receive the k-th bit of the first data and the second data. The output end of the first-class circuit structure is connected to the input end of the third-class circuit structure, and the input end of the third-class circuit structure is also connected to the output end of the first-class circuit structure in the previous vertical path for receiving the k-1-th bit of the first data and the second data. The output end of the third-class circuit structure is connected to the input end of the fourth-class circuit structure, and the input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the next vertical path for receiving the k+1-th bit of the first data and the k+1-th bit of the second data. The fourth-class circuit structure outputs the sum value of the k+1th bit.

[0060] This design reduces the number of circuit structures by simplifying the circuit structure in the even-bit vertical path (requiring only one type 1 circuit, one type 3 circuit, and one type 4 circuit), lowers the power consumption of the adder, and reduces the area occupied by the overall topology.

[0061] The odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, at least one type II circuit structure, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i;

[0062] The first type of circuit structure is used to receive the kth bit of the first data and the second data. The output end of the first type of circuit structure is connected to the input end of the first type of circuit structure. The input end of the first type of circuit structure is also connected to the output end of the first type of circuit structure in the previous vertical path for receiving the kth bit of the first data and the second data. The output end of the last type of circuit structure is connected to the input end of the third type of circuit structure. The input end of the third type of circuit structure is also connected to the output end of the third type of circuit structure in the previous even-numbered vertical path. The output end of the third type of circuit structure is connected to the input end of the fourth type of circuit structure. The input end of the fourth type of circuit structure is also connected to the output end of the first type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data. The fourth type of circuit structure outputs the sum value of the k+2th bit.

[0063] With this design, the number of circuit structures is reduced by simplifying the circuit structure in the odd-bit vertical path, the power consumption of the adder is reduced, and the area occupied by the overall topology structure is reduced.

[0064] In the adder circuit structure, two or more of the second-type circuit structures reuse the calculation result of one second-type circuit structure, or two or more of the third-type circuit structures reuse the calculation result of one third-type circuit structure.

[0065] With this design, the number of circuit structures can be reduced by reusing the calculation results of the circuit structures, the power consumption of the adders can be reduced, and the area occupied by the overall topology can be reduced.

[0066] The following describes how multiple circuit structures can reuse the calculation results of the same circuit structure.

[0067] As described above, the adder circuit structure includes 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, the path from the i-th input terminal to the (i+1)-th output terminal is a vertical path, and each path (or path) from the input terminal to the output terminal is provided with one or more of the aforementioned type 1 circuit structure, type 2 circuit structure, type 3 circuit structure, and type 4 circuit structure;

[0068] In an exemplary embodiment, within each of eight adjacent vertical paths, the fourth circuit structure in the eighth vertical path and the third circuit structure in the sixth vertical path reuse the calculation results of the third circuit structure in the fourth vertical path. For example, each of the eight adjacent vertical paths may be: path 0 to path 7, path 8 to path 15, path 16 to path 23, path 24 to path 31, path 32 to path 39, path 40 to path 47, path 48 to path 55, path 56 to path 63, and so on. The fourth circuit structure in the eighth vertical path refers to the circuit result ranked fourth in the eighth vertical path, meaning there are three circuit structures preceding it. The fourth circuit structure may be referred to as a fourth-level circuit structure, representing the number of logic levels in that vertical path. The number of circuit structures, i.e., the total number of logic levels, in the longest path from the input to the output of the adder circuit structure is the logical depth of the adder circuit structure. Among them, the fourth circuit structure in the eighth longitudinal path, the third circuit structure in the sixth longitudinal path, and the third circuit structure in the fourth longitudinal path are all type II circuit structures or type III circuit structures.

[0069] In an exemplary embodiment, in every 16 adjacent vertical paths, the fifth circuit structure in the 16th vertical path, the fourth circuit structure in the 14th vertical path, the fourth circuit structure in the 12th vertical path, and the third circuit structure in the 10th vertical path reuse the calculation results of the fourth circuit structure in the 8th vertical path. For example, the 16 adjacent vertical paths are: paths 0 to 15, paths 16 to 31, paths 32 to 47, paths 48 to 63, and so on. The fifth circuit structure in the 16th vertical path, the fourth circuit structure in the 14th vertical path, the fourth circuit structure in the 12th vertical path, the third circuit structure in the 10th vertical path, and the fourth circuit structure in the 8th vertical path are all third-category circuit structures.

[0070] In an exemplary embodiment, in every 32 adjacent vertical paths, the sixth circuit structure in the 32nd vertical path, the fifth circuit structure in the 30th vertical path, the fifth circuit structure in the 28th vertical path, the fourth circuit structure in the 26th vertical path, the fifth circuit structure in the 24th vertical path, the fourth circuit structure in the 22nd vertical path, the fourth circuit structure in the 20th vertical path, and the third circuit structure in the 18th vertical path reuse the calculation result of the fifth circuit structure in the 16th vertical path. For example, the 32 adjacent vertical paths include: paths 0 to 31, paths 32 to 63, and so on. Among them, the sixth circuit structure in the thirty-second longitudinal pathway, the fifth circuit structure in the thirtieth longitudinal pathway, the fifth circuit structure in the twenty-eighth longitudinal pathway, the fourth circuit structure in the twenty-sixth longitudinal pathway, the fifth circuit structure in the twenty-fourth longitudinal pathway, the fourth circuit structure in the twenty-second longitudinal pathway, the fourth circuit structure in the twentieth longitudinal pathway, the third circuit structure in the eighteenth longitudinal pathway, and the fifth circuit structure in the sixteenth longitudinal pathway are all three types of circuit structures.

[0071] The following describes the connection relationship of the circuit structure for implementing multiplexing in the odd-numbered bit vertical path when n is different values.

[0072] In an exemplary embodiment, when n=3, the odd-bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, one or two type II circuit structures, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i; wherein:

[0073] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0074] The input end of the first-two-type circuit structure is further connected to the output end of the first-type circuit structure in the previous vertical path for receiving the k-th bit of the first data and the second data, the output end of the first-two-type circuit structure (for example, the second-type circuit structure in the vertical path for receiving the third bit of data and the fifth bit of data starting from 0) is connected to the input end of the one of the three-type circuit structures, or the output end of the first-two-type circuit structure is connected to the input end of the second-two-type circuit structure, the input end of the second-two-type circuit structure (for example, the second-type circuit structure in the vertical path for receiving the seventh bit of data starting from 0) is further connected to the output end of a second-type circuit structure in the second vertical path, and the output end of the second-two-type circuit structure is connected to the input end of the one of the three-type circuit structures;

[0075] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal path, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0076] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0077] In the above structure of this example, the calculation results of the circuit structure can be multiplexed in the following manner: the three types of circuit structures in the sixth vertical path of the adder circuit structure that receives the fifth-bit data of the first data and the second data, and the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the seventh-bit data of the first data and the second data, and the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure that receives the third-bit data of the first data and the second data are multiplexed.

[0078] In an exemplary embodiment, when n=4, the odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, one, two, or three type II circuit structures, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i; wherein:

[0079] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0080] The input end of the first-two-category circuit structure is also connected to the output end of the first-category circuit structure in the previous vertical path for receiving the k-th bit of the first data and the second data, and the output end of the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 3rd bit of data, the 5th bit of data, and the 9th bit of data) is connected to the input end of the one of the three-category circuit structures; or the output end of the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 7th bit of data, the 11th bit of data, and the 13th bit of data) is connected to the input end of the second-two-category circuit structure, and the input end of the second-two-category circuit structure is also connected to the output end of the first-two-category circuit structure in the first two vertical paths, and the output end of the second-two-category circuit structure is connected to the input end of the one of the three-category circuit structures; or the first-two-category circuit structure (for example, the first-two-category circuit structure in the vertical path for receiving the 15th bit of data) is connected to the input end of the second-two-category circuit structure. The output end of the first type-two circuit structure is connected to the input end of the second type-two circuit structure, the input end of the second type-two circuit structure is also connected to the output end of the second type-two circuit structure in the first two vertical paths, the output end of the second type-two circuit structure is connected to the input end of the third type-two circuit structure, the input end of the third type-two circuit structure is also connected to the output end of the last type-two circuit structure (the second type-two circuit structure) in the first four vertical paths, and the output end of the third type-two circuit structure is connected to the input end of the first type-three circuit structure; the first type-two circuit structure in each vertical path is the first type-two circuit structure, the second type-two circuit structure in each vertical path is the second type-two circuit structure, the third type-two circuit structure in each vertical path is the third type-two circuit structure, and so on; the above-mentioned 3rd, 5th, 7th, 9th, 11th, 13th, 15th, etc. all refer to bits starting from 0. Unless otherwise specified below, the i-th bit refers to the bit number starting from 0.

[0081] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal paths, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0082] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0083] In the above structure of this example, the circuit structure calculation results can be reused in the following way:

[0084] Reuse of the results of the second type of circuit structure:

[0085] The second-class-2 circuit structure in the fourteenth vertical path of the adder circuit structure that receives the 13th-bit data of the first data and the second data, and the third-class-2 circuit structure in the sixteenth vertical path of the adder circuit structure that receives the 15th-bit data of the first data and the second data, multiplex the calculation results of the second-class-2 circuit structure in the twelfth vertical path of the adder circuit structure that receives the 11th-bit data of the first data and the second data.

[0086] Reuse of three types of circuit structure results:

[0087] The three types of circuit structures in the sixth vertical path of the adder circuit structure that receives the fifth bit of the first and second data, and the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the seventh bit of the first and second data, multiplex the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure that receives the third bit of the first and second data;

[0088] The three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the 9th bit of the first data and the second data, the three types of circuit structures in the twelfth vertical path that receives the 11th bit of the first data and the second data, and the three types of circuit structures in the fourteenth vertical path that receives the 13th bit of the first data and the second data, multiplex the calculation results of the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the 7th bit of the first data and the second data.

[0089] When the output includes a carry result, the three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the 9th bit data of the first data and the second data, the three types of circuit structures in the twelfth vertical path that receives the 11th bit data of the first data and the second data, the three types of circuit structures in the fourteenth vertical path that receives the 13th bit data of the first data and the second data, and the three types of circuit structures in the sixteenth vertical path that receives the 15th bit data of the first data and the second data multiplex the calculation results of the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the 7th bit data of the first data and the second data.

[0090] In an exemplary embodiment, when n=5, the odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, one, two, three, or four type II circuit structures, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i; wherein:

[0091] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0092] The input end of the first two types of circuit structures is further connected to the output end of a type of circuit structure in the previous vertical path for receiving the k-th data in the first data and the second data, and the output end of the first two types of circuit structures (for example, the first two types of circuit structures in the vertical path for receiving the 3rd data, the 5th data, the 9th data, and the 17th data) is connected to the input end of the one of the three types of circuit structures; or the output end of the first two types of circuit structures (for example, the first two types of circuit structures in the vertical path for receiving the 7th data, the 11th data, the 13th data, the 19th data, the 21st data, and the 25th data) is connected to the input end of the one of the three types of circuit structures. The output end of the first-class circuit structure (for example, the first-class circuit structure in the vertical path receiving the 15th-bit data, the 23rd-bit data, the 27th-bit data, and the 29th-bit data) is connected to the input end of the second-class circuit structure, the input end of the second-class circuit structure is further connected to the output end of the first-class circuit structure in the second vertical path, and the output end of the second-class circuit structure is connected to the input end of the one-class circuit structure; or the output end of the first-class circuit structure (for example, the first-class circuit structure in the vertical path receiving the 15th-bit data, the 23rd-bit data, the 27th-bit data, and the 29th-bit data) is connected to the input end of the second-class circuit structure, and the input end of the second-class circuit structure is further connected to the first two vertical paths. the output end of the second-class-II circuit structure, the output end of the second-class-II circuit structure is connected to the input end of the third-class-II circuit structure, the input end of the third-class-II circuit structure is further connected to the output end of the last-class-II circuit structure in the fourth or sixth vertical path, and the output end of the third-class-II circuit structure is connected to the input end of the one-class-III circuit structure; or the output end of the first-class-II circuit structure (e.g., the first-class-II circuit structure in the vertical path receiving the 31st bit of data) is connected to the input end of the second-class-II circuit structure, the input end of the second-class-II circuit structure is further connected to the output end of the second-class-II circuit structure in the first two vertical paths, the output end of the second-class-II circuit structure is connected to the input end of the third-class-II circuit structure, the input end of the third-class-II circuit structure is further connected to the output end of the second-class-II circuit structure in the fourth vertical path, the output end of the third-class-II circuit structure is connected to the input end of the fourth-class-II circuit structure, the input end of the fourth-class-II circuit structure is further connected to the output end of the last-class-II circuit structure (the third-class-II circuit structure) in the eighth vertical path, and the output end of the fourth-class-II circuit structure is connected to the input end of the one-class-III circuit structure;

[0093] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal path, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0094] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0095] In the above structure of this example, the circuit structure calculation results can be reused in the following way:

[0096] Reuse of the results of the second type of circuit structure:

[0097] The second-type-II circuit structure in the fourteenth vertical path of the adder circuit structure that receives the 13th bit of data among the first data and the second data, and the third-type-II circuit structure in the sixteenth vertical path of the adder circuit structure that receives the 15th bit of data among the first data and the second data, multiplex the calculation result of the second-type-II circuit structure in the twelfth vertical path of the adder circuit structure that receives the 11th bit of data among the first data and the second data;

[0098] The second-class-2 circuit structure in the twenty-second vertical path of the adder circuit structure that receives the 21st bit of the first data and the second data, and the third-class-2 circuit structure in the twenty-fourth vertical path of the adder circuit structure that receives the 23rd bit of the first data and the second data, multiplex the calculation results of the second-class-2 circuit structure in the twentieth vertical path of the adder circuit structure that receives the 19th bit of the first data and the second data.

[0099] When the output includes a carry result, in addition to the above-mentioned structural multiplexing, the following structural multiplexing is also adopted: the second-class-2 circuit structure in the 30th vertical path of the adder circuit structure that receives the 29th bit data of the first data and the second data, and the third-class-2 circuit structure in the 32nd vertical path of the adder circuit structure that receives the 31st bit data of the first data and the second data, multiplex the calculation result of the second-class-2 circuit structure in the 28th vertical path of the adder circuit structure that receives the 27th bit data of the first data and the second data.

[0100] Reuse of three types of circuit structure results:

[0101] The three types of circuit structures in the sixth vertical path of the adder circuit structure that receives the fifth bit of the first and second data, and the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the seventh bit of the first and second data, multiplex the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure that receives the third bit of the first and second data;

[0102] The three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the ninth bit of the first and second data, the three types of circuit structures in the twelfth vertical path that receives the eleventh bit of the first and second data, the three types of circuit structures in the fourteenth vertical path that receives the thirteenth bit of the first and second data, and the three types of circuit structures in the sixteenth vertical path that receives the fifteenth bit of the first and second data, and the calculation results of the three types of circuit structures in the eighth vertical path that receives the seventh bit of the first and second data in the adder circuit structure are multiplexed;

[0103] The three types of circuit structures in the eighteenth vertical path of the adder circuit structure that receives the 17th bit of the first and second data, the three types of circuit structures in the 20th vertical path that receives the 19th bit of the first and second data, the three types of circuit structures in the 22nd vertical path that receives the 21st bit of the first and second data, the three types of circuit structures in the 24th vertical path that receives the 23rd bit of the first and second data, the three types of circuit structures in the 26th vertical path that receives the 25th bit of the first and second data, the three types of circuit structures in the 28th vertical path that receives the 27th bit of the first and second data, and the three types of circuit structures in the 30th vertical path that receives the 29th bit of the first and second data, reuse the calculation results of the three types of circuit structures in the sixteenth vertical path that receives the 15th bit of the first and second data in the adder circuit structure.

[0104] When the output includes a carry result, in addition to the above-mentioned structural multiplexing, the following structural multiplexing is also adopted: the three types of circuit structures in the eighteenth vertical path receiving the 17th bit of the first and second data in the adder circuit structure, the three types of circuit structures in the 20th vertical path receiving the 19th bit of the first and second data, the three types of circuit structures in the 22nd vertical path receiving the 21st bit of the first and second data, the three types of circuit structures in the 24th vertical path receiving the 23rd bit of the first and second data, the three types of circuit structures in the 26th vertical path receiving the 25th bit of the first and second data, the three types of circuit structures in the 28th vertical path receiving the 27th bit of the first and second data, the three types of circuit structures in the 30th vertical path receiving the 29th bit of the first and second data, and the three types of circuit structures in the 32nd vertical path receiving the 31st bit of the first and second data, and the calculation results of the three types of circuit structures in the sixteenth vertical path receiving the 15th bit of the first and second data in the adder circuit structure are multiplexed.

[0105] In an exemplary embodiment, when n=6, the odd-numbered bit vertical path may adopt the following structure: the vertical path receiving the k+1th bit of the first data and the second data in the adder circuit structure includes one type I circuit structure, one, two, three, or four type II circuit structures, one type III circuit structure, and one type IV circuit structure, where k is an even number other than 0 in i; wherein:

[0106] The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the first and second type of circuit structures;

[0107] The input end of the first-two-type circuit structure is further connected to the output end of a type of circuit structure in the previous vertical path for receiving the k-th data in the first data and the second data, and the output end of the first-two-type circuit structure (for example, the first-two-type circuit structure in the vertical path for receiving the 3rd data, the 5th data, the 9th data, the 17th data, the 33rd data, and the 49th data) is connected to the input end of the one of the three types of circuit structures; or the output end of the first-two-type circuit structure (for example, the first-two-type circuit structure in the vertical path for receiving the 7th data, the 11th data, the 13th data, the 19th data, the 21st data, the 25th data, the 35th data, the 37th data, the 41st data, the 51st data, the 53rd data) is connected to the input end of the one of the three types of circuit structures. The output end of the first-second-type circuit structure (for example, the first-second-type circuit structure in the vertical path receiving the 15th-bit data, the 23rd-bit data, the 27th-bit data, the 29th-bit data, the 39th-bit data, the 43rd-bit data, the 45th-bit data, the 55th-bit data, the 59th-bit data, and the 61st-bit data) is connected to the input end of the second-second-type circuit structure, the input end of the second-second-type circuit structure is further connected to the output end of the first-second-type circuit structure in the second preceding vertical path, and the output end of the second-second-type circuit structure is connected to the input end of the one of the three-type circuit structures; or the output end of the first-second-type circuit structure (for example, the first-second-type circuit structure in the vertical path receiving the 15th-bit data, the 23rd-bit data, the 27th-bit data, the 29th-bit data, the 39th-bit data, the 43rd-bit data, the 45th-bit data, the 55th-bit data, the 59th-bit data, and the 61st-bit data) is connected to the input end of the second-second-type circuit structure, the input end of the second-second-type circuit structure is further connected to the output end of the second-second-type circuit structure in the first two vertical paths or the first four vertical paths, the output end of the second-second-type circuit structure is connected to the input end of the third-second-type circuit structure, and the input end of the third-second-type circuit structure is further connected to the first fourth vertical path or the first sixth vertical path. the output end of the last Class-II circuit structure in the first vertical path, the output end of the third Class-II circuit structure is connected to the input end of the one Class-III circuit structure; or the output end of the first Class-II circuit structure (for example, the first Class-II circuit structure in the vertical path that receives the 31st bit of data, the 47th bit of data, and the 63rd bit of data) is connected to the input end of the second Class-II circuit structure, the input end of the second Class-II circuit structure is further connected to the output end of the second Class-II circuit structure in the first two vertical paths, the output end of the second Class-II circuit structure is connected to the input end of the third Class-II circuit structure, the input end of the third Class-II circuit structure is further connected to the output end of the second Class-II circuit structure in the first four vertical paths, the output end of the third Class-II circuit structure is connected to the input end of the fourth Class-II circuit structure, the input end of the fourth Class-II circuit structure is further connected to the output end of the last Class-II circuit structure (the third Class-II circuit structure) in the first eight vertical paths, and the output end of the fourth Class-II circuit structure is connected to the input end of the one Class-III circuit structure;

[0108] The input end of the three-type circuit structure is also connected to the output end of the three-type circuit structure in the first even-numbered longitudinal path, and the output end of the three-type circuit structure is connected to the input end of the four-type circuit structure;

[0109] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the k+2th bit of the first data and the second data, and the four types of circuit structures output the sum value of the k+2th bit.

[0110] In the above structure of this example, the circuit structure calculation results can be reused in the following way:

[0111] Reuse of the results of the second type of circuit structure:

[0112] The second-type-II circuit structure in the fourteenth vertical path of the adder circuit structure that receives the 13th bit of data among the first data and the second data, and the third-type-II circuit structure in the sixteenth vertical path of the adder circuit structure that receives the 15th bit of data among the first data and the second data, multiplex the calculation result of the second-type-II circuit structure in the twelfth vertical path of the adder circuit structure that receives the 11th bit of data among the first data and the second data;

[0113] The second-class-2 circuit structure in the twenty-second vertical path of the adder circuit structure that receives the 21st bit of the first data and the second data, and the third-class-2 circuit structure in the twenty-fourth vertical path of the adder circuit structure that receives the 23rd bit of the first data and the second data, multiplex the calculation results of the second-class-2 circuit structure in the twentieth vertical path of the adder circuit structure that receives the 19th bit of the first data and the second data.

[0114] The second-type-II circuit structure in the 30th vertical path of the adder circuit structure that receives the 29th bit of the first and second data, and the third-type-II circuit structure in the 32nd vertical path of the adder circuit structure that receives the 31st bit of the first and second data, multiplex the calculation result of the second-type-II circuit structure in the 28th vertical path of the adder circuit structure that receives the 27th bit of the first and second data;

[0115] The second-type-II circuit structure in the thirty-eighth vertical path of the adder circuit structure that receives the 37th bit of the first and second data, and the third-type-II circuit structure in the fortieth vertical path of the adder circuit structure that receives the 39th bit of the first and second data, multiplex the calculation result of the second-type-II circuit structure in the thirty-sixth vertical path of the adder circuit structure that receives the 35th bit of the first and second data;

[0116] The second-type-II circuit structure in the forty-sixth vertical path of the adder circuit structure that receives the 45th bit of the first and second data, and the third-type-II circuit structure in the forty-eighth vertical path of the adder circuit structure that receives the 47th bit of the first and second data, multiplex the calculation result of the second-type-II circuit structure in the forty-fourth vertical path of the adder circuit structure that receives the 43rd bit of the first and second data;

[0117] The second-type-II circuit structure in the fifty-fourth vertical path of the adder circuit structure that receives the 53rd bit of the first and second data, and the third-type-II circuit structure in the fifty-sixth vertical path of the adder circuit structure that receives the 55th bit of the first and second data, multiplex the calculation result of the second-type-II circuit structure in the fifty-second vertical path of the adder circuit structure that receives the 51st bit of the first and second data;

[0118] The second-second type circuit structure in the sixty-second vertical path of the adder circuit structure that receives the 61st bit of the first and second data, and the third-second type circuit structure in the sixty-fourth vertical path of the adder circuit structure that receives the 63rd bit of the first and second data, multiplex the calculation result of the second-second type circuit structure in the sixtieth vertical path of the adder circuit structure that receives the 59th bit of the first and second data (when the adder output includes a carry result);

[0119] The second-second type circuit structure in the twenty-sixth vertical path of the adder circuit structure that receives the 25th bit of the first and second data, the third-second type circuit structure in the twenty-eighth vertical path that receives the 27th bit of the first and second data, the third-second type circuit structure in the 30th vertical path that receives the 29th bit of the first and second data, and the fourth-second type circuit structure in the thirty-second vertical path that receives the 31st bit of the first and second data, and the calculation result of the third-second type circuit structure in the twenty-fourth vertical path that receives the 23rd bit of the first and second data in the adder circuit structure are multiplexed;

[0120] The second-second type circuit structure in the forty-second vertical path of the adder circuit structure that receives the 41st bit of the first and second data, the third-second type circuit structure in the forty-fourth vertical path that receives the 43rd bit of the first and second data, the third-second type circuit structure in the forty-sixth vertical path that receives the 45th bit of the first and second data, and the fourth-second type circuit structure in the forty-eighth vertical path that receives the 47th bit of the first and second data, and the calculation result of the third-second type circuit structure in the fortieth vertical path that receives the 39th bit of the first and second data in the adder circuit structure are multiplexed;

[0121] The second-second type circuit structure in the fifty-eighth vertical path of the adder circuit structure that receives the 57th bit of the first and second data, the third-second type circuit structure in the sixtieth vertical path that receives the 59th bit of the first and second data, the third-second type circuit structure in the sixtieth vertical path that receives the 61st bit of the first and second data, and the fourth-second type circuit structure in the sixtieth vertical path that receives the 63rd bit of the first and second data (when the adder output includes a carry result), and the calculation result of the third-second type circuit structure in the fifty-sixth vertical path that receives the 55th bit of the first and second data in the adder circuit structure are multiplexed;

[0122] Reuse of three types of circuit structure results:

[0123] The three types of circuit structures in the sixth vertical path of the adder circuit structure that receives the fifth bit of the first and second data, and the three types of circuit structures in the eighth vertical path of the adder circuit structure that receives the seventh bit of the first and second data, multiplex the calculation results of the three types of circuit structures in the fourth vertical path of the adder circuit structure that receives the third bit of the first and second data;

[0124] The three types of circuit structures in the tenth vertical path of the adder circuit structure that receives the ninth bit of the first and second data, the three types of circuit structures in the twelfth vertical path that receives the eleventh bit of the first and second data, the three types of circuit structures in the fourteenth vertical path that receives the thirteenth bit of the first and second data, and the three types of circuit structures in the sixteenth vertical path that receives the fifteenth bit of the first and second data, and the calculation results of the three types of circuit structures in the eighth vertical path that receives the seventh bit of the first and second data in the adder circuit structure are multiplexed;

[0125] the three types of circuit structures in the eighteenth vertical path receiving the 17th bit of the first and second data in the adder circuit structure, the three types of circuit structures in the 20th vertical path receiving the 19th bit of the first and second data, the three types of circuit structures in the twenty-second vertical path receiving the 21st bit of the first and second data, the three types of circuit structures in the twenty-fourth vertical path receiving the 23rd bit of the first and second data, the three types of circuit structures in the twenty-sixth vertical path receiving the 25th bit of the first and second data, the three types of circuit structures in the twenty-eighth vertical path receiving the 27th bit of the first and second data, the three types of circuit structures in the 30th vertical path receiving the 29th bit of the first and second data, and the three types of circuit structures in the thirty-second vertical path receiving the 31st bit of the first and second data, and the calculation results of the three types of circuit structures in the sixteenth vertical path receiving the 15th bit of the first and second data in the adder circuit structure are multiplexed;

[0126] the three types of circuit structures in the 34th vertical path receiving the 33rd bit of the first and second data in the adder circuit structure, the three types of circuit structures in the 36th vertical path receiving the 35th bit of the first and second data, the three types of circuit structures in the 38th vertical path receiving the 37th bit of the first and second data, the three types of circuit structures in the 40th vertical path receiving the 39th bit of the first and second data, the three types of circuit structures in the 42nd vertical path receiving the 41st bit of the first and second data, the three types of circuit structures in the 44th vertical path receiving the 43rd bit of the first and second data, the three types of circuit structures in the 46th vertical path receiving the 45th bit of the first and second data, and the three types of circuit structures in the 48th vertical path receiving the 47th bit of the first and second data, and the calculation results of the three types of circuit structures in the 32nd vertical path receiving the 31st bit of the first and second data in the adder circuit structure are multiplexed;

[0127] The three types of circuit structures in the 50th vertical path receiving the 49th bit of the first and second data in the adder circuit structure, the three types of circuit structures in the 52nd vertical path receiving the 51st bit of the first and second data, the three types of circuit structures in the 54th vertical path receiving the 53rd bit of the first and second data, the three types of circuit structures in the 56th vertical path receiving the 55th bit of the first and second data, the three types of circuit structures in the 58th vertical path receiving the 57th bit of the first and second data, the three types of circuit structures in the 60th vertical path receiving the 59th bit of the first and second data, the three types of circuit structures in the 62nd vertical path receiving the 61st bit of the first and second data, and the three types of circuit structures in the 64th vertical path receiving the 63rd bit of the first and second data (when the adder output includes a carry result), and the calculation results of the three types of circuit structures in the 48th vertical path receiving the 47th bit of the first and second data in the adder circuit structure are multiplexed.

[0128] The above examples illustrate the connection of even-numbered vertical paths and odd-numbered vertical paths of 3 or more. The following describes the vertical path for receiving the 0th bit data and the vertical path for receiving the 1st bit data.

[0129] In an exemplary embodiment, the first vertical path in the adder circuit structure is used to receive the i-th bit of the first data and the second data, i=0, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a first-class circuit structure and a fourth-class circuit structure. The first-class circuit structure is used to receive the 0th bit of the first data and the second data, and output the G logic result and the P logic result of the 0th bit. The output end of the first-class circuit structure is connected to the input end of the fourth-class circuit structure. The input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the latter vertical path for receiving the 1st bit of the first data and the second data. The fourth-class circuit structure outputs the sum of the 1st bit, and the P logic result of the 0th bit output by the first-class circuit structure is the sum of the 0th bit.

[0130] In an exemplary embodiment, the second vertical path in the adder circuit structure is used to receive the i-th bit of the first data and the second data, i=1, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a first-class circuit structure, a third-class circuit structure, and a fourth-class circuit structure. The first-class circuit structure is used to receive the first-bit data of the first data and the second data. The output end of the first-class circuit structure is connected to the input end of the third-class circuit structure. The input end of the third-class circuit structure is also connected to the output end of the first-class circuit structure in the previous vertical path for receiving the 0th bit data of the first data and the second data. The output end of the third-class circuit structure is connected to the input end of the fourth-class circuit structure. The input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure in the next vertical path for receiving the second-bit data of the first data and the second data. The fourth-class circuit structure outputs the sum of the second bit.

[0131] In an exemplary embodiment, the 2^nth vertical path is used as a path for calculating a carry value, and the path includes a first-class circuit structure, at least two second-class circuit structures, a third-class circuit structure, and a fourth-class circuit structure, wherein:

[0132] The first type of circuit structure is used to receive the 2^n-1th bit of the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of the second type of circuit structure.

[0133] The at least two Class-II circuit structures are connected in sequence, wherein the input end of the first Class-II circuit structure is connected to the output end of the Class-II circuit structure in addition to being connected to the output end of the Class-I circuit structure, and is also connected to the output end of the Class-I circuit structure in the previous longitudinal path for receiving the 2^n-2th bit of the first data and the second data; the output end of the first Class-II circuit structure is connected to the input end of the one Class-III circuit structure, or is connected to the input end of the second Class-II circuit structure; the input end of the second Class-II circuit structure is also connected to the output end of the first Class-II circuit structure in the second previous longitudinal path; the output end of the second Class-II circuit structure is connected to the input end of the one Class-III circuit structure, or is connected to the input end of the third Class-II circuit structure; the input end of the third Class-II circuit structure is also connected to the output end of the second Class-II circuit structure in the fourth previous longitudinal path, or the input end of the third Class-II circuit structure is also connected to the output end of the third Class-II circuit structure in the eighth previous longitudinal path; the output end of the third Class-II circuit structure is connected to the input end of the one Class-III circuit structure;

[0134] The input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front fourth vertical path, or the input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front eighth vertical path, or the input end of the one three-type circuit structure is further connected to the output end of the three-type circuit structure in the front sixteenth vertical path, and the output end of the one three-type circuit structure is connected to the input end of the four-type circuit structure;

[0135] The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the 2^n+1th bit data in the first data and the second data, and the four types of circuit structures output carry values.

[0136] In an exemplary embodiment, the adder circuit structure includes a data path for summing the values, and the data path for summing the values ​​includes one or more of the following data paths:

[0137] The first data path includes: a first type of circuit structure and a fourth type of circuit structure;

[0138] The second data path includes: a first-class circuit structure, a third-class circuit structure, and a fourth-class circuit structure;

[0139] The third data path includes: a first type circuit structure, a second type circuit structure, a third type circuit structure and a fourth type circuit structure.

[0140] In an exemplary embodiment, the adder circuit structure may further include a data path (fourth data path) for calculating a carry value, and the fourth data path includes: a first-type circuit structure, a second-type circuit structure, and a third-type circuit structure.

[0141] The adder can be used to implement an addition operation with or without a carry on 2^n bit input data, where n is a positive integer greater than or equal to 3.

[0142] When the data length of the first data and the second data is 2^n bits, and n=3, the adder includes 2^n=8 inputs and 2^n=8 summation outputs, and the adder includes 2^n=8 first-class circuit structures, (2^(n-2)-1)*2=2 second-class circuit structures, (2^n)-2=6 third-class circuit structures, and (2^n)-1=7 fourth-class circuit structures; or the adder includes 2^n=8 inputs, 2^n=8 summation outputs, and 1 carry output, and the adder includes 2^n=8 first-class circuit structures, (2^(n-2)-1)*2+2=4 second-class circuit structures, (2^n)-1=7 third-class circuit structures, and (2^n)-1=7 fourth-class circuit structures.

[0143] When the data length of the first data and the second data is 2^n bits, and n=4, the adder includes 2^n=16 inputs and 2^n=16 summation outputs, and the adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3=9 second-class circuit structures, (2^n)-2=14 third-class circuit structures, and (2^n)-1=15 fourth-class circuit structures; or the adder includes 2^n=16 inputs, 2^n=16 summation outputs, and 1 carry output, and the adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3+3=12 second-class circuit structures, (2^n)-1=15 third-class circuit structures, and (2^n)-1=15 fourth-class circuit structures.

[0144] When the data length of the first data and the second data is 2^n bits and n=5, the adder includes 2^n=32 inputs and 2^n=32 summation outputs, and the adder includes 2^n=32 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-2)=28 second-class circuit structures, (2^n)-2=30 third-class circuit structures and (2^n)-1=3 1 four-category circuit structure; or the adder includes 2^n=32 inputs, 2^n=32 summation outputs and 1 carry output, the adder includes 2^n=32 first-category circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-2)+4=32 second-category circuit structures, (2^n)-1=31 third-category circuit structures and (2^n)-1=31 fourth-category circuit structures.

[0145] When the data length of the first data and the second data is 2^n bits, and n=6, the adder includes 2^n=64 inputs and 2^n=64 summation outputs, and the adder includes (2^n)=64 first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3)=68 second-class circuit structures, (2^n)-2=62 third-class circuit structures, and (2^n)-1= 63 four-category circuit structures; or the adder includes 2^n=64 inputs, 2^n=64 sum outputs and 1 carry output, and the adder includes 2^n=64 first-category circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3)+4=72 second-category circuit structures, (2^n)-1=63 third-category circuit structures and (2^n)-1=63 fourth-category circuit structures.

[0146] The adder circuit structures provided by the disclosed embodiments all have low maximum logic depths. The lower the maximum logic depth, the shorter the computation path and the faster the computation speed. This shows that the disclosed embodiments not only achieve low power consumption but also ensure high adder computation speeds, achieving a good balance between operating speed and power consumption.

[0147] The following example illustrates the topology of an 8-bit unsigned integer, carry-free adder built using the aforementioned circuit structures S01-S04. The expression for this adder is: sum[7:0] = a[7:0] + b[7:0], where sum represents summation. As shown in Figure 5, this adder includes 8 inputs and 8 outputs. In the figure, 0-7 represent inputs 0-7 (bits 0-7), respectively. Each input includes a and b. For example, input 0 represents a0 and b0, input 1 represents a1 and b1, and so on. S0-S7 in the figure represent the eight summed outputs, respectively. In the figure, the path from 0 to S1 is the first vertical path, referred to as the first path. The path from 1 to S2 is the second vertical path, referred to as the second path, and so on. For ease of illustration, subscripts are not used to represent numbers in the figure. For clarity, the circuit structure and connection relationships of the adder are described below in units of paths.

[0148] The first path (path 0 in the figure) can be used to obtain the sum values ​​S0 and S1. The first path includes a circuit structure S01 (hereinafter referred to as S01-1, represented by 1-1 in the figure, and the number after "-" represents the sequence number) and a circuit structure S04 (hereinafter referred to as S04-1, represented by 4-1 in the figure) connected to the circuit structure S01-1. The circuit structure S01-1 is used to calculate G0 and P0, and the circuit structure S04-1 is used to calculate S1. Among them, the input of the circuit structure S01-1 is a0 and b0, and the output is G0 and P0. The expression of the circuit structure S01-1 is: G0 = a0·b0, The output P0 of circuit structure S01-1 is S0. The expression of circuit structure S04-1 is: S1 = P1·G0. Circuit structure S04-1 is connected to circuit structure S01-1 to obtain G0. Circuit structure S04-1 is also connected to the next circuit structure (second circuit) S01-2 to obtain P1. The output of circuit structure S04-1 is S1.

[0149] The second path (path 1 in the figure) can be used to obtain the sum S2. The second path includes a circuit structure S01 (hereinafter referred to as S01-2, represented by 1-2 in the figure), a circuit structure S03 (hereinafter referred to as S03-1, represented by 3-1 in the figure), and a circuit structure S04 (hereinafter referred to as S04-2, represented by 4-2 in the figure) connected in sequence. The circuit structure S01-2 is used to calculate G1 and P1, and the circuit structure S03-1 is used to calculate G 1:0, the circuit structure S04-2 is used to calculate S2. Wherein, the expression of the circuit structure S01-2 is: G1=a1·b1, The inputs of circuit structure S01-2 are a1 and b1, and the outputs are G1 and P1. The expression of circuit structure S03-1 is: G 1:0 =(P1·G0)|G1, the circuit structure S03-1 is connected to the circuit structure S01-2 to obtain G1 and P1, and the circuit structure S03-1 is also connected to the first circuit structure S01-1 to obtain G0. The output of the circuit structure S03-1 is G 1:0 The expression of circuit structure S04-2 is: S2=P2·G 1:0 , the circuit structure S04-2 is connected to the circuit structure S03-1 to obtain G 1:0 The circuit structure S04-2 is also connected to the circuit structure S01-3 of the next path (the third path) to obtain P2. The output of the circuit structure S04-2 is S2.

[0150] The third path (path 2 in the figure) can be used to obtain the sum S3. The third path includes a circuit structure S01 (hereinafter referred to as S01-3, represented by 1-3 in the figure), a circuit structure S03 (hereinafter referred to as S03-2, represented by 3-2 in the figure), and a circuit structure S04 (hereinafter referred to as S04-3, represented by 4-3 in the figure) connected in sequence. The circuit structure S01-3 is used to calculate G2 and P2, and the circuit structure S03-2 is used to calculate G 2:0 , the circuit structure S04-3 is used to calculate S3. Wherein, the expression of the circuit structure S01-3 is: G2=a2·b2, The inputs of circuit structure S01-3 are a2 and b2, and the outputs are G2 and P2. The expression of circuit structure S03-2 is: G 2:0 =(P2·G 1:0 )|G2, the circuit structure S03-2 is connected to the circuit structure S01-3 to obtain G2, P2, and the circuit structure S03-2 is also connected to the second circuit structure S03-1 to obtain G 1:0 , the output of circuit structure S03-2 is G 2:0 The expression of circuit structure S04-3 is: S3=P3·G 2:0 , the circuit structure S04-3 is connected to the circuit structure S03-2 to obtain G 2:0 The circuit structure S04-2 is also connected to the circuit structure S01-4 of the next path (the fourth path) to obtain P3. The output of the circuit structure S04-3 is S3.

[0151] The fourth path (path 3 in the figure) can be used to obtain the sum S4. The fourth path includes a circuit structure S01 (hereinafter referred to as S01-4, represented by 1-4 in the figure), a circuit structure S02 (hereinafter referred to as S02-1, represented by 2-1 in the figure), a circuit structure S03 (hereinafter referred to as S03-3, represented by 3-3 in the figure), and a circuit structure S04 (hereinafter referred to as S04-4, represented by 4-4 in the figure) connected in sequence. Circuit structure S01-4 is used to calculate G3 and P3, and circuit structure S02-1 is used to calculate P 3:2 and G 3:2 , circuit structure S03-3 is used to calculate G 3:0 , the circuit structure S04-4 is used to calculate S4. Wherein, the expression of the circuit structure S01-4 is: G3=a3·b3, The inputs of circuit structure S01-4 are a3 and b3, and the outputs are G3 and P3. The expression of circuit structure S02-1 is: P 3:2 =P3·P2,G 3:2 =(P3·G2)|G3, the circuit structure S02-1 is connected to the circuit structure S01-4 to obtain G3 and P3, and the circuit structure S02-1 is also connected to the third circuit structure S01-3 to obtain G2 and P2. The output of the circuit structure S02-1 is P 3:2 and G 3:2 The expression of circuit structure S03-3 is: G 3:0 =(P 3:2 ·G 1:0 )|G 3:2 , the circuit structure S03-3 is connected to the circuit structure S02-1 to obtain P 3:2 and G 3:2 The circuit structure S03-3 is also connected to the second circuit structure S03-1 to obtain P 3:2 and G 3:2 , the output of circuit structure S03-3 is G 3:0 The expression of circuit structure S04-4 is: S4=P4·G 3:0 , the circuit structure S04-4 is connected to the circuit structure S03-3 to obtain G 3:0 The circuit structure S04-4 is also connected to the circuit structure S01-5 of the next path (the fifth path) to obtain P4. The output of the circuit structure S04-4 is S4.

[0152] The fifth path (4th path in the figure) can be used to obtain the sum S5. The fifth path includes a circuit structure S01 (hereinafter referred to as S01-5, represented by 1-5 in the figure), a circuit structure S03 (hereinafter referred to as S03-4, represented by 3-4 in the figure), and a circuit structure S04 (hereinafter referred to as S04-5, represented by 4-5 in the figure) connected in sequence. The circuit structure S01-5 is used to calculate G4 and P4, and the circuit structure S03-4 is used to calculate G 4:0 , the circuit structure S04-5 is used to calculate S5. Wherein, the expression of the circuit structure S01-5 is: G4=a4·b4, The inputs of circuit structure S01-5 are a4 and b4, and the outputs are G4 and P4. The expression of circuit structure S03-4 is: G 4:0 =(P4·G 3:0 )|G4, the circuit structure S03-4 is connected to the circuit structure S01-5 to obtain G4 and P4, and the circuit structure S03-4 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-4 is G 4:0 The expression of circuit structure S04-5 is: S5=P5·G 4:0 , the circuit structure S04-5 is connected to the circuit structure S03-4 to obtain G 4:0 The circuit structure S04-5 is also connected to the circuit structure S01-6 of the next path (the sixth path) to obtain P5. The output of the circuit structure S04-5 is S5.

[0153] The sixth path (path 5 in the figure) can be used to obtain the sum S6. The sixth path includes a circuit structure S01 (hereinafter referred to as S01-6, represented by 1-6 in the figure), a circuit structure S02 (hereinafter referred to as S02-2, represented by 2-2 in the figure), a circuit structure S03 (hereinafter referred to as S03-5, represented by 3-5 in the figure), and a circuit structure S04 (hereinafter referred to as S04-6, represented by 4-6 in the figure) connected in sequence. Circuit structure S01-6 is used to calculate G5 and P5, and circuit structure S02-2 is used to calculate P 5:4 and G 5:4 , circuit structure S03-5 is used to calculate G 5:0 , the circuit structure S04-6 is used to calculate S6. Wherein, the expression of the circuit structure S01-6 is: G5=a5·b5, The inputs of circuit structure S01-6 are a5 and b5, and the outputs are G5 and P5. The expression of circuit structure S02-2 is: P 5:4 =P5·P4,G 5:4=(P5·G4)|G5, the circuit structure S02-2 is connected to the circuit structure S01-6 to obtain G5 and P5, and the circuit structure S02-2 is also connected to the fifth circuit structure S01-5 to obtain G4 and P4. The output of the circuit structure S02-2 is P 5:4 and G 5:4 The expression of circuit structure S03-5 is: G 5:0 =(P 5:4 ·G 3:0 )|G 5:4 , the circuit structure S03-5 is connected to the circuit structure S02-2 to obtain P 5:4 and G 5:4 The circuit structure S03-5 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-5 is G 5:0 The expression of circuit structure S04-6 is: S6=P6·G 5:0 , the circuit structure S04-6 is connected to the circuit structure S03-5 to obtain G 5:0 The circuit structure S04-6 is also connected to the circuit structure S01-7 of the next path (the seventh path) to obtain P6. The output of the circuit structure S04-6 is S6.

[0154] The seventh path (path 6 in the figure) can be used to obtain the sum S7. The seventh path includes a circuit structure S01 (hereinafter referred to as S01-7, represented by 1-7 in the figure), a circuit structure S03 (hereinafter referred to as S03-6, represented by 3-6 in the figure), and a circuit structure S04 (hereinafter referred to as S4-7, represented by 4-7 in the figure) connected in sequence. The circuit structure S01-7 is used to calculate G6 and P6, and the circuit structure S03-6 is used to calculate G 6:0 , circuit structure S04-7 is used to calculate S7. Wherein, the expression of circuit structure S01-7 is: G6=a6·b6, The inputs of circuit structure S01-7 are a6 and b6, and the outputs are G6 and P6. The expression of circuit structure S03-6 is: G 6:0 =(P6·G 5:0 )|G6, the circuit structure S03-6 is connected to the circuit structure S01-7 to obtain G6 and P6, and the circuit structure S03-6 is also connected to the sixth circuit structure S03-5 to obtain G 5:0 , the output of circuit structure S03-6 is G 6:0 The expression of circuit structure S04-7 is: S7=P7·G 6:0 , the circuit structure S04-7 is connected to the circuit structure S03-6 to obtain G 6:0The circuit structure S04-7 is also connected to the circuit structure S01-8 of the next path (the eighth path) to obtain P7. The output of the circuit structure S04-7 is S7.

[0155] The eighth path (path 7 in the figure) can be used to obtain P7. The seventh path includes a circuit structure S01 (hereinafter referred to as S01-8, represented by 1-8 in the figure). Circuit structure S01-8 is used to calculate G7 and P7. The expression of circuit structure S01-8 is: G7 = a7·b7, The inputs of circuit structure S01-8 are a7 and b7, and the outputs are G7 and P7.

[0156] In this embodiment, to implement a (2^3)-bit, or 8-bit, carry-free adder, a total of 2^3 = 8 circuit structures S01, (2^1-1)*2 = 2 circuit structures S02, (2^3)-2 = 6 circuit structures S03, and (2^3)-1 = 7 circuit structures S04 are required, for a total of 8 + 2 + 6 + 7 = 23 circuit structures. As shown in FIG5 , the maximum logical depth of the adder structure in this example is 6 levels. The maximum logical depth can be understood as the maximum number of circuit structures traversed along the input-to-output path. Taking FIG5 as an example, the longest path traversed by data input from the fourth path (path 3 in the figure) includes: circuit structure S01-4, circuit structure S02-1, circuit structure S03-3, circuit structure S03-5, circuit structure S03-6, and circuit structure S04-7, for a total of 6 circuit structures. Therefore, the maximum logical depth of the adder is 6 levels. An adder can have multiple longest paths. In this example, the longest data path includes one circuit structure S01, one circuit structure S02, three circuit structures S03, and one circuit structure S04, or includes one circuit structure S01, four circuit structures S03, and one circuit structure S04.

[0157] In this embodiment, four circuit structures are used to implement an 8-bit adder without carry. Only 23 circuit structures are needed to implement an adder with a logic depth of 5 levels, achieving a balance between low power consumption, high speed and small area.

[0158] The following example illustrates the topology of an 8-bit unsigned integer adder with carry, built using the above-mentioned circuit structures S01-S04. The expression of the adder is: {carry,sum[7:0]}=a[7:0]+b[7:0], where carry represents carry and sum represents sum. As shown in Figure 6, the adder includes 8 inputs and 9 outputs. In the figure, 0-7 represent inputs 0-7 (0-7 bits), each input including a and b. In the figure, S0-S7 represent 8 summation outputs, respectively. In addition, there is a carry output, carry. The following describes the 8-bit unsigned integer adder with carry provided in this embodiment.

[0159] The topology of the first to seventh paths is the same as that of the 8-bit unsigned integer adder excluding carry in FIG5 , and will not be described again here.

[0160] The eighth path (path 7 in the figure) can be used to obtain the carry value. The eighth path includes a circuit structure S01 (hereinafter referred to as S01-8, represented by 1-8 in the figure), two circuit structures S02 (including circuit structure S02-3 and circuit structure S02-4, represented by 2-3 and 2-4 in the figure), and a circuit structure S03 (hereinafter referred to as S03-7, represented by 3-7 in the figure) connected in sequence. Circuit structure S01-8 is used to calculate G7 and P7, and circuit structure S02-3 is used to calculate P 7:6 and G 7:6 , circuit structure S02-4 is used to calculate P 7:4 and G 7:4 , circuit structure S03-7 is used to calculate G 7:0 Among them, the expression of circuit structure S01-8 is: G7=a7·b7, The inputs of circuit structure S01-8 are a7 and b7, and the outputs are G7 and P7. The expression of circuit structure S02-3 is P 7:6 =P7·P6,G 7:6 =(P7·G6)|G7, the circuit structure S02-3 is connected to the circuit structure S01-8 to obtain G7 and P7, and the circuit structure S02-3 is also connected to the seventh circuit structure S01-7 to obtain G6 and P6. The output of the circuit structure S02-3 is G 7:6 and P 7:6 The expression of circuit structure S02-4 is P 7:4 =P 7:6 ·P 5:4 , G 7:4 =(P 7:6 ·G 5:4 )|G 7:6 , the circuit structure S02-4 is connected to the circuit structure S02-3 to obtain G 7:6 and P7:6 The circuit structure S02-4 is also connected to the sixth circuit structure S02-2 to obtain G 5:4 and P 5:4 , the output of circuit structure S02-4 is G 7:4 and P 7:4 The expression of circuit structure S03-7 is G 7:0 =(P 7:4 ·G 3:0 )|G 7:4 , the circuit structure S03-7 is connected to the circuit structure S02-4 to obtain G 7:4 and P 7:4 The circuit structure S03-7 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output G of the circuit structure S03-7 7:0 This is the carry result.

[0161] In this embodiment, to implement a (2^3)-bit, or 8-bit, adder with carry, a total of 2^3 = 8 circuit structures S01, (2^1-1)*2+2 = 4 circuit structures S02, (2^3)-1 = 7 circuit structures S03, and (2^3)-1 = 7 circuit structures S04 are required, for a total of 8+4+7+7 = 26 circuit structures, which is 3 more circuit structures than an 8-bit adder without carry. As shown in Figure 6, the maximum logic depth of the adder structure in this example is still 6 levels, and the longest data path includes one circuit structure S01, one circuit structure S02, three circuit structures S03, and one circuit structure S04, or includes one circuit structure S01, four circuit structures S03, and one circuit structure S04.

[0162] In this embodiment, two or more (including two) three-type circuit structures are used to reuse the calculation results of one three-type circuit structure (hereinafter referred to as "three-type circuit structure reuse"). By designing circuit structures S03-7 and S03-5 at the fourth level to reuse the calculation results of circuit structure S03-3, the number of circuit structures can be reduced. This embodiment uses four circuit structures to implement an 8-bit adder with carry. Only 26 circuit structures are required to implement an adder with a logic depth of 5 levels, achieving a balance between low power consumption, high speed, and small area.

[0163] The following example illustrates the topology of a 16-bit unsigned integer, carry-free adder built using the above circuit structures S01-S04. The expression of the adder is: sum[15:0]=a[15:0]+b[15:0], where sum represents summation. As shown in Figure 7, the adder includes 16 inputs and 16 outputs. In the figure, 0-15 represent inputs 0-15 (0-15 bits), and each input includes a and b. For example, input 0 represents a0 and b0, input 1 represents a1 and b1, and so on. S0-S04 in the figure 15 For the sake of convenience, subscripts are not used to represent numbers in the figure.

[0164] The topology of the first to seventh paths is the same as that of the 8-bit unsigned integer adder excluding carry in FIG5 , and will not be described again here.

[0165] The eighth path (path 7 in the figure) can be used to obtain the sum value S8. The eighth path includes a circuit structure S01 (hereinafter referred to as S01-8, represented by 1-8 in the figure), two circuit structures S02 (including circuit structure S02-3 and circuit structure S02-4, represented by 2-3 and 2-4 in the figure), a circuit structure S03 (hereinafter referred to as S03-7, represented by 3-7 in the figure), and a circuit structure S04 (hereinafter referred to as S4-8, represented by 4-8 in the figure) connected in sequence. Circuit structure S01-8 is used to calculate G7 and P7, and circuit structure S02-3 is used to calculate P 7:6 and G 7:6 , circuit structure S02-4 is used to calculate P 7:4 and G 7:4 , circuit structure S03-7 is used to calculate G 7:0 , circuit structure S04-8 is used to calculate S8. Wherein, the expression of circuit structure S01-8 is: G7=a7·b7, The inputs of circuit structure S01-8 are a7 and b7, and the outputs are G7 and P7. The expression of circuit structure S02-3 is P 7:6 =P7·P6,G 7:6 =(P7·G6)|G7, the circuit structure S02-3 is connected to the circuit structure S01-8 to obtain G7 and P7, and the circuit structure S02-3 is also connected to the seventh circuit structure S01-7 to obtain G6 and P6. The output of the circuit structure S02-3 is G 7:6 and P 7:6 The expression of circuit structure S02-4 is P 7:4 =P 7:6 ·P 5:4 , G 7:4 =(P 7:6 ·G 5:4 )|G 7:6, the circuit structure S02-4 is connected to the circuit structure S02-3 to obtain G 7:6 and P 7:6 The circuit structure S02-4 is also connected to the sixth circuit structure S02-2 to obtain G 5:4 and P 5:4 , the output of circuit structure S02-4 is G 7:4 and P 7:4 The expression of circuit structure S03-7 is G 7:0 =(P 7:4 ·G 3:0 )|G 7:4 , the circuit structure S03-7 is connected to the circuit structure S02-4 to obtain G 7:4 and P 7:4 The circuit structure S03-7 is also connected to the fourth circuit structure S03-3 to obtain G 3:0 , the output of circuit structure S03-7 is G 7:0 The expression of circuit structure S04-8 is: S8=P8·G 7:0 , the circuit structure S04-8 is connected to the circuit structure S03-7 to obtain G 7:0 The circuit structure S04-8 is also connected to the circuit structure S01-9 of the next path (the ninth path) to obtain P8. The output of the circuit structure S04-8 is S8.

[0166] The ninth path (path 8 in the figure) can be used to obtain the sum S9. The ninth path includes a circuit structure S01 (hereinafter referred to as S01-9, represented by 1-9 in the figure), a circuit structure S03 (hereinafter referred to as S03-8, represented by 3-8 in the figure), and a circuit structure S04 (hereinafter referred to as S4-9, represented by 4-9 in the figure) connected in sequence. The circuit structure S01-9 is used to calculate G8 and P8, and the circuit structure S03-8 is used to calculate G 8:0 , the circuit structure S04-9 is used to calculate S9. Wherein, the expression of the circuit structure S01-9 is: G8=a8·b8, The inputs of circuit structure S01-9 are a8 and b8, and the outputs are G8 and P8. The expression of circuit structure S03-8 is: G 8:0 =(P8·G 7:0 )|G8, the circuit structure S03-8 is connected to the circuit structure S01-9 to obtain G8 and P8, and the circuit structure S03-8 is also connected to the circuit structure S03-7 of the eighth path to obtain G 7:0 , the output of circuit structure S03-8 is G 8:0 The expression of circuit structure S04-9 is: S9=P9·G 8:0 , the circuit structure S04-9 is connected to the circuit structure S03-8 to obtain G8:0 The circuit structure S04-9 is also connected to the circuit structure S01-10 of the next path (the tenth path) to obtain P9. The output of the circuit structure S04-9 is S9.

[0167] The tenth path (9th path in the figure) can be used to obtain the sum value S 10 The tenth path includes a circuit structure S01 (hereinafter referred to as S01-10, represented by 1-10 in the figure), a circuit structure S02 (hereinafter referred to as S02-5, represented by 2-5 in the figure), a circuit structure S03 (hereinafter referred to as S03-9, represented by 3-9 in the figure), and a circuit structure S04 (hereinafter referred to as S04-10, represented by 4-10 in the figure) connected in sequence. The circuit structure S01-10 is used to calculate G9 and P9, and the circuit structure S02-5 is used to calculate P 9:8 and G 9:8 , circuit structure S03-9 is used to calculate G 9:0 , circuit structure S04-10 is used to calculate S 10 Among them, the expression of circuit structure S01-10 is: G9=a9·b9, The inputs of circuit structure S01-10 are a9 and b9, and the outputs are G9 and P9. The expression of circuit structure S02-5 is: P 9:8 =P9·P8,G 9:8 =(P9·G8)|G9, the circuit structure S02-5 is connected to the circuit structure S01-10 to obtain G9 and P9, and the circuit structure S02-5 is also connected to the ninth circuit structure S01-9 to obtain G8 and P8. The output of the circuit structure S02-5 is P 9:8 and G 9:8 The expression of circuit structure S03-9 is: G 9:0 =(P 9:8 ·G 7:0 )|G 9:8 , the circuit structure S03-9 is connected to the circuit structure S02-5 to obtain G 9:8 and P 9:8 , the circuit structure S03-9 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-5 is G 9:0 The expression of circuit structure S04-10 is: S 10 =P 10 ·G 9:0 , the circuit structure S04-10 is connected to the circuit structure S03-9 to obtain G 9:0 The circuit structure S04-10 is also connected to the circuit structure S01-11 of the next path (the eleventh path) to obtain P 10, the output of circuit structure S04-10 is S 10 .

[0168] The eleventh path (path 10 in the figure) can be used to obtain the sum value S 11 The eleventh path includes a circuit structure S01 (hereinafter referred to as S01-11, represented by 1-11 in the figure), a circuit structure S03 (hereinafter referred to as S03-10, represented by 3-10 in the figure), and a circuit structure S04 (hereinafter referred to as S4-11, represented by 4-11 in the figure) connected in sequence. The circuit structure S01-11 is used to calculate G 10 and P 10 , circuit structure S03-10 is used to calculate G 10:0 , circuit structure S04-11 is used to calculate S 11 Among them, the expression of circuit structure S01-11 is: G 10 =a 10 b 10 , The input of circuit structure S01-11 is a 10 and b 10 , the output is G 10 and P 10 The expression of circuit structure S03-10 is: G 10:0 =(P 10 ·G 9:0 )|G 10 , the circuit structure S03-10 is connected to the circuit structure S01-11 to obtain G 10 and P 10 The circuit structure S03-10 is also connected to the circuit structure S03-9 of the tenth path to obtain G 9:0 , the output of circuit structure S03-10 is G 10:0 The expression of circuit structure S04-11 is: S 11 =P 11 ·G 10:0 , the circuit structure S04-11 is connected to the circuit structure S03-10 to obtain G 10:0 The circuit structure S04-11 is also connected to the circuit structure S01-12 of the next path (the twelfth path) to obtain P 11 , the output of circuit structure S04-11 is S 11 .

[0169] The twelfth path (path 11 in the figure) can be used to obtain the sum value S 12The twelfth path includes a circuit structure S01 (hereinafter referred to as S01-12, represented by 1-12 in the figure), two circuit structures S02 (including circuit structure S02-6 and circuit structure S02-7, represented by 2-6 and 2-7 in the figure), a circuit structure S03 (hereinafter referred to as S03-11, represented by 3-11 in the figure) and a circuit structure S04 (hereinafter referred to as S4-12, represented by 4-12 in the figure). Circuit structure S01-12 is used to calculate G 11 and P 11 , circuit structure S02-6 is used to calculate P 11:10 and G 11:10 , circuit structure S02-7 is used to calculate P 11:8 and G 11:8 , circuit structure S03-11 is used to calculate G 11:0 , circuit structure S04-12 is used to calculate S 12 Among them, the expression of circuit structure S01-12 is: G 11 =a 11 b 11 , The input of circuit structure S01-12 is a 11 and b 11 , the output is G 11 and P 11 The expression of circuit structure S02-6 is P 11:10 =P 11 ·P 10 , G 11:10 =(P 11 ·G 10 )|G 11 , the circuit structure S02-6 is connected to the circuit structure S01-12 to obtain G 11 and P 11 The circuit structure S02-6 is also connected to the circuit structure S01-11 of the eleventh path to obtain G 10 and P 10 , the output of circuit structure S02-6 is G 11:10 and P 11:10 The expression of circuit structure S02-7 is P 11:8 =P 11:10 ·P 9:8 , G 11:8 =(P 11:10 ·G 9:8 )|G 11:10 , the circuit structure S02-7 is connected to the circuit structure S02-6 to obtain G 11:10 and P 11:10 , the circuit structure S02-7 is also connected to the tenth circuit structure S02-5, for obtaining G 9:8and P 9:8 , the output of circuit structure S02-7 is G 11:8 and P 11:8 The expression of circuit structure S03-11 is G 11:0 =(P 11:8 ·G 7:0 )|G 11:8 , the circuit structure S03-11 is connected to the circuit structure S02-7 to obtain G 11:8 and P 11:8 The circuit structure S03-11 is also connected to the circuit structure S03-7 of the eighth path to obtain G 7:0 , the output of circuit structure S03-11 is G 11:0 The expression of circuit structure S04-12 is: S 12 =P 12 ·G 11:0 , the circuit structure S04-12 is connected to the circuit structure S03-11 to obtain G 11:0 The circuit structure S04-12 is also connected to the circuit structure S01-13 of the next path (the thirteenth path) to obtain P 12 The output of the circuit structure S04-8 is S 12 .

[0170] The thirteenth path (12th path in the figure) can be used to obtain the sum value S 13 The thirteenth path includes a circuit structure S01 (hereinafter referred to as S01-13, represented by 1-13 in the figure), a circuit structure S03 (hereinafter referred to as S03-12, represented by 3-12 in the figure), and a circuit structure S04 (hereinafter referred to as S4-13, represented by 4-13 in the figure) connected in sequence. The circuit structure S01-13 is used to calculate G 12 and P 12 , circuit structure S03-12 is used to calculate G 12:0 , circuit structure S04-13 is used to calculate S 13 Among them, the expression of circuit structure S01-13 is: G 12 =a 12 b 12 , The input of circuit structure S01-13 is a 12 and b 12 , the output is G 12 and P 12 The expression of circuit structure S03-12 is: G 12:0 =(P 12 ·G 11:0 )|G 12 , the circuit structure S03-12 is connected to the circuit structure S01-13 to obtain G 12 and P12 The circuit structure S03-12 is also connected to the twelfth circuit structure S03-11 to obtain G 11:0 , the output of circuit structure S03-12 is G 12:0 The expression of circuit structure S04-13 is: S 13 =P 13 ·G 12:0 , the circuit structure S04-13 is connected to the circuit structure S03-12 to obtain G 12:0 The circuit structure S04-13 is also connected to the circuit structure S01-14 of the next path (the fourteenth path) to obtain P 13 , the output of circuit structure S04-11 is S 13 .

[0171] The fourteenth path (path 13 in the figure) can be used to obtain the sum value S 14 The fourteenth path includes a circuit structure S01 (hereinafter referred to as S01-14, represented by 1-14 in the figure), two circuit structures S02 (including circuit structure S02-8 and circuit structure S02-9, represented by 2-8 and 2-9 in the figure), a circuit structure S03 (hereinafter referred to as S03-13, represented by 3-13 in the figure), and a circuit structure S04 (hereinafter referred to as S4-14, represented by 4-14 in the figure) connected in sequence. Circuit structure S01-14 is used to calculate G 13 and P 13 , circuit structure S02-8 is used to calculate P 13:12 and G 13:12 , circuit structure S02-9 is used to calculate P 13:8 and G 13:8 , circuit structure S03-13 is used to calculate G 13:0 , circuit structure S04-14 is used to calculate S 14 Among them, the expression of circuit structure S01-14 is: G 13 =a 13 b 13 , The input of circuit structure S01-14 is a 13 and b 13 , the output is G 13 and P 13 The expression of circuit structure S02-8 is P 13:12 =P 13 ·P 12 , G 13:12 =(P 13 ·G 12 )|G 13 , the circuit structure S02-8 is connected to the circuit structure S01-14 to obtain G 13 and P13 , the circuit structure S02-8 is also connected to the thirteenth circuit structure S01-13, for obtaining G 12 and P 12 , the output of circuit structure S02-8 is G 13:12 and P 13:12 The expression of circuit structure S02-9 is P 13:8 =P 13:12 ·P 11:8 , G 13:8 =(P 13:12 ·G 11:8 )|G 13:12 , the circuit structure S02-9 is connected to the circuit structure S02-8 to obtain G 13:12 and P 13:12 The circuit structure S02-9 is also connected to the twelfth circuit structure S02-7 to obtain G 11:8 and P 11:8 , the output of circuit structure S02-9 is G 13:8 and P 13:8 The expression of circuit structure S03-13 is G 13:0 =(P 13:8 ·G 7:0 )|G 13:8 , the circuit structure S03-13 is connected to the circuit structure S02-9 to obtain G 13:8 and P 13:8 , the circuit structure S03-13 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-13 is G 13:0 The expression of circuit structure S04-14 is: S 14 =P 14 ·G 13:0 , the circuit structure S04-14 is connected to the circuit structure S03-13 to obtain G 13:0 The circuit structure S04-14 is also connected to the circuit structure S01-15 of the next path (the fifteenth path) to obtain P 14 , the output of the circuit structure S04-14 is S 14 .

[0172] The 15th path (14th path in the figure) can be used to obtain the sum value S 15 The fifteenth path includes a circuit structure S01 (hereinafter referred to as S01-15, represented by 1-15 in the figure), a circuit structure S03 (hereinafter referred to as S03-14, represented by 3-14 in the figure), and a circuit structure S04 (hereinafter referred to as S4-15, represented by 4-15 in the figure) connected in sequence. The circuit structure S01-15 is used to calculate G 14 and P14 , circuit structure S03-14 is used to calculate G 14:0 , circuit structure S04-15 is used to calculate S 15 Among them, the expression of circuit structure S01-15 is: G 14 =a 14 b 14 , The input of circuit structure S01-15 is a 14 and b 14 , the output is G 14 and P 14 The expression of circuit structure S03-14 is: G 14:0 =(P 14 ·G 13:0 )|G 14 , the circuit structure S03-14 is connected to the circuit structure S01-15 to obtain G 14 and P 14 , the circuit structure S03-14 is also connected to the fourteenth circuit structure S03-13, for obtaining G 13:0 , the output of circuit structure S03-14 is G 14:0 The expression of circuit structure S04-15 is: S 15 =P 15 ·G 14:0 , the circuit structure S04-15 is connected to the circuit structure S03-14 to obtain G 14:0 The circuit structure S04-15 is also connected to the circuit structure S01-16 of the next path (the sixteenth path) to obtain P 15 , the output of circuit structure S04-15 is S 15 .

[0173] The sixteenth path (path 15 in the figure) can be used to obtain P 15 The sixteenth path includes a circuit structure S01 (hereinafter referred to as S01-16, represented by 1-16 in the figure). The circuit structure S01-16 is used to calculate G 15 and P 15 The expression of circuit structure S01-16 is: G 15 =a 15 b 15 , The input of circuit structure S01-16 is a 15 and b 15 , the output is G 15 and P 15 .

[0174] In this embodiment, in order to realize a (2^4)-bit, i.e., a 16-bit adder excluding carry, a total of 2^4=16 circuit structures S01, (2^2-1)*3=9 circuit structures S02, (2^4)-2=14 circuit structures S03, (2^4)-1=15 circuit structures S04 are required, for a total of 16+9+14+15=54 circuit structures. As shown in Figure 7, the maximum logic depth of the adder structure in this example is 7 levels, and the longest data path includes 1 circuit structure S01, 3 circuit structures S02, 2 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 3 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 5 circuit structures S03 and 1 circuit structure S04.

[0175] This embodiment reuses three types of circuit structures. By designing circuit structures S03-7 and S03-5 to reuse the calculation results of circuit structure S03-3, and circuit structures S03-13, S03-11, and S03-9 to reuse the calculation results of circuit structure S03-7, the number of circuit structures can be reduced. This embodiment uses four circuit structures to implement a 16-bit adder without carry bits. Only 54 circuit structures are required to implement an adder with a logic depth of 7 levels, achieving a balance between low power consumption, high speed, and small area.

[0176] The following example illustrates the topology of a 16-bit unsigned integer adder with carry built using the above circuit structures S01-S04. The expression of the adder is: {carry,sum[15:0]}=a[15:0]+b[15:0], where carry represents carry and sum represents sum. As shown in Figure 8, the adder includes 16 inputs and 17 outputs. In the figure, 0-15 represent inputs 0-15 (0-15 bits), each input includes a and b. In the figure, S0-S 15 The following describes the 16-bit unsigned integer adder including carry provided in this embodiment.

[0177] The topology of the first to fifteenth paths is the same as that of the 16-bit unsigned integer adder excluding carry in FIG7 , and will not be described again here.

[0178] The sixteenth path (path 15 in the figure) can be used to obtain the carry value. The sixteenth path includes a circuit structure S01 (hereinafter referred to as S01-16, represented by 1-16 in the figure), three circuit structures S02 (including circuit structure S02-10, circuit structure S02-11 and circuit structure 2-12, represented by 2-10, 2-11 and 2-12 in the figure) and a circuit structure S03 (hereinafter referred to as S03-15, represented by 3-15 in the figure) connected in sequence. Circuit structure S01-16 is used to calculate G 15 and P 15 , circuit structure S02-10 is used to calculate P 15:14 and G 15:14 , circuit structure S02-11 is used to calculate P 15:12 and G 15:12 , circuit structure S02-12 is used to calculate P 15:8 and G 15:8 , circuit structure S03-15 is used to calculate G 15:0 Among them, the expression of circuit structure S01-16 is: G 15 =a 15 b 15 , The input of circuit structure S01-16 is a 15 and b 15 , the output is G 15 and P 15 The expression of circuit structure S02-10 is P 15:14 =P 15 ·P 14 , G 15:14 =(P 15 ·G 14 )|G 15 , the circuit structure S02-10 is connected to the circuit structure S01-16 to obtain G 15 and P 15 , the circuit structure S02-10 is also connected to the circuit structure S01-15 of the fifteenth path, for obtaining G 14 and P 14 , the output of circuit structure S02-10 is G 15:14 and P 15:14 The expression of circuit structure S02-11 is P 15:12 =P 15:14 ·P 13:12 , G 15:12 =(P 15:14 ·G 13:12 )|G 15:14 , the circuit structure S02-11 is connected to the circuit structure S02-10 to obtain G 15:14 and P 15:14, the circuit structure S02-11 is also connected to the fourteenth circuit structure S02-8, for obtaining G 13:12 and P 13:12 , the output of circuit structure S02-11 is G 15:12 and P 15:12 The expression of circuit structure S02-12 is P 15:8 =P 15:12 ·P 11:8 , G 15:8 =(P 15:12 ·G 11:8 )|G 15:12 , the circuit structure S02-12 is connected to the circuit structure S02-11 to obtain G 15:12 and P 15:12 The circuit structure S02-12 is also connected to the twelfth circuit structure S02-7 to obtain G 11:8 and P 11:8 , the output of circuit structure S02-12 is G 15:8 and P 15:8 The expression of circuit structure S03-15 is G 15:0 =(P 15:8 ·G 7:0 )|G 15:8 , the circuit structure S03-15 is connected to the circuit structure S02-12 to obtain G 15:8 and P 15:8 , the circuit structure S03-15 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output G of circuit structure S03-15 15:0 This is the carry result.

[0179] In this embodiment, to implement a (2^4)-bit, i.e., a 16-bit adder including carry, a total of 2^4=16 circuit structures S01, (2^2-1)*3+3=12 circuit structures S02, (2^4)-1=15 circuit structures S03, and (2^4)-1=15 circuit structures S04 are required, totaling 16+12+15+15=58 circuit structures, which is 4 more circuit structures than a 16-bit adder excluding carry. As shown in Figure 8, the maximum logic depth of the adder structure in this example is still 7 levels, and the longest data path includes 1 circuit structure S01, 3 circuit structures S02, 2 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 3 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 5 circuit structures S03 and 1 circuit structure S04.

[0180] In this embodiment, the number of circuit structures is reduced by multiplexing three types of circuit structures and multiplexing the calculation results of one type-two circuit structure with two or more (including two) type-two circuit structures (hereinafter referred to as "type-two circuit structure multiplexing"). By designing circuit structures S02-12 and S02-9 to reuse the calculation results of circuit structure S02-7, circuit structures S03-7 and S03-5 to reuse the calculation results of circuit structure S03-3, and circuit structures S03-15, S03-13, S03-11, and S03-9 to reuse the calculation results of circuit structure S03-7, this embodiment uses four circuit structures to implement a 16-bit adder with carry bits. Only 58 circuit structures are required to implement an adder with a logic depth of 7 levels, achieving a balance between low power consumption, high speed, and small area.

[0181] The following example illustrates the topology of a 32-bit unsigned integer, carry-free adder built using the above circuit structures S01-S04. The expression of the adder is: sum[31:0]=a[31:0]+b[31:0], where sum represents summation. As shown in Figure 9, the adder includes 32 inputs and 32 outputs. In the figure, 0-31 represent inputs 0-31 (0-31 bits), and each input includes a and b. For example, input 0 represents a0 and b0, input 1 represents a1 and b1, and so on. S0-S04 in the figure 31 For the sake of convenience, subscripts are not used to represent numbers in the figure.

[0182] The topology of the first to fifteenth paths is the same as that of the 16-bit unsigned integer adder excluding carry in FIG7 , and will not be described again here.

[0183] The sixteenth path (15th path in the figure) can be used to obtain the sum value S 16 The sixteenth path includes a circuit structure S01 (hereinafter referred to as S01-16, represented by 1-16 in the figure), three circuit structures S02 (including circuit structure S02-10, circuit structure S02-11 and circuit structure 2-12, represented by 2-10, 2-11 and 2-12 in the figure), a circuit structure S03 (hereinafter referred to as S03-15, represented by 3-15 in the figure) and a circuit structure S04 (hereinafter referred to as S4-16, represented by 4-16 in the figure) connected in sequence. Circuit structure S01-16 is used to calculate G 15 and P 15 , circuit structure S02-10 is used to calculate P 15:14 and G 15:14 , circuit structure S02-11 is used to calculate P 15:12 and G 15:12, circuit structure S02-12 is used to calculate P 15:8 and G 15:8 , circuit structure S03-15 is used to calculate G 15:0 , circuit structure S04-16 is used to calculate S 16 Among them, the expression of circuit structure S01-16 is: G 15 =a 15 b 15 , The input of circuit structure S01-16 is a 15 and b 15 , the output is G 15 and P 15 The expression of circuit structure S02-10 is P 15:14 =P 15 ·P 14 , G 15:14 =(P 15 ·G 14 )|G 15 , the circuit structure S02-10 is connected to the circuit structure S01-16 to obtain G 15 and P 15 , the circuit structure S02-10 is also connected to the circuit structure S01-15 of the fifteenth path, for obtaining G 14 and P 14 , the output of circuit structure S02-10 is G 15:14 and P 15:14 The expression of circuit structure S02-11 is P 15:12 =P 15:14 ·P 13:12 , G 15:12 =(P 15:14 ·G 13:12 )|G 15:14 , the circuit structure S02-11 is connected to the circuit structure S02-10 to obtain G 15:14 and P 15:14 , the circuit structure S02-11 is also connected to the fourteenth circuit structure S02-8, for obtaining G 13:12 and P 13:12 , the output of circuit structure S02-11 is G 15:12 and P 15:12 The expression of circuit structure S02-12 is P 15:8 =P 15:12 ·P 11:8 , G 15:8 =(P 15:12 ·G 11:8 )|G 15:12 , the circuit structure S02-12 is connected to the circuit structure S02-11 to obtain G 15:12 and P15:12 The circuit structure S02-12 is also connected to the twelfth circuit structure S02-7 to obtain G 11:8 and P 11:8 , the output of circuit structure S02-12 is G 15:8 and P 15:8 The expression of circuit structure S03-15 is G 15:0 =(P 15:8 ·G 7:0 )|G 15:8 , the circuit structure S03-15 is connected to the circuit structure S02-12 to obtain G 15:8 and P 15:8 , the circuit structure S03-15 is also connected to the circuit structure S03-7 of the eighth path, for obtaining G 7:0 , the output of circuit structure S03-15 is G 15:0 The expression of circuit structure S04-16 is: S 16 =P 16 ·G 15:0 , the circuit structure S04-16 is connected to the circuit structure S03-15 to obtain G 15:0 The circuit structure S04-16 is also connected to the circuit structure S01-17 of the next path (the seventeenth path) to obtain P 16 The output of the circuit structure S04-16 is S 16 .

[0184] The 17th path (16th path in the figure) can be used to obtain the sum value S 17 The seventeenth path includes a circuit structure S01 (hereinafter referred to as S01-17, represented by 1-17 in the figure), a circuit structure S03 (hereinafter referred to as S03-16, represented by 3-16 in the figure), and a circuit structure S04 (hereinafter referred to as S4-17, represented by 4-17 in the figure) connected in sequence. The circuit structure S01-17 is used to calculate G 16 and P 16 , circuit structure S03-16 is used to calculate G 16:0 , circuit structure S04-17 is used to calculate S 17 Among them, the expression of circuit structure S01-17 is: G 16 =a 16 b 16 , The input of circuit structure S01-17 is a 16 and b 16 , the output is G 16 and P 16 The expression of circuit structure S03-16 is: G 16:0 =(P 16 ·G 15:0)|G 16 , the circuit structure S03-16 is connected to the circuit structure S01-17 to obtain G 16 and P 16 The circuit structure S03-16 is also connected to the circuit structure S03-15 of the sixteenth path, and is used to obtain G 15:0 , the output of circuit structure S03-16 is G 16:0 The expression of circuit structure S04-17 is: S 17 =P 17 ·G 16:0 , the circuit structure S04-17 is connected to the circuit structure S03-16 to obtain G 16:0 The circuit structure S04-17 is also connected to the circuit structure S01-18 of the next path (the eighteenth path) to obtain P 17 , the output of circuit structure S04-17 is S 17 .

[0185] The 18th path (17th path in the figure) can be used to obtain the sum value S 18 The eighteenth path includes a circuit structure S01 (hereinafter referred to as S01-18, represented by 1-18 in the figure), a circuit structure S02 (hereinafter referred to as S02-13, represented by 2-13 in the figure), a circuit structure S03 (hereinafter referred to as S03-17, represented by 3-17 in the figure), and a circuit structure S04 (hereinafter referred to as S04-18, represented by 4-18 in the figure) connected in sequence. The circuit structure S01-18 is used to calculate G 17 and P 17 , circuit structure S02-13 is used to calculate P 17:16 and G 17:16 , circuit structure S03-17 is used to calculate G 17:0 , circuit structure S04-18 is used to calculate S 18 Among them, the expression of circuit structure S01-18 is: G 17 =a 17 b 17 , The input of circuit structure S01-18 is a 17 and b 17 , the output is G 17 and P 17 The expression of circuit structure S02-13 is: P 17:16 =P 17 ·P 16 , G 17:16 =(P 17 ·G 16 )|G 17 , the circuit structure S02-13 is connected to the circuit structure S01-18 to obtain G 17and P 17 , the circuit structure S02-13 is also connected to the circuit structure S01-17 of the seventeenth path, for obtaining G 16 and P 16 , the output of circuit structure S02-13 is P 17:16 and G 17:16 The expression of circuit structure S03-17 is: G 17:0 =(P 17:16 ·G 15:0 )|G 17:16 , the circuit structure S03-17 is connected to the circuit structure S02-13 to obtain G 17:16 and P 17:16 , the circuit structure S03-17 is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-17 is G 17:0 The expression of circuit structure S04-18 is: S 18 =P 18 ·G 17:0 , the circuit structure S04-18 is connected to the circuit structure S03-17 to obtain G 17:0 The circuit structure S04-18 is also connected to the circuit structure S01-19 of the next path (the nineteenth path) to obtain P 18 , the output of circuit structure S04-18 is S 18 .

[0186] The 19th path (18th path in the figure) can be used to obtain the sum value S 19 The nineteenth path includes a circuit structure S01 (hereinafter referred to as S01-19, represented by 1-19 in the figure), a circuit structure S03 (hereinafter referred to as S03-18, represented by 3-18 in the figure), and a circuit structure S04 (hereinafter referred to as S4-19, represented by 4-19 in the figure) connected in sequence. The circuit structure S01-19 is used to calculate G 18 and P 18 , circuit structure S03-18 is used to calculate G 18:0 , circuit structure S04-19 is used to calculate S 19 Among them, the expression of circuit structure S01-19 is: G 18 =a 18 b 18 , The input of circuit structure S01-19 is a 18 and b 18 , the output is G 18 and P 18 The expression of circuit structure S03-18 is: G 18:0 =(P 18 ·G17:0 )|G 18 , the circuit structure S03-18 is connected to the circuit structure S01-19 to obtain G 18 and P 18 , the circuit structure S03-18 is also connected to the circuit structure S03-17 of the eighteenth path, for obtaining G 17:0 , the output of circuit structure S03-18 is G 18:0 The expression of circuit structure S04-19 is: S 19 =P 19 ·G 18:0 , the circuit structure S04-19 is connected to the circuit structure S03-18 to obtain G 18:0 The circuit structure S04-19 is also connected to the circuit structure S01-20 of the next path (the 20th path) to obtain P 19 , the output of circuit structure S04-19 is S 19 .

[0187] The 20th path (19th path in the figure) can be used to obtain the sum value S 20 The twentieth path includes a circuit structure S01 (hereinafter referred to as S01-20, represented by 1-20 in the figure), two circuit structures S02 (including circuit structure S02-14 and circuit structure S02-15, represented by 2-14 and 2-15 in the figure), a circuit structure S03 (hereinafter referred to as S03-19, represented by 3-18 in the figure) and a circuit structure S04 (hereinafter referred to as S4-20, represented by 4-20 in the figure) connected in sequence. The circuit structure S01-20 is used to calculate G 19 and P 19 , circuit structure S02-14 is used to calculate P 19:18 and G 19:18 , circuit structure S02-15 is used to calculate P 19:16 and G 19:16 , circuit structure S03-19 is used to calculate G 19:0 , circuit structure S04-20 is used to calculate S 20 Among them, the expression of circuit structure S01-20 is: G 19 =a 19 b 19 , The input of circuit structure S01-20 is a 19 and b 19 , the output is G 19 and P 19 The expression of circuit structure S02-14 is P 19:18 =P 19 ·P 18 , G 19:18 =(P 19·G 18 )|G 19 , the circuit structure S02-14 is connected to the circuit structure S01-20 to obtain G 19 and P 19 , the circuit structure S02-14 is also connected to the circuit structure S01-19 of the nineteenth path, for obtaining G 18 and P 18 , the output of circuit structure S02-14 is G 19:18 and P 19:18 The expression of circuit structure S02-15 is P 19:16 =P 19:18 ·P 17:16 , G 19:16 =(P 19:18 ·G 17:16 )|G 19:18 , the circuit structure S02-15 is connected to the circuit structure S02-14 to obtain G 19:18 and P 19:18 The circuit structure S02-15 is also connected to the circuit structure S02-13 of the eighteenth path to obtain G 17:16 and P 17:16 , the output of circuit structure S02-15 is G 19:16 and P 19:16 The expression of circuit structure S03-19 is G 19:0 =(P 19:16 ·G 15:0 )|G 19:16 , the circuit structure S03-19 is connected to the circuit structure S02-15 to obtain G 19:16 and P 19:16 , the circuit structure S03-19 is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-19 is G 19:0 The expression of circuit structure S04-20 is: S 20 =P 20 ·G 19:0 , the circuit structure S04-20 is connected to the circuit structure S03-19 to obtain G 19:0 The circuit structure S04-20 is also connected to the circuit structure S01-21 of the next path (the 21st path) to obtain P 20 , the output of the circuit structure S04-20 is S 20 .

[0188] The 21st path (20th path in the figure) can be used to obtain the sum value S 21The twenty-first path includes a circuit structure S01 (hereinafter referred to as S01-21, represented by 1-21 in the figure), a circuit structure S03 (hereinafter referred to as S03-20, represented by 3-20 in the figure), and a circuit structure S04 (hereinafter referred to as S4-21, represented by 4-21 in the figure) connected in sequence. The circuit structure S01-21 is used to calculate G 20 and P 20 , circuit structure S03-20 is used to calculate G 20:0 , circuit structure S04-21 is used to calculate S 21 Among them, the expression of circuit structure S01-21 is: G 20 =a 20 b 20 , The input of circuit structure S01-21 is a 20 and b 20 , the output is G 20 and P 20 The expression of circuit structure S03-20 is: G 20:0 =(P 20 ·G 19:0 )|G 20 , the circuit structure S03-20 is connected to the circuit structure S01-21 to obtain G 20 and P 20 The circuit structure S03-20 is also connected to the twentieth circuit structure S03-19 to obtain G 19:0 , the output of circuit structure S03-20 is G 20:0 The expression of circuit structure S04-21 is: S 21 =P 21 ·G 20:0 , the circuit structure S04-21 is connected to the circuit structure S03-20 to obtain G 20:0 The circuit structure S04-21 is also connected to the circuit structure S01-22 of the next path (the 22nd path) to obtain P 21 , the output of circuit structure S04-21 is S 21 .

[0189] The 22nd path (21st path in the figure) can be used to obtain the sum value S 22 The twenty-second path includes a circuit structure S01 (hereinafter referred to as S01-22, represented by 1-22 in the figure), two circuit structures S02 (including circuit structure S02-16 and circuit structure S02-17, represented by 2-16 and 2-17 in the figure), a circuit structure S03 (hereinafter referred to as S03-21, represented by 3-21 in the figure), and a circuit structure S04 (hereinafter referred to as S4-22, represented by 4-22 in the figure) connected in sequence. The circuit structure S01-22 is used to calculate G21 and P 21 , circuit structure S02-16 is used to calculate P 21:20 and G 21:20 , circuit structure S02-17 is used to calculate P 21:16 and G 21:16 , circuit structure S03-21 is used to calculate G 21:0 , circuit structure S04-22 is used to calculate S 22 Among them, the expression of circuit structure S01-22 is: G 21 =a 21 b 21 , The input of circuit structure S01-22 is a 21 and b 21 , the output is G 21 and P 21 The expression of circuit structure S02-16 is P 21:20 =P 21 ·P 20 , G 21:20 =(P 21 ·G 20 )|G 21 , the circuit structure S02-16 is connected to the circuit structure S01-22 to obtain G 21 and P 21 The circuit structure S02-16 is also connected to the twenty-first circuit structure S01-21 to obtain G 20 and P 20 , the output of circuit structure S02-16 is G 21:20 and P 21:20 The expression of circuit structure S02-17 is P 21:16 =P 21:20 ·P 19:16 , G 21:16 =(P 21:20 ·G 19:16 )|G 21:20 , the circuit structure S02-17 is connected to the circuit structure S02-16 to obtain G 21:20 and P 21:20 , the circuit structure S02-17 is also connected to the twentieth circuit structure S02-15, for obtaining G 19:16 and P 19:16 , the output of circuit structure S02-17 is G 21:16 and P 21:16 The expression of circuit structure S03-21 is G 21:0 =(P 21:16 ·G 15:0 )|G 21:16, the circuit structure S03-21 is connected to the circuit structure S02-17 to obtain G 21:16 and P 21:16 The circuit structure S03-21 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-21 is G 21:0 The expression of circuit structure S04-22 is: S 22 =P 22 ·G 21:0 , the circuit structure S04-22 is connected to the circuit structure S03-21 to obtain G 21:0 The circuit structure S04-22 is also connected to the circuit structure S01-23 of the next path (the 23rd path) to obtain P 22 The output of the circuit structure S04-22 is S 22 .

[0190] The 23rd path (22nd path in the figure) can be used to obtain the sum value S 23 The twenty-third path includes a circuit structure S01 (hereinafter referred to as S01-21, represented by 1-23 in the figure), a circuit structure S03 (hereinafter referred to as S03-22, represented by 3-22 in the figure), and a circuit structure S04 (hereinafter referred to as S4-23, represented by 4-23 in the figure) connected in sequence. The circuit structure S01-23 is used to calculate G 22 and P 22 , circuit structure S03-22 is used to calculate G 22:0 , circuit structure S04-23 is used to calculate S 23 Among them, the expression of circuit structure S01-21 is: G 22 =a 22 b 22 , The input of circuit structure S01-23 is a 22 and b 22 , the output is G 22 and P 22 The expression of circuit structure S03-22 is: G 22:0 =(P 22 ·G 21:0 )|G 22 , the circuit structure S03-22 is connected to the circuit structure S01-23 to obtain G 22 and P 22 The circuit structure S03-22 is also connected to the twenty-second circuit structure S03-21 to obtain G 21:0 , the output of circuit structure S03-22 is G 22:0 The expression of circuit structure S04-23 is: S 23 =P23 ·G 22:0 , the circuit structure S04-23 is connected to the circuit structure S03-22 to obtain G 22:0 The circuit structure S04-23 is also connected to the circuit structure S01-24 of the next path (the 24th path) to obtain P 23 , the output of circuit structure S04-23 is S 23 .

[0191] The 24th path (23rd path in the figure) can be used to obtain the sum value S 24 The twenty-fourth path includes a circuit structure S01 (hereinafter referred to as S01-24, represented by 1-24 in the figure), three circuit structures S02 (including circuit structure S02-18, circuit structure S02-19 and circuit structure 2-20, represented by 2-18, 2-19 and 2-20 in the figure), a circuit structure S03 (hereinafter referred to as S03-23, represented by 3-23 in the figure) and a circuit structure S04 (hereinafter referred to as S4-24, represented by 4-24 in the figure) connected in sequence. The circuit structure S01-24 is used to calculate G 23 and P 23 , circuit structure S02-18 is used to calculate P 23:22 and G 23:22 , circuit structure S02-19 is used to calculate P 23:20 and G 23:20 , circuit structure S02-20 is used to calculate P 23:16 and G 23:16 , circuit structure S03-23 ​​is used to calculate G 23:0 , circuit structure S04-24 is used to calculate S 24 Among them, the expression of circuit structure S01-24 is: G 23 =a 23 b 23 , The input of circuit structure S01-24 is a 23 and b 23 , the output is G 23 and P 23 The expression of circuit structure S02-18 is P 23:22 =P 23 ·P 22 , G 23:22 =(P 23 ·G 22 )|G 23 , the circuit structure S02-18 is connected to the circuit structure S01-24 to obtain G 23 and P 23 , the circuit structure S02-18 is also connected to the twenty-third circuit structure S01-23, for obtaining G 22and P 22 , the output of circuit structure S02-18 is G 23:22 and P 23:22 The expression of circuit structure S02-19 is P 23:20 =P 23:22 ·P 21:20 , G 23:20 =(P 23:22 ·G 21:20 )|G 23:22 , the circuit structure S02-19 is connected to the circuit structure S02-18 to obtain G 23:22 and P 23:22 The circuit structure S02-19 is also connected to the twenty-second circuit structure S02-16 to obtain G 21:20 and P 21:20 , the output of circuit structure S02-19 is G 23:20 and P 23:20 The expression of circuit structure S02-20 is P 23:16 =P 23:20 ·P 19:16 , G 23:20 =(P 23:20 ·G 19:16 )|G 23:20 , the circuit structure S02-20 is connected to the circuit structure S02-19 to obtain G 23:20 and P 23:20 The circuit structure S02-20 is also connected to the twentieth circuit structure S02-15 to obtain G 19:16 and P 19:16 , the output of circuit structure S02-20 is G 23:16 and P 23:16 The expression of circuit structure S03-23 ​​is G 23:0 =(P 23:16 ·G 15:0 )|G 23:16 , the circuit structure S03-23 ​​is connected to the circuit structure S02-20 to obtain G 23:16 and P 23:16 , the circuit structure S03-23 ​​is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G 15:0 , the output of circuit structure S03-23 ​​is G 23:0 The expression of circuit structure S04-24 is: S 24 =P 24 ·G 23:0 , the circuit structure S04-24 is connected to the circuit structure S03-23 ​​to obtain G 23:0 The circuit structure S04-24 is also connected to the circuit structure S01-25 of the next path (the 25th path) to obtain P24 The output of the circuit structure S04-24 is S 24 .

[0192] The 25th path (24th path in the figure) can be used to obtain the sum value S 25 The twenty-fifth path includes a circuit structure S01 (hereinafter referred to as S01-25, represented by 1-25 in the figure), a circuit structure S03 (hereinafter referred to as S03-24, represented by 3-24 in the figure), and a circuit structure S04 (hereinafter referred to as S4-25, represented by 4-25 in the figure) connected in sequence. The circuit structure S01-25 is used to calculate G 24 and P 24 , circuit structure S03-24 is used to calculate G 24:0 , circuit structure S04-25 is used to calculate S 25 Among them, the expression of circuit structure S01-25 is: G 24 =a 24 b 24 , The input of circuit structure S01-25 is a 24 and b 24 , the output is G 24 and P 24 The expression of circuit structure S03-24 is: G 24:0 =(P 24 ·G 23:0 )|G 24 , the circuit structure S03-24 is connected to the circuit structure S01-25 to obtain G 24 and P 24 The circuit structure S03-24 is also connected to the twenty-fourth circuit structure S03-23 ​​to obtain G 23:0 , the output of circuit structure S03-24 is G 24:0 The expression of circuit structure S04-25 is: S 25 =P 25 ·G 24:0 , the circuit structure S04-25 is connected to the circuit structure S03-24 to obtain G 24:0 The circuit structure S04-25 is also connected to the circuit structure S01-26 of the next path (the 26th path) to obtain P 25 , the output of circuit structure S04-25 is S 25 .

[0193] The 26th path (25th path in the figure) can be used to obtain the sum value S 26The twenty-sixth path includes a circuit structure S01 (hereinafter referred to as S01-26, represented by 1-26 in the figure), two circuit structures S02 (including circuit structure S02-21 and circuit structure S02-22, represented by 2-21 and 2-22 in the figure), a circuit structure S03 (hereinafter referred to as S03-25, represented by 3-25 in the figure), and a circuit structure S04 (hereinafter referred to as S4-26, represented by 4-26 in the figure) connected in sequence. The circuit structure S01-26 is used to calculate G 25 and P 25 , circuit structure S02-21 is used to calculate P 25:24 and G 25:24 , circuit structure S02-22 is used to calculate P 25:16 and G 25:16 , circuit structure S03-25 is used to calculate G 25:0 , circuit structure S04-26 is used to calculate S 26 Among them, the circuit structure S01-26 is expressed as: G 25 =a 25 b 25 , The input of circuit structure S01-26 is a 25 and b 25 , the output is G 25 and P 25 The expression of circuit structure S02-21 is P 25:24 =P 25 ·P 24 , G 25:24 =(P 25 ·G 24 )|G 25 , the circuit structure S02-21 is connected to the circuit structure S01-26, for obtaining G 25 and P 25 The circuit structure S02-21 is also connected to the twenty-fifth circuit structure S01-25 to obtain G 24 and P 24 , the output of circuit structure S02-21 is G 25:24 and P 25:24 The expression of circuit structure S02-22 is P 25:16 =P 25:24 ·P 23:16 , G 25:16 =(P 25:24 ·G 23:16 )|G 25:24 , the circuit structure S02-22 is connected to the circuit structure S02-21 to obtain G 25:24 and P 25:24The circuit structure S02-22 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-22 is G 25:16 and P 25:16 The expression of circuit structure S03-25 is G 25:0 =(P 25:16 ·G 15:0 )|G 25:16 , the circuit structure S03-25 is connected to the circuit structure S02-22 to obtain G 25:16 and P 25:16 The circuit structure S03-25 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-25 is G 25:0 The expression of circuit structure S04-26 is: S 26 =P 26 ·G 25:0 , the circuit structure S04-26 is connected to the circuit structure S03-25 to obtain G 25:0 The circuit structure S04-26 is also connected to the circuit structure S01-27 of the next path (the 27th path) to obtain P 26 The output of the circuit structure S04-26 is S 26 .

[0194] The 27th path (26th path in the figure) can be used to obtain the sum value S 27 The twenty-seventh path includes a circuit structure S01 (hereinafter referred to as S01-27, represented by 1-27 in the figure), a circuit structure S03 (hereinafter referred to as S03-26, represented by 3-26 in the figure), and a circuit structure S04 (hereinafter referred to as S4-27, represented by 4-27 in the figure) connected in sequence. The circuit structure S01-27 is used to calculate G 26 and P 26 , circuit structure S03-26 is used to calculate G 26:0 , circuit structure S04-27 is used to calculate S 27 Among them, the expression of circuit structure S01-27 is: G 26 =a 26 b 26 , The input of circuit structure S01-27 is a 26 and b 26 , the output is G 26 and P 26 The expression of circuit structure S03-26 is: G 26:0 =(P 26 ·G 25:0 )|G26 , the circuit structure S03-26 is connected to the circuit structure S01-27 to obtain G 26 and P 26 The circuit structure S03-26 is also connected to the twenty-sixth circuit structure S03-25 to obtain G 25:0 , the output of circuit structure S03-26 is G 26:0 The expression of circuit structure S04-27 is: S 27 =P 27 ·G 26:0 , the circuit structure S04-27 is connected to the circuit structure S03-26 to obtain G 26:0 The circuit structure S04-27 is also connected to the circuit structure S01-28 of the next path (the 28th path) to obtain P 27 , the output of circuit structure S04-27 is S 27 .

[0195] The 28th path (27th path in the figure) can be used to obtain the sum value S 28 The twenty-eighth path includes a circuit structure S01 (hereinafter referred to as S01-28, represented by 1-28 in the figure), three circuit structures S02 (including circuit structure S02-23, circuit structure S02-24 and circuit structure 2-25, represented by 2-23, 2-24 and 2-25 in the figure), a circuit structure S03 (hereinafter referred to as S03-27, represented by 3-27 in the figure) and a circuit structure S04 (hereinafter referred to as S4-28, represented by 4-28 in the figure). Circuit structure S01-28 is used to calculate G 27 and P 27 , circuit structure S02-23 is used to calculate P 27:26 and G 27:26 , circuit structure S02-24 is used to calculate P 27:24 and G 27:24 , circuit structure S02-25 is used to calculate P 27:16 and G 27:16 , circuit structure S03-27 is used to calculate G 27:0 , circuit structure S04-28 is used to calculate S 28 Among them, the expression of circuit structure S01-28 is: G 27 =a 27 b 27 , The input of circuit structure S01-28 is a 27 and b 27 , the output is G 27 and P 27 The expression of circuit structure S02-23 is P 27:26 =P 27·P 26 , G 27:26 =(P 27 ·G 26 )|G 27 , the circuit structure S02-23 is connected to the circuit structure S01-28 to obtain G 27 and P 27 The circuit structure S02-23 is also connected to the twenty-seventh circuit structure S01-27 to obtain G 26 and P 26 , the output of circuit structure S02-23 is G 27:26 and P 27:26 The expression of circuit structure S02-24 is P 27:24 =P 27:26 ·P 25:24 , G 27:24 =(P 27:26 ·G 25:24 )|G 27:26 , the circuit structure S02-24 is connected to the circuit structure S02-23 to obtain G 27:26 and P 27:26 The circuit structure S02-24 is also connected to the twenty-sixth circuit structure S02-21 to obtain G 25:24 and P 25:24 , the output of circuit structure S02-24 is G 27:24 and P 27:24 The expression of circuit structure S02-25 is P 27:16 =P 27:24 ·P 23:16 , G 27:16 =(P 27:24 ·G 23:16 )|G 27:24 , the circuit structure S02-25 is connected to the circuit structure S02-24 to obtain G 27:24 and P 27:24 The circuit structure S02-25 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-25 is G 27:16 and P 27:16 The expression of circuit structure S03-27 is G 27:0 =(P 27:16 ·G 15:0 )|G 27:16 , the circuit structure S03-27 is connected to the circuit structure S02-25 to obtain G 27:16 and P 27:16 , the circuit structure S03-27 is also connected to the circuit structure S03-15 of the sixteenth path, for obtaining G15:0 , the output of circuit structure S03-27 is G 27:0 The expression of circuit structure S04-28 is: S 28 =P 28 ·G 27:0 , the circuit structure S04-28 is connected to the circuit structure S03-27 to obtain G 27:0 The circuit structure S04-28 is also connected to the circuit structure S01-29 of the next path (the 29th path) to obtain P 28 , the output of the circuit structure S04-28 is S 28 .

[0196] The 29th path (28th path in the figure) can be used to obtain the sum value S 29 The 29th path includes a circuit structure S01 (hereinafter referred to as S01-29, represented by 1-29 in the figure), a circuit structure S03 (hereinafter referred to as S03-28, represented by 3-28 in the figure), and a circuit structure S04 (hereinafter referred to as S4-29, represented by 4-29 in the figure) connected in sequence. The circuit structure S01-29 is used to calculate G 28 and P 28 , circuit structure S03-28 is used to calculate G 28:0 , circuit structure S04-29 is used to calculate S 29 Among them, the expression of circuit structure S01-29 is: G 28 =a 28 b 28 , The input of circuit structure S01-29 is a 28 and b 28 , the output is G 28 and P 28 The expression of circuit structure S03-28 is: G 28:0 =(P 28 ·G 27:0 )|G 28 , the circuit structure S03-28 is connected to the circuit structure S01-29 to obtain G 28 and P 28 The circuit structure S03-28 is also connected to the twenty-eighth circuit structure S03-27 to obtain G 27:0 , the output of circuit structure S03-28 is G 28:0 The expression of circuit structure S04-29 is: S 29 =P 29 ·G 28:0 , the circuit structure S04-29 is connected to the circuit structure S03-28 to obtain G 28:0The circuit structure S04-29 is also connected to the circuit structure S01-30 of the next path (the 30th path) to obtain P 29 , the output of circuit structure S04-29 is S 29 .

[0197] The 30th path (29th path in the figure) can be used to obtain the sum value S 30 The 30th path includes a circuit structure S01 (hereinafter referred to as S01-30, represented by 1-30 in the figure), three circuit structures S02 (including circuit structure S02-26, circuit structure S02-27 and circuit structure 2-28, represented by 2-26, 2-27 and 2-28 in the figure), a circuit structure S03 (hereinafter referred to as S03-29, represented by 3-29 in the figure) and a circuit structure S04 (hereinafter referred to as S4-30, represented by 4-30 in the figure). The circuit structure S01-30 is used to calculate G 29 and P 29 , circuit structure S02-26 is used to calculate P 29:28 and G 29:28 , circuit structure S02-27 is used to calculate P 29:24 and G 29:24 , circuit structure S02-28 is used to calculate P 29:16 and G 29:16 , circuit structure S03-29 is used to calculate G 29:0 , circuit structure S04-30 is used to calculate S 30 Among them, the expression of circuit structure S01-30 is: G 29 =a 29 b 29 , The input of circuit structure S01-30 is a 29 and b 29 , the output is G 29 and P 29 The expression of circuit structure S02-26 is P 29:28 =P 29 ·P 28 , G 29:28 =(P 29 ·G 28 )|G 29 , the circuit structure S02-26 is connected to the circuit structure S01-30 to obtain G 29 and P 29 , the circuit structure S02-26 is also connected to the twenty-ninth circuit structure S01-29, for obtaining G 28 and P 28 , the output of circuit structure S02-26 is G 29:28 and P 29:28The expression of circuit structure S02-27 is P 29:24 =P 29:28 ·P 27:24 , G 29:24 =(P 29:28 ·G 27:24 )|G 29:28 , the circuit structure S02-27 is connected to the circuit structure S02-26 to obtain G 29:28 and P 29:28 The circuit structure S02-27 is also connected to the twenty-eighth circuit structure S02-24 to obtain G 27:24 and P 27:24 , the output of circuit structure S02-27 is G 29:24 and P 29:24 The expression of circuit structure S02-28 is P 29:16 =P 29:24 ·P 23:16 , G 29:16 =(P 29:24 ·G 23:16 )|G 29:24 , the circuit structure S02-28 is connected to the circuit structure S02-27 to obtain G 29:24 and P 29:24 The circuit structure S02-28 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-28 is G 29:16 and P 29:16 The expression of circuit structure S03-29 is G 29:0 =(P 29:16 ·G 15:0 )|G 29:16 , the circuit structure S03-29 is connected to the circuit structure S02-28 to obtain G 29:16 and P 29:16 The circuit structure S03-29 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output of circuit structure S03-29 is G 29:0 The expression of circuit structure S04-30 is: S 30 =P 30 ·G 29:0 , the circuit structure S04-30 is connected to the circuit structure S03-29 to obtain G 29:0 The circuit structure S04-30 is also connected to the circuit structure S01-31 of the next path (the 31st path) to obtain P 30 , the output of the circuit structure S04-30 is S 30 .

[0198] The 31st path (30th path in the figure) can be used to obtain the sum value S 31 The thirty-first path includes a circuit structure S01 (hereinafter referred to as S01-31, represented by 1-31 in the figure), a circuit structure S03 (hereinafter referred to as S03-30, represented by 3-30 in the figure), and a circuit structure S04 (hereinafter referred to as S4-31, represented by 4-31 in the figure) connected in sequence. The circuit structure S01-31 is used to calculate G 30 and P 30 , circuit structure S03-30 is used to calculate G 30:0 , circuit structure S04-31 is used to calculate S 31 Among them, the expression of circuit structure S01-31 is: G 30 =a 30 b 30 , The input of circuit structure S01-31 is a 30 and b 30 , the output is G 30 and P 30 The expression of circuit structure S03-30 is: G 30:0 =(P 30 ·G 29:0 )|G 30 , the circuit structure S03-30 is connected to the circuit structure S01-31 to obtain G 30 and P 30 The circuit structure S03-30 is also connected to the 30th circuit structure S03-29 to obtain G 29:0 , the output of circuit structure S03-30 is G 30:0 The expression of circuit structure S04-31 is: S 31 =P 31 ·G 30:0 , the circuit structure S04-31 is connected to the circuit structure S03-30 to obtain G 30:0 The circuit structure S04-31 is also connected to the circuit structure S01-32 of the next path (the 32nd path) to obtain P 31 , the output of circuit structure S04-31 is S 31 .

[0199] The 32nd route (31st route in the figure) can be used to obtain P 31 The 32nd path includes a circuit structure S01 (hereinafter referred to as S01-32, represented by 1-32 in the figure). The circuit structure S01-32 is used to calculate G 31 and P 31 The expression of circuit structure S01-32 is: G 31 =a 31 b31 , The input of circuit structure S01-32 is a 31 and b 31 , the output is G 31 and P 31 .

[0200] In this embodiment, in order to realize a (2^5)-bit, i.e., a 32-bit adder excluding carry, a total of 2^5=32 circuit structures S01, (2^4-1)+(2^3-1)*3-2^3=28 circuit structures S02, (2^5)-2=30 circuit structures S03, and (2^5)-1=31 circuit structures S04 are required, for a total of 32+28+30+31=121 circuit structures. As shown in Figure 9, the maximum logic depth of the adder structure in this example is 8 levels, and the longest data path includes 1 circuit structure S01, 4 circuit structures S02, 2 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 3 circuit structures S02, 3 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 5 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 6 circuit structures S03 and 1 circuit structure S04.

[0201] In this embodiment, the reuse of three types of circuit structures and the reuse of two types of circuit structures are adopted. By designing circuit structures S02-20 and S02-17 to reuse the calculation results of circuit structure S02-15, circuit structures S02-12 and S02-9 to reuse the calculation results of circuit structure S02-7, circuit structures S02-28, S02-25 and S02-22 to reuse the calculation results of circuit structure S02-20, and circuit structure S03-7 to reuse the calculation results of circuit structure S02-7. The calculation results of circuit structure S03-3 are multiplexed with S03-5; the calculation results of circuit structure S03-7 are multiplexed with circuit structures S03-15, S03-13, S03-11, and S03-9; and the calculation results of circuit structure S03-15 are multiplexed with circuit structures S03-29, S03-27, S03-25, S03-23, S03-21, S03-19, and S03-17. This reduces the number of circuit structures. This embodiment uses four circuit structures to implement a 32-bit adder without carry. Only 121 circuit structures are required to implement an adder with a logic depth of 8 levels, achieving a balance between low power consumption, high speed, and small area.

[0202] The following example illustrates the topology of a 32-bit unsigned integer adder with carry built using the above circuit structures S01-S04. The expression of the adder is: {carry,sum[31:0]}=a[31:0]+b[31:0], where carry represents carry and sum represents sum. As shown in Figure 10, the adder includes 32 inputs and 33 outputs. In the figure, 0-31 represent inputs 0-31 (0-31 bits), each input includes a and b. In the figure, S0-S 31 The following describes the 16-bit unsigned integer adder including carry provided in this embodiment.

[0203] The topology of the first to thirty-first paths is the same as that of the 32-bit unsigned integer adder excluding carry in FIG9 , and will not be described again here.

[0204] The 32nd path (31st path in the figure) can be used to obtain the carry value. The 32nd path includes a circuit structure S01 (hereinafter referred to as S01-32, represented by 1-32 in the figure), four circuit structures S02 (including circuit structure S02-29, circuit structure S02-30, circuit structure S02-31 and circuit structure 2-32, represented by 2-29, 2-30, 2-31 and 2-32 in the figure) and a circuit structure S03 (hereinafter referred to as S03-31, represented by 3-31 in the figure). The circuit structure S01-32 is used to calculate G 31 and P 31 , circuit structure S02-29 is used to calculate P 31:30 and G 31:30 , circuit structure S02-30 is used to calculate P 31:28 and G 31:28 , circuit structure S02-31 is used to calculate P 31:24 and G 31:24 , circuit structure S02-32 is used to calculate P 31:16 and G 31:16 , circuit structure S03-31 is used to calculate G 31:0 Among them, the expression of circuit structure S01-32 is: G 31 =a 31 b 31 , The input of circuit structure S01-32 is a 31 and b 31 , the output is G 31 and P 31 The expression of circuit structure S02-29 is P 31:30 =P 31 ·P 30 , G31:30 =(P 31 ·G 30 )|G 31 , the circuit structure S02-29 is connected to the circuit structure S01-32 to obtain G 31 and P 31 The circuit structure S02-29 is also connected to the thirty-first circuit structure S01-31 to obtain G 30 and P 30 , the output of circuit structure S02-29 is G 31:30 and P 31:30 The expression of circuit structure S02-30 is P 31:28 =P 31:30 ·P 29:28 , G 31:28 =(P 31:30 ·G 29:28 )|G 31:30 , the circuit structure S02-30 is connected to the circuit structure S02-29 to obtain G 31:30 and P 31:30 The circuit structure S02-30 is also connected to the 30th circuit structure S02-26 to obtain G 29:28 and P 29:28 , the output of circuit structure S02-30 is G 31:28 and P 31:28 The expression of circuit structure S02-31 is P 31:24 =P 31:28 ·P 27:24 , G 31:24 =(P 31:28 ·G 27:24 )|G 31:28 , the circuit structure S02-31 is connected to the circuit structure S02-30 to obtain G 31:28 and P 31:28 The circuit structure S02-31 is also connected to the twenty-eighth circuit structure S02-24 to obtain G 27:24 and P 27:24 , the output of circuit structure S02-31 is G 31:24 and P 31:24 The expression of circuit structure S02-32 is P 31:16 =P 31:24 ·P 23:16 , G 31:16 =(P 31:24 ·G 23:16 )|G 31:16 , the circuit structure S02-32 is connected to the circuit structure S02-31 to obtain G 31:24 and P 31:24The circuit structure S02-32 is also connected to the twenty-fourth circuit structure S02-20 to obtain G 23:16 and P 23:16 , the output of circuit structure S02-32 is G 31:16 and P 31:16 The expression of circuit structure S03-31 is G 31:0 =(P 31:16 ·G 15:0 )|G 31:16 , the circuit structure S03-31 is connected to the circuit structure S02-32 to obtain G 31:16 and P 31:16 The circuit structure S03-32 is also connected to the circuit structure S03-15 of the sixteenth path to obtain G 15:0 , the output G of circuit structure S03-31 31:0 This is the carry result.

[0205] In this embodiment, to implement a (2^5)-bit, i.e., a 32-bit adder including carry, a total of 2^5=32 circuit structures S01, (2^4-1)+(2^3-1)*3-2^3+4=32 circuit structures S02, (2^5)-1=31 circuit structures S03, and (2^5)-1=31 circuit structures S04 are required, for a total of 32+32+31+31=126 circuit structures, which is 5 more circuit structures than a 32-bit adder excluding carry. As shown in Figure 10, the maximum logic depth of the adder structure in this example is still 8 levels, and the longest data path includes 1 circuit structure S01, 4 circuit structures S02, 2 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 3 circuit structures S02, 3 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 5 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 6 circuit structures S03 and 1 circuit structure S04.

[0206] In this embodiment, the multiplexing of three types of circuit structures and the multiplexing of two types of circuit structures are adopted. By designing circuit structures S02-31 and S02-27 to multiplex the calculation results of circuit structure S02-24, circuit structures S02-20 and S02-17 to multiplex the calculation results of circuit structure S02-15, circuit structures S02-12 and S02-9 to multiplex the calculation results of circuit structure S02-7, and circuit structures S02-32, S02-28, S02-25 and S02-22 to multiplex the calculation results of circuit structure S02-24. The calculation results for circuit structures S03-20 are shown in Figure 1. Circuit structures S03-7 and S03-5 reuse the calculation results for circuit structure S03-3; circuit structures S03-15, S03-13, S03-11, and S03-9 reuse the calculation results for circuit structure S03-7; and circuit structures S03-31, S03-29, S03-27, S03-25, S03-23, S03-21, S03-19, and S03-17 reuse the calculation results for circuit structure S03-15. This reduces the number of circuit structures. This embodiment uses four circuit structures to implement a 32-bit adder with carry bits. Only 126 circuit structures are required to implement an adder with a logic depth of 8 levels, achieving a balance between low power consumption, high speed, and small area.

[0207] The following example illustrates the topology of a 64-bit unsigned integer, carry-free adder built using the above circuit structures S01-S04. The expression of the adder is: sum[63:0]=a[63:0]+b[63:0], where sum represents summation. As shown in Figures 11A and 11B, the adder includes 64 inputs and 64 outputs. In the figure, 0-63 represent inputs 0-63 (0-63 bits), respectively. Each input includes a and b. For example, input 0 represents a0 and b0, input 1 represents a1 and b1, and so on. S0-S04 in the figure represent inputs 0-63 (0-63 bits). 63 For the sake of convenience, subscripts are not used to represent numbers in the figure.

[0208] The first to thirty-first paths have the same topology as the 32-bit unsigned integer adder without carry in FIG9 . The circuit structures used in the thirty-second to sixty-fourth paths and the connection relationships between the circuit structures can be seen in FIG11A and FIG11B , and will not be repeated here.

[0209] In this embodiment, in order to realize a (2^6)-bit, i.e., a 64-bit adder excluding carry, a total of 2^6=64 circuit structures S01, (2^5-1)+(2^4-1)*3-2^3=68 circuit structures S02, (2^6)-2=62 circuit structures S03, (2^6)-1=63 circuit structures S04, and a total of 64+68+62+63=257 circuit structures are required. As shown in Figures 11A and 11B, the maximum logic depth of the adder structure in this example is 10 levels, and the longest data path includes 1 circuit structure S01, 4 circuit structures S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 3 circuit structures S02, 5 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 6 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 7 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 8 circuit structures S03 and 1 circuit structure S04.

[0210] In this embodiment, three types of circuit structures are reused, along with two types of circuit structures. By designing and reusing circuit structure calculation results, the number of circuit structures is reduced. The circuit structures whose calculation results are reused include S02-7, S02-15, S02-24, S02-35, S02-44, S02-55, S02-64, S03-3, S03-7, S03-15, S03-31, and S03-47. The reused circuit structures are shown in Figures 11A and 11B. This embodiment uses four circuit structures to implement a 64-bit carry-free adder. Only 257 circuit structures are required to implement an adder with a logic depth of 10 levels, achieving a balance between low power consumption, high speed, and small area.

[0211] The following example illustrates the topology of a 64-bit unsigned integer adder with carry built using the above circuit structures S01-S04. The expression of the adder is: {carry,sum[63:0]}=a[63:0]+b[63:0], where carry represents carry and sum represents sum. As shown in Figures 12A and 12B, the adder includes 64 inputs and 65 outputs. In the figure, 0-63 represent inputs 0-63 (0-63 bits), each input includes a and b. In the figure, S0-S 63 The following describes a 64-bit unsigned integer adder including carry provided in this embodiment.

[0212] The first to thirty-first paths have the same topology as the 32-bit unsigned integer adder without carry in FIG11A . The circuit structures used in the thirty-second to sixty-fourth paths and the connection relationships between the circuit structures can be found in FIG12A and FIG12B and will not be repeated here.

[0213] In this embodiment, to implement a (2^6)-bit, i.e., a 64-bit adder including carry, a total of 2^6=64 circuit structures S01, (2^5-1)+(2^4-1)*3-2^3+4=72 circuit structures S02, (2^6)-1=63 circuit structures S03, and (2^6)-1=63 circuit structures S04 are required, for a total of 64+72+63+63=262 circuit structures, which is 5 more circuit structures than a 64-bit adder excluding carry. As shown in Figures 12A and 12B, the maximum logic depth of the adder structure in this example is still 10 levels, and the longest data path includes 1 circuit structure S01, 4 circuit structures S02, 4 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 3 circuit structures S02, 5 circuit structures S03 and one circuit structure S04, or includes 1 circuit structure S01, 2 circuit structures S02, 6 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 1 circuit structure S02, 7 circuit structures S03 and 1 circuit structure S04, or includes 1 circuit structure S01, 8 circuit structures S03 and 1 circuit structure S04.

[0214] In this embodiment, three types of circuit structures are reused, along with two types of circuit structures. By designing and reusing circuit structure calculation results, the number of circuit structures is reduced. The circuit structures whose calculation results are reused include S02-7, S02-15, S02-24, S02-35, S02-44, S02-55, S02-64, S03-3, S03-7, S03-15, S03-31, and S03-47. The reused circuit structures are shown in Figures 12A and 12B. This embodiment uses four circuit structures to implement a 64-bit adder with carry bits. Only 262 circuit structures are required to implement an adder with a logic depth of 10 levels, achieving a balance between low power consumption, high speed, and small area.

[0215] It can be clearly seen from the above embodiments that the reuse of calculation results of the circuit structure can greatly reduce power consumption and achieve a balance between low power consumption, high speed and small area. The above description is made by taking an adder including a type 1 circuit structure, a type 2 circuit structure, a type 3 circuit structure and a type 4 circuit structure as an example. In other embodiments, the circuit structure can be replaced as needed and the embodiment of the present disclosure can still be used. The embodiment of the present disclosure also provides an adder circuit structure for implementing the addition operation of 2^n bits of data, where n is a positive integer greater than or equal to 3, and the adder circuit structure includes 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, and one or more circuit structures for logical calculations are provided on each path from the input terminal to the output terminal; wherein,

[0216] In every eight adjacent vertical paths, an input end of the fourth circuit structure in the eighth vertical path and an input end of the third circuit structure in the sixth vertical path are both connected to the output end of the third circuit structure in the fourth vertical path. The vertical path is a path from the i-th input end to the i+1-th output end.

[0217] In an exemplary embodiment, in every 16 adjacent vertical paths, an input end of the fifth circuit structure in the sixteenth vertical path, an input end of the fourth circuit structure in the fourteenth vertical path, an input end of the fourth circuit structure in the twelfth vertical path, and an input end of the third circuit structure in the tenth vertical path are all connected to the output end of the fourth circuit structure in the eighth vertical path.

[0218] In an exemplary embodiment, in every 32 adjacent vertical pathways, an input end of the sixth circuit structure in the thirty-second vertical pathway, an input end of the fifth circuit structure in the thirtieth vertical pathway, an input end of the fifth circuit structure in the twenty-eighth vertical pathway, an input end of the fourth circuit structure in the twenty-sixth vertical pathway, an input end of the fifth circuit structure in the twenty-fourth vertical pathway, an input end of the fourth circuit structure in the twenty-second vertical pathway, an input end of the fourth circuit structure in the twentieth vertical pathway, and an input end of the third circuit structure in the eighteenth vertical pathway are all connected to the output end of the fifth circuit structure in the sixteenth vertical pathway.

[0219] By connecting the input ends of multiple circuit structures to the output end of the same circuit structure, the calculation results of the circuit structures are reused, thereby reducing the number of circuit structures, reducing the power consumption of the adder, and reducing the area occupied by the overall topology structure.

[0220] A 32-bit carry-less KSA (Kogge Stone Adder) adder uses a total of 187 circuit structures, with a maximum logic depth of 7 levels. In contrast, the 32-bit carry-less adder in the disclosed embodiment uses only 121 circuit structures, with a maximum logic depth of 8 levels. Although the maximum logic depth increases by one level, 66 circuit structures are reduced, significantly reducing power consumption.

[0221] As can be seen, the adder circuit structure provided by the embodiments of the present disclosure has a relatively smaller overall circuit area. Since circuit area is directly proportional to power consumption, the adder circuit structure provided by the embodiments of the present disclosure has relatively lower power consumption. In practical applications, this adder can achieve a better balance between operating speed and power consumption.

[0222] An embodiment of the present disclosure further provides a processor, which may include the adder in any of the above embodiments.

[0223] The above are only preferred embodiments of the present disclosure and the technical principles used. Those skilled in the art will understand that the present disclosure is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of this application. Therefore, although the present disclosure has been described in more detail through the above embodiments, the present disclosure is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present disclosure, and the scope of the present disclosure is determined by the scope of the appended claims.

Claims

1. An adder circuit structure for implementing an addition operation of 2^n-bit data, where n is a positive integer greater than or equal to 3, the adder comprising: At least 2^n first-class circuit structures, at least 2 second-class circuit structures, at least 2^n-2 third-class circuit structures, and at least 2^n-1 fourth-class circuit structures, wherein: The circuit structure is configured to receive the i-th bit of the input first data and the i-th bit of the second data, 0≥i≥2^n, and output the G logic result and the P logic result of the i-th bit; The second type of circuit structure is configured to receive the G logic result and the P logic result, and output a G logic result sub-combination and a P logic result sub-combination; The three types of circuit structures are configured to receive the G logic result and the P logic result or receive the G logic result sub-combination and the P logic result sub-combination, and output a new G logic result sub-combination; The four types of circuit structures are configured to receive the P logic result and the G logic result or receive the P logic result and the new G logic result sub-combination, and output a sum value; In the adder circuit structure, two or more of the two-type circuit structures reuse the calculation result of one two-type circuit structure, or two or more of the three-type circuit structures reuse the calculation result of one three-type circuit structure.

2. The adder circuit structure according to claim 1, wherein: The adder circuit structure includes 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, the path from the ith input terminal to the (i+1)th output terminal is a vertical path, and one or more of the first type of circuit structure, the second type of circuit structure, the third type of circuit structure and the fourth type of circuit structure are arranged on each path from the input terminal to the output terminal; In every eight adjacent vertical paths, the fourth circuit structure in the eighth vertical path and the third circuit structure in the sixth vertical path reuse the calculation result of the third circuit structure in the fourth vertical path.

3. The adder circuit structure according to claim 2, wherein: The fourth circuit structure in the eighth longitudinal path, the third circuit structure in the sixth longitudinal path, and the third circuit structure in the fourth longitudinal path are all type II circuit structures or type III circuit structures.

4. The adder circuit structure according to claim 1 or 2, wherein: In every 16 adjacent vertical paths, the fifth circuit structure in the sixteenth vertical path, the fourth circuit structure in the fourteenth vertical path, the fourth circuit structure in the twelfth vertical path, and the third circuit structure in the tenth vertical path reuse the calculation results of the fourth circuit structure in the eighth vertical path.

5. The adder circuit structure according to claim 4, wherein: The fifth circuit structure in the sixteenth longitudinal path, the fourth circuit structure in the fourteenth longitudinal path, the fourth circuit structure in the twelfth longitudinal path, the third circuit structure in the tenth longitudinal path, and the fourth circuit structure in the eighth longitudinal path are all three types of circuit structures.

6. The adder circuit structure according to claim 4, wherein: In every 32 adjacent vertical paths, the sixth circuit structure in the thirty-second vertical path, the fifth circuit structure in the thirtieth vertical path, the fifth circuit structure in the twenty-eighth vertical path, the fourth circuit structure in the twenty-sixth vertical path, the fifth circuit structure in the twenty-fourth vertical path, the fourth circuit structure in the twenty-second vertical path, the fourth circuit structure in the twentieth vertical path, and the third circuit structure in the eighteenth vertical path reuse the calculation results of the fifth circuit structure in the sixteenth vertical path.

7. The adder circuit structure according to claim 6, wherein: The sixth circuit structure in the thirty-second longitudinal pathway, the fifth circuit structure in the thirtieth longitudinal pathway, the fifth circuit structure in the twenty-eighth longitudinal pathway, the fourth circuit structure in the twenty-sixth longitudinal pathway, the fifth circuit structure in the twenty-fourth longitudinal pathway, the fourth circuit structure in the twenty-second longitudinal pathway, the fourth circuit structure in the twentieth longitudinal pathway, the third circuit structure in the eighteenth longitudinal pathway, and the fifth circuit structure in the sixteenth longitudinal pathway are all three types of circuit structures.

8. The adder circuit structure according to claim 1, wherein: The adder circuit structure includes at least 2^n vertical paths, and the vertical paths are used to receive the i-th bit data of the first data and the second data, and output the i+1-th bit sum value, wherein the vertical path for receiving the k-th bit data of the first data and the second data includes a first-class circuit structure, a third-class circuit structure and a fourth-class circuit structure, k is an even number other than 0 in i, and the first-class circuit structure is used to receive the k-th bit data of the first data and the second data, and the output end of the first-class circuit structure is connected to the input end of the third-class circuit structure, and the input end of the third-class circuit structure is also connected to the output end of the first-class circuit structure for receiving the k-1-th bit data of the first data and the second data in the previous vertical path, and the output end of the third-class circuit structure is connected to the input end of the fourth-class circuit structure, and the input end of the fourth-class circuit structure is also connected to the output end of the first-class circuit structure for receiving the k+1-th bit data of the first data and the k+1-th bit data of the second data in the next vertical path, and the fourth-class circuit structure outputs the k+1-th bit sum value.

9. The adder circuit structure according to claim 1, wherein: The vertical path receiving the k+1th bit of data in the first data and the second data in the adder circuit structure includes a first-class circuit structure, at least a second-class circuit structure, a third-class circuit structure and a fourth-class circuit structure, and k is an even number other than 0 in i; The first type of circuit structure is used to receive the k-th bit of data in the first data and the second data. The output end of the first type of circuit structure is connected to the input end of the first type of circuit structure. The input end of the first type of circuit structure is also connected to the output end of the first type of circuit structure in the previous longitudinal path for receiving the k-th bit of data in the first data and the second data. The output end of the last type of circuit structure is connected to the input end of the third type of circuit structure. The input end of the third type of circuit structure is also connected to the output end of the third type of circuit structure in the previous even-numbered longitudinal path. The output end of the third type of circuit structure is connected to the input end of the fourth type of circuit structure. The input end of the fourth type of circuit structure is also connected to the output end of the first type of circuit structure in the next longitudinal path for receiving the k+2-th bit of data in the first data and the second data. The fourth type of circuit structure outputs the sum value of the k+2-th bit.

10. The adder circuit structure according to claim 1 or 8 or 9, wherein: The first vertical path in the adder circuit structure is used to receive the data of the i-th bit of the first data and the second data, i=0, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a first-class circuit structure and a fourth-class circuit structure. The first-class circuit structure is used to receive the data of the 0th bit of the first data and the second data, and output the G logic result and the P logic result of the 0th bit. The output end of one type of circuit structure is connected to the input end of the four types of circuit structures, and the input end of the four types of circuit structures is also connected to the output end of a type of circuit structure in the subsequent vertical path for receiving the first bit of data in the first data and the second data. The four types of circuit structures output the sum of the first bit, and the P logic result of the 0th bit output by the one type of circuit structure is the sum of the 0th bit.

11. The adder circuit structure according to claim 1 or 8 or 9, wherein: The second vertical path in the adder circuit structure is used to receive the i-th bit of the first data and the second data, i=1, and output the sum of the i-th bit and the i+1-th bit. The first vertical path includes a type-one circuit structure, a type-three circuit structure and a type-four circuit structure. The type-one circuit structure is used to receive the first bit of the first data and the second data. The output end of the type-one circuit structure is connected to the input end of the type-three circuit structure. The input end of the type-three circuit structure is also connected to the output end of the type-one circuit structure in the previous vertical path for receiving the 0th bit of the first data and the second data. The output end of the type-three circuit structure is connected to the input end of the type-four circuit structure. The input end of the type-four circuit structure is also connected to the output end of the type-one circuit structure in the next vertical path for receiving the second bit of the first data and the second data. The type-four circuit structure outputs the sum of the second bit.

12. The adder circuit structure according to claim 1, wherein: The 2^nth vertical path is used as a path for obtaining a carry value, and the path includes a first-class circuit structure, at least two second-class circuit structures, a third-class circuit structure and a fourth-class circuit structure, wherein: The first type of circuit structure is used to receive the 2^n-1th bit of data in the first data and the second data, and the output end of the first type of circuit structure is connected to the input end of a second type of circuit structure. The at least two type-two circuit structures are connected in sequence, wherein the input end of the first type-two circuit structure is connected to the output end of the type-one circuit structure in addition to being connected to the output end of the type-one circuit structure, and is also connected to the output end of the type-one circuit structure in the previous longitudinal path for receiving the 2^n-2th bit of the first data and the second data, the output end of the first type-two circuit structure is connected to the input end of the type-three circuit structure, or is connected to the input end of the second type-two circuit structure, the input end of the second type-two circuit structure is also connected to the output end of the first type-two circuit structure in the second longitudinal path, the output end of the second type-two circuit structure is connected to the input end of the type-three circuit structure, or is connected to the input end of the third type-two circuit structure, the input end of the third type-two circuit structure is also connected to the output end of the second type-two circuit structure in the fourth longitudinal path, The output end, or the input end of the third type-II circuit structure is also connected to the output end of the third type-II circuit structure in the first eighth longitudinal path, and the output end of the third type-II circuit structure is connected to the input end of the one type-III circuit structure; The input end of the one of the three types of circuit structures is also connected to the output end of the three types of circuit structures in the first fourth longitudinal path, or the input end of the one of the three types of circuit structures is also connected to the output end of the three types of circuit structures in the first eighth longitudinal path, or the input end of the one of the three types of circuit structures is also connected to the output end of the three types of circuit structures in the first sixteenth longitudinal path, and the output end of the one of the three types of circuit structures is connected to the input end of the four types of circuit structures; The input ends of the four types of circuit structures are also connected to the output ends of a type of circuit structure in the next vertical path for receiving the 2^n+1th bit data in the first data and the second data, and the four types of circuit structures output carry values.

13. The adder circuit structure according to claim 1, wherein: When the data length of the first data and the second data is 2^n bits, and n=3, the adder includes 8 inputs and 8 summation outputs, and the adder includes 2^n first-class circuit structures, (2^(n-1)-1)*2 second-class circuit structures, (2^n)-2 third-class circuit structures, and (2^n)-1 fourth-class circuit structures; or the adder includes 8 inputs, 8 summation outputs, and 1 carry output, and the adder includes 2^n first-class circuit structures, (2^(n-1)-1)*2+2 second-class circuit structures, (2^n)-1 third-class circuit structures, and (2^n)-1 fourth-class circuit structures; When the data length of the first data and the second data is 2^n bits, and n=4, the adder includes 16 inputs and 16 summation outputs, and the adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3 second-class circuit structures, (2^n)-2 third-class circuit structures, and (2^n)-1 fourth-class circuit structures; or the adder includes 16 inputs, 16 summation outputs, and 1 carry output, and the adder includes 2^n=16 first-class circuit structures, (2^(n-2)-1)*3+3 second-class circuit structures, (2^n)-1 third-class circuit structures, and (2^n)-1 fourth-class circuit structures; When the data length of the first data and the second data is 2^n bits, and n=5, the adder includes 32 inputs and 32 sum outputs, the adder includes 2^n first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-2) second-class circuit structures, (2^n)-2 third-class circuit structures, and (2^n)-1 fourth-class circuit structures; or the adder includes 32 inputs, 32 sum outputs, and 1 carry output, the adder includes 2^n=32 first-class circuit structures, (2^(n-1) -1)+(2^(n-2)-1)*3-2^(n-2)+4 second-class circuit structures, (2^n)-1 third-class circuit structure and (2^n)-1 fourth-class circuit structure; When the data length of the first data and the second data is 2^n bits, and n=6, the adder includes 64 inputs and 64 summation outputs, and the adder includes (2^n) first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3) second-class circuit structures, (2^n)-2 third-class circuit structures and (2^n)-1 fourth-class circuit structures; or the adder includes 64 inputs, 64 summation outputs and 1 carry output, and the adder includes 2^n first-class circuit structures, (2^(n-1)-1)+(2^(n-2)-1)*3-2^(n-3)+4 second-class circuit structures, (2^n)-1 third-class circuit structures and (2^n)-1 fourth-class circuit structures.

14. An adder circuit structure, for implementing an addition operation of 2^n-bit data, where n is a positive integer greater than or equal to 3, the adder circuit structure comprising 2^n input terminals for inputting 2^n bits and at least 2^n output terminals, and one or more circuit structures for logic calculation are arranged on each path from the input terminal to the output terminal; In every 8 adjacent vertical paths, an input end of the fourth circuit structure in the eighth vertical path and an input end of the third circuit structure in the sixth vertical path are both connected to the output end of the third circuit structure in the fourth vertical path, and the vertical path is a path from the i-th input end to the i+1-th output end, 0≤i≤2^n.

15. The adder circuit structure according to claim 14, wherein: In every 16 adjacent vertical paths, an input end of the fifth circuit structure in the sixteenth vertical path, an input end of the fourth circuit structure in the fourteenth vertical path, an input end of the fourth circuit structure in the twelfth vertical path, and an input end of the third circuit structure in the tenth vertical path are all connected to the output end of the fourth circuit structure in the eighth vertical path.

16. The adder circuit structure according to claim 14, wherein: In every 32 adjacent vertical paths, an input end of the sixth circuit structure in the 32nd vertical path, an input end of the fifth circuit structure in the 30th vertical path, an input end of the fifth circuit structure in the 28th vertical path, an input end of the fourth circuit structure in the 26th vertical path, an input end of the fifth circuit structure in the 24th vertical path, an input end of the fourth circuit structure in the 22nd vertical path, an input end of the fourth circuit structure in the 20th vertical path, an input end of the fifth circuit structure in the 26th vertical path, an input end of the fifth circuit structure in the 24th vertical path, an input end of the fourth circuit structure in the 22nd vertical path, an input end of the fifth circuit structure in the 20th vertical path, an input end of the fifth circuit structure in the 25th vertical path, an input end of the fifth circuit structure in the 26 ... An input end of the fourth circuit structure in the eighteenth vertical path and an input end of the third circuit structure in the eighteenth vertical path are both connected to the output end of the fifth circuit structure in the sixteenth vertical path.

17. A processor, comprising: An adder circuit structure as described in any one of claims 1-13 or 14-16.

Images