Bonding method, wafer stack structure, and chip structure

Abstract

Provided in the present application are a bonding method, a wafer stack structure, and a chip structure. The bonding method comprises: providing at least one first wafer stack structure, and testing each chip region in the first wafer stack structure, wherein the first wafer stack structure comprises a plurality of first wafers which are bonded together; cutting the first wafer stack structure to form chips corresponding to the chip regions; and bonding the chips with a second wafer, wherein it has been determined during the test that the chips function properly. By means of the method, screening is performed to select a few chips, which have been determined to function properly in a test, and the chips are then bonded, such that a relatively high yield can be maintained regarding bonded multi-layer stack structures, performance can be realized, and loss can also be reduced.

Description

Bonding method, wafer stacking structure, and chip structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority based on Chinese patent application 2023111685105 filed on September 8, 2023, and all of its contents are incorporated herein by reference.

Technical field

[0003] The present invention relates to the technical field of semiconductor devices, and in particular to a bonding method, a wafer stacking structure, and a chip structure. [Background Technology]

[0004] With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology has been widely used, and chip structures are moving towards a three-dimensional direction. Specifically, the chip-to-wafer (C2W) stacking structure can realize different functions in one, improving performance, enhancing functionality, and reducing size.

[0005] The current C2W stacking structure involves sequentially bonding multiple wafers to form a multi-layer wafer bonded structure, which is then cut into corresponding chip structures. Since it is difficult to maintain a 100% yield during the stacking process, the yield of the bonded wafer stack gradually decreases as the number of wafer layers increases, resulting in increasing losses.

[0006] [Summary of the invention]

[0007] The present application provides a bonding method and a wafer stacking structure and a chip structure, which can not only realize multi-layer wafer or chip stacking, but also improve the yield of multi-layer wafer or chip stacking and reduce losses.

[0008] To address the above technical issues, the present application provides a first bonding method. The method comprises: providing at least one first wafer stack structure, testing each chip region in the first wafer stack structure; wherein the first wafer stack structure comprises at least two bonded first wafers; dicing the first wafer stack structure to form chips corresponding to the chip regions; and bonding the chips that have been tested to be functional to a second wafer.

[0009] Among them, providing at least one first wafer stacking structure and testing each chip area in the first wafer stacking structure includes: bonding at least two first wafers together in sequence to form the first wafer stacking structure; forming a test pad on the first surface of the first wafer stacking structure, the first surface being the outermost surface of the first wafer stacking structure perpendicular to the stacking direction; and testing the chip area in the first wafer stacking structure through the test pad to determine whether the corresponding chip area is functioning well.

[0010] Among them, the first wafer stacking structure includes a top wafer located at the outermost side of the first wafer stacking structure perpendicular to the stacking direction, and a bottom wafer located at the other outermost side and arranged opposite to the top wafer, the top wafer is reserved with a test lead-out metal sheet, and the first surface is away from the bottom wafer; the test pad is formed on the first surface of the first wafer stacking structure, including: opening a through hole in the dielectric layer on the top wafer in the first wafer stacking structure to expose the test lead-out metal sheet; forming a connecting structure in the through hole, and forming the test pad on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the top wafer, and the test pad is connected to the test lead-out metal sheet through the connecting structure.

[0011] Wherein, after testing the chip area in the first wafer stacking structure through the test pad, the bonding method further includes: removing at least part of the test pad and the connection structure; and planarizing the first surface.

[0012] Among them, cutting the first wafer stacking structure to form a chip corresponding to the chip area includes: temporarily bonding the first wafer stacking structure to a carrier wafer; cutting the first wafer stacking structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer; using the carrier wafer to transfer the chip to a wafer rack, and removing the carrier wafer.

[0013] Among them, temporarily bonding the first wafer stacking structure to the carrier wafer includes: using the first surface of the first wafer stacking structure as a bonding surface to bond to the carrier wafer, the first surface being the outermost surface of the first wafer stacking structure perpendicular to the stacking direction; after temporarily bonding the first wafer stacking structure to the carrier wafer, the bonding method also includes: thinning the bottom wafer of the first wafer stacking structure until the silicon vias in the bottom wafer and the metal columns in the silicon vias are exposed, the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

[0014] The step of bonding the chips that are determined to be functionally good by the test to the second wafer includes: sequentially bonding the plurality of chips that are determined to be functionally good by the test to the second wafer using a chip-to-wafer bonding technology.

[0015] In order to solve the above technical problems, the second aspect of the present application also provides a wafer stacking structure, including: a functional wafer; at least one first chip bonded to the functional wafer, the first chip including at least two bonded grains, and one of the outer layer grains of the first chip forming a test lead-out metal sheet.

[0016] The first chip is obtained by cutting a first wafer stack structure and corresponds to a chip area of ​​the first wafer stack structure that has good functionality as determined by testing;

[0017] The outer layer die of the first chip is bonded to the functional wafer, or bonded to other adjacent first chips.

[0018] To solve the above technical problems, the third aspect of the present application also provides a chip structure, including: at least one first chip, the first chip includes at least two grains bonded together, and one of the outer layer grains of the first chip forms a metal sheet led out by testing.

[0019] Among them, the first chip is obtained by cutting a first wafer stacking structure, and corresponds to a chip area with good functionality determined by testing in the first wafer stacking structure; the chip structure also includes functional grains, and the functional grains are bonded to the outer grains of the first chip.

[0020] The bonding method provided in some embodiments of the present application includes: providing at least one first wafer stacking structure, and testing each chip area in the first wafer stacking structure; wherein the first wafer stacking structure includes a plurality of first wafers bonded together; forming chips corresponding to the chip areas by cutting the first wafer stacking structure; and bonding the chips that have good functions determined by the test to a second wafer. Compared to the traditional wafer multi-layer wafer bonding method, the present application tests each chip area of ​​a wafer stacking structure with fewer layers, and then bonds the chips that have good functions determined by the test to a second wafer, so as to achieve a higher number of chip-wafer stacking layers. During the chip stacking process, the bonded multi-layer stacking structure can maintain a higher yield, which not only achieves performance but also reduces losses.

Brief Description of the Drawings

[0021] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, or any of the best modes of these inventions currently understood.

[0022] FIG1 is a schematic diagram of the structure of two wafers bonded in conventional technology;

[0023] FIG2 is a schematic diagram of the structure of two wafers bonded together in conventional technology, wherein one wafer includes a through-silicon via and a bonding metal pattern;

[0024] FIG3 is a schematic diagram of the structure of three wafers bonded in conventional technology;

[0025] FIG4 is a schematic diagram of a wafer stacking structure after bonding multiple wafers in conventional technology;

[0026] FIG5 is a flow chart of a bonding method provided in some embodiments of the present application;

[0027] FIG6 is a sub-flowchart of step S11 in FIG5 provided in some embodiments of the present application;

[0028] FIG7 is a schematic diagram of a first wafer stacking structure provided by some embodiments of the present application;

[0029] FIG8 is a schematic diagram of the wafer structure after being processed in step S112 in FIG6 ;

[0030] FIG9 is a sub-flowchart of step S112 in FIG6 provided in some embodiments of the present application;

[0031] FIG10 is a schematic diagram of the wafer structure after being processed in step S114 and step S115 in FIG6 ;

[0032] FIG11 is a sub-flowchart of step S12 in FIG5 provided in some embodiments of the present application;

[0033] FIG12 is a schematic diagram of the wafer structure after being processed in step S121 in FIG11 ;

[0034] FIG13 is a schematic diagram of the wafer structure after being processed in step S122 in FIG11 ;

[0035] FIG14 is a schematic diagram of the wafer structure after being processed in step S123 in FIG11 ;

[0036] FIG15 is a schematic diagram of the wafer structure in FIG11 after the chips are transferred to the wafer rack using the carrier wafer in step S124;

[0037] FIG16 is a schematic diagram of the wafer structure in FIG11 after the carrier wafer is removed by debonding in step S124;

[0038] FIG17 is a schematic diagram of the wafer structure of FIG5 , to which a chip having good functionality determined by testing is bonded in step S13;

[0039] FIG18 is a schematic diagram of the wafer structure of the chips having good functions determined by bonding multiple tests in step S13 in FIG5 ;

[0040] FIG19 is a schematic diagram of a wafer stacking structure provided by some embodiments of the present application;

[0041] FIG20 is a schematic diagram of a chip structure provided in some embodiments of the present application. [Specific implementation method]

[0042] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0044] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The "front side" of the wafer mentioned in this article is the side where electronic components are provided, and the "back side" is the side opposite to the "front side". The wafer bonding mentioned in this article is not limited to the front-to-back bonding of the wafer, but can also be the front-to-front bonding of the wafer, or the back-to-back bonding of the wafer.

[0046] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0047] Figure 1 is a schematic diagram of the structure of two wafers bonded in traditional technology; Figure 2 is a schematic diagram of the structure of two wafers bonded in traditional technology, where one wafer includes a through-silicon via and a bonding metal pattern; Figure 3 is a schematic diagram of the structure of three wafers bonded in traditional technology; Figure 4 is a schematic diagram of the wafer stacking structure after multiple wafers are bonded in traditional technology.

[0048] Referring to Figures 1-4, in conventional technology, a wafer stacking structure 90 is formed by sequentially bonding multiple wafers 91 to form a multi-layer wafer bonding structure. First, two wafers 91 are bonded face-to-face to form a two-layer wafer stacking structure. Before bonding with the third wafer 91, the back of one of the wafers needs to be thinned to form a through-silicon via 911, a metal layer 913, and a bonding metal pattern 912, wherein the through-silicon via 911 connects the metal layer 913 on the front and back of the wafer 91. Then, the third wafer 91 is bonded to form a three-layer wafer stacking structure. The above process is then repeated until the desired multi-layer wafer stacking structure 90 is formed. However, during the wafer stacking process, it is difficult to maintain a 100% yield for wafer bonding. As the number of wafer stacking layers increases, the yield of the bonded wafer stacking structure will gradually decrease, and the resulting losses will also become increasingly greater. For example, if the yield of a wafer before bonding is 96% (assuming the yield of wafer-to-wafer bonding is 100%), then after four stacking steps, that is, forming a five-layer wafer stack, the yield will drop to 82%. After eight stacking steps, that is, forming a nine-layer wafer stack, the yield will drop to 69%. In other words, forming a nine-layer wafer stack will incur the cost of the process itself, as well as a 31% yield loss in addition to the cost.

[0049] To solve the above problems, the first aspect of the present application provides a bonding method. Referring to FIG5 , FIG5 is a flow chart of the bonding method provided in some embodiments of the present application; the method specifically includes:

[0050] Step S11: providing at least one first wafer stacking structure, and testing each chip region in the first wafer stacking structure; wherein the first wafer stacking structure includes at least two first wafers bonded together.

[0051] In the specific implementation process, refer to FIG6 , which is a sub-flowchart of step S11 in FIG5 provided in some embodiments of the present application; specifically, step S11 includes:

[0052] Step S111: bonding at least two of the first wafers together in sequence to form the first wafer stacking structure.

[0053] Wherein, referring to Figure 7, Figure 7 is a schematic diagram of the first wafer stacking structure provided in some embodiments of the present application. In this embodiment, the first wafer stacking structure 10 is formed by bonding and stacking 4 first wafers 11, and the first wafer stacking structure 10 includes at least one chip area 12, and each first wafer 11 includes at least one through-silicon via 111 and a metal layer 113. The through-silicon via 111 is filled with a conductive material to form a metal column 112, wherein the conductive material is copper, tungsten, or other metal material, and the metal layer 113 of the adjacent first wafers 11 is electrically connected through the through-silicon via 111 and the corresponding bonding metal pattern 114 set in one of the first wafers 11. In other embodiments, according to different needs or to achieve different functions, the first wafer stacking structure 10 can be set to be formed by stacking at least 2 first wafers 11, and specifically can be formed by stacking 3, 5, 6 or other numbers of first wafers 11. In some embodiments, the through silicon via 111 is made using a via-middle and BVR (backside via review) process, that is, the through silicon via 111 is prepared after the FEOL (front end of line) (e.g., transistor) and MOL (middle of line) (e.g., metal contact) and before the BEOL (back end of line) (e.g., metal layer). In other embodiments, to achieve different functions, the through silicon via 111 can be made using other processes, such as via-first or via-last. In some embodiments, the metal layer 113 and the bonding metal pattern 114 are formed using processes such as photolithography and etching.

[0054] Step S112 : forming a test pad on a first surface of the first wafer stacking structure, where the first surface is an outermost surface of the first wafer stacking structure perpendicular to the stacking direction.

[0055] Specifically, refer to Figure 8, which is a schematic diagram of the wafer structure after processing in step S112 in Figure 6; in this embodiment, the first wafer 11 of the first wafer stacking structure 10 is bonded front-to-back as an example. In this embodiment, the first wafer stacking structure 10 includes a top wafer 11a arranged on the outermost side of the first wafer stacking structure 10 perpendicular to the stacking direction, and a bottom wafer 11b located on the other outermost side and arranged opposite to the top wafer. Among them, the front side of the top wafer 11a, that is, the outermost side surface of the first wafer stacking structure 10 is the first surface 11a1. The top wafer 11a is reserved with a test lead-out metal sheet 121. In some embodiments, the test lead-out metal sheet 121 is formed at the same time as the metal layer 113 is formed in the dielectric layer 11a2 of the top wafer 11a, and the test lead-out metal sheet 121 is electrically connected to the metal layer 113 formed at the same time.

[0056] In the specific implementation process, refer to FIG9 , which is a sub-flowchart of step S112 in FIG6 provided in some embodiments of the present application; specifically, step S112 includes:

[0057] Step S1121: opening a through hole in the dielectric layer on the top wafer in the first wafer stack structure to expose the test lead-out metal sheet;

[0058] Continuing with FIG8 , the top wafer 11a includes a dielectric layer 11a2, disposed on a side away from the bottom wafer 11b. A test lead metal sheet 121 is embedded within the dielectric layer 11a2. A through hole 122 is defined in the dielectric layer 11a2 and is disposed on the side of the test lead metal sheet 121 away from the bottom wafer 11b, exposing the test lead metal sheet 121.

[0059] Step S1122: forming a connection structure in the through hole and forming the test pad on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the bottom wafer, and the test pad being connected to the test lead-out metal sheet through the connection structure.

[0060] Continuing with FIG8 , a conductive material is filled in the through-hole 122 to form a connection structure 123. Simultaneously, a test pad 124 is formed on the first surface 11 a 1 , thereby electrically connecting the test lead metal sheet 121 to the test pad 124. Since aluminum is resistant to oxidation compared to other metals, such as copper, in some embodiments, the conductive material filled in the through-hole 122 is aluminum.

[0061] Step S113: testing the chip region in the first wafer stack structure through the test pad to determine whether the corresponding chip region functions well.

[0062] Specifically, in some embodiments, the tests performed on the chip area 12 include, but are not limited to, WAT (wafer acceptable test) and CP (chip probing). WAT is a test of a dedicated test key (test pattern) that monitors the normality and stability of each process step through electrical parameters; CP is a test of the wafer, including tests of some basic device parameters such as VT (threshold voltage) and Rdson (specific on-resistance). Through these tests, well-functioning chip areas 12 can be identified and marked. In some embodiments, well-functioning chip areas 12 are chip areas that can implement corresponding electrical functions.

[0063] In this embodiment, referring to FIG6 , the following two steps are further included after step S113:

[0064] Step S114: removing the test pad and at least a portion of the connection structure;

[0065] Step S115: performing a planarization process on the first surface.

[0066] Specifically, see Figure 10, which is a schematic diagram of the wafer structure after steps S114 and S115 in Figure 6. After testing is completed and the chip areas with good functionality are screened, the test pads 124 and connection structures 123 need to be removed, that is, the electrical connection between the test lead metal sheet 121 and the outside of the corresponding chip area 12 is disconnected. To ensure that subsequent chip stacking is not affected, the through-holes 122 need to be filled with a non-conductive material to form an insulating layer 125, and the first surface 11a1 needs to be planarized. The test pads 124 and connection structures 123 can be completely removed during the removal process; a portion of the structure away from the bottom wafer 11b can also be removed; or a portion of the first dielectric layer 11a2 surrounding the test pads 124 and connection structures 123 can be removed simultaneously. As long as the electrical connection between the test lead metal sheet 121 and the outside of the corresponding chip area 12 is disconnected without affecting subsequent chip stacking, it is sufficient. In some embodiments, a wet etching process is used to etch the conductive material, i.e., aluminum metal, filled in the through-hole 122, thereby removing the test pad 124 and the connection structure 123. After the etching process is completed, in some embodiments, an oxide deposition process is used to fill the through-hole 122, wherein the oxide deposition can be filled with silicon dioxide; then a CMP (Chemical Mechanical Polishing) process is used to planarize the first surface 11a1. In other embodiments, other methods may be used to remove the conductive material, such as chemical etching, reactive ion etching, or other dry etching methods.

[0067] Step S12: cutting the first wafer stack structure to form chips corresponding to the chip area.

[0068] In the specific implementation process, refer to FIG11, which is a sub-flowchart of step S12 in FIG5 provided in some embodiments of the present application; specifically, step S12 includes:

[0069] Step S121: temporarily bonding the first wafer stacking structure to the carrier wafer.

[0070] Specifically, refer to Figure 12, which is a schematic diagram of the wafer structure after processing in step S121 in Figure 11. Before cutting the first wafer stacking structure 10, a carrier wafer 20 needs to be bonded. In this embodiment, the first surface 11a1 is set to bond with the carrier wafer 20, and the first wafer stacking structure 10 is bonded to the carrier wafer 20 by temporary bonding. Among them, in order to facilitate subsequent chip stacking, before bonding, a bonding metal pattern 114 can be formed in the dielectric layer 11a2, and the bonding metal pattern 114 is connected to the metal layer 113 in the top wafer 11a. In some embodiments, the bonding metal pattern 114 is formed by etching, deposition and other processes.

[0071] Step S122: Thinning the bottom wafer of the first wafer stacking structure until the through silicon vias in the bottom wafer and the metal pillars in the through silicon vias are exposed, the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

[0072] Specifically, see Figure 13, which is a schematic diagram of the wafer structure after step S122 in Figure 11. To facilitate subsequent chip stacking, the surface of the bottom wafer 11b away from the top wafer 11a, i.e., the back side of the bottom wafer 11b, needs to be thinned to expose the through-silicon vias 111 of the bottom wafer 11b and the metal pillars 112 in the through-silicon vias 111. In some embodiments, the BVR (backside via review) process is still used to thin the bottom wafer 11b.

[0073] In this embodiment, the sequence of first temporarily bonding the carrier wafer 20 and then thinning the bottom wafer 11b of the first wafer stack structure 10 is adopted. In other embodiments, the bottom wafer 11b of the first wafer stack structure 10 may be thinned first and then the carrier wafer 20 is temporarily bonded, as long as it does not affect subsequent chip stacking.

[0074] Step S123: cutting the first wafer stack structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer.

[0075] Specifically, refer to Figures 13-14. Figure 14 is a schematic diagram of the wafer structure after processing in step S123 in Figure 11. In some embodiments, the chip area 12 is first divided by photolithography; then the first wafer stacking structure 10 is cut by etching to separate the chip area 12 to form the chip 30. Since the temporarily bonded carrier wafer 20 serves to carry the chip 30 and does not participate in the subsequent chip stacking, in order to facilitate the subsequent removal of the carrier wafer 20, in some embodiments, when etching is used to cut the first wafer stacking structure 10, it stays on the bonding surface of the carrier wafer 20. In this way, a plurality of chips 30 bonded to the carrier wafer 20 can be obtained.

[0076] Step S124: using the carrier wafer to transfer the chip to a wafer rack, and removing the carrier wafer.

[0077] Specifically, referring to Figures 15 and 16, Figure 15 is a schematic diagram of the wafer structure after the chip is transferred to the wafer rack for processing using the carrier wafer in step S124 in Figure 11; Figure 16 is a schematic diagram of the wafer structure after the carrier wafer is removed in step S124 in Figure 11. In this embodiment, in order to facilitate the removal of the carrier wafer 20 and to facilitate the support and fixation of the chip 30 after the carrier wafer 20 is removed, the chip 30 needs to be transferred to the wafer rack 40 before removing the carrier wafer 20, wherein the surface of the chip 30 away from the carrier wafer 20 contacts the wafer rack 40. In this embodiment, the carrier wafer is removed by debonding. In other embodiments, the carrier wafer can be removed by etching, CMP or other methods. In some embodiments, the wafer rack 40 is a blue film or a UV film (ultraviolet irradiation tape).

[0078] Step S13: bonding the chip that has good function determined by the test to a second wafer.

[0079] Specifically, referring to Figures 17 and 18, Figure 17 is a schematic diagram of the wafer structure of Figure 5 after bonding one chip that has been tested and confirmed to be functional in step S13; Figure 18 is a schematic diagram of the wafer structure of Figure 5 after bonding multiple chips that have been tested and confirmed to be functional in step S13. After the above steps, in this embodiment, the multiple chips 30 that have been tested and confirmed to be functional are sequentially bonded to a second wafer 50 using chip-to-wafer bonding technology to form a multi-layer wafer stack structure 100. In some embodiments, the second wafer 50 is a functional wafer, such as a logic wafer.

[0080] The bonding method provided in this embodiment provides a first wafer stacking structure 10 with at least two layers. After testing the chip regions 12, the chip regions 12 with good functionality are screened and marked. The first wafer stacking structure 10 is then cut to obtain multiple chips 30 corresponding to the chip regions 12, thereby selecting multiple chips 30 with good functionality. Finally, the multiple chips 30 with good functionality determined by the test are sequentially bonded to a second wafer 50 using chip-to-wafer bonding technology. This results in a multi-layer wafer stacking structure 100, in which each of the chips 30 to be bonded and stacked is fully functional, maintaining a high yield for the wafer stacking structure 100.

[0081] Furthermore, in order to solve the above-mentioned problem, the second aspect of the present application provides a wafer stacking structure. Specifically, refer to Figure 19, which is a schematic diagram of the wafer stacking structure provided by some embodiments of the present application. The wafer stacking structure 100 includes at least one first chip 110 and a functional wafer 120. In this embodiment, a plurality of first chips 110 are bonded to the functional wafer 120 in sequence to form a multi-layer stacking structure. The first chip 110 is obtained by cutting the above-mentioned first wafer stacking structure 10, and the first chip 110 corresponds to the chip area 12 with good function, that is, the first chip 110 is a chip with good function among the multiple chips 30 obtained after cutting the above-mentioned first wafer stacking structure 10. In other words, the first wafer stacking structure 10 may include at least two first wafers 11 bonded together, and cutting the first wafer stacking structure 10 can obtain multiple chips 30, wherein a chip 30 with good function is selected from the chips 30 obtained by cutting as the first chip 110 to perform the subsequent operations described in the above-mentioned embodiments of the present application. In addition, those skilled in the art can understand that when cutting the first wafer stacking structure 10, each first wafer 11 in the first wafer stacking structure 10 is also cut into multiple grains 31 respectively, and the chip 30 and the first chip 110 obtained by cutting are stacked by at least two grains 31 obtained by cutting the corresponding first wafer 11 in the first wafer stacking structure 10.

[0082] In some embodiments, one of the die 31 in the outer layer of the first chip 110 is formed with a tested test lead-out metal sheet 121. In some embodiments, the die 31 in the outer layer of the first chip 110 is used to bond with the functional wafer 120, or with other adjacent first chips 110. In some embodiments, the functional wafer 120 is a logic wafer. In other embodiments, the functional wafer may also be a wafer that implements other functions.

[0083] Furthermore, to solve the above problems, the third aspect of the present application provides a chip structure. Specifically, refer to Figure 20, which is a schematic diagram of the chip structure provided by some embodiments of the present application. The chip structure 200 includes at least one first chip 110. Similarly, the first chip 110 is obtained by cutting the above-mentioned first wafer stacking structure 10, and the first chip 110 corresponds to the well-functioning chip area 12, that is, the first chip 110 is a well-functioning chip. Similarly, the first chip 110 is stacked by at least two grains 31.

[0084] In some embodiments, a test lead-out metal sheet 121 is formed on one of the outer layers of the first chip 110 of the chip structure 200. In some embodiments, the chip structure 200 includes a functional die 210, which is bonded to the outer layer die 31 of the first chip 110. When the chip structure 200 includes a plurality of bonded first chips 110, the outer layer die 31 of the first chip 110 is used to bond to the functional die 210, or to bond to other adjacent first chips 110. In some embodiments, the functional die 210 is a logic die. In other embodiments, the functional die may also be a die that implements other functions.

[0085] The above is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A bonding method, wherein: include: Providing at least one first wafer stacking structure, and testing each chip region in the first wafer stacking structure; wherein the first wafer stacking structure comprises at least two first wafers bonded together; cutting the first wafer stack structure to form chips corresponding to the chip area; The chips that are determined to be functioning well by the test are bonded to a second wafer.

2. The bonding method according to claim 1, wherein: include: The providing at least one first wafer stacking structure and testing each chip region in the first wafer stacking structure comprises: bonding at least two of the first wafers together in sequence to form the first wafer stacking structure; forming a test pad on a first surface of the first wafer stacking structure, wherein the first surface is an outermost surface of the first wafer stacking structure perpendicular to a stacking direction; The chip region in the first wafer stacking structure is tested by the test pad to determine whether the corresponding chip region functions well.

3. The bonding method according to claim 2, wherein: The first wafer stacking structure comprises a top wafer located at an outermost side of the first wafer stacking structure perpendicular to the stacking direction, and a bottom wafer located at another outermost side and arranged opposite to the top wafer, the top wafer is reserved with a test lead-out metal sheet, and the first surface is away from the bottom wafer; The forming of a test pad on the first surface of the first wafer stack structure comprises: Opening a through hole in the dielectric layer on the top wafer in the first wafer stack structure to expose the test lead-out metal sheet; A connection structure is formed in the through hole, and the test pad is formed on the first surface of the first wafer stacking structure, the first surface being the surface of the dielectric layer away from the bottom wafer, and the test pad is connected to the test lead-out metal sheet through the connection structure.

4. The bonding method according to claim 3, wherein: After testing the chip region in the first wafer stack structure by using the test pad, the bonding method further includes: removing the test pad and at least a portion of the connecting structure; The first surface is planarized.

5. The bonding method according to claim 1, wherein: The step of cutting the first wafer stack structure to form chips corresponding to the chip area includes: Temporarily bonding the first wafer stack structure to the carrier wafer; Cutting the first wafer stacking structure until the bonding surface of the carrier wafer to form the chip on the bonding surface of the carrier wafer; The chip is transferred to a wafer rack using the carrier wafer, and the carrier wafer is removed.

6. The bonding method according to claim 5, wherein: The step of temporarily bonding the first wafer stacking structure to the carrier wafer comprises: Bonding the first surface of the first wafer stacking structure to the carrier wafer as a bonding surface, wherein the first surface is an outermost surface of the first wafer stacking structure perpendicular to the stacking direction; After temporarily bonding the first wafer stack structure to the carrier wafer, the bonding method further comprises: The bottom wafer of the first wafer stacking structure is thinned until the through silicon vias in the bottom wafer and the metal columns in the through silicon vias are exposed, and the bottom wafer is located at the other outermost side of the first wafer stacking structure perpendicular to the stacking direction, and the first surface is away from the bottom wafer.

7. The bonding method according to claim 1, wherein: The step of bonding the chip having good functions determined by the test to a second wafer comprises: The plurality of chips having good functions determined by the test are bonded sequentially onto the second wafer using chip-to-wafer bonding technology.

8. A wafer stacking structure, wherein: include: Functional wafers; At least one first chip is bonded on the functional wafer, wherein the first chip comprises at least two crystal grains bonded together, and a test lead-out metal sheet is formed on one of the outer crystal grains of the first chip.

9. The wafer stacking structure according to claim 8, wherein: The first chip is obtained by cutting a first wafer stack structure, and corresponds to a chip area with good functions determined by testing in the first wafer stack structure; The outer layer die of the first chip is bonded to the functional wafer, or bonded to other adjacent first chips.

10. A chip structure, wherein: include: At least one first chip, the first chip includes at least two dies bonded together, and a test lead-out metal sheet is formed on one of the outer dies of the first chip.

11. The chip structure according to claim 10, wherein: The first chip is obtained by cutting a first wafer stack structure, and corresponds to a chip area with good functions determined by testing in the first wafer stack structure; The chip structure further includes a functional die, and the functional die is bonded to the outer layer die of the first chip.

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