Device layout method and apparatus for chip layout, and computer device and storage medium

Abstract

The embodiments of the present application relate to the technical field of chips. Disclosed are a device layout method and apparatus for a chip layout, and a computer device and a storage medium. The method comprises: acquiring a chip layout, wherein a first device and a second device are to be laid out on the chip layout (301); on the basis of a first layout parameter of the first device, determining a genus region that is in the chip layout and that corresponds to the first device, wherein the first layout parameter is a parameter used for laying out the first device on the chip layout, and the genus region is a hollow region that is in the chip layout and that is located inside the first device (302); and when the genus region does not support the layout of the second device, on the basis of a second layout parameter of the second device and the genus region, laying out the second device in a region on the chip layout other than the genus region, wherein the second layout parameter is a parameter used for laying out the second device on the chip layout (303).

Description

Device layout method, device, computer equipment and storage medium for chip layout

[0001] This application claims priority to Chinese patent application No. 202311160034.2, filed on September 8, 2023, entitled “Device layout method, apparatus, computer equipment and storage medium for chip layout”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of the present application relate to the field of chip technology, and in particular to a device layout method, apparatus, computer equipment, and storage medium for a chip layout. Background Art

[0003] In order to realize the functions of performing calculations and information processing, different types of core devices (such as superconducting quantum bits, reading cavities, etc.) and auxiliary devices (such as indium pillars, magnetic flux capture holes, through holes in multi-layer stacked chips, etc.) are arranged on the chip.

[0004] In related technologies, electronic design automation (EDA) tools are often used to lay out core and auxiliary components on a layout. If the core components are already on the layout, the auxiliary components are typically evenly laid out across the entire layout in a specific array. A Boolean difference operation is then performed with the core components, and the result is used as the layout plan for the auxiliary components.

[0005] Summary of the Invention

[0006] The present invention provides a device layout method, apparatus, computer equipment, and storage medium for a chip layout. The technical solution is as follows:

[0007] In one aspect, an embodiment of the present application provides a device layout method for a chip layout, the method being executed by a computer device, the method comprising:

[0008] Obtaining a chip layout, on which a first device and a second device are to be arranged;

[0009] determining, based on first layout parameters of the first device, a genus region corresponding to the first device in the chip layout, wherein the first layout parameters are parameters used for laying out the first device on the chip layout, and the genus region refers to a hollow region within the first device in the chip layout;

[0010] When the deficient area does not support the layout of the second device, the second device is laid out in an area outside the deficient area on the chip layout based on second layout parameters of the second device and the deficient area, where the second layout parameters are parameters used for laying out the second device on the chip layout.

[0011] On the other hand, an embodiment of the present application provides a device for placing devices in a chip layout, the device comprising:

[0012] an acquisition module, configured to acquire a chip layout on which the first device and the second device are to be arranged;

[0013] a determining module, configured to determine a genus region corresponding to the first device in the chip layout based on first layout parameters of the first device, wherein the first layout parameters are parameters used for laying out the first device on the chip layout, and the genus region refers to a hollow region within the first device in the chip layout;

[0014] A layout module is configured to layout the second device in an area outside the deficient area on the chip layout based on second layout parameters of the second device and the deficient area, if the deficient area does not support the layout of the second device, wherein the second layout parameters are parameters used to layout the second device on the chip layout.

[0015] On the other hand, an embodiment of the present application provides a computer device, which includes a processor and a memory; the memory stores at least one computer instruction, and the at least one computer instruction is used to be executed by the processor to implement the device layout method of the chip layout described in the above aspect.

[0016] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer instruction, and the computer instruction is loaded and executed by a processor to implement the device layout method of the chip layout as described in the above aspects.

[0017] In another aspect, embodiments of the present application provide a computer program product comprising computer instructions stored in a computer-readable storage medium. A processor of a terminal reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the terminal to perform the device placement method for a chip layout as described in the above aspects.

[0018] In an embodiment of the present application, a genus region corresponding to the first device in a chip layout can be determined based on a first layout parameter of the first device. Since the genus region is a hollow area within the first device in the chip layout, if the genus region does not support placement of a second device, the second device can be placed outside the genus region on the chip layout based on the second layout parameter of the second device and the genus region. This can avoid placing the second device in the hollow area within the first device, reduce the occurrence of device malfunction, and thus improve the device placement quality of the chip layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a schematic diagram showing a genus region inside a core device provided by an exemplary embodiment of the present application;

[0020] FIG2 is a schematic diagram showing an auxiliary device provided by an exemplary embodiment of the present application being arranged in a genus region inside a core device;

[0021] FIG3 is a flow chart of a device layout method for a chip layout provided by an exemplary embodiment of the present application;

[0022] FIG4 is a schematic diagram of a node arrangement sequence provided by an exemplary embodiment of the present application;

[0023] FIG5 is a schematic diagram of a node arrangement sequence provided by another exemplary embodiment of the present application;

[0024] 6 is a schematic diagram of placing a second device in an area other than an intersection between the candidate placement area and the genus area, provided by an exemplary embodiment of the present application;

[0025] FIG7 is a schematic diagram of a code for configuring a target control based on the protobuf protocol provided by an exemplary embodiment of the present application;

[0026] FIG8 is a flow chart of laying out a second device on a chip layout according to an exemplary embodiment of the present application;

[0027] FIG9 is a schematic diagram of translating a candidate layout adjustment area provided by an exemplary embodiment of the present application;

[0028] FIG10 is a schematic diagram of adding a second device in a genus region when the area of ​​the genus region is greater than an area threshold, according to an exemplary embodiment of the present application;

[0029] FIG11 is a schematic diagram of adding a second device in a genus region when the density of the second devices in a sub-block is less than a density threshold, according to an exemplary embodiment of the present application;

[0030] FIG12 is a structural block diagram of a device layout apparatus for a chip layout provided by an exemplary embodiment of the present application;

[0031] FIG13 is a schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0033] In order to arrange auxiliary devices on the chip layout, relevant technologies use EDA tools to evenly lay out the auxiliary devices in an array on the chip layout, and perform Boolean difference operations with the core devices already arranged on the chip layout, and use the results of the operation as the layout plan for the auxiliary devices.

[0034] However, due to the diverse structures and functions of devices, directly using Boolean difference operations to arrange devices can easily cause device malfunctions.

[0035] In one possible scenario, there may be a genus region inside the core device on the chip layout, where the genus region refers to a hollow area located inside the core device on the chip layout.

[0036] "Genesis" is a definition in topology. For a figure, if there are n mutually non-intersecting closed curves in the figure, and these n mutually non-intersecting closed curves do not separate the figure into different regions, then the genus of the figure is called n.

[0037] Refer to FIG. 1 , which is a schematic diagram of a core device provided by an exemplary embodiment of the present application, in which a genus region exists inside the core device.

[0038] As shown in FIG1 , a rectangular genus region 111 exists inside the core device 101 , a triangular genus region 112 exists inside the core device 102 , and an irregular polygonal genus region 113 exists inside the core device 103 .

[0039] This embodiment is illustrated by taking the genus region as a rectangle, triangle or irregular polygon as an example, but this is not a limitation. In fact, the genus region inside the core device can be of various shapes. For example, there may be a genus region with a "cross" structure inside a superconducting quantum bit, or a genus region with other special structures (such as a "flipmon" structure). Genesis regions of various shapes such as these are all within the scope of protection of this application.

[0040] When there is a defective area inside the core device, the method of evenly laying out the auxiliary devices in an array on the chip layout and performing Boolean difference operations with the core devices already laid out on the chip layout may cause the auxiliary devices to be laid out in the defective area inside the core device. If the defective area does not support the laying out of auxiliary devices, it may cause the core device to malfunction.

[0041] 2 , which is a schematic diagram showing an auxiliary device provided by an exemplary embodiment of the present application being arranged in a genus region inside a core device.

[0042] As shown in Figure 2, when there is a genus region inside the core device, the auxiliary devices are evenly laid out in an array on the chip layout and a Boolean difference operation is performed with the core devices already laid out on the chip layout. As a result, eight auxiliary devices (including auxiliary device 211) are laid out in the genus region inside core device 201, two auxiliary devices (including auxiliary device 212) are laid out in the genus region inside core device 202, and three auxiliary devices (including auxiliary device 213) are laid out in the genus region inside core device 203. If the above-mentioned genus regions do not support the layout of auxiliary devices, core devices 201, 202, and 203 may malfunction.

[0043] In order to solve the problem of abnormal operation caused by auxiliary devices being arranged in the defective area inside the core device, the present application provides a device arrangement method for a chip layout, so that the auxiliary devices can be arranged not in the defective area inside the core device, thereby improving the device arrangement quality of the chip layout and reducing the problem of abnormal operation.

[0044] Referring to FIG. 3 , FIG. 3 is a flow chart of a device layout method for a chip layout according to an exemplary embodiment of the present application. The method is performed by a computer device. In some embodiments, the computer device includes an application (e.g., an EDA tool) capable of generating a chip layout. The flow chart includes the following steps:

[0045] Step 301: Obtain a chip layout, on which a first device and a second device are to be arranged.

[0046] The chip layout is a layout that reflects the physical information such as the device type, device size, relative position between devices, and connection relationship between various devices corresponding to various devices in the chip.

[0047] Optionally, the chip layout is a layout corresponding to a superconducting quantum chip.

[0048] In some embodiments, the first device is a core device arranged on the chip layout, and the second device is an auxiliary device arranged on the chip layout.

[0049] Optionally, the first device is a core device such as a superconducting quantum bit, a resonant cavity, a reading cavity or a top-piece test junction.

[0050] Optionally, the second device is an auxiliary device such as an indium pillar, a magnetic flux capturing hole, a through hole in a multi-layer stacked chip, etc.

[0051] In some embodiments, the first device may also be other types of core devices, and the second device may also be other types of auxiliary devices. The embodiments of the present application do not limit the specific types of the first device and the second device.

[0052] The secondary device serves as an auxiliary device, providing support to the core primary device. For example, on a superconducting quantum chip, indium pillars are bumps made of metallic indium that establish an electrical connection between the bottom and top sheets. Magnetic flux capture holes are micron-sized holes or perforations etched into the quantum processor, capturing magnetic flux and preventing it from interfering with quantum bits, thereby reducing errors and the impact of decoherence and improving the accuracy of quantum computing. Through-holes in multi-layer stacked chips are used to connect vertically stacked three-dimensional chips, enabling vertical interconnection between and within chips.

[0053] Step 302 : Determine a genus region corresponding to the first device in the chip layout based on first layout parameters of the first device. The first layout parameters are parameters used to layout the first device on the chip layout. The genus region refers to a hollow region inside the first device in the chip layout.

[0054] The first layout parameter is used to indicate how to layout the first device on the chip layout.

[0055] Optionally, the first layout parameters include shape, side length, position and size parameters of the first device, or distance parameters between the first device and the upper, lower, left and right boundaries of the chip layout, or other parameters used for laying out the first device.

[0056] In some embodiments, the first layout parameter includes a layout node sequence. The layout node sequence includes a plurality of layout nodes, which are used to represent a plurality of vertices of the first device on the chip layout.

[0057] In some embodiments, the layout node sequence includes a plurality of layout nodes connected in sequence, and the plurality of layout nodes can be connected in sequence to form a connected area where the first device is located.

[0058] The genus region corresponding to the first device refers to a hollow area inside the first device in the chip layout. For example, the genus region corresponding to the core device 101 in FIG1 is a rectangular area inside the core device 101.

[0059] In some embodiments, whether the first device has a corresponding genus region can be determined based on a first layout parameter of the first device. If the first device has a corresponding genus region, the genus region can be determined based on the first layout parameter used in laying out the first device.

[0060] Step 303 : If the genus region does not support placement of the second device, place the second device in an area outside the genus region on the chip layout based on second placement parameters of the second device and the genus region, where the second placement parameters are parameters used for placing the second device on the chip layout.

[0061] In some embodiments, all or part of the genus region on the chip layout may not support placement of the second device.

[0062] The second layout parameter is used to indicate how to layout the second device on the chip layout.

[0063] Optionally, the second layout parameters include shape, side length, position and size parameters of the second device, or distance parameters between the second device and the upper, lower, left and right boundaries of the chip layout, or other parameters used for laying out the second device.

[0064] In some embodiments, the second layout parameter also includes a distance limit parameter between the second device and the first device, wherein the distance limit parameter is used to ensure the spacing distance between the first device and the second device to avoid abnormal operation due to the close distance between the devices.

[0065] In a possible implementation, the computer device may place the second device array in an area on the chip layout that does not intersect with the genus area according to the second placement parameter.

[0066] In some embodiments, the computer device may obtain first layout parameters and second layout parameters set by a user, so as to perform device layout on a chip layout according to the first layout parameters and the second layout parameters.

[0067] To determine the genus region corresponding to the first device according to the first layout parameters, in some embodiments, the computer device may set the first layout parameters according to certain rules.

[0068] In some embodiments, the first layout parameter includes a layout node sequence, wherein the layout node sequence includes layout nodes connected in sequence, and a connected area formed by the layout nodes connected in sequence is the layout area of ​​the first device.

[0069] Refer to FIG4 , which is a schematic diagram of a node deployment sequence provided by an exemplary embodiment of the present application.

[0070] As shown in FIG4 , the first layout parameter corresponding to the first device may include a layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> .

[0071] Among them, the connection area 410 formed by sequentially connecting the layout nodes A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 is the layout area of ​​the first device.

[0072] In some embodiments, a first connected node and a second connected node in a layout node sequence can be determined, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside a connected area.

[0073] For example, when laying out a node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> In the example, there are two adjacent nodes A5 and A6, and the line A5A6 formed by A5 and A6 is located inside the connected area. Then A5 can be used as the first connected node and A6 as the second connected node; or A5 can be used as the second connected node and A6 as the first connected node.

[0074] In some embodiments, a layout node having the same node coordinates as the head layout node in the layout node sequence may be determined as a first connected node, and an adjacent node of the first connected node may be determined as a second connected node.

[0075] For example, when laying out a node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> , the node coordinates of A5 are the same as the node coordinates of the head layout node A1 in the layout node sequence. Therefore, A5 can be used as the first connected node, and the adjacent node A6 of the first connected node A5 can be determined as the second connected node.

[0076] To determine the genus region corresponding to the first device based on the first layout parameter, in some embodiments, the layout nodes in the layout node sequence can be traversed sequentially in a first direction starting from the first connected node to obtain a first closed curve formed by connecting the layout nodes.

[0077] For example, starting from the first connected node A5, traverse the node sequence in reverse order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in are obtained to obtain a first closed curve S1 formed by connecting the layout nodes A5, A4, A3, A2, and A1.

[0078] Starting from the second connected node, the layout nodes in the layout node sequence are traversed in sequence along the second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction.

[0079] For example, starting from the second connected node A6, the node sequence is traversed in sequence.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in are obtained to obtain a second closed curve S2 formed by connecting the layout nodes A6, A7, A8, A9, and A10.

[0080] In some embodiments, a genus region may be determined based on the first closed curve and the second closed curve.

[0081] In some embodiments, when the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as a genus area.

[0082] As shown in FIG4 , the enclosed area corresponding to the second closed curve S2 is located within the enclosed area corresponding to the first closed curve S1 . Therefore, the enclosed area corresponding to the second closed curve S2 can be determined as a genus area.

[0083] Optionally, node coordinates of the layout vertices in the first closed curve S1 and the second closed curve S2 may be compared to determine whether the enclosed area corresponding to the second closed curve S2 is within the enclosed area corresponding to the first closed curve S1.

[0084] In some embodiments, the first or second connectivity node may be located at a vertex or boundary of the layout area of ​​the first device. For example, in FIG4 , the first connectivity node A5 and the second connectivity node A6 are located at a vertex of the layout area 410 of the first device; in FIG5 , the first connectivity node A6 is located at a boundary of the layout area 510 of the first device, and the second connectivity node A7 is located at a vertex of the layout area 510 of the first device.

[0085] Refer to FIG5 , which is a schematic diagram of a node deployment sequence provided by another exemplary embodiment of the present application.

[0086] As shown in FIG5 , the first layout parameter corresponding to the first device may include a layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11> .

[0087] Among them, the connected area 510 formed by sequentially connecting the layout nodes A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, and A11 is the layout area of ​​the first device.

[0088] In the node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11> In the example, there are two adjacent nodes A6 and A7, and the line A6A7 formed by A6 and A7 is located inside the connected area. Then A6 can be used as the first connected node and A7 as the second connected node; or A6 can be used as the second connected node and A7 as the first connected node.

[0089] Alternatively, since the node coordinates of A6 are the same as the node coordinates of the head layout node A1 in the layout node sequence, A6 can be used as the first connected node, and the adjacent node A7 of the first connected node A6 can be determined as the second connected node.

[0090] Starting from the first connected node A6, traverse the node sequence in reverse order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in are obtained to obtain a first closed curve S1 formed by connecting the layout nodes A6, A5, A4, A3, A2, and A1.

[0091] Starting from the second connected node A7, traverse the node sequence in order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in are obtained to obtain a second closed curve S2 formed by connecting the layout nodes A7, A8, A9, A10, and A11.

[0092] In some embodiments, since the enclosed area corresponding to the second closed curve S2 is located within the enclosed area corresponding to the first closed curve S1 , the enclosed area corresponding to the second closed curve S2 can be determined as a genus area.

[0093] In this embodiment, after determining the first connected node and the second connected node based on the layout node sequence, traversal can be performed in opposite directions to determine the first closed curve and the second closed curve, thereby efficiently determining the genus region, thereby improving the efficiency of device layout.

[0094] Based on the second layout parameter of the second device and the genus region, when the second device is laid out on the chip layout, it can be determined whether there is an intersection between the area where the second device is laid out and the genus region. If there is an intersection, the second device is not laid out in the area.

[0095] In some embodiments, a candidate layout area of ​​the second device in the chip layout may be determined based on the second layout parameter.

[0096] Optionally, the candidate layout areas can be determined in a uniform array according to the shape, side length, position and size parameters of the second device in the second layout parameters, and the distance parameters between the second device and the upper, lower, left and right boundaries of the chip layout.

[0097] Optionally, the candidate layout area may be determined based on a distance limit parameter between the first device and the second device to ensure that the distance between the candidate layout area and the layout area of ​​the first device is greater than or equal to the distance limit parameter.

[0098] Optionally, candidate layout areas may be determined in a uniform array manner in an area outside the first device on the chip layout.

[0099] If the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, the second device is placed in regions of the candidate placement region excluding the intersection.

[0100] 6 , which is a schematic diagram of placing a second device in an area other than an intersection between the candidate placement area and the genus area, according to an exemplary embodiment of the present application.

[0101] As shown in FIG6 , on the chip layout, the genus region corresponding to the first device 601 is a rectangular region, the genus region corresponding to the first device 602 is a triangular region, and the genus region corresponding to the first device 603 is an irregular polygonal region.

[0102] In some embodiments, a candidate layout area (shown as a dotted box) for the second device can be determined based on the second layout parameter. For example, in FIG6 , candidate layout areas for the second device exist both outside the layout area of ​​the first device and in the genus area corresponding to the first device.

[0103] In some embodiments, when the genus regions corresponding to the first device 601, the first device 602, and the first device 603 do not support the layout of the second device, the intersection of the candidate layout area of ​​the second device and the genus region (i.e., the area where the dotted box in the genus region is located) can be determined.

[0104] Therefore, the computer device arranges the second device in an area other than the intersection in the candidate arrangement area to form a arrangement area for the second device (shown in a solid line box), thereby avoiding arrangement of the second device in the defective area corresponding to the first device and avoiding abnormal operation problems.

[0105] In one possible scenario, the genus region corresponding to the first device may support the placement of the second device.

[0106] For example, for some special device structures, such as the "flipmon" structure of a superconducting quantum bit, the genus region supports the layout of indium pillars.

[0107] For example, for some special device functions, such as the pad of the top piece test junction, since the resistance of the junction after welding needs to be measured on the bottom piece after welding the top and bottom pieces, an indium column needs to be arranged in the pad of the top piece test junction to serve as a connection; or, when a control line needs to be added from the bottom piece to the top piece, an indium column also needs to be arranged in the pad of the top piece test junction.

[0108] Therefore, in some embodiments, when the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the computer device may place the second device in the candidate placement region.

[0109] Determining whether the deficient region corresponding to the first device supports the placement of the second device may include at least one of the following methods: wherein the placement support condition includes whether the deficient region does not support the placement of the second device or whether the deficient region supports the placement of the second device.

[0110] (1) In some embodiments, the support of the Deficit Region corresponding to the first device for the layout of the second device may be determined based on the device information of the first device.

[0111] The device information includes at least one of device type, device structure and device function.

[0112] Optionally, the device information further includes device size or other information related to the first device, which is not limited in this embodiment.

[0113] Optionally, the device type of the first device is the type to which the first device belongs, for example, the device type may be a superconducting quantum bit, a reading cavity, or the like.

[0114] Optionally, the device structure of the first device is a morphological structure of the first device, for example, the device structure may be a “cross” structure, a “flipmon” structure, or the like.

[0115] Optionally, the device function of the first device is a function to be implemented by the first device, for example, the device function may be used to measure the resistance of the node after pressure welding, or to add a control line from the bottom plate to the top plate, etc.

[0116] (2) In some embodiments, the support of the genus region corresponding to the first device for the layout of the second device can be determined based on the switch state of the target control, wherein the target control has a genus layout control function.

[0117] Optionally, the target control can be used to control the layout support of the second device in the defective areas corresponding to all first devices in the chip layout with one click, and can also be used to control the layout support of the second device in the defective areas corresponding to some first devices.

[0118] In some embodiments, the computer device may configure the target control based on the protobuf protocol.

[0119] See FIG. 7 , which is a schematic diagram of code for configuring a target control based on the protobuf protocol provided by an exemplary embodiment of the present application.

[0120] As shown in Figure 7, in the configuration file based on the protobuf protocol, the target control can be configured by setting the parameter value of "cheese_placement_in_genus_region".

[0121] For example, “cheese_placement_in_genus_region: 0” indicates that all genus regions corresponding to the first devices on the chip layout do not support placement of the second device.

[0122] For example, “cheese_placement_in_genus_region: 1” indicates that all genus regions corresponding to the first devices on the chip layout support placement of the second device.

[0123] Through the parameter value of "cheese_placement_in_genus_region", the support of the genus region for the placement of the second device can be determined according to user needs.

[0124] In a configuration file based on the protobuf protocol, the first layout parameters or the second layout parameters can also be set. For example, the distance parameters between the second device and the upper, lower, left, and right boundaries of the chip layout can be set based on the parameters in "margin_config" (for example, the parameter values ​​of "left_margin", "right_margin", "up_margin", and "down_margin" are all 4000, indicating that the distance between the second device and the upper, lower, left, and right boundaries of the chip layout must not be less than 4000 microns). The size parameters of the second device in the bottom and top sheets can be set based on "shape_config" (for example, "ubm_edge_length:100" indicates that the side length of the indium housing in the top sheet is 100 microns, and "indium_edge_length:0" indicates that no indium housing is set in the bottom sheet). The spacing between the second devices and the distance limit parameters between the second device and the first device can be set based on "placement_config" (for example, "step:200" indicates that the spacing between the indium housings is 200 microns, and the distance between the indium housings and the first device does not exceed 50 microns).

[0125] It should be noted that Figure 7 only uses the target control to control whether all the defect areas on the chip layout support or do not support the layout of the second device. In fact, for multiple first devices of different device types, device structures or device functions, separate controls can also be set to control whether the defect area corresponding to a single first device supports or does not support the layout of the second device.

[0126] (3) Matching the device combination of the first device and the second device with the standard device combination to determine the support of the defect area corresponding to the first device for the layout of the second device.

[0127] For example, the standard device combination is a pre-set device combination that supports the placement of the second device in the defective area of ​​the first device. If the matching is successful, the placement support status is determined to be supported; if the matching is unsuccessful, the placement support status is determined to be not supported.

[0128] Optionally, the first and second components may be matched with a standard component combination based on features such as component type, component position, or component size.

[0129] Referring to FIG8 , FIG8 is a flowchart of laying out a second device on a chip layout according to an exemplary embodiment of the present application. The flowchart includes the following steps:

[0130] Step 810: Obtain a chip layout, on which a first device and a second device are to be arranged.

[0131] Step 820 : Determine a genus region corresponding to the first device in the chip layout based on the first layout parameter of the first device.

[0132] Step 830 : Determine a candidate layout area for the second device in the chip layout based on the second layout parameter.

[0133] Optionally, the second layout parameters include size parameters of the second components, spacing parameters between the second components, and distance limit parameters between the second components and the first component.

[0134] Optionally, based on the second layout parameters, candidate layout areas for the second device may be determined in a chip layout according to a uniform array.

[0135] Step 841 : Based on the device information of the first device, determine the support of the deficient region corresponding to the first device for the layout of the second device.

[0136] The device information includes at least one of device type, device structure and device function.

[0137] For example, if the device type and device structure of the first device are a specific combination, the support of the genus region corresponding to the first device for the placement of the second device can be determined. For example, if the device type is a superconducting qubit and the device structure is a "cross" structure, the placement support is determined to be that the genus region does not support the placement of the second device.

[0138] For example, if the device type and device function of a first device are a specific combination, the support of the genus region corresponding to the first device for the placement of a second device can be determined. For example, if the device type is a pad for a top-sheet test junction and the device function is used to measure the resistance of a bonded junction on a bottom sheet, the placement support condition is determined to be that the genus region supports the placement of the second device.

[0139] In some embodiments, the device type may be obtained based on a category of the first device stored in the computer device. In some embodiments, the device function may be obtained based on user input.

[0140] In some embodiments, the device structure of the first device can be determined based on the first layout parameters. In some embodiments, the first layout parameters of the first device can be matched with reference layout parameters of a reference device, and if the match is successful, the device structure corresponding to the reference device is used as the device structure of the first device.

[0141] The reference device is a device having a device structure stored therein. For example, the reference device may be a standard device stored in a computer device, or another first device having a known device structure.

[0142] Step 842 : Based on the switch state of the target control, determine the support status of the genus region corresponding to the first component for the layout of the second component.

[0143] Optionally, the parameter value of the parameter "cheese_placement_in_genus_region" corresponding to the switch state of the target control can be obtained in the configuration file based on the protobuf protocol to determine the support of the genus region corresponding to the first device for the layout of the second device. For example, a parameter value of 0 indicates that the genus regions corresponding to all the first devices on the chip layout do not support the layout of the second device, and a parameter value of 1 indicates that all the genus regions corresponding to the first devices on the chip layout support the layout of the second device.

[0144] After determining the support status of the genus region corresponding to the first device for the placement of the second device, the second device may be placed in the chip layout based on the placement support status.

[0145] Step 851 : If the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, place the second device in regions of the candidate placement region excluding the intersection.

[0146] Step 852 : If the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or if there is no intersection between the candidate placement region and the genus region, place the second device in the candidate placement region.

[0147] In this embodiment, the support of the defect area for the layout of the second device can be determined through at least one of the device type, device structure or device function of the first device, or through the switching state of the target control, so as to selectively layout or not layout the second device in the defect area, enriching the device layout function of the chip layout and improving the quality of device layout.

[0148] After the second device is laid out in the chip layout, the layout of the second device may be adjusted in some areas (such as increasing the number of second devices and adjusting the layout area of ​​the second device to increase the density of the second device) to improve the quality of device layout.

[0149] In some embodiments, a candidate layout adjustment region of the second device may be determined. The candidate layout adjustment region is a candidate layout region for performing layout adjustment on the second device, wherein the density of the second device after the layout adjustment is higher than the density of the second device before the layout adjustment.

[0150] During the layout adjustment process, certain requirements and restrictions need to be met. In some embodiments, the second layout parameter includes a distance limit parameter between the second device and the first device. After the layout adjustment, the distance between the second device and the first device should still be greater than or equal to the distance limit parameter.

[0151] In a possible scenario, it is necessary to consider the intersection between the candidate layout area and the genus area, and determine the layout adjustment method for the second device based on the intersection.

[0152] If there is no intersection between the candidate placement adjustment region and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first device is greater than or equal to the distance limit parameter, the second device is placed in the candidate placement adjustment region.

[0153] When there is an intersection between the candidate layout adjustment region and the genus region, or when the distance between the candidate layout adjustment region and the layout region of the first device is less than the distance limit parameter, the layout of the second device is not adjusted.

[0154] In a possible scenario, when there is an intersection between the candidate layout adjustment area and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than a distance limit parameter, the candidate layout adjustment area can also be translated according to a certain step size. When there is no intersection between the candidate layout adjustment area and the defect area after translation, and the distance between the candidate layout adjustment area and the layout area of ​​the first device after translation is greater than or equal to the distance limit parameter, the second device can be laid out in the candidate layout adjustment area after translation.

[0155] Refer to FIG. 9 , which is a schematic diagram of translating a candidate layout adjustment area provided by an exemplary embodiment of the present application.

[0156] As shown in Figure 9, a genus region exists inside the first device 901 on the chip layout. After the second device is laid out in the second device layout area (shown as a solid box) on the chip layout, the layout of the second device can be adjusted to increase the density of the second device.

[0157] In order to increase the density of the second device, candidate layout adjustment regions (shown in dotted boxes) of the second device may be determined.

[0158] Since the candidate layout adjustment region and the genus region of the first device 901 intersect, the candidate layout adjustment region may be shifted according to a certain step size.

[0159] In some embodiments, when there is an intersection between the candidate placement adjustment region and the genus region, or when the distance between the candidate placement adjustment region and the placement region of the first device is less than a distance limit parameter, an adjustment step size set may be determined.

[0160] The adjustment step size set includes at least one candidate adjustment step size. For example, the adjustment step size set may be {10 microns, 9 microns, ..., 1 micron}.

[0161] In some embodiments, the candidate placement adjustment area may be shifted based on the i-th candidate adjustment step in the adjustment step set.

[0162] For example, the first candidate adjustment step size of 10 microns in the adjustment step size set is selected, and the candidate layout adjustment area is shifted 10 microns to the left or right.

[0163] If there is no intersection between the candidate placement adjustment region after translation and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first device is greater than or equal to the distance limit parameter, the second device can be placed in the candidate placement adjustment region after translation.

[0164] When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter, the candidate layout adjustment area is re-translated based on the i+1th candidate adjustment step in the adjustment step set... until the second device can be laid out in the translated candidate layout adjustment area, or all candidate adjustment steps in the adjustment step set are traversed.

[0165] For example, in Figure 9, after the candidate layout adjustment area of ​​the second device is shifted to the right based on the candidate adjustment step size of 4 microns, there is no intersection between the candidate layout adjustment area of ​​the second device and the defect area of ​​the first device, and the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter. Therefore, the candidate layout adjustment area after being shifted to the right based on the candidate adjustment step size of 4 microns can be used as the layout area of ​​the second device.

[0166] In some embodiments, after all candidate adjustment step sizes in the adjustment step size set are traversed and a suitable candidate adjustment step size cannot be found so that there is no intersection between the candidate layout adjustment area and the defect area, and the distance between the candidate layout adjustment area and the first device is greater than or equal to the distance limit parameter, the second device can also be laid out according to one of the following schemes.

[0167] (1) The layout of the second device is not adjusted.

[0168] The second component is directly arranged according to the original arrangement area of ​​the second component.

[0169] (2) All candidate layout adjustment regions are translated in a first translation direction according to the i-th candidate adjustment step size in the adjustment step size set, and some candidate layout adjustment regions in the candidate layout adjustment regions are translated in a second translation direction according to the j-th candidate adjustment step size. For example, all candidate layout adjustment regions in FIG. 9 may be horizontally adjusted to the left by 4 microns, while the candidate layout adjustment regions in odd columns may be vertically adjusted upward by 2 microns.

[0170] If there is no intersection between the candidate placement adjustment region after translation and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first device is greater than or equal to the distance limit parameter, the second device can be placed in the candidate placement adjustment region after translation.

[0171] When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the first device is less than the distance limit parameter, the candidate layout adjustment area is re-translated based on the i-th candidate adjustment step and the j+1-th candidate adjustment step in the adjustment step set... until the second device can be laid out in the translated candidate layout adjustment area, or the combination traversal of all i-th candidate adjustment steps and j-th candidate adjustment steps in the adjustment step set is completed.

[0172] In this embodiment, by translating the candidate layout adjustment area based on the candidate adjustment step in the adjustment step set, it can be determined whether there is a suitable layout area in the chip layout, which can not only increase the density of the second device but also meet the distance limit requirements between the first device and the second device.

[0173] In one possible scenario, after the second device is laid out on the chip layout, to better implement the function of the second device, if there is at least one of the following situations: the area of ​​the defective region corresponding to the first device is too large, or the density of the second devices in certain areas is low, the computer device can appropriately add the second device in the defective region without affecting the normal operation of the first device.

[0174] In some embodiments, when the area of ​​the genus region is greater than an area threshold, a second device is added to the genus region, wherein the number of the added second devices is positively correlated with the area of ​​the genus region.

[0175] 10 , which is a schematic diagram illustrating adding a second device in a genus region when the area of ​​the genus region is greater than an area threshold, according to an exemplary embodiment of the present application.

[0176] As shown in Figure 10, second devices are evenly distributed across the chip layout, excluding the first device layout area and the genus region. If the areas of the genus regions corresponding to first device 1001 and first device 1002 are both greater than the area threshold, additional second devices can be added to the genus regions corresponding to first device 1001 and first device 1002. The number of additional second devices in the genus region corresponding to first device 1001 is two, and the number of additional second devices in the genus region corresponding to first device 1002 is eight. The number of additional second devices is positively correlated with the area of ​​the genus region.

[0177] When adding a second device to a defective region, it is also necessary to consider that the distance between the added second device and the existing first device must be greater than or equal to a distance limit parameter. Therefore, to add a second device to a defective region, candidate regions for adding the second device can be determined. If the distance between the candidate region and the first device layout area is greater than or equal to the distance limit parameter, the second device is added to the candidate region.

[0178] The candidate additional region may be a region determined from the genus region based on the second layout parameter (such as a size parameter of the second device).

[0179] In some embodiments, multiple sub-blocks can be determined from the chip layout based on various methods. For example, the chip layout can be divided into multiple rectangular sub-blocks according to a preset side length; or, the chip layout can be irregularly divided to form multiple sub-blocks; or, after determining a sub-block, the sub-block is slid to obtain other sub-blocks in the chip layout, wherein different sub-blocks may intersect or not intersect. In the case where the density of the second device in the sub-block is less than the density threshold, the defect areas in the sub-block can be arranged in descending order of area to obtain a defect area sequence. In the case where the density of the second device in the sub-block is less than the density threshold, the second device is arranged in the defect areas in the defect area sequence in sequence until the density of the second device is greater than or equal to the density threshold.

[0180] 11 , which is a schematic diagram of adding a second device in a genus region when the density of the second devices in a sub-block is less than a density threshold, according to an exemplary embodiment of the present application.

[0181] As shown in FIG11 , a first device 1101 , a first device 1102 , a first device 1103 , a first device 1104 , a first device 1105 and a first device 1106 are arranged in the chip layout.

[0182] In the chip layout, there is a sub-block 1110 , wherein a first device 1101 , a first device 1102 , a first device 1103 , and a first device 1104 are all located within the sub-block 1110 .

[0183] In some embodiments, the placement density of the second device in the sub-block 1110 may be calculated.

[0184] Optionally, the ratio of the layout area of ​​the second device in the sub-block 1110 to the area of ​​the sub-block can be used as the layout density of the second device.

[0185] Assuming that the layout density of the second device in sub-block 1110 is 4.5% and the density threshold is 5%, the genus regions in sub-block 1110 can be arranged in descending order of area to obtain a genus region sequence: genus region A, genus region B, genus region C and genus region D, where genus region A is located inside the first device 1101, genus region B is located inside the first device 1102, genus region C is located inside the first device 1103, and genus region D is located inside the first device 1104.

[0186] In some embodiments, the second devices may be sequentially arranged in the genus regions of the genus region sequence until the density of the second devices is greater than or equal to a density threshold. For example, the second device may be firstly arranged in the genus region A corresponding to the first device 1101 based on second arrangement parameters (e.g., size parameters of the second device, distance limit parameters between the second device and the first device, spacing between the second devices, etc.).

[0187] After adding the second device to genus region A corresponding to first device 1101, the layout density of the second devices in sub-block 1110 (assuming it is 4.8%) is calculated. Since the layout density is still less than the density threshold, the second device can be added to the second genus region in the genus region sequence (i.e., genus region C corresponding to first device 1103).

[0188] Similarly, a second device may be added in the corresponding genus region C of the first device 1103 based on second layout parameters (such as size parameters of the second device, distance limit parameters between the second device and the first device, intervals between second devices, etc.).

[0189] After adding the second device in the genus region C corresponding to the first device 1103 , the layout density of the second devices in the sub-block 1110 (assuming it is 5.1%) is calculated. Since the density threshold has been reached, adding the second device can be stopped.

[0190] For each of the multiple sub-blocks determined from the chip layout, a second device can be added in the above-described manner, such that, for each sub-block, the layout density of the second devices in the sub-block is greater than or equal to a density threshold. In this embodiment, the genus regions in the sub-blocks are arranged in descending order of area to obtain a genus region sequence, and the second devices are sequentially arranged in the genus regions in the genus region sequence until the second device density is greater than or equal to the density threshold. This not only increases the density of the second devices in the sub-blocks on the chip layout, but also reduces the impact of the second devices placed in the genus regions on the first devices. Furthermore, the distance requirement between the first and second devices is met, thereby improving the quality of device layout on the chip layout.

[0191] Referring to FIG12 , FIG12 is a block diagram of a device layout apparatus for a chip layout according to an exemplary embodiment of the present application. The apparatus includes:

[0192] An acquisition module 1201 is configured to acquire a chip layout on which a first device and a second device are to be arranged;

[0193] a determining module 1202 configured to determine a genus region corresponding to the first device in the chip layout based on first layout parameters of the first device, wherein the first layout parameters are parameters used for laying out the first device on the chip layout, and the genus region is a hollow region within the first device in the chip layout;

[0194] A placement module 1203 is configured to place the second device in an area outside the secundum area on the chip layout based on second placement parameters of the second device and the secundum area, if the secundum area does not support placement of the second device. The second placement parameters are parameters used to place the second device on the chip layout.

[0195] Optionally, the first layout parameter includes a layout node sequence, the layout node sequence includes layout nodes connected in sequence, and a connected area formed by the layout nodes connected in sequence is the layout area of ​​the first device. The determination module 1202 is configured to:

[0196] Determining a first connected node and a second connected node in the layout node sequence, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside the connected area;

[0197] Taking the first connected node as a starting point, sequentially traversing the layout nodes in the layout node sequence along a first direction to obtain a first closed curve formed by connecting the layout nodes;

[0198] Taking the second connected node as a starting point, sequentially traversing the layout nodes in the layout node sequence along a second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction;

[0199] The genus region is determined based on the first closed curve and the second closed curve.

[0200] Optionally, the determination module 1202 is configured to:

[0201] determining a layout node having the same node coordinates as the head layout node in the layout node sequence as the first connected node;

[0202] An adjacent node of the first connected node is determined as the second connected node.

[0203] Optionally, the determination module 1202 is configured to:

[0204] When the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as the genus area.

[0205] Optionally, the deployment module 1203 is used to:

[0206] determining a candidate layout area for the second device in the chip layout based on the second layout parameter;

[0207] If the deficient region does not support placement of the second device and there is an intersection between the candidate placement region and the deficient region, the second device is placed in a region other than the intersection among the candidate placement regions.

[0208] Optionally, the deployment module 1203 is used to:

[0209] When the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the second device is placed in the candidate placement region.

[0210] Optionally, the deployment module 1203 is used to:

[0211] Determining, based on device information of the first device, support for placement of the second device by the deficient region corresponding to the first device, wherein the device information includes at least one of device type, device structure, and device function; or

[0212] Based on the switch state of the target control, the support status of the secundum area corresponding to the first component for the layout of the second component is determined, and the target control has a secundum layout control function.

[0213] Optionally, the deployment module 1203 is used to:

[0214] matching the first layout parameters of the first device with reference layout parameters of a reference device;

[0215] If the matching is successful, the device structure corresponding to the reference device is used as the device structure of the first device, wherein the reference device is a device storing the device structure.

[0216] Optionally, the second placement parameter includes a distance limit parameter between the second device and the first device. The placement module 1203 is configured to:

[0217] Determining a candidate layout adjustment region of the second device, where the candidate layout adjustment region is a candidate layout region for performing layout adjustment on the second device, wherein a density of the second device after the layout adjustment is higher than a density of the second device before the layout adjustment;

[0218] When there is no intersection between the candidate placement adjustment area and the genus area, and the distance between the candidate placement adjustment area and the placement area of ​​the first component is greater than or equal to the distance limit parameter, the second component is placed in the candidate placement adjustment area.

[0219] Optionally, the deployment module 1203 is used to:

[0220] determining an adjustment step size set when there is an intersection between the candidate layout adjustment area and the genus area, or when a distance between the candidate layout adjustment area and the layout area of ​​the first component is less than the distance limit parameter, wherein the adjustment step size set includes at least one candidate adjustment step size;

[0221] translating the candidate layout adjustment area based on the i-th candidate adjustment step in the adjustment step set;

[0222] When there is no intersection between the candidate placement adjustment region after translation and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first component is greater than or equal to the distance limit parameter, placing the second component in the candidate placement adjustment region after translation;

[0223] When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter, the candidate layout adjustment area is translated based on the i+1th candidate adjustment step in the adjustment step set.

[0224] Optionally, the deployment module 1203 is configured to perform at least one of the following:

[0225] When the area of ​​the defective region is greater than an area threshold, adding the second device in the defective region, wherein the number of the second devices added is positively correlated with the area of ​​the defective region;

[0226] A sub-block in the chip layout is determined, wherein the sub-block includes at least one genus-deficient region; and when a density of the second devices in the sub-block is less than a density threshold, the second device is added to the genus-deficient region.

[0227] Optionally, the deployment module 1203 is used to:

[0228] determining a candidate additional area for the second device;

[0229] In a case where the distance between the candidate additional area and the layout area of ​​the first component is greater than or equal to the distance limit parameter, the second component is added in the candidate additional area.

[0230] Optionally, the deployment module 1203 is used to:

[0231] Arrange the genus regions in the sub-blocks in descending order of area to obtain a genus region sequence;

[0232] When the density of the second devices in the sub-block is less than a density threshold, the second devices are arranged sequentially in the genus regions in the genus region sequence until the density of the second devices is greater than or equal to the density threshold.

[0233] Referring to FIG. 13 , FIG. 13 is a schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application. Specifically, the computer device 1300 includes a central processing unit (CPU) 1301, a system memory 1304 including a random access memory 1302 and a read-only memory 1303, and a system bus 1305 connecting the system memory 1304 and the CPU 1301. The computer device 1300 also includes a basic input / output system (I / O system) 1306 for facilitating information transmission between various components within the computer, and a mass storage device 1307 for storing an operating system 1313, application programs 1314, and other program modules 1315.

[0234] The basic input / output system 1306 includes a display 1308 for displaying information and an input device 1309, such as a mouse or keyboard, for user input. Both the display 1308 and the input device 1309 are connected to the central processing unit 1301 via an input / output controller 1310 connected to the system bus 1305. The basic input / output system 1306 may also include an input / output controller 1310 for receiving and processing input from a variety of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 1310 also provides output to a display screen, printer, or other types of output devices.

[0235] The mass storage device 1307 is connected to the central processing unit 1301 via a mass storage controller (not shown) connected to the system bus 1305. The mass storage device 1307 and its associated computer-readable media provide non-volatile storage for the computer device 1300. In other words, the mass storage device 1307 may include computer-readable media (not shown) such as a hard disk or drive.

[0236] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, tape cassettes, magnetic tapes, disk storage or other magnetic storage devices. Of course, those skilled in the art will appreciate that the computer storage media are not limited to the above-mentioned ones. The above-mentioned system memory 1304 and mass storage device 1307 can be collectively referred to as memory.

[0237] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 1301. The one or more programs contain computer instructions for implementing the above-mentioned method. The central processing unit 1301 executes the one or more programs to implement the device layout method of the chip layout provided by the above-mentioned various method embodiments.

[0238] According to various embodiments of the present application, the computer device 1300 may also be connected to a remote computer on a network such as the Internet for operation. That is, the computer device 1300 may be connected to a network 1312 via a network interface unit 1311 connected to the system bus 1305. Alternatively, the network interface unit 1311 may be used to connect to other types of networks or remote computer systems (not shown).

[0239] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0240] An embodiment of the present application also provides a computer-readable storage medium, which stores at least one computer instruction. The at least one computer instruction is loaded and executed by a processor to implement the device layout method of the chip layout described in any of the above embodiments.

[0241] Optionally, the computer-readable storage medium may include: ROM, RAM, solid state drives (SSDs) or optical disks, etc. Among them, RAM may include resistance random access memory (ReRAM) and dynamic random access memory (DRAM).

[0242] An embodiment of the present application provides a computer program product comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the device placement method for a chip layout as described in the above embodiment.

[0243] Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware, or by programs instructing related hardware to accomplish the steps. The programs may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0244] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A device layout method for a chip layout, the method being executed by a computer device, the method comprising: Acquire a chip layout, on which a first device and a second device are to be arranged; Determining a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used to layout the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout; When the genus region does not support the layout of the second device, the second device is laid out in an area outside the genus region on the chip layout based on a second layout parameter of the second device and the genus region, the second layout parameter being a parameter used for laying out the second device on the chip layout.

2. The method according to claim 1, wherein: The first layout parameter includes a layout node sequence, the layout node sequence includes layout nodes connected in sequence, and a connected area formed by the layout nodes connected in sequence is a layout area of ​​the first device; The determining, based on the first layout parameter of the first device, a genus region corresponding to the first device in the chip layout includes: Determine a first connected node and a second connected node in the layout node sequence, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside the connected area; Taking the first connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a first direction to obtain a first closed curve formed by connecting the layout nodes; Taking the second connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction; The genus region is determined based on the first closed curve and the second closed curve.

3. The method according to claim 2, wherein: The determining of the first connected node and the second connected node in the arranged node sequence comprises: Determine a layout node having the same node coordinates as the head layout node in the layout node sequence as the first connected node; An adjacent node of the first connected node is determined as the second connected node.

4. The method according to claim 2 or 3, wherein: The determining the genus region based on the first closed curve and the second closed curve comprises: When the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as the genus area.

5. The method according to any one of claims 1 to 4, wherein: The step of arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region includes: Based on the second layout parameters, determining a candidate layout area for the second device in the chip layout; When the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, the second device is placed in a region other than the intersection among the candidate placement regions.

6. The method according to claim 5, wherein: The method further comprises: When the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the second device is placed in the candidate placement region.

7. The method according to claim 5 or 6, wherein: After determining the candidate layout area of ​​the second device in the chip layout based on the second layout parameter, the method further includes: Determining, based on device information of the first device, the support of the deficient region corresponding to the first device for the layout of the second device, wherein the device information includes at least one of a device type, a device structure, and a device function; or, Based on the switch state of the target control, the support status of the layout of the second device by the defect area corresponding to the first device is determined, and the target control has a defect layout control function.

8. The method according to claim 7, wherein: The determining, based on the device information of the first device, the support status of the layout of the second device by the defect area corresponding to the first device includes: matching the first layout parameters of the first device with reference layout parameters of a reference device; When the matching is successful, the device structure corresponding to the reference device is used as the device structure of the first device, wherein the reference device is a device storing the device structure.

9. The method according to any one of claims 1 to 8, wherein: The second layout parameter includes a distance limit parameter between the second device and the first device; After arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region, the method further includes: Determine a candidate layout adjustment region of the second device, where the candidate layout adjustment region is a candidate layout region for performing layout adjustment on the second device, wherein the density of the second device after the layout adjustment is higher than the density of the second device before the layout adjustment; When there is no intersection between the candidate placement adjustment region and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first component is greater than or equal to the distance limit parameter, the second component is placed in the candidate placement adjustment region.

10. The method according to claim 9, wherein: The method further comprises: In the case where there is an intersection between the candidate layout adjustment region and the genus region, or the distance between the candidate layout adjustment region and the layout region of the first device is less than the distance limit parameter, determining an adjustment step set, wherein the adjustment step set includes at least one candidate adjustment step; Based on the i-th candidate adjustment step in the adjustment step set, translating the candidate layout adjustment area; When there is no intersection between the candidate layout adjustment region after translation and the genus region, and the distance between the candidate layout adjustment region and the layout region of the first device is greater than or equal to the distance limit parameter, layout the second device in the candidate layout adjustment region after translation; When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter, the candidate layout adjustment area is translated based on the i+1th candidate adjustment step in the adjustment step set.

11. The method according to any one of claims 1 to 10, wherein: After arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region, the method further includes at least one of the following: When the area of ​​the defective region is greater than the area threshold, the second device is added in the defective region, wherein the number of the second devices added is positively correlated with the area of ​​the defective region; A sub-block in the chip layout is determined, wherein the sub-block includes at least one deficient region; and when the density of the second devices in the sub-block is less than a density threshold, the second device is added in the deficient region.

12. The method according to claim 11, wherein: The second layout parameter includes a distance limit parameter between the second device and the first device, and the adding of the second device in the genus region includes: determining a candidate region for adding the second device; When the distance between the candidate additional region and the layout region of the first component is greater than or equal to the distance limit parameter, the second component is added in the candidate additional region.

13. The method according to claim 11, wherein: When the density of the second devices in the sub-block is less than a density threshold, adding the second devices in the genus region comprises: Arrange the genus regions in the sub-blocks in descending order of area to obtain a genus region sequence; When the density of the second devices in the sub-block is less than a density threshold, the second devices are arranged in the genus regions in the genus region sequence in sequence until the density of the second devices is greater than or equal to the density threshold.

14. A device for placing devices in a chip layout, the device comprising: An acquisition module, used for acquiring a chip layout, on which the first device and the second device are to be arranged; a determination module, configured to determine a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used for laying out the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout; A layout module is used to layout the second device in an area outside the defect area on the chip layout based on a second layout parameter of the second device and the defect area when the defect area does not support the layout of the second device, wherein the second layout parameter is a parameter used to layout the second device on the chip layout.

15. A computer device, comprising a processor and a memory; the memory stores at least one computer instruction, and the at least one computer instruction is used to be executed by the processor to implement the device layout method of the chip layout as described in any one of claims 1 to 13.

16. A computer-readable storage medium, wherein at least one computer instruction is stored in the computer-readable storage medium, wherein the computer instruction is loaded and executed by a processor to implement the device layout method of a chip layout according to any one of claims 1 to 13.

17. A computer program product, comprising computer instructions, wherein the computer instructions are stored in a computer-readable storage medium; a processor of a terminal reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the terminal executes the device layout method of the chip layout as described in any one of claims 1 to 13.

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