High-speed communication method and apparatus of heterogeneous device and heterogeneous communication system

Abstract

The present application relates to the field of communications, and provides a high-speed communication method and apparatus of a heterogeneous device and a heterogeneous communication system. The method comprises: a high-speed interconnection remote virtualization processor receives a high-speed interconnection operation; the high-speed interconnection remote virtualization processor converts the high-speed interconnection operation to a register operation and a memory data migration operation on a heterogeneous accelerator of a target heterogeneous device; the high-speed interconnection remote virtualization processor converts the register operation and the memory data migration operation to a communication request; and the high-speed interconnection remote virtualization processor communicates with the target heterogeneous device by means of the communication request, so as to execute the register operation and the memory data migration operation. The present application achieves the local mapping of the state of a remote heterogeneous device without relying on software and without damaging the performance of the communication device, reducing the communication delay and the occupation of computing resources of the communication device, guaranteeing the communication performance and the operation performance of local application services.

Description

High-speed communication method, device and heterogeneous communication system for heterogeneous devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 4, 2023, with application number 202311127077.0, and application name “A high-speed communication method, device and heterogeneous communication system for heterogeneous devices”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of communications, and in particular to a high-speed communication method and apparatus for heterogeneous devices, a heterogeneous communication system, a non-volatile readable storage medium, and a communication device. Background Art

[0004] Currently, access to remote heterogeneous devices on a host relies on communication software and virtual device drivers. Both of these are software and significantly impact performance. They also need to be converted into multiple application software and virtual device driver operations, significantly increasing processing latency and occupying significant computing resources, impacting the operation of other applications and services.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a high-speed communication method, apparatus, heterogeneous communication system, non-volatile readable storage medium and communication device for heterogeneous devices, virtualizing the operation context of remote heterogeneous devices to a local high-speed interconnected remote virtualization module processor, realizing the mapping of the remote heterogeneous device state to the local, and the high-speed interconnected remote virtualization module processor can perform related operations locally based on the remote state.

[0007] To solve the above technical problems, the present application provides a high-speed communication method for heterogeneous devices, which is applied to a communication device including a high-speed interconnected remote virtualization processor, comprising:

[0008] The high-speed interconnect remote virtualization processor receives the high-speed interconnect operation;

[0009] The high-speed interconnect remote virtualization processor converts high-speed interconnect operations into register operations and memory data movement operations on the heterogeneous accelerator on the target heterogeneous device;

[0010] High-speed interconnected remote virtualization processors convert register operations and memory data movement operations into communication requests;

[0011] The high-speed interconnected remote virtualization processor communicates with the target heterogeneous device through communication requests to perform register operations and memory data movement operations.

[0012] Before the high-speed interconnect remote virtualization processor receives the high-speed interconnect operation, the process further includes:

[0013] After the target heterogeneous device is started, a connection between the high-speed interconnected remote virtualization processor and the target heterogeneous device is established through a high-speed communication link.

[0014] After the target heterogeneous device is started, a connection is established between the high-speed interconnected remote virtualization processor and the target heterogeneous device via a high-speed communication link, and the method further includes:

[0015] The high-speed interconnected remote virtualization processor distributes context information corresponding to the target heterogeneous device.

[0016] The context information corresponding to the high-speed interconnect remote virtualization processor allocation target heterogeneous device includes:

[0017] The memory function data and register-related data corresponding to the target heterogeneous device are distributed on the high-speed interconnected remote virtualization processor.

[0018] After the high-speed interconnect remote virtualization processor allocates context information corresponding to the target heterogeneous device, the following steps are also included:

[0019] The central processing unit on the host sends the high-speed interconnection operation to the high-speed interconnection remote virtualization processor through the high-speed interconnection module.

[0020] The high-speed interconnect remote virtualization processor converts the high-speed interconnect operation into a register operation and a memory data movement operation on the heterogeneous accelerator on the target heterogeneous device, including:

[0021] The high-speed interconnect remote virtualization processor maps the processing unit and the microcode processing unit through high-speed interconnect operations, and converts the high-speed interconnect operations into register operations and memory data movement operations on the heterogeneous accelerator on the target heterogeneous device.

[0022] Among them, also include:

[0023] The microcode processing unit sets corresponding configuration information according to the register information of the target heterogeneous device; the configuration information is used for communication adaptation with the target heterogeneous device.

[0024] Among them, also include:

[0025] The operation context of the target heterogeneous device is virtualized to a local high-speed interconnect remote virtualization processor.

[0026] After the high-speed interconnect remote virtualization processor receives the high-speed interconnect operation instruction, the process further includes:

[0027] The high-speed interconnect remote virtualization processor splits the high-speed interconnect operation instructions into multiple high-performance communication instructions.

[0028] Wherein, if the high-speed interconnect operation instruction includes a read instruction, a write instruction, and a cache instruction, after the high-speed interconnect remote virtualization processor splits the high-speed interconnect operation instruction into multiple high-performance communication instructions, it also includes:

[0029] If the high-speed interconnect operation instruction includes a read instruction;

[0030] Receive a read instruction and allocate corresponding read request memory for the read instruction;

[0031] Read memory data on heterogeneous devices according to read instructions, and respond to read instructions based on the memory data;

[0032] Release read request memory;

[0033] If the high-speed interconnect operation instruction includes a write instruction;

[0034] Receive write instructions and allocate corresponding write request memory;

[0035] Write data to the write request memory and write the write data to the memory on the heterogeneous device through the write operation;

[0036] The high-speed interconnected remote virtualization processor responds to the read request and releases the read request memory;

[0037] If the high-speed interconnect operation instruction includes a cache instruction;

[0038] Receive cache instructions and allocate corresponding cache request memory;

[0039] Request cache memory to write cache data;

[0040] Write the cache data in the cache request memory to the memory on the heterogeneous device through a write operation, and update the cache status of the heterogeneous device;

[0041] The cache data is read to the memory on the high-speed interconnect remote virtualization processor through a read operation; the high-speed interconnect remote virtualization processor then releases the cache request memory and synchronizes the virtualization cache state.

[0042] After the high-speed interconnect remote virtualization processor allocates context information corresponding to the target heterogeneous device, the following steps are also included:

[0043] Determine the accessible memory address range of the target heterogeneous device based on the context information.

[0044] Among them, also include:

[0045] The high-speed interconnect remote virtualization processor updates context information on the high-speed interconnect remote virtualization processor according to the device state of the target heterogeneous device.

[0046] Among them, also include:

[0047] The high-speed interconnect remote virtualization processor utilizes an input and output protocol based on a high-speed interconnect protocol to perform input and output data transmission with a target heterogeneous device.

[0048] Among them, also include:

[0049] The high-speed interconnect remote virtualization processor uses the system memory protocol based on the high-speed interconnect protocol to access the memory of the central processor.

[0050] Among them, also include:

[0051] The high-speed interconnect remote virtualization processor uses a system memory protocol based on a high-speed interconnect protocol to achieve sharing of the central processing unit and graphics card memory.

[0052] The present application also provides a heterogeneous communication system, including:

[0053] A host, a switch with high-speed communication capabilities, and at least one heterogeneous device connected in sequence;

[0054] The host includes a central processing unit, a high-speed interconnection module and a high-speed interconnection remote virtualization module;

[0055] The host is configured to perform the following operations via a high-speed interconnect remote virtualization processor located on the host;

[0056] Convert high-speed interconnect operations into register operations and memory data movement operations on heterogeneous accelerators on heterogeneous devices; convert register operations and memory data movement operations into communication requests; communicate with heterogeneous devices through communication requests to perform register operations and memory data movement operations.

[0057] Among them, the high-speed interconnect remote virtualization processor includes:

[0058] The microcode processing unit is used to set corresponding configuration information according to the register information of the target heterogeneous device; the configuration information is used to adapt the communication with the target heterogeneous device.

[0059] Among them, the high-speed interconnect remote virtualization processor includes:

[0060] The context information management unit is used to allocate context information corresponding to the target heterogeneous device.

[0061] The context information management unit is further configured to update the context information on the high-speed interconnected remote virtualization processor according to the device status of the target heterogeneous device.

[0062] The present application also provides a high-speed communication device for heterogeneous devices, which is applied to a communication device including a high-speed interconnected remote virtualization processor, comprising:

[0063] A receiving module, configured to receive high-speed interconnect operations;

[0064] An operation conversion module, configured to convert high-speed interconnect operations into register operations and memory data movement operations on heterogeneous accelerators on target heterogeneous devices;

[0065] Request conversion module, used to convert register operations and memory data movement operations into communication requests;

[0066] The communication module is used to communicate with the target heterogeneous device through communication requests to perform register operations and memory data movement operations.

[0067] Among them, also include:

[0068] The establishment module is used to establish a connection between the high-speed interconnected remote virtualization processor and the target remote heterogeneous device through a high-speed communication link after the target heterogeneous device is started.

[0069] Among them, also include:

[0070] The allocation module is used to allocate context information corresponding to the target remote heterogeneous device after the target heterogeneous device is started and a connection is established between the high-speed interconnected remote virtualization processor and the target remote heterogeneous device through a high-speed communication link.

[0071] Among them, the allocation module includes:

[0072] The allocation unit is used to allocate memory function data and register related data corresponding to the target remote heterogeneous device.

[0073] Among them, also include:

[0074] The connection module is used to distribute the context information corresponding to the target remote heterogeneous device and then send the high-speed interconnection operation to the high-speed interconnection remote virtualization processor through the high-speed interconnection module.

[0075] The operation conversion module includes:

[0076] The conversion unit is used to map the processing unit and the microcode processing unit through high-speed interconnect operations, and convert the high-speed interconnect operations into register operations and memory data movement operations on the heterogeneous accelerator on the target heterogeneous device.

[0077] Among them, also include:

[0078] The configuration information setting module is used to set corresponding configuration information according to the register information of the target remote heterogeneous device through the microcode processing unit; the configuration information is used for communication adaptation with the target remote heterogeneous device.

[0079] Among them, also include:

[0080] The virtualization module is used to virtualize the operation context of the target remote heterogeneous device to a local high-speed interconnected remote virtualization processor.

[0081] Among them, also include:

[0082] The splitting module is used for splitting the high-speed interconnection operation instruction into multiple high-performance communication instructions if the high-speed interconnection remote virtualization processor receives the high-speed interconnection operation instruction.

[0083] Among them, also include:

[0084] A read processing module is configured to: if the high-speed interconnect operation instruction includes a read instruction; receive the read instruction, allocate a corresponding read request memory for the read instruction; read memory data on the heterogeneous device according to the read instruction, and respond to the read instruction based on the memory data; and release the read request memory;

[0085] A write processing module is configured to: if the high-speed interconnect operation instruction includes a write instruction; receive the write instruction, allocate a corresponding write request memory; write data to the write request memory, and write the write data to the memory on the heterogeneous device through a write operation; the high-speed interconnect remote virtualization processor responds to the read request and releases the read request memory;

[0086] The cache processing module is used to receive the cache instruction if the high-speed interconnect operation instruction includes a cache instruction, allocate a corresponding cache request memory, and write cache data to the cache request memory;

[0087] The cache data in the cache request memory is written to the memory on the heterogeneous device through a write operation, and the cache status of the heterogeneous device is updated; the cache data is read to the memory on the high-speed interconnected remote virtualization processor through a read operation; the high-speed interconnected remote virtualization processor then releases the cache request memory and synchronizes the virtualization cache status.

[0088] Among them, also include:

[0089] The determination module is configured to allocate context information corresponding to the target remote heterogeneous device and then determine an accessible memory address range of the target remote heterogeneous device according to the context information.

[0090] Among them, also include:

[0091] The update module is used to update the context information on the high-speed interconnected remote virtualization processor according to the device status of the target heterogeneous device.

[0092] Among them, also include:

[0093] The transmission module is used to perform input and output data transmission with the target heterogeneous device using an input and output protocol based on a high-speed interconnection protocol.

[0094] Among them, also include:

[0095] The access module is used to access the memory of the central processing unit by utilizing a system memory protocol based on a high-speed interconnection protocol.

[0096] Among them, also include:

[0097] The sharing module is used to realize the sharing of the central processing unit and the graphics card memory by utilizing the system memory protocol based on the high-speed interconnection protocol.

[0098] The present application also provides a non-volatile readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0099] The present application also provides a communication device, including a memory and a processor, wherein a computer program is stored in the memory, and the steps of the above method are implemented when the processor calls the computer program in the memory.

[0100] The present application provides a high-speed communication method for heterogeneous devices, which is applied to a communication device including a high-speed interconnect remote virtualization processor, comprising: the high-speed interconnect remote virtualization processor receiving a high-speed interconnect operation; the high-speed interconnect remote virtualization processor converting the high-speed interconnect operation into a register operation and a memory data movement operation on a heterogeneous accelerator on a target heterogeneous device; the high-speed interconnect remote virtualization processor converting the register operation and the memory data movement operation into a communication request; and the high-speed interconnect remote virtualization processor communicating with the target heterogeneous device via the communication request to execute the register operation and the memory data movement operation.

[0101] In the present application, the local communication device can access the near-end and far-end heterogeneous accelerators indiscriminately through the high-speed interconnected remote virtualization processor. The remote accelerator only needs to support conventional high-performance communication standards without adding additional hardware requirements. The high-speed interconnection operation is converted into register operation and memory data movement operation of the heterogeneous accelerator, realizing the conversion of the high-speed interconnection operation to the traditional high-speed communication mode. The remote heterogeneous device operation context is virtualized to the local high-speed interconnected remote virtualization module processor to realize the mapping of the remote heterogeneous device state to the local. The high-speed interconnected remote virtualization module processor can perform related operations locally according to the remote state, which is equivalent to the central processing unit in the local communication device accessing the high-speed interconnected remote virtualization module processor by accessing the local heterogeneous accelerator. It does not have to rely on software and has no performance damage to the communication device. It reduces the communication delay and the computing resource occupation of the communication device, and ensures the communication performance and local application business operation performance.

[0102] The present application also provides a high-speed communication device for heterogeneous devices, a heterogeneous communication system, a non-volatile readable storage medium and a communication device, which have the above-mentioned beneficial effects and are not repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0104] FIG1 is a schematic diagram of an access structure between a host and a remote heterogeneous device provided in an embodiment of the present application;

[0105] FIG2 is a flow chart of a high-speed communication method for heterogeneous devices provided in an embodiment of the present application;

[0106] FIG3 is a schematic diagram of functional layer offloading of high-speed communication of heterogeneous devices provided in an embodiment of the present application;

[0107] FIG4 is a schematic diagram of a network logic for high-speed communication of heterogeneous devices provided in an embodiment of the present application;

[0108] FIG5 is a schematic diagram of a structure of a heterogeneous device hybrid network provided in an embodiment of the present application;

[0109] FIG6 is a schematic structural diagram of a high-speed communication device for heterogeneous devices provided in an embodiment of the present application;

[0110] FIG7 is a schematic structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0111] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0112] Access to near-end heterogeneous devices can be achieved using Compute Express Link (CXL), a new interconnect technology standard that enables high-speed and efficient interconnection between the CPU and GPUs (graphics processing units), FPGAs (Field Programmable Gate Arrays), or other accelerators, thereby meeting the requirements of high-performance heterogeneous computing. It also maintains consistency between the CPU memory space and the memory of connected devices. CXL enables high-performance, low-CPU utilization heterogeneous accelerator access. However, access to remote heterogeneous devices is more difficult because CXL requires hardware support to meet performance requirements (similar to 5G, 5G support requires a 5G mobile phone). Heterogeneous accelerators generally do not support CXL remote access.

[0113] To virtualize remote heterogeneous devices, it is necessary to connect to the remote heterogeneous accelerator through communication software APIs (such as RDMA verbs and sockets), send instructions through the communication software to complete access to the heterogeneous device, and then encapsulate the operations on the remote heterogeneous device in the driver to complete the virtualization of the remote heterogeneous device. This access efficiency is low.

[0114] Referring to FIG1 , FIG1 is a schematic diagram of the access structure between the host and the remote heterogeneous device provided in an embodiment of the present application. As can be seen from FIG1 , the host's access to the remote heterogeneous device requires reliance on communication software and virtual device drivers. The basic access operations of the host's central processing unit to the remote heterogeneous device must be converted into multiple application software and virtual device driver operations, which significantly damages performance. In addition, the host needs to distinguish between proximal and remote heterogeneous accelerators and process different devices through different logic. Because operations need to be performed through virtualization drivers and communication software, the complexity of logical processing is increased. The remote accelerator and the central processing unit are not in the same host, while the proximal accelerator and the central processing unit are in the same host. When the device is registered with the operating system, if it is connected via local PCIE mode, it can be determined as a proximal heterogeneous accelerator when the PCIE device is registered. When the remote device is registered through the virtualization driver device, it can be determined as a remote heterogeneous accelerator.

[0115] As a result, host access to remote heterogeneous devices relies on software such as communication software and virtual device drivers, significantly impacting performance. Furthermore, since application software and virtual device drivers are software, they consume significant CPU computing resources, preventing valuable CPU resources from being used for application processing. Furthermore, basic access operations by the host CPU to remote heterogeneous devices must be converted into multiple application software and virtual device driver operations, significantly increasing processing latency. Furthermore, the host needs to distinguish between near-end and far-end heterogeneous accelerators, increasing the complexity of logical processing.

[0116] To solve the above technical problems, refer to FIG2 , which is a flow chart of a high-speed communication method for heterogeneous devices provided in an embodiment of the present application. The method specifically includes:

[0117] S101: A high-speed interconnect remote virtualization processor receives a high-speed interconnect operation.

[0118] The high-speed interconnect remote virtualization module processor is a chip or accelerator card on the host or local device. Its main function is to split high-speed interconnect operation requests into multiple instructions for other high-performance communication technologies (such as IB instructions, the full English name is InfiniBand, Chinese name is InfiniBand instructions) and maintain the relevant context of high-speed interconnect operations, such as cache information. The high-speed interconnect operations in this step are CXL operations.

[0119] This embodiment assumes that a connection between the high-speed interconnected remote virtualization processor and the target heterogeneous device has already been established before executing this step. Of course, the essence of this connection process is the connection between the host or local device containing the high-speed interconnected remote virtualization processor and the target heterogeneous device. In particular, the target heterogeneous device can be a remote heterogeneous device, thereby enabling remote communication.

[0120] Furthermore, after the target heterogeneous device boots up and a connection is established between the high-speed interconnect remote virtualization processor and the target heterogeneous device via a high-speed communication link, the high-speed interconnect remote virtualization processor can also distribute context information corresponding to the target heterogeneous device. Specifically, the high-speed interconnect remote virtualization processor can allocate memory function data and register-related data corresponding to the target heterogeneous device. Since CXL is a set of functional modules for accessing memory data on heterogeneous acceleration devices, divided into three major sub-protocols: CXL.mem, CXL.cache, and CXL.io, CXL is a hardware-implemented heterogeneous device memory access application. Therefore, CXL requests cannot completely correspond to communication functions and inevitably involve some functions related to memory, cache, and data synchronization. These functions are converted into a series of data and register reads, writes, and modifications based on the internal implementation of the heterogeneous device. Therefore, if the high-speed interconnect remote virtualization processor receives a high-speed interconnect operation instruction, it can also split the high-speed interconnect operation instruction into multiple high-performance communication instructions. During the specific splitting, the high-speed interconnect remote virtualization processor may split the high-speed interconnect operation instruction into multiple high-performance communication instructions according to at least one of the memory configuration, cache configuration, register configuration and data synchronization setting.

[0121] Currently, the only way to connect to a remote heterogeneous accelerator is through communication software APIs (such as RDMA verbs and sockets). Accessing the heterogeneous device is accomplished by sending commands through the communication software. This encapsulates remote heterogeneous device operations within the driver, completing the virtualization of the remote heterogeneous device. However, this process not only fails to achieve cache coherence, but also requires upper-layer applications to modify the application software logic to achieve cache coherence. Therefore, existing technologies do not support cache-related commands, which leads to poor performance in accessing remote heterogeneous devices.

[0122] Taking the current read instruction as an example, it includes the following process:

[0123] 1. The host application calls the system device API;

[0124] 2. The host system calls the virtualized device driver;

[0125] 3. The host virtualization device driver calls the high-speed communication API;

[0126] 4. Read the data back from the memory on the heterogeneous device through the IB RDMA verbs read operation;

[0127] 5. After reading is completed, return to the software stack step by step.

[0128] When the embodiment of the present application specifically splits the high-speed interconnect operation instructions, it can split them into read instructions, write instructions and cache instructions. These three instructions can usually be split together, or any one or a combination of any two of them can be obtained.

[0129] The following describes the split processing process using read instructions, write instructions, and cache instructions as examples:

[0130] If the high-speed interconnect operation instruction includes a read instruction, the steps may include:

[0131] Receive a read instruction and allocate corresponding read request memory for the read instruction;

[0132] Read memory data on heterogeneous devices according to read instructions, and respond to read instructions based on the memory data;

[0133] Releases read request memory.

[0134] It can be seen that this embodiment targets read instructions in high-speed interconnect operation instructions. There is no need to call various APIs and virtualized device drivers. It only needs to allocate corresponding memory to execute read instructions. It does not involve calling many APIs and complex operations, which greatly improves access performance.

[0135] If the high-speed interconnect operation instruction includes a write instruction, the steps may include:

[0136] Receive write instructions and allocate corresponding write request memory;

[0137] Write data to the write request memory and write the write data to the memory on the heterogeneous device through the write operation;

[0138] The high-speed interconnected remote virtualization processor responds to the read request and releases the read request memory;

[0139] If the high-speed interconnect operation instruction includes a cache instruction, the steps may include:

[0140] Receive cache instructions and allocate corresponding cache request memory;

[0141] Request cache memory to write cache data;

[0142] Write the cache data in the cache request memory to the memory on the heterogeneous device through a write operation, and update the cache status of the heterogeneous device;

[0143] Read cache data to the memory on the remote virtualization processor via a high-speed interconnection through a read operation;

[0144] Thereafter, the high-speed interconnected remote virtualization processor releases the cache request memory and synchronizes the virtualization cache state.

[0145] Context information is intermediate data for CXL-related functions, such as the accessible memory address range of a remote heterogeneous device. Therefore, the accessible memory address range of the target heterogeneous device can be determined based on this context information. Simultaneously, the target heterogeneous device's operational context can be virtualized to a local high-speed interconnect remote virtualization processor. It should be noted that this context information is not necessarily exposed; the high-speed interconnect remote virtualization processor can update the context information based on the device status of the target heterogeneous device.

[0146] S102: The high-speed interconnect remote virtualization processor converts the high-speed interconnect operation into a register operation and a memory data movement operation on the heterogeneous accelerator on the target heterogeneous device.

[0147] S103: The high-speed interconnect remote virtualization processor converts the register operation and the memory data movement operation into a communication request.

[0148] S104: The high-speed interconnected remote virtualization processor communicates with the target heterogeneous device through a communication request to perform register operations and memory data movement operations.

[0149] During step S102, the high-speed interconnect operation mapping processing unit and the microcode processing unit can be used to convert the high-speed interconnect operation into register operations and memory data movement operations for the heterogeneous accelerator on the target heterogeneous device. The microcode processing unit can also set corresponding configuration information based on the register information of the target heterogeneous device; this configuration information is used to adapt communication with the target heterogeneous device. Specifically, the high-speed interconnect remote virtualization module processor can be equipped with a microcode processing unit to provide simple configurability to adapt to the implementation differences of different heterogeneous accelerator cards.

[0150] After obtaining the register operation and memory data movement operation, they can be integrated into a communication request and communicate with the target heterogeneous device through the native high-speed communication protocol to perform the register operation and memory data movement operation.

[0151] Local communication equipment can access near-end and far-end heterogeneous accelerators without distinction through high-speed interconnected remote virtualization processors. Remote accelerators only need to support conventional high-performance communication standards without additional hardware requirements. High-speed interconnect operations are converted into register operations and memory data movement operations on heterogeneous accelerators, realizing the conversion of high-speed interconnect operations to traditional high-speed communication methods. The operation context of remote heterogeneous devices is virtualized to the local high-speed interconnected remote virtualization module processor to realize the mapping of remote heterogeneous device states to local ones. The high-speed interconnected remote virtualization module processor can perform related operations locally based on the remote state, which is equivalent to the central processing unit in the local communication device accessing the high-speed interconnected remote virtualization module processor by accessing the local heterogeneous accelerator. There is no need to rely on software, there is no performance damage to the communication device, the communication delay and the computing resource usage of the communication device are reduced, and the communication performance and local application business operation performance are guaranteed.

[0152] Based on the above embodiment, after the high-speed interconnect remote virtualization processor allocates context information corresponding to the target heterogeneous device, the central processor on the host can send the high-speed interconnect operation to the high-speed interconnect remote virtualization processor through the high-speed interconnect module.

[0153] Taking InfiniBand instructions as an example, if applied to a remote heterogeneous device, the corresponding complete execution process can be as follows:

[0154] (1) Remote heterogeneous devices are started by connecting to high-speed interconnected remote virtualization module processors through high-speed communication technology.

[0155] (2) Remote heterogeneous devices register their own information and allocate corresponding context information on the high-speed interconnected remote virtualization module processor.

[0156] (3) The host central processing unit transmits the high-speed interconnection operation to the high-speed interconnection remote virtualization module processor through the high-speed interconnection interface.

[0157] (4) High-speed interconnection The remote virtualization module processor receives high-speed interconnection operations.

[0158] (5) The high-speed interconnect remote virtualization module processor maps the processing unit and the remote heterogeneous device microcode processing unit through the high-speed interconnect operation, converting the high-speed interconnect operation into the register operation and memory data movement operation of the heterogeneous accelerator.

[0159] (6) The high-speed interconnect remote virtualization module processor updates the remote heterogeneous device context information on the high-speed interconnect remote virtualization module processor according to the heterogeneous device status.

[0160] (7) The high-speed interconnected remote virtualization module processor converts register operations and memory data movement operations into IB communication requests.

[0161] (8) High-speed interconnected remote virtualization module processors communicate with heterogeneous devices through the InfiniBand protocol to complete register operations and memory data movement operations.

[0162] (9) Complete high-speed interconnection operations.

[0163] In step (1), the remote heterogeneous device is connected to the high-speed interconnection remote virtualization module processor of the host through high-speed communication technology. After that, the remote heterogeneous device needs to be registered so that the high-speed interconnection remote virtualization module processor can identify it as a near-end device or a remote device. During registration, the high-speed interconnection remote virtualization module processor allocates context information for it. After that, the remote heterogeneous device sends the high-speed interconnection operation, and the central processing unit of the host sends the high-speed interconnection operation to the high-speed interconnection remote virtualization module processor, virtualizing the remote heterogeneous device operation context to the local high-speed interconnection remote virtualization module processor, realizing the mapping of the remote heterogeneous device state to the local, and the high-speed interconnection remote virtualization module processor can perform related operations locally according to the state of the remote heterogeneous device. The subsequent process can be referred to above and will not be repeated here.

[0164] Referring to FIG3 , FIG3 is a functional hierarchical offloading diagram of high-speed communication of heterogeneous devices provided by an embodiment of the present application. Taking a field programmable gate array as an example of a heterogeneous device, in order to more clearly demonstrate the functional role of the high-speed interconnect remote virtualization processor in the communication process using the InfiniBand protocol as an example, the high-speed interconnect remote virtualization processor is displayed independently. In actual applications, it should be located above the host. The high-speed interconnect remote virtualization processor may include a high-speed interconnect context management unit for allocating or updating context information of remote heterogeneous devices. The high-speed interconnect operation mapping processing unit is based on the InfiniBand protocol. At the same time, the high-speed interconnect operation mapping processing unit and the microcode processing unit are used to perform conversion of high-speed interconnect operations, thereby obtaining register operations and memory data movement operations, which are then communicated based on the wireless bandwidth interface and transmitted to the heterogeneous devices.

[0165] CXL is an open standard for high-speed CPU-to-device and CPU-to-memory connections, specifically designed for high-performance data center computers. It supports not only I / O device interconnection but also memory and cache interconnection. This interconnection standard supports three protocols:

[0166] CXL.io: This protocol is functionally equivalent to the PCIe 5.0 protocol and serves as I / O transmission between devices.

[0167] CXL.memory: This protocol primarily breaks down memory sharing between the CPU and other devices. For example, if the CPU is connected to a graphics card via CXL, this protocol allows the CPU to access the graphics card's video memory, and the graphics card to access the CPU's memory. The graphics card accesses the CPU's memory via the CXL.Cache protocol.

[0168] CXL.Cache: This protocol is designed for more specific applications and enables accelerators to efficiently access the main CPU's cache memory to optimize performance.

[0169] Correspondingly, the high-speed interconnect remote virtualization processor can utilize the input and output protocols based on the high-speed interconnect protocol to perform input and output data transmission with the target heterogeneous device. Simultaneously, the high-speed interconnect remote virtualization processor can also utilize the system memory protocol based on the high-speed interconnect protocol to access the CPU's memory, and can also utilize the system memory protocol based on the high-speed interconnect protocol to enable sharing of CPU and graphics card memory.

[0170] In summary, it can be seen that in the embodiments of the present application, the host central processing unit accesses the remote heterogeneous accelerator through the high-speed interconnect remote virtualization module technology, and the central processing unit accesses the high-speed interconnect remote virtualization module processor in the same way as accessing the local heterogeneous accelerator. The entire access process is offloaded by the high-speed interconnect remote virtualization module processor. The present application can also convert high-speed interconnect operations into register operations and memory data movement operations of the heterogeneous accelerator, realizing the conversion of high-speed interconnect operations to native high-speed communication methods, while providing certain programmable and configurable capabilities to adapt to the differences between different remote heterogeneous devices.

[0171] Referring to FIG. 4 , FIG. 4 is a network logic diagram of high-speed communication of heterogeneous devices provided in an embodiment of the present application. The present application also provides a heterogeneous communication system, including:

[0172] A host, a switch with high-speed communication capabilities, and at least one heterogeneous device connected in sequence;

[0173] The host includes a central processing unit, a high-speed interconnection module and a high-speed interconnection remote virtualization module;

[0174] The host is configured to perform the following operations via a high-speed interconnect remote virtualization processor located on the host;

[0175] Convert high-speed interconnect operations into register operations and memory data movement operations on heterogeneous accelerators on heterogeneous devices; convert register operations and memory data movement operations into communication requests; communicate with heterogeneous devices through communication requests to perform register operations and memory data movement operations.

[0176] The switch only requires support for high-speed communication infrastructure, and mainly requires hardware optimization of the host and heterogeneous devices to support CXL operations.

[0177] In a feasible embodiment, the high-speed interconnect remote virtualization processor includes:

[0178] The microcode processing unit is used to set corresponding configuration information according to the register information of the target heterogeneous device; the configuration information is used to adapt the communication with the target heterogeneous device.

[0179] In other feasible embodiments, the high-speed interconnect remote virtualization processor may include a context information management unit, where the context information management unit is used to allocate context information corresponding to the target heterogeneous device.

[0180] In a feasible embodiment, the context information management unit is further configured to update the context information on the high-speed interconnect remote virtualization processor according to the device status of the target heterogeneous device.

[0181] See Figure 5, which is a structural diagram of the hybrid networking of heterogeneous devices provided in an embodiment of the present application. In addition to the wireless bandwidth protocol, the high-speed communication method for heterogeneous devices provided in this application can also be applied to all heterogeneous accelerators, including but not limited to RoCE (RDMA over Converged Ethernet, remote direct access memory communication), NVLink (NVIDIA high-speed interconnect protocol), private protocols of major manufacturers, etc. In addition, it is also possible to achieve the hybrid networking of different communication technologies and different types of accelerators, further improve the system compatibility, and achieve more hybrid networking of devices with different standards. It can be seen that this application can achieve the hybrid networking of different communication technologies and different types of accelerators, further improving the system compatibility.

[0182] 6 , the present application further provides a high-speed communication apparatus for heterogeneous devices, which is applied to a communication device including a high-speed interconnected remote virtualization processor, including:

[0183] A receiving module, configured to receive high-speed interconnect operations;

[0184] An operation conversion module, configured to convert high-speed interconnect operations into register operations and memory data movement operations on heterogeneous accelerators on target heterogeneous devices;

[0185] Request conversion module, used to convert register operations and memory data movement operations into communication requests;

[0186] The communication module is used to communicate with the target heterogeneous device through communication requests to perform register operations and memory data movement operations.

[0187] The high-speed communication device for heterogeneous devices provided in this embodiment allows local communication devices to access local and remote heterogeneous accelerators without distinction through a high-speed interconnected remote virtualization processor. The remote accelerator only needs to support conventional high-performance communication standards without additional hardware requirements. The high-speed interconnection operation is converted into register operations and memory data movement operations on the heterogeneous accelerator, thereby realizing the conversion of high-speed interconnection operations to traditional high-speed communication methods. The operation context of the remote heterogeneous device is virtualized to the local high-speed interconnected remote virtualization module processor to realize the mapping of the remote heterogeneous device state to the local. The high-speed interconnected remote virtualization module processor can perform related operations locally based on the remote state, which is equivalent to the central processing unit in the local communication device accessing the high-speed interconnected remote virtualization module processor by accessing the local heterogeneous accelerator. There is no need to rely on software, there is no performance damage to the communication device, the communication delay and the computing resource occupation of the communication device are reduced, and the communication performance and local application business operation performance are guaranteed.

[0188] Based on the above embodiment, the present invention further includes:

[0189] The establishment module is used to establish a connection between the high-speed interconnected remote virtualization processor and the target remote heterogeneous device through a high-speed communication link after the target heterogeneous device is started.

[0190] Based on the above embodiment, the present invention further includes:

[0191] The allocation module is used to allocate context information corresponding to the target remote heterogeneous device after the target heterogeneous device is started and a connection is established between the high-speed interconnected remote virtualization processor and the target remote heterogeneous device through a high-speed communication link.

[0192] Based on the above embodiment, the allocation module includes:

[0193] The allocation unit is used to allocate memory function data and register related data corresponding to the target remote heterogeneous device.

[0194] Based on the above embodiment, other feasible embodiments further include:

[0195] The connection module is used to distribute the context information corresponding to the target remote heterogeneous device and then send the high-speed interconnection operation to the high-speed interconnection remote virtualization processor through the high-speed interconnection module.

[0196] Based on the above embodiment, the operation conversion module includes:

[0197] The conversion unit is used to map the processing unit and the microcode processing unit through high-speed interconnect operations, and convert the high-speed interconnect operations into register operations and memory data movement operations on the heterogeneous accelerator on the target heterogeneous device.

[0198] Based on the above embodiment, other feasible embodiments further include:

[0199] The configuration information setting module is used to set corresponding configuration information according to the register information of the target remote heterogeneous device through the microcode processing unit; the configuration information is used for communication adaptation with the target remote heterogeneous device.

[0200] Based on the above embodiment, other feasible embodiments further include:

[0201] The virtualization module is used to virtualize the operation context of the target remote heterogeneous device to a local high-speed interconnected remote virtualization processor.

[0202] Based on the above embodiment, other feasible embodiments further include:

[0203] The splitting module is used for splitting the high-speed interconnection operation instruction into multiple high-performance communication instructions if the high-speed interconnection remote virtualization processor receives the high-speed interconnection operation instruction.

[0204] Based on the above embodiment, if a split module is included, the following may also be included:

[0205] A read processing module is configured to: if the high-speed interconnect operation instruction includes a read instruction; receive the read instruction, allocate a corresponding read request memory for the read instruction; read memory data on the heterogeneous device according to the read instruction, and respond to the read instruction based on the memory data; and release the read request memory;

[0206] A write processing module is configured to: if the high-speed interconnect operation instruction includes a write instruction; receive the write instruction, allocate a corresponding write request memory; write data to the write request memory, and write the write data to the memory on the heterogeneous device through a write operation; the high-speed interconnect remote virtualization processor responds to the read request and releases the read request memory;

[0207] The cache processing module is used to receive the cache instruction if the high-speed interconnect operation instruction includes a cache instruction, allocate a corresponding cache request memory, and write cache data to the cache request memory;

[0208] The cache data in the cache request memory is written to the memory on the heterogeneous device through a write operation, and the cache status of the heterogeneous device is updated; the cache data is read to the memory on the high-speed interconnected remote virtualization processor through a read operation; the high-speed interconnected remote virtualization processor then releases the cache request memory and synchronizes the virtualization cache status.

[0209] Based on the above embodiment, other feasible embodiments further include:

[0210] The determination module is configured to allocate context information corresponding to the target remote heterogeneous device and then determine an accessible memory address range of the target remote heterogeneous device according to the context information.

[0211] Based on the above embodiment, other feasible embodiments further include:

[0212] The update module is used to update the context information on the high-speed interconnected remote virtualization processor according to the device status of the target heterogeneous device.

[0213] Based on the above embodiment, other feasible embodiments further include:

[0214] The transmission module is used to perform input and output data transmission with the target heterogeneous device using an input and output protocol based on a high-speed interconnection protocol.

[0215] Based on the above embodiment, other feasible embodiments further include:

[0216] The access module is used to access the memory of the central processing unit by utilizing a system memory protocol based on a high-speed interconnection protocol.

[0217] Based on the above embodiment, other feasible embodiments further include:

[0218] The sharing module is used to realize the sharing of the central processing unit and the graphics card memory by utilizing the system memory protocol based on the high-speed interconnection protocol.

[0219] The present application also provides a non-volatile readable storage medium having a computer program stored thereon, which, when executed, can implement the steps provided in the above embodiment. The non-volatile readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0220] The present application also provides a communication device. Referring to FIG. 7 , a structural diagram of a communication device provided in an embodiment of the present application, as shown in FIG. 7 , may include a processor 1410 and a memory 1420 .

[0221] The processor 1410 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1410 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 1410 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1410 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1410 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0222] The memory 1420 may include one or more non-volatile readable storage media, which may be non-transitory. The memory 1420 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 1420 is used to store at least the following computer program 1421, wherein, after the computer program is loaded and executed by the processor 1410, it can implement the relevant steps in the high-speed communication method of heterogeneous devices executed by the communication device side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 1420 may also include an operating system 1422 and data 1423, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 1422 may include Windows, Linux, Android, etc.

[0223] In some embodiments, the communication device may further include a display screen 1430 , an input / output interface 1440 , a communication interface 1450 , a sensor 1460 , a power supply 1470 , and a communication bus 1480 .

[0224] Of course, the structure of the communication device shown in FIG7 does not constitute a limitation on the communication device in the embodiment of the present application. In actual applications, the communication device may include more or fewer components than those shown in FIG7, or combine certain components.

[0225] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems provided in the embodiments, since they correspond to the methods provided in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0226] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the method and core ideas of this application. It should be noted that for those skilled in the art, without departing from the principles of this application, various improvements and modifications can be made to this application, and such improvements and modifications also fall within the scope of protection of the claims of this application.

[0227] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A high-speed communication method for heterogeneous devices, characterized in that: Applicable to communication equipment containing high-speed interconnect remote virtualization processors, including: The high-speed interconnect remote virtualization processor receives a high-speed interconnect operation; The high-speed interconnect remote virtualization processor converts the high-speed interconnect operation into a register operation and a memory data movement operation on a heterogeneous accelerator on a target heterogeneous device; The high-speed interconnect remote virtualization processor converts the register operation and the memory data moving operation into a communication request; The high-speed interconnect remote virtualization processor communicates with the target heterogeneous device through the communication request to perform the register operation and the memory data movement operation.

2. The high-speed communication method according to claim 1, characterized in that: Before the high-speed interconnect remote virtualization processor receives the high-speed interconnect operation, the process further includes: After the target heterogeneous device is started, a connection is established between the high-speed interconnected remote virtualization processor and the target heterogeneous device through a high-speed communication link.

3. The high-speed communication method according to claim 2, characterized in that: After the target heterogeneous device is started, after the connection between the high-speed interconnected remote virtualization processor and the target heterogeneous device is established through a high-speed communication link, the method further includes: The high-speed interconnect remote virtualization processor distributes context information corresponding to the target heterogeneous device.

4. The high-speed communication method according to claim 3, characterized in that: The high-speed interconnect remote virtualization processor allocates the context information corresponding to the target heterogeneous device, including: The memory function data and register-related data corresponding to the target heterogeneous device are allocated on the high-speed interconnect remote virtualization processor.

5. The high-speed communication method according to claim 1, characterized in that: After the high-speed interconnect remote virtualization processor allocates the context information corresponding to the target heterogeneous device, the method further includes: The central processing unit on the host sends the high-speed interconnect operation to the high-speed interconnect remote virtualization processor through the high-speed interconnect module.

6. The high-speed communication method according to claim 1, characterized in that: The high-speed interconnect remote virtualization processor converts the high-speed interconnect operation into a register operation and a memory data movement operation on a heterogeneous accelerator on a target heterogeneous device, including: The high-speed interconnect remote virtualization processor maps the processing unit and the microcode processing unit through the high-speed interconnect operation, and converts the high-speed interconnect operation into a register operation and a memory data moving operation on the heterogeneous accelerator on the target heterogeneous device.

7. The high-speed communication method according to claim 6, characterized in that: Also includes: Setting corresponding configuration information according to register information of the target heterogeneous device by the microcode processing unit; The configuration information is used for communication adaptation with the target heterogeneous device.

8. The high-speed communication method according to claim 6, characterized in that: Also includes: The operation context of the target heterogeneous device is virtualized to the high-speed interconnect remote virtualization processor located locally.

9. The high-speed communication method according to claim 1, characterized in that: After the high-speed interconnect remote virtualization processor receives the high-speed interconnect operation instruction, the process further includes: The high-speed interconnect remote virtualization processor splits the high-speed interconnect operation instruction into multiple high-performance communication instructions.

10. The high-speed communication method according to claim 9, characterized in that: If the high-speed interconnect operation instruction includes a read instruction, a write instruction, and a cache instruction, after the high-speed interconnect remote virtualization processor splits the high-speed interconnect operation instruction into a plurality of high-performance communication instructions, the high-speed interconnect operation instruction further includes: If the high-speed interconnect operation instruction includes a read instruction; receiving the read instruction, and allocating a corresponding read request memory for the read instruction; Reading memory data on a heterogeneous device according to the read instruction, and responding to the read instruction based on the memory data; releasing the read request memory; If the high-speed interconnect operation instruction includes a write instruction; receiving the write instruction and allocating a corresponding write request memory; Writing data to the write request memory, and writing the write data to the memory on the heterogeneous device through a write operation; The high-speed interconnect remote virtualization processor responds to the read request and releases the read request memory; If the high-speed interconnect operation instruction includes a cache instruction; Receive the cache instruction and allocate corresponding cache request memory; Writing cache data to the cache request memory; Writing the cache data in the cache request memory to the memory on the heterogeneous device through a write operation, and updating the cache state of the heterogeneous device; The cache data is read to the memory on the high-speed interconnect remote virtualization processor through a read operation; the high-speed interconnect remote virtualization processor then releases the cache request memory and synchronizes the virtualization cache state.

11. The high-speed communication method according to claim 3, characterized in that: After the high-speed interconnect remote virtualization processor allocates the context information corresponding to the target heterogeneous device, the method further includes: Determine an accessible memory address range of the target heterogeneous device according to the context information.

12. The high-speed communication method according to claim 3 or 11, characterized in that: Also includes: The high-speed interconnect remote virtualization processor updates the context information on the high-speed interconnect remote virtualization processor according to the device status of the target heterogeneous device.

13. The high-speed communication method according to claim 1, characterized in that: Also includes: The high-speed interconnect remote virtualization processor uses an input-output protocol based on a high-speed interconnect protocol to perform input-output data transmission with the target heterogeneous device.

14. The high-speed communication method according to claim 1, characterized in that: Also includes: The high-speed interconnect remote virtualization processor uses a system memory protocol based on a high-speed interconnect protocol to access the memory of the central processor.

15. The high-speed communication method according to claim 1, characterized in that: Also includes: The high-speed interconnect remote virtualization processor utilizes a system memory protocol based on a high-speed interconnect protocol to achieve sharing of the central processing unit and the graphics card memory.

16. A heterogeneous communication system, characterized in that: include: A host, a switch with high-speed communication capabilities, and at least one heterogeneous device connected in sequence; Wherein, the host comprises a central processing unit, a high-speed interconnect module and a high-speed interconnect remote virtualization module; The host is used to perform the following operations through a high-speed interconnect remote virtualization processor located on the host; Converting the high-speed interconnect operation into a register operation and a memory data movement operation on a heterogeneous accelerator on the heterogeneous device; converting the register operation and the memory data movement operation into a communication request; Communicate with the heterogeneous device through the communication request to perform the register operation and the memory data moving operation.

17. The heterogeneous communication system according to claim 16, characterized in that: The high-speed interconnect remote virtualization processor comprises: The microcode processing unit is used to set corresponding configuration information according to the register information of the target heterogeneous device; the configuration information is used for communication adaptation with the target heterogeneous device.

18. The heterogeneous communication system according to claim 16, characterized in that: The high-speed interconnect remote virtualization processor comprises: The context information management unit is used to allocate context information corresponding to the target heterogeneous device.

19. The heterogeneous communication system according to claim 18, characterized in that: The context information management unit is further configured to update the context information on the high-speed interconnect remote virtualization processor according to the device status of the target heterogeneous device.

20. A high-speed communication device for heterogeneous devices, characterized in that: Applicable to communication equipment containing high-speed interconnect remote virtualization processors, including: A receiving module, used for receiving a high-speed interconnect operation; An operation conversion module, used for converting the high-speed interconnect operation into a register operation and a memory data movement operation on a heterogeneous accelerator on a target heterogeneous device; A request conversion module, used for converting the register operation and the memory data moving operation into a communication request; A communication module is used to communicate with the target heterogeneous device through the communication request to perform the register operation and the memory data moving operation.

21. A non-volatile readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the high-speed communication method for heterogeneous devices as described in any one of claims 1 to 15 are implemented.

22. A communication device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program, and when the processor calls the computer program in the memory, the steps of the high-speed communication method for heterogeneous devices as described in any one of claims 1 to 15 are implemented.

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