Semiconductor device and preparation method therefor, and electronic device

Abstract

Provided are a semiconductor device and a preparation method therefor and an electronic device. The semiconductor device comprises a substrate, and a storage part, a wiring part, and a peripheral circuit part which are arranged on one side of the substrate; the positions of the storage part, the wiring part, and the peripheral circuit part are different in a direction perpendicular to the substrate; the storage part comprises at least two sub-storage arrays, and the at least two sub-storage arrays are sequentially arranged in a first direction parallel to the substrate; each sub-storage array comprises at least one storage unit, and the storage unit comprises a transistor; the wiring part comprises at least one shared word line; and in the at least two sub-storage arrays, the gates of the transistors of the storage units located in different sub-storage arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit part.

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] This application claims priority to Chinese patent application number 202311138443.2, filed on September 5, 2023, with invention name “Semiconductor Devices and Electronic Devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor device and a method for manufacturing the same, and an electronic device. Background Art

[0003] Memory is the primary medium for storing data in computers. With the development and advancement of storage technology, storage devices are constantly moving towards miniaturization, higher device density, and higher integration.

[0004] Summary of the Invention

[0005] The present application provides a semiconductor device, a method for manufacturing the same, and an electronic device.

[0006] In a first aspect, embodiments of the present application provide a semiconductor device comprising: a substrate, and a storage portion, a routing portion, and a peripheral circuit portion disposed on one side of the substrate, wherein the storage portion, the routing portion, and the peripheral circuit portion are positioned differently in a direction perpendicular to the substrate; the storage portion comprises at least two sub-memory arrays, the at least two sub-memory arrays being arranged sequentially along a first direction parallel to the substrate; the sub-memory arrays comprising at least one memory cell, each memory cell comprising a transistor; and the routing portion comprising at least one shared word line.

[0007] In at least two sub-memory arrays, gates of transistors of memory cells located in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit portion.

[0008] In some optional embodiments of the present application, gates of transistors of memory cells located at the same corresponding positions in different sub-memory arrays are electrically connected to the same shared word line.

[0009] In some optional embodiments of the present application, the routing portion further includes at least two shared bit lines, and the at least two shared bit lines are connected to the at least two sub-memory arrays in a one-to-one correspondence.

[0010] In some optional embodiments of the present application, the sub-memory array includes a local bit line, a gating structure, and a plurality of memory cells, and the plurality of memory cells are sequentially arranged along a second direction parallel to the substrate;

[0011] The local bit lines are electrically connected to the source or drain of the transistors of the plurality of memory cells, respectively, and the local bit lines are electrically connected to the gating structure to form a column of memory cells;

[0012] The gating structure is electrically connected to the corresponding shared bit line;

[0013] The second direction intersects with the first direction, that is, the second direction and the first direction are arranged at an angle.

[0014] In some optional embodiments of the present application, multiple shared word lines connected one-to-one with multiple memory cells in the same sub-memory array are located in the same routing layer, which is parallel to the substrate. Within the routing layer, the multiple shared word lines are arranged sequentially along the second direction.

[0015] In some optional embodiments of the present application, the sub-memory array has at least two memory cell columns, and the at least two memory cell columns are arranged sequentially along the first direction;

[0016] At least two memory cell columns of the same sub-memory array are electrically connected to the corresponding same shared bit line;

[0017] In at least two memory cell columns of the same sub-memory array, shared word lines respectively connected to different memory cell columns are located in different routing layers, and at least two routing layers respectively connected to at least two memory cell columns are arranged in sequence along a direction perpendicular to the substrate.

[0018] In some optional embodiments of the present application, the memory cell includes a first transistor and a second transistor, wherein a source or a drain of the first transistor and a source or a drain of the second transistor are both electrically connected to a local bit line;

[0019] The shared word line correspondingly connected to the memory cell includes a first sub-shared word line and a second sub-shared word line, the first sub-shared word line is electrically connected to the gate of the first transistor, and the second sub-shared word line is electrically connected to the gate of the second transistor;

[0020] The first sub-shared word line and the second sub-shared word line are located in the same routing layer. In the routing layer, the first sub-shared word line and the second sub-shared word line are spaced apart along the second direction and staggered in the first direction.

[0021] In some optional embodiments of the present application, at least two sub-memory arrays are located in the same memory array layer, the memory portion has multiple memory array layers, and the multiple memory array layers are stacked in sequence in a direction perpendicular to the substrate; the multiple memory array layers meet at least one of the following conditions:

[0022] In the plurality of memory array layers, the sub-memory arrays whose orthographic projections overlap on the substrate are electrically connected to the same shared bit line;

[0023] In a plurality of memory array layers, transistors of memory cells whose orthographic projections overlap on the substrate are electrically connected to the same shared word line.

[0024] In some optional embodiments of the present application, the peripheral circuit portion includes a word line driver circuit, and the shared word line is electrically connected to the word line driver circuit;

[0025] The orthographic projection of the word line driver circuit on the substrate, the orthographic projection of the shared word line on the substrate, and the orthographic projection of the corresponding connected memory cell on the substrate overlap.

[0026] In some optional embodiments of the present application, there are multiple sub-storage arrays, and the multiple sub-storage arrays arranged sequentially along the first direction are divided into at least two storage arrays;

[0027] The gates of the transistors of the memory cells located at the same corresponding positions in each sub-memory array of the same memory array are electrically connected to the same shared word line;

[0028] The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to the same shared word line; or,

[0029] The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to different shared word lines respectively.

[0030] In some optional embodiments of the present application, gates of transistors of memory cells located at the same corresponding positions in sub-memory arrays of different memory arrays are electrically connected to different shared word lines respectively;

[0031] The word line driver circuit includes at least two sub-word line driver circuits, and the at least two sub-word line driver circuits are connected to the at least two memory arrays in a one-to-one correspondence; and / or,

[0032] At least two shared word lines electrically connected to the gates of transistors of memory cells at the same corresponding positions in sub-memory arrays of different memory arrays are located in the same routing layer or in different routing layers.

[0033] In some optional embodiments of the present application, the peripheral circuit unit includes a word line driver circuit, and the first sub-shared word line and the second sub-shared word line corresponding to the same memory cell are respectively connected to different positions of the same word line driver circuit.

[0034] In some optional embodiments of the present application, the peripheral circuit portion further includes at least two sense amplifier circuits connected to the at least two shared bit lines in a one-to-one correspondence;

[0035] An orthographic projection of the sense amplifier circuit on the substrate overlaps with an orthographic projection of the correspondingly connected shared bit line on the substrate.

[0036] In some optional embodiments of the present application, the peripheral circuit portion includes a word line driver circuit, and the word line driver circuit includes a plurality of sites arranged in a matrix;

[0037] Shared word lines located in the same routing layer are respectively connected to different sites in the same column of the word line driver circuit, and shared word lines located in different routing layers are respectively connected to sites in different columns of the word line driver circuit.

[0038] In some optional embodiments of the present application, the storage portion, the routing portion, and the peripheral circuit portion are sequentially arranged in a direction away from the substrate; or,

[0039] Along the direction away from the substrate, the peripheral circuit part, the wiring part and the storage part are arranged in sequence.

[0040] In a second aspect, embodiments of the present application provide a method for fabricating a semiconductor device, for fabricating the semiconductor device provided in the above aspects. The method comprises: providing a substrate; forming a storage portion, a routing portion, and a peripheral circuit portion on one side of the substrate; wherein the storage portion, the routing portion, and the peripheral circuit portion are positioned differently in a direction perpendicular to the substrate; the storage portion comprises at least two sub-memory arrays, the at least two sub-memory arrays being arranged sequentially along a first direction parallel to the substrate; the sub-memory arrays comprising at least one memory cell, the memory cell comprising a transistor;

[0041] The routing portion includes at least one shared word line; in at least two sub-memory arrays, gates of transistors of memory cells in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit portion.

[0042] In a third aspect, an embodiment of the present application provides an electronic device comprising the above-mentioned semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1a is a schematic structural diagram of an optional example of a semiconductor device provided in an embodiment of the present application;

[0044] FIG1b is another schematic structural diagram of the semiconductor device in FIG1a;

[0045] FIG2 is a schematic structural diagram of another optional example of a semiconductor device provided in an embodiment of the present application;

[0046] FIG3 a is a schematic structural diagram of another optional example of a semiconductor device provided in an embodiment of the present application;

[0047] FIG3 b is a schematic structural diagram of yet another optional example of a semiconductor device provided in an embodiment of the present application;

[0048] FIG4 is a schematic top view of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0049] FIG5 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0050] FIG6 is a schematic top view of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0051] FIG7 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0052] FIG8 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0053] FIG9 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0054] FIG10 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0055] FIG11 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0056] Figure markings: 100-semiconductor device; 20-storage unit; 21-storage array layer; 211-sub-storage array; 212-storage cell; 213-local bit line; 214-selection structure; 215-storage cell column; 216-first transistor; 217-second transistor; 218-word line; 22-storage array; 30-routing unit; 31-shared bit line; 32-shared word line; 321-first sub-shared word line; 322-second sub-shared word line; 33-routing layer; 40-peripheral circuit unit; 41-word line driver circuit; 411-sub-word line driver circuit; 412-first word line driver circuit; 413-second word line driver circuit; 42-sense amplifier circuit. DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0058] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0059] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0060] Some implementations of the memory device are described below:

[0061] With the increasing demand for device density and integration in various memory devices, three-dimensional memory devices have emerged. These devices can store and transfer data in three dimensions, significantly increasing their storage capacity, reducing storage costs, and improving their integration and storage density, thus contributing to their miniaturization.

[0062] Three-dimensional memory devices use a stacked structure to increase density and integration. However, since the stacked structure requires numerous metal wires to connect to peripheral circuits, the traditional wiring method of connecting each transistor to the peripheral circuit via a single word line results in a large area occupied by the wiring and peripheral circuits, thus negating the purpose of increasing density and integration by making the memory array three-dimensional.

[0063] The semiconductor device, its manufacturing method, and electronic device provided in the embodiments of the present application are intended to solve the above technical problems.

[0064] The following specific examples are used to describe in detail the technical solutions of the embodiments of the present application and how the technical solutions of the embodiments of the present application solve the above-mentioned technical problems. It should be noted that the following embodiments can refer to, learn from, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0065] An embodiment of the present application provides a semiconductor device, which may be a memory device. A schematic structural diagram of the semiconductor device 100 is shown in Figures 1 to 10. Referring to Figures 1a to 3b, the semiconductor device 100 includes: a substrate, and a storage unit 20, a routing unit 30, and a peripheral circuit unit 40 disposed on one side of the substrate. The storage unit 20, the routing unit 30, and the peripheral circuit unit 40 are positioned differently in a direction perpendicular to the substrate. The storage unit 20 includes at least two sub-memory arrays 211, which are arranged sequentially along a first direction parallel to the substrate. The sub-memory array 211 includes at least one memory cell 212, each including a transistor. The routing unit 30 includes at least one shared word line 32. In the at least two sub-memory arrays 211, the gates of the transistors of the memory cells 212 located in different sub-memory arrays 211 are electrically connected to the same shared word line 32, which is connected to the peripheral circuit unit 40.

[0066] In the embodiment of the present application, the substrate supports the storage unit 20, the wiring unit 30, and the peripheral circuit unit 40. In a direction perpendicular to the substrate, the storage unit 20, the wiring unit 30, and the peripheral circuit unit 40 are arranged at different positions to facilitate reasonable space allocation and reduce the occupied area.

[0067] In the embodiment of the present application, the at least two sub-storage arrays 211 included in the storage unit 20 are arranged in sequence along a first direction parallel to the substrate, which facilitates the arrangement of the at least two sub-storage arrays 211 and can avoid interference.

[0068] In the embodiment of the present application, each sub-memory array 211 includes at least one memory cell 212, and the wiring section 30 includes at least one shared word line 32. The at least one shared word line 32 corresponds one-to-one to at least one memory cell 212 in any sub-memory array 211. Furthermore, in at least two sub-memory arrays 211, the gates of the transistors of the memory cells 212 located in different sub-memory arrays 211 are electrically connected to the same shared word line 32. That is, in the at least two sub-memory arrays 211 included in the storage section 20, the gates of the transistors of the memory cells 212 located in different sub-memory arrays 211 can share a shared word line 32, and can be connected to the peripheral circuit section 40 through the shared shared word line 32. Compared to the traditional technology of connecting a transistor to a peripheral circuit via a word line, the embodiment of the present application can significantly reduce wiring and reduce the area of ​​the peripheral circuit by sharing word lines, without occupying excess area, thereby improving device density and integration.

[0069] In some optional embodiments of the present application, as shown in FIG2 , in at least two sub-memory arrays 211, the gates of the transistors of the memory cells 212 located at the same corresponding positions of different sub-memory arrays 211 are electrically connected to the same shared word line 32. That is, in at least two sub-memory arrays 211 of the storage unit 20, the gates of the transistors of the memory cells 212 located at the same corresponding positions of different sub-memory arrays 211 can share a shared word line 32, and can be connected to the peripheral circuit unit 40 through the shared shared word line 32. The embodiment of the present application can significantly reduce wiring and reduce the peripheral circuit area by sharing word lines, without occupying excess area, thereby improving device density and integration. Moreover, by making the transistors of the memory cells 212 at the same corresponding positions in different sub-memory arrays 211 share a shared word line 32, it is convenient to arrange the wiring reasonably and avoid clutter.

[0070] Of course, in other optional implementations of the present application, the gates of the transistors of the memory cells 212 located at different corresponding positions of different sub-memory arrays 211 may be electrically connected to the same shared word line 32 according to actual needs.

[0071] It can be understood that the position of the storage unit 212 in the sub-storage array 211 can be represented by the coordinates (M, N), where M is the row and N is the column, and both M and N can be integers greater than or equal to 1. The coordinates of the storage unit 212 are (M, N) which means that the position of the storage unit 212 is in the Mth row and the Nth column of the sub-storage array 211. In the embodiment of the present application, "the transistors of the storage unit 212 located at the same corresponding position of different sub-storage arrays 211 in at least two sub-storage arrays 211" include the transistors of all storage units 212 located in different sub-storage arrays 211 in at least two sub-storage arrays 211 whose coordinates are (M, N). The embodiment of the present application is described by taking the example that the storage unit 20 includes two sub-storage arrays 211, and each sub-storage array 211 includes four storage units 212 arranged in an array, that is, taking M=N=2 as an example:

[0072] The coordinates of the four memory cells 212 in each sub-memory array 211 are (1, 1), (1, 2), (2, 1), and (2, 2). In two sub-memory arrays 211, the transistors of the memory cells 212 located at the same corresponding position in different sub-memory arrays 211 are:

[0073] The transistors of the memory cells 212 with coordinates (1, 1) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 1st row and the 1st column in both sub-memory arrays 211; or

[0074] The transistors of the memory cells 212 with coordinates (1, 2) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 1st row and the 2nd column in both sub-memory arrays 211; or

[0075] The transistors of the memory cells 212 with coordinates (2, 1) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 2nd row and the 1st column in both sub-memory arrays 211; or

[0076] The transistors of the memory cells 212 with coordinates (2, 2) in both sub-memory arrays 211 , ie, the transistors of the memory cells 212 located in the 2nd row and the 2nd column in both sub-memory arrays 211 .

[0077] It can also be understood that the meaning of "same corresponding position" in the following text of this application is similar to the above explanation of the meaning of "same corresponding position" and will not be repeated here.

[0078] Optionally, in an embodiment of the present application, as shown in FIG. 1 a to FIG. 3 b , the gate of the transistor of the memory cell 212 is electrically connected to the shared word line 32 via a word line 218 correspondingly connected to the transistor.

[0079] In some optional embodiments of the present application, as shown in FIG. 2 , the routing portion 30 includes at least two shared bit lines 31 connected to at least two sub-memory arrays 211 in a one-to-one correspondence.

[0080] In the embodiment of the present application, at least two shared bit lines 31 of the routing portion 30 are connected to at least two sub-memory arrays 211 in a one-to-one correspondence, and different sub-memory arrays 211 are connected to different shared bit lines 31 in a one-to-one correspondence. Data in a memory cell 212 in a corresponding sub-memory array 211 can be read or data can be written to a memory cell 212 in a corresponding sub-memory array 211 via the shared bit lines 31.

[0081] Optionally, in the embodiment of the present application, both the shared word line 32 and the shared bit line 31 may be made of metal material.

[0082] In some optional embodiments of the present application, as shown in FIG2 , the sub-memory array 211 includes a local bit line 213, a gating structure 214, and a plurality of memory cells 212. The plurality of memory cells 212 are arranged in sequence along a second direction parallel to the substrate. The local bit lines 213 are also arranged along the second direction. The local bit lines 213 are electrically connected to the source or drain of the transistors of the plurality of memory cells 212, respectively, and the local bit lines 213 are electrically connected to the gating structure 214 to form a memory cell column 215. That is, the memory cell column 215 includes a local bit line 213, and the transistors and gating structure 214 of the plurality of memory cells 212 electrically connected to the local bit line 213. The gating structure 214 is electrically connected to the corresponding shared bit line 31. The second direction intersects with the first direction, that is, the second direction is set at an angle to the first direction.

[0083] In the embodiment of the present application, multiple memory cells 212 are arranged sequentially along the second direction for convenient placement and to avoid interference. Each sub-memory array 211 is connected to a corresponding shared bit line 31. Within a sub-memory array 211, the source or drain of the transistors of multiple memory cells 212 are electrically connected to a local bit line 213, which is electrically connected to a gating structure 214, forming a memory cell column 215. The gating structure 214 is electrically connected to the corresponding shared bit line 31, thereby achieving electrical connection between the memory cell column 215 and the shared bit line 31.

[0084] In the embodiment of the present application, as shown in FIG2 , the gates of the transistors of multiple memory cells 212 in the same sub-memory array 211 correspond one-to-one to and are electrically connected to different shared word lines 32. The gates of the transistors of the memory cells 212 located at the same corresponding position in different sub-memory arrays 211 are electrically connected to the same shared word line 32. The shared word line 32 can be used to control the turning on or off of the transistors of the memory cells 212 located at the same corresponding position in the corresponding different sub-memory arrays 211.

[0085] Each sub-memory array 211 is connected to a corresponding shared bit line 31. Data in a memory cell 212 in the corresponding sub-memory array 211 can be read or written to via the shared bit line 31. A gating structure 214 is used to write multiple data signals to each memory cell 212 in a one-to-one correspondence under the control of multiple shared word line 32 signals.

[0086] Optionally, in some embodiments of the present application, the second direction is perpendicular to the first direction.

[0087] In some optional embodiments of the present application, as shown in Figures 2 and 7, multiple shared word lines 32 connected one-to-one to the transistors of multiple memory cells 212 in the same sub-memory array 211 are located in the same routing layer 33. Optionally, the routing layer 33 is parallel to the substrate. Within the routing layer 33, the multiple shared word lines 32 are arranged sequentially along the second direction. Through this design approach, the routing can be rationally arranged, simplifying the routing portion 30 structure and avoiding clutter, which helps save peripheral circuit area and improve device density and integration.

[0088] In some optional embodiments of the present application, as shown in Figures 6 and 8, the sub-memory array 211 has at least two memory cell columns 215. The at least two memory cell columns 215 are sequentially arranged along the first direction for easy arrangement and to avoid interference.

[0089] In some optional embodiments of the present application, as shown in Figures 6 and 8, at least two memory cell columns 215 in the same sub-memory array 211 are electrically connected to the same corresponding shared bit line 31. Data can be read from or written to the memory cells 212 in at least two memory cell columns 215 in the same sub-memory array 211 via the same shared bit line 31, simplifying the structure of the routing portion 30, helping to save peripheral circuit area and improving device density and integration.

[0090] In some optional embodiments of the present application, as shown in Figures 8, 9, and 10, in at least two memory cell columns 215 of the same sub-memory array 211, different memory cell columns 215 are connected to different shared word lines 32. The shared word lines 32 respectively connected to different memory cell columns 215 are located in different routing layers 33, and the at least two routing layers 33 respectively connected to the at least two memory cell columns 215 are arranged sequentially in a direction perpendicular to the substrate.

[0091] For example, as shown in Figures 8, 9, and 10, in at least two memory cell columns 215 of the same sub-memory array 211, the gates of the transistors of the memory cells 212 located at the same corresponding positions in different memory cell columns 215 are respectively connected to different shared word lines 32. Furthermore, the shared word lines 32 respectively connected to the gates of the transistors of the memory cells 212 located at the same corresponding positions in different memory cell columns 215 are located in different routing layers 33, and the at least two routing layers 33 respectively connected to the at least two memory cell columns 215 are arranged sequentially in a direction perpendicular to the substrate.

[0092] If all shared word lines are arranged on the same routing layer, the area of ​​the routing layer will increase, which will in turn reduce the degree of reduction in peripheral circuit area. Therefore, in order to arrange the shared word lines 32, the embodiment of the present application needs to increase the number of routing layers 33, making the area of ​​each routing layer 33 smaller, thereby saving peripheral circuit area.

[0093] As shown in Figures 8 and 9, each shared bit line 31 includes a horizontal shared bit line and a vertical shared bit line connected to each other. The horizontal shared bit line is connected to the gating structure 214, and the vertical shared bit line is connected to the sense amplifier (SA) circuit 42 of the peripheral circuit unit 40. The horizontal shared bit line can be parallel to the substrate, for example, parallel to the first direction. The vertical shared bit line can be perpendicular to the substrate.

[0094] Optionally, as shown in FIG8 , each horizontal shared bit line is connected to an SA circuit 42 of a peripheral circuit unit 40 via a vertical shared bit line. Alternatively, as shown in FIG9 , multiple (three are used as an example in FIG9 ) horizontal shared bit lines whose orthographic projections on the substrate overlap with each other are connected to a vertical shared bit line (i.e., multiple horizontal shared bit lines whose orthographic projections on the substrate overlap with each other share a single vertical shared bit line), and are then connected to an SA circuit 42 of a peripheral circuit unit via this vertical shared bit line.

[0095] It will be understood that Figures 8, 9 and 10 also show word line row switches (i.e., wl row switches), word line column switches (i.e., wl column switches), word line column lines (i.e., wl column lines), selected columns (i.e., selected columns), word line row lines (i.e., wl row lines), word line selectors (i.e., wl selectors), 3D module (i.e., selected rows), and selected word lines (i.e., selected wls), where wl is the abbreviation of word line.

[0096] Optionally, in an embodiment of the present application, when each sub-memory array 211 has multiple memory cell columns 215, when connected to the peripheral circuit unit 40 through a shared word line 32, the number of columns of transistors in the word line driver circuit composed of multiple transistor arrays needs to be increased in the corresponding peripheral circuit unit 40.

[0097] In some optional embodiments of the present application, as shown in Figures 1a, 1b, 4, and 5, the memory cell 212 includes a first transistor 216 and a second transistor 217. The source or drain of the first transistor 216 and the source or drain of the second transistor 217 are both electrically connected to the local bit line 213. The shared word line 32 corresponding to the memory cell 212 includes a first sub-shared word line 321 and a second sub-shared word line 322. The first sub-shared word line 321 is electrically connected to the gate of the first transistor 216, and the second sub-shared word line 322 is electrically connected to the gate of the second transistor 217. The first sub-shared word line 321 and the second sub-shared word line 322 are located in the same routing layer 33. Within the routing layer 33, the first sub-shared word line 321 and the second sub-shared word line 322 are arranged at intervals along the second direction and staggered in the first direction.

[0098] Among them, the staggered arrangement of the first sub-shared word line 321 and the second sub-shared word line 322 in the first direction may mean that the first sub-shared word line 321 and the second sub-shared word line 322 are staggered in the first direction, that is, the first sub-shared word line 321 and the second sub-shared word line 322 are not aligned.

[0099] Through this design approach, the different sub-shared word lines corresponding to the different transistors of the same memory cell 212 can be arranged on the same routing layer 33. The staggered arrangement of the different sub-shared word lines facilitates convenient and reasonable arrangement on the same routing layer 33, and only one routing layer is required to accommodate all the sub-shared word lines corresponding to the different transistors of the same memory cell 212.

[0100] It will be appreciated that FIG1a and FIG1b respectively illustrate the connection relationship between different transistors of a memory cell 212 of the same memory array 22 and the shared word line and the peripheral circuit section 40. FIG1a illustrates the connection relationship between the first transistor 216 of the memory cell 212 of the memory array 22 and the shared word line and the peripheral circuit section 40. FIG1b illustrates the connection relationship between the second transistor 217 of the memory cell 212 of the memory array 22 and the shared word line and the peripheral circuit section 40.

[0101] Optionally, as shown in Figures 1a, 1b, and 2, in an embodiment of the present application, the first transistor 216 and the second transistor 217 of the memory cell 212 share a source or drain, which is referred to as a shared source or drain. The shared source or drain is electrically connected to the local bit line 213 and, in turn, is electrically connected to a corresponding shared bit line 31 via the local bit line 213 and the gating structure 214.

[0102] In some optional embodiments of the present application, as shown in Figures 8, 9, and 10, at least two sub-memory arrays 211 are located in the same memory array layer 21. The storage unit 20 has multiple memory array layers 21, which are stacked in sequence along a direction perpendicular to the substrate. The multiple memory array layers 21 can meet at least one of the following conditions:

[0103] In the plurality of memory array layers 21 , the sub-memory arrays 211 whose orthographic projections overlap on the substrate are electrically connected to the same shared word line 32 or to different shared word lines 32 ;

[0104] In the plurality of memory array layers 21 , the gates of the transistors of the memory cells 212 whose orthographic projections overlap on the substrate are electrically connected to the same shared word line 32 .

[0105] In the embodiment of the present application, the storage unit 20 has multiple storage array layers 21, each storage array layer 21 is arranged with at least two sub-storage arrays 211, and the multiple storage array layers 21 are stacked in sequence along a direction perpendicular to the substrate. Through this design method, the semiconductor device 100 can form a 3D (3D) stacked structure, which can improve the storage capacity of the semiconductor device, reduce storage costs, increase integration and storage density, and help achieve miniaturization. In addition, this design method can reduce the number of bit lines and word lines, which is beneficial to layout design, improve structural density and practicality.

[0106] In the embodiment of the present application, in the multiple memory array layers 21, the sub-memory arrays 211 whose orthographic projections overlap on the substrate are electrically connected to the same shared bit line 31. That is, in the sub-memory arrays 211 located in different memory array layers 21, the sub-memory arrays 211 whose orthographic projections overlap on the substrate can share the same shared bit line 31. In the multiple memory array layers 21, the gates of the transistors of the memory cells 212 whose orthographic projections overlap on the substrate are electrically connected to the same shared word line 32. That is, in the memory cells 212 of the sub-memory arrays 211 located in different memory array layers 21, the transistors of the memory cells 212 whose orthographic projections overlap on the substrate can share the same shared word line 32.

[0107] This design allows multiple memory array layers 21, multiple sub-memory arrays 211, and multiple memory cells 212 of the semiconductor device 100 to operate simultaneously, achieving bit line and word line sharing, thereby minimizing the peripheral circuit area. Furthermore, when the memory portion 20 is a three-dimensional structure having multiple memory array layers 21, the layout of the routing portion 30 and the peripheral circuit portion 40 is not affected.

[0108] In some optional embodiments of the present application, as shown in Figures 2 and 5, the peripheral circuit unit 40 includes a word line driver circuit 41, which may also be called a sub word line driver (SWD) circuit. The shared word line 32 is electrically connected to the word line driver circuit 41. The orthographic projection of the word line driver circuit 41 and the orthographic projection of the shared word line 32 on the substrate overlap with the orthographic projection of the corresponding memory cell 212 on the substrate.

[0109] In the embodiment of the present application, the word line driver circuit 41 is electrically connected to the shared word line 32, and the word line driver circuit 41 provides a word line voltage for the shared word line 32. The orthographic projections of the word line driver circuit 41 and the shared word line 32 on the substrate overlap with the orthographic projections of the corresponding memory cells 212 on the substrate. The word line driver circuit 41, the shared word line 32, and the corresponding memory cells 212 are arranged sequentially in a direction perpendicular to the substrate, so that the word line driver circuit 41, the shared word line 32, and the corresponding memory cells 212 are located in the same area on different layers, eliminating redundant space and saving wiring and peripheral circuit area.

[0110] Moreover, compared with the traditional technology of connecting a transistor to the peripheral circuit through a word line, the embodiment of the present application can significantly save the SWD circuit area by sharing the word line, does not occupy excess area, and improves device density and integration.

[0111] Optionally, in the embodiment of the present application, from bottom to top, they are the storage unit 20, the routing layer 33, and the word line driver circuit 41. That is, the word line driver circuit 41 is located directly above the routing layer 33, and the routing layer 33 is located directly above the storage unit 20. As shown in Figures 1b and 5, the word line driver circuit 41 (SWD circuit) includes a first word line driver circuit 412 (SWDx), a second word line driver circuit 413 (SWDy), and a transistor array, which includes a plurality of transistors arranged in an array. SWDx is connected to the gates of the plurality of transistors in the transistor array, and SWDy is connected to the sources or drains of the plurality of transistors in the transistor array.

[0112] In some optional embodiments of the present application, different transistors in a memory cell 212 of a sub-memory array 211 are connected to different shared word lines 32, and the different shared word lines 32 are connected to different positions of the same word line driver circuit 41. Specifically, the shared word line connected to the transistor on the left side of the memory cell 212 (such as the first transistor 216 in FIG. 1 a ) is connected to the transistor array on the left side of the peripheral circuit section 40, and the shared word line connected to the transistor on the right side of the memory cell 212 (such as the second transistor 217 in FIG. 1 b ) is connected to the transistor array on the right side of the peripheral circuit section 40. This allows different shared word lines 32 connected to different transistors of the same memory cell 212 to share the same word line driver circuit 41.

[0113] In some optional embodiments of the present application, as shown in Figures 1a and 1b, Figure 1a shows that the first transistor 216 is connected to the word line driver circuit 41 via the first sub-shared word line 321, and Figure 1b shows that the second transistor 217 is connected to the word line driver circuit 41 via the second sub-shared word line 322. The first sub-shared word line 321 and the second sub-shared word line 322 respectively connected to the first transistor 216 and the second transistor 217 of the same memory cell 212 are connected to different positions of the same word line driver circuit 41, so that the first sub-shared word line 321 and the second sub-shared word line 322 respectively connected to the first transistor 216 and the second transistor 217 of the same memory cell 212 can share the same word line driver circuit 41.

[0114] In some optional embodiments of the present application, as shown in FIG2 , there are multiple sub-memory arrays 211, and the multiple sub-memory arrays 211 arranged sequentially along the first direction are divided into at least two memory arrays 22. The gates of the transistors of the memory cells 212 located at the same corresponding positions in each sub-memory array 211 of the same memory array 22 are electrically connected to the same shared word line 32, that is, the gates of the transistors of the memory cells 212 located at the same corresponding positions in each sub-memory array 211 of the same memory array 22 can share a shared word line 32. By electrically connecting this shared shared word line 32 to the word line driver circuit 41, the wiring and peripheral circuit area can be greatly reduced, thereby improving device density and integration.

[0115] In some optional embodiments of the present application, as shown in FIG2 , the gates of transistors of memory cells 212 located at the same corresponding positions in sub-memory arrays 211 of different memory arrays 22 are electrically connected to the same shared word line 32. By sharing a shared word line 32, wiring and peripheral circuit area can be significantly reduced, thereby improving device density and integration.

[0116] In some optional embodiments of the present application, the gates of the transistors of the memory cells 212 located at the same corresponding positions in the sub-memory arrays 211 of different memory arrays 22 are electrically connected to different shared word lines 32 respectively, so as to avoid interference.

[0117] In some optional embodiments of the present application, as shown in Figures 3a and 3b, the gates of the transistors of memory cells 212 located at the same corresponding position in sub-memory arrays 211 of different memory arrays 22 are electrically connected to different shared word lines 32 to avoid interference. The word line driver circuit 41 includes at least two sub-word line driver circuits 411, and the at least two sub-word line driver circuits 411 are connected to the at least two memory arrays 22 in a one-to-one correspondence.

[0118] In the embodiment of the present application, each memory array 22 is electrically connected to a corresponding sub-word line driver circuit 411 via a corresponding shared word line 32, thereby avoiding interference. Furthermore, multiple memory arrays 22, multiple sub-memory arrays 211, and multiple memory cells 212 of the semiconductor device 100 can operate simultaneously, achieving bit line and word line sharing, thereby minimizing the area of ​​the peripheral circuit unit 40.

[0119] In the embodiment of the present application, as shown in FIG2 , at least two shared word lines 32 electrically connected to the gates of transistors of memory cells 212 located at the same corresponding positions in sub-memory arrays 211 of different memory arrays 22 are located on the same routing layer 33, or are located on different routing layers 33. By arranging at least two shared word lines 32 on the same routing layer, the routing can be rationally arranged, simplifying the structure of the routing portion 30 and avoiding clutter, thereby saving peripheral circuit area and improving device density and integration.

[0120] In some optional embodiments of the present application, at least two shared word lines 32 electrically connected to the gates of transistors of memory cells 212 located at different corresponding positions in sub-memory arrays 211 of different memory arrays 22 are located in the same routing layer 33. This design approach allows for a reasonable routing arrangement, simplifies the routing portion 30 structure, avoids clutter, helps save peripheral circuit area, and improves device density and integration.

[0121] According to the above description, in the embodiment of the present application, "the transistors of the memory cells 212 located at the same corresponding position in different sub-memory arrays 211 in at least two sub-memory arrays 211" include the transistors of all memory cells 212 located in different sub-memory arrays 211 in at least two sub-memory arrays 211, whose coordinates are (M, N). For example, take the example where the storage unit 20 includes two sub-memory arrays 211, and each sub-memory array 211 includes four memory cells 212 arranged in an array. In the two sub-memory arrays 211, the transistors of the memory cells 212 located at the same corresponding position in different sub-memory arrays 211 include:

[0122] The transistors of the memory cells 212 with coordinates (1, 1) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 1st row and the 1st column in both sub-memory arrays 211; or

[0123] The transistors of the memory cells 212 with coordinates (1, 2) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 1st row and the 2nd column in both sub-memory arrays 211; or

[0124] The transistors of the memory cells 212 with coordinates (2, 1) in both sub-memory arrays 211, that is, the transistors of the memory cells 212 located in the 2nd row and the 1st column in both sub-memory arrays 211; or

[0125] The transistors of the memory cells 212 with coordinates (2, 2) in both sub-memory arrays 211 , ie, the transistors of the memory cells 212 located in the 2nd row and the 2nd column in both sub-memory arrays 211 .

[0126] It can be understood that, in the embodiment of the present application, “the gates of the transistors of the memory cells 212 located at different corresponding positions in the sub-memory arrays 211 of different memory arrays 22” include the gates of the transistors of the memory cells 212 located at different coordinates in the sub-memory arrays 211 of different memory arrays 22. Here, the example in which the memory unit 20 includes two sub-memory arrays 211, and each sub-memory array 211 includes four memory cells 212 arranged in an array is still used for explanation. The transistors of the memory cells 212 located at different coordinates in the sub-memory arrays 211 of different memory arrays 22 include: the transistors of the memory cells 212 with coordinates (1, 1) of the sub-memory array 211 of one memory array 22, and the transistors of the memory cells 212 with coordinates (1, 2), (2, 1) and / or (2, 2) of the sub-memory array 211 of another memory array 22.

[0127] It can be understood that the meaning of "different corresponding positions" in the embodiments of the present application below is similar to the above explanation of the meaning of "different corresponding positions" and will not be repeated here.

[0128] In other optional embodiments of the present application, at least two shared word lines 32 electrically connected to memory cells 212 at different corresponding positions in sub-memory arrays 211 of different memory arrays 22 are located in different routing layers 33. This design allows for a reasonable routing arrangement, allowing the shared word lines 32 to be spaced apart, reducing the area of ​​each routing layer 33, thereby saving area in the peripheral circuit unit 40 and improving device density and integration.

[0129] In other optional embodiments of the present application, as shown in FIG2 , when there are multiple different memory arrays 22, they can also be connected to the same word line driver circuit 41 via a shared word line 32. That is, there are multiple sub-memory arrays 211, and the multiple sub-memory arrays 211 arranged sequentially along the first direction are divided into at least two memory arrays 22. The gates of the transistors of the memory cells 212 located at the same corresponding positions in the multiple sub-memory arrays 211 of different memory arrays 22 can be connected together via a shared word line 32, and further connected to the corresponding word line driver circuit 41. The multiple shared word lines 32 respectively connected to the memory cells 212 in the sub-memory arrays 211 of the storage unit 20 are electrically connected to the same word line driver circuit 41. As a result, multiple sub-memory arrays 211 share a single word line driver circuit 41, which can significantly save the area of ​​the word line driver circuit 41. In other words, the word line driver circuit 41 can save area through word line sharing.

[0130] For example, as shown in FIG2 , there are two memory arrays 22 from the left side to the right side of FIG2 (of course, three or more memory arrays 22 may be selected). Each memory array 22 has two sub-memory arrays 211 (of course, three or more sub-memory arrays 211 may be selected). Each sub-memory array 211 has only one layer of memory cells 212 (of course, two or more memory array layers 21 may be selected). Each sub-memory array 211 has one memory cell column 215 (of course, two or more memory cell columns 215 may be selected). Each memory cell column 215 has 2×2 1T1C bits (of course, multiple 1T1C bits may be selected). A 1T1C bit refers to a transistor (T) and a capacitor (C).

[0131] Two 1T1C bit cells arranged along the first direction form a memory cell 212. The memory cell columns 215 of each sub-memory array 211 share a shared bit line 31. The gates of the two 1T1C bit transistors (i.e., the first transistor 216 and the second transistor 217 described above) of the same memory cell 212 are electrically connected to two shared word lines 32, respectively. The two shared word lines 32 are located on the same routing layer 33 and are spaced apart along the second direction within the routing layer 33, and are staggered in the first direction. The two 1T1C bit transistors arranged along the second direction are electrically connected to two shared word lines 32, respectively. The two shared word lines 32 are located on the same routing layer 33 and are spaced apart along the second direction within the routing layer 33. The 1T1C bits located at the same corresponding positions in the two sub-memory arrays 211, for example, the 1T1C bits with coordinates (1, 1) and located on the left sides of the two memory cells 212 arranged along the first direction, are electrically connected to the same shared word line 32 and electrically connected to the corresponding word line driver circuit 41 through the shared word line 32.

[0132] When there are multiple different memory arrays 22, they can also be connected to array bits in the same peripheral circuit unit 40 through shared word lines 32. Array bits refer to multiple bits arranged in an array, and a bit refers to a shared source or drain of two transistors in the peripheral circuit unit 40.

[0133] The peripheral circuit array region shown in FIG2 includes a sense amplifier circuit 42 (SA circuit) and a word line driver circuit 41 (SWD circuit). The SA circuit 42 is located directly above the shared word line 32 and the stepped metal line and is connected to the gating structure 214 via the shared bit line 31. The SWD circuit 41 comprises a plurality of transistor arrays located directly above the memory section 20 and the routing section 30. The shared source or drain of each pair of transistors is connected to the shared word line 32 at the corresponding position below. The shared word line 32 is then connected to the word line (WL) of the memory array 22 at the corresponding position.

[0134] The gating structure 214 is a transistor whose gate is connected to different bits of the SWD circuit 41 , ie, different shared sources or drains of the SWD circuit 41 .

[0135] In some optional embodiments of the present application, as shown in Figures 7, 8, and 9, the word line driver circuit 41 of the peripheral circuit unit 40 includes multiple sites arranged in a matrix, and the shared word lines 32 on the same layer are respectively connected to different sites in the same column of the word line driver circuit 41. As shown in Figure 10, the shared word lines 32 on different layers are respectively connected to sites in different columns of the word line driver circuit 41. Here, a site refers to a shared source or drain of two transistors in a transistor array.

[0136] In some optional embodiments of the present application, as shown in Figures 1a, 1b, and 2, the peripheral circuit portion 40 further includes at least two sense amplifier circuits 42 (SA circuits) connected in a one-to-one correspondence with at least two shared bit lines 31. The orthographic projections of the sense amplifier circuits 42 on the substrate overlap with the orthographic projections of the corresponding shared bit lines 31 on the substrate.

[0137] In the embodiment of the present application, at least two sense amplifier circuits 42 are connected to at least two shared bit lines 31 in a one-to-one correspondence. The sense amplifier circuits 42 are capable of sensing and amplifying data received from the corresponding shared bit lines 31, or transmitting data to the corresponding shared bit lines 31. The orthographic projections of the sense amplifier circuits 42 on the substrate overlap with the orthographic projections of the corresponding shared bit lines 31 on the substrate. The sense amplifier circuits 42 and the corresponding shared bit lines 31 are arranged sequentially in a direction perpendicular to the substrate, so that the sense amplifier circuits 42 and the corresponding shared bit lines 31 are located in the same area on different layers, eliminating redundant space and saving wiring and peripheral circuit area.

[0138] In the embodiment of the present application, the peripheral circuit section 40 includes an SA circuit 42 and an SWD circuit 41. The SA circuit 42 is located directly above the shared bit line 31 and is interconnected. The SWD circuit 41 is composed of multiple transistor arrays and is located directly above the memory section 20 and the routing layer 33. This routing method and structure allows the memory section 20, routing section 30, and peripheral circuit section 40 to be located on the same area on different layers, eliminating the need for additional area and saving routing and peripheral circuit area.

[0139] In some optional embodiments of the present application, as shown in Figures 1a, 1b, and 2, the storage unit 20, the wiring unit 30, and the peripheral circuit unit 40 are sequentially arranged in a direction away from the substrate. As shown in Figure 5, the peripheral circuit unit 40 is located on top of the storage unit 20. Specifically, the wiring unit 30 is located on top of the storage unit 20, and the peripheral circuit unit 40 is located on top of the wiring unit 30.

[0140] Of course, in some other optional embodiments of the present application, the peripheral circuit portion 40, the wiring portion 30 and the storage portion 20 are sequentially arranged in a direction away from the substrate. The peripheral circuit portion 40 is located at the bottom of the wiring portion 30, and the wiring portion 30 is located at the bottom of the storage portion 20.

[0141] An embodiment of the present application provides a semiconductor device that connects the gates of transistors in the same corresponding positions in different sub-memory arrays or word lines connected to the gates together through a shared word line, and then connects them to a word line driver circuit, so that one word line driver circuit in the peripheral circuit part can control multiple memory bits. By sharing word lines among different sub-memory arrays, the area of ​​the word line driver circuit region is saved. The shared word lines are designed so that the word lines of the left bit and the right bit of the memory cell in each memory cell column in the sub-memory array are respectively connected to the staggered shared word lines. The routing layer can be placed directly above the memory array, the word line driver circuit is placed directly above the routing layer, and the sense amplifier circuit is placed directly above the shared bit line, thereby saving the peripheral circuit area. Through reasonable circuit design, the word lines or bit lines in different memory arrays are combined and connected to the word line driver circuit or the sense amplifier circuit, which can greatly reduce the occupied area of ​​the word line driver circuit or the sense amplifier circuit.

[0142] By sharing word and bit lines and designing routing structures, the shared bit lines and shared word lines are connected to the SA circuit and SWD circuit, respectively. This allows local bit lines in different layers of sub-memory arrays to share a single SA circuit, while word lines for memory cells in different columns can use the same SWD circuit, significantly reducing the SWD circuit area. Furthermore, metal routing and peripheral circuitry are placed directly above the memory array, eliminating excess area and increasing device integration density.

[0143] The present invention provides a semiconductor device in the field of semiconductor device manufacturing, suitable for three-dimensional transistor memory, and applicable to the connection structure and connection method of three-dimensional memory storage array structure and peripheral circuit. Of course, the semiconductor device can also be a random access memory, specifically static random access memory or dynamic random access memory, and of course, flash memory can also be used.

[0144] Based on the same inventive concept, an embodiment of the present application provides a method for manufacturing a semiconductor device, which can manufacture the semiconductor device provided in the above embodiment. As shown in FIG11 , the method includes:

[0145] Step 50: Provide a substrate.

[0146] Step 60: forming a storage portion, a wiring portion, and a peripheral circuit portion on one side of the substrate.

[0147] The memory portion, the wiring portion, and the peripheral circuit portion are positioned at different positions in a direction perpendicular to the substrate; the memory portion includes at least two sub-memory arrays, which are sequentially arranged along a first direction parallel to the substrate; the sub-memory array includes at least one memory cell, and the memory cell includes a transistor;

[0148] The routing portion includes at least one shared word line; in at least two sub-memory arrays, gates of transistors of memory cells in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit portion.

[0149] It can be understood that the preparation method of the semiconductor device of the embodiment of the present application can be used to prepare the semiconductor device provided in the above embodiment. Therefore, the preparation method also has the above-mentioned beneficial effects of the semiconductor device of the embodiment of the present application, which will not be repeated here.

[0150] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the semiconductor device 100 provided by the above embodiment.

[0151] It can be understood that since the electronic device of the embodiment of the present application includes the semiconductor device of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the semiconductor device of the embodiment of the present application, which will not be repeated here.

[0152] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0153] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0154] In the embodiments of the present application, the storage unit, wiring unit, and peripheral circuit unit are positioned at different locations perpendicular to the substrate. This allows for the storage unit, wiring unit, and peripheral circuit unit to be arranged at different locations perpendicular to the substrate, facilitating rational space allocation and reducing footprint. The at least two sub-memory arrays of the storage unit are arranged sequentially along a first direction parallel to the substrate, facilitating the arrangement of the at least two sub-memory arrays and preventing interference.

[0155] In an embodiment of the present application, each sub-memory array includes at least one memory cell, and the wiring portion includes at least one shared word line, and the at least one shared word line corresponds one-to-one to at least one memory cell in each sub-memory array. Moreover, in at least two sub-memory arrays, the gates of the transistors of the memory cells located in different sub-memory arrays are electrically connected to the same shared word line, that is, in at least two sub-memory arrays of the storage portion, the gates of the transistors of the memory cells located in different sub-memory arrays can share a shared word line, and can be connected to the peripheral circuit portion through this shared shared word line. By sharing word lines, the embodiment of the present application can significantly reduce wiring and reduce the area of ​​peripheral circuits, without occupying excess area, thereby improving device density and integration.

[0156] In an embodiment of the present application, at least two shared bit lines of the routing portion are connected to at least two sub-memory arrays in a one-to-one correspondence, and different sub-memory arrays are connected to different shared bit lines in a one-to-one correspondence. The shared bit lines can be used to read data from the storage cells in the corresponding sub-memory arrays or write data to the storage cells in the corresponding sub-memory arrays. In multiple storage array layers, each sub-memory array whose orthographic projections overlap on the substrate is electrically connected to the same shared bit line, that is, in sub-memory arrays located in different storage array layers, each sub-memory array whose orthographic projections overlap on the substrate can share the same shared bit line. In multiple storage array layers, the transistors of each storage cell whose orthographic projections overlap on the substrate are electrically connected to the same shared word line, that is, in storage cells of sub-memory arrays located in different storage array layers, each storage cell whose orthographic projections overlap on the substrate can share the same shared word line. Through this design method, multiple storage array layers, multiple sub-memory arrays, and multiple storage cells of a semiconductor device can work simultaneously, realizing bit line sharing and word line sharing, thereby minimizing the peripheral circuit area. Furthermore, when the storage portion is a three-dimensional structure having multiple storage array layers, the arrangement of the wiring portion and the peripheral circuit portion is not affected.

[0157] The orthographic projections of the wordline driver circuit and the shared wordline on the substrate overlap with the orthographic projections of the corresponding memory cells on the substrate, allowing the wordline driver circuit, shared wordline, and corresponding memory cells to be located on different layers within the same area, eliminating redundant space and saving wiring and peripheral circuit area. Furthermore, by sharing wordlines, embodiments of the present application can significantly reduce wordline driver circuit area, eliminating redundant space and improving device density and integration.

[0158] The orthographic projection of the sense amplifier circuit on the substrate overlaps with the orthographic projection of the corresponding shared bit line on the substrate, so that the sense amplifier circuit and the corresponding shared bit line are located in the same area on different layers, without occupying redundant area, saving wiring and peripheral circuit area.

[0159] Through the above wiring method and structure, the storage part, wiring part and peripheral circuit part are located in the same area on different layers without occupying other redundant areas, thus saving wiring and peripheral circuit area.

[0160] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0161] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0162] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0163] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0164] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0165] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor device, comprising: A substrate and a storage portion, a wiring portion and a peripheral circuit portion arranged on one side of the substrate; In a direction perpendicular to the substrate, the storage portion, the wiring portion, and the peripheral circuit portion are located at different positions; The storage portion includes at least two sub-storage arrays, and the at least two sub-storage arrays are arranged in sequence along a first direction parallel to the substrate; The sub-memory array includes at least one memory cell, and the memory cell includes a transistor; The routing section includes at least one shared word line; In the at least two sub-memory arrays, gates of transistors of the memory cells located in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit unit.

2. The semiconductor device according to claim 1, wherein The gates of the transistors of the memory cells located at the same corresponding positions of different sub-memory arrays are electrically connected to the same shared word line.

3. The semiconductor device according to claim 1 or 2, wherein: The routing section further includes at least two shared bit lines, and the at least two shared bit lines are connected to the at least two sub-storage arrays in a one-to-one correspondence.

4. The semiconductor device according to claim 3, wherein: The sub-memory array comprises a local bit line, a gating structure and a plurality of the memory cells, wherein the plurality of the memory cells are arranged in sequence along a second direction parallel to the substrate; The local bit lines are electrically connected to the sources or drains of transistors in the plurality of memory cells, respectively, and the local bit lines are electrically connected to the gating structure to form a memory cell column; The gating structure is electrically connected to the corresponding shared bit line; The second direction intersects with the first direction.

5. The semiconductor device according to claim 4, wherein: The multiple shared word lines connected one-to-one with the multiple storage cells in the same sub-storage array are located in the same routing layer, the routing layer is parallel to the substrate, and in the routing layer, the multiple shared word lines are arranged in sequence along the second direction.

6. The semiconductor device according to claim 4, wherein: The sub-storage array has at least two storage cell columns, and the at least two storage cell columns are arranged in sequence along the first direction; At least two memory cell columns of the same sub-memory array are electrically connected to the corresponding same shared bit line; In at least two memory cell columns of the same sub-memory array, the shared word lines respectively connected to different memory cell columns are located in different routing layers, and at least two routing layers respectively connected to at least two memory cell columns are arranged in sequence along a direction perpendicular to the substrate.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The memory cell comprises a first transistor and a second transistor, wherein a source or a drain of the first transistor and a source or a drain of the second transistor are both electrically connected to a local bit line; The shared word line correspondingly connected to the memory cell includes a first sub-shared word line and a second sub-shared word line, the first sub-shared word line is electrically connected to the gate of the first transistor, and the second sub-shared word line is electrically connected to the gate of the second transistor; The first sub-shared word line and the second sub-shared word line are located in a same routing layer. In the routing layer, the first sub-shared word line and the second sub-shared word line are arranged at intervals along the second direction and staggered in the first direction.

8. The semiconductor device according to any one of claims 3 to 6, wherein: The at least two sub-storage arrays are located in the same storage array layer, the storage portion has a plurality of storage array layers, and the plurality of storage array layers are stacked in sequence along a direction perpendicular to the substrate; the plurality of storage array layers meet at least one of the following conditions: In the plurality of memory array layers, each sub-memory array whose orthographic projections overlap on the substrate is electrically connected to the same shared bit line; In the plurality of memory array layers, gates of transistors of memory cells whose orthographic projections overlap on the substrate are electrically connected to the same shared word line.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The peripheral circuit section includes a word line driver circuit, and the shared word line is electrically connected to the word line driver circuit; The orthographic projection of the word line driver circuit on the substrate and the orthographic projection of the shared word line on the substrate both overlap with the orthographic projection of the correspondingly connected memory cell on the substrate.

10. The semiconductor device according to claim 9, wherein There are multiple sub-storage arrays, and the multiple sub-storage arrays arranged in sequence along the first direction are divided into at least two storage arrays; The gates of the transistors of the memory cells located at the same corresponding positions in each sub-memory array of the same memory array are electrically connected to the same shared word line; The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to the same shared word line.

11. The semiconductor device according to claim 9, wherein: There are multiple sub-storage arrays, and the multiple sub-storage arrays arranged in sequence along the first direction are divided into at least two storage arrays; The gates of the transistors of the memory cells located at the same corresponding positions in each sub-memory array of the same memory array are electrically connected to the same shared word line; The gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are electrically connected to different shared word lines respectively.

12. The semiconductor device according to claim 11, wherein The word line driver circuit includes at least two sub-word line driver circuits, and the at least two sub-word line driver circuits are connected to the at least two memory arrays in a one-to-one correspondence.

13. The semiconductor device according to claim 11 or 12, wherein: At least two shared word lines electrically connected to the gates of the transistors of the memory cells located at the same corresponding positions in the sub-memory arrays of different memory arrays are located in the same routing layer, or are located in different routing layers.

14. The semiconductor device according to claim 7, wherein: The peripheral circuit unit includes a word line driver circuit, and the first sub-shared word line and the second sub-shared word line connected to the same memory cell are respectively connected to different positions of the same word line driver circuit.

15. The semiconductor device according to any one of claims 3 to 6, wherein: The peripheral circuit section further includes at least two sense amplifier circuits connected to the at least two shared bit lines in a one-to-one correspondence; An orthographic projection of the sense amplifier circuit on the substrate overlaps with an orthographic projection of the correspondingly connected shared bit line on the substrate.

16. The semiconductor device according to claim 6, wherein: The peripheral circuit section includes a word line driver circuit, and the word line driver circuit includes a plurality of sites arranged in a matrix; The shared word lines located in the same routing layer are respectively connected to different sites in the same column of the word line driver circuit, and the shared word lines located in different routing layers are respectively connected to sites in different columns of the word line driver circuit.

17. The semiconductor device according to any one of claims 1 to 16, wherein: Along a direction away from the substrate, the storage part, the routing part and the peripheral circuit part are arranged in sequence.

18. The semiconductor device according to any one of claims 1 to 16, wherein: Along the direction away from the substrate, the peripheral circuit part, the wiring part and the storage part are arranged in sequence.

19. A method for preparing a semiconductor device, the method comprising: providing a substrate; forming a storage portion, a routing portion, and a peripheral circuit portion on one side of the substrate; Wherein, in a direction perpendicular to the substrate, the storage portion, the routing portion and the peripheral circuit portion are located at different positions; the storage portion includes at least two sub-storage arrays, and the at least two sub-storage arrays are arranged in sequence along a first direction parallel to the substrate; the sub-storage array includes at least one storage cell, and the storage cell includes a transistor; The routing section includes at least one shared word line; in the at least two sub-memory arrays, gates of transistors of the memory cells located in different sub-memory arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit section.

20. An electronic device, wherein: include: The semiconductor device according to any one of claims 1 to 18.

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