Method and apparatus for processing data, and communication system

Abstract

The present application belongs to the technical field of communications. Provided are a method and apparatus for processing data, and a communication system. The method comprises: acquiring a data sequence, wherein the data sequence comprises a plurality of forward error correction (FEC) codewords; performing FEC decoding on at least one FEC codeword in the data sequence, so as to obtain at least one decoded codeword; and finding a preset sequence in the at least one decoded codeword. Since the bit error rate of a decoded codeword is lower, the consumed time for searching for a preset sequence in at least one decoded codeword of a data sequence is shorter, such that the efficiency, precision and reliability of searching for the preset sequence in the data sequence can be improved.

Description

Data processing method and device, and communication system

[0001] This application claims priority to Chinese patent application filed on September 4, 2023, with application number 202311139917.5 and application name “Method and device for processing data, communication system”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a method and device for processing data, and a communication system. Background Art

[0003] In the field of communications, when an Ethernet transmitter sends data to a receiver, it periodically inserts a preset sequence into the data. The transmitter then sends a data sequence containing the preset sequence to the receiver. These periodic preset sequences can be used by the receiver to find codeword boundaries in the received data sequence, pad the data sequence to a specific length, and so on. After receiving the data sequence, the receiver finds the preset sequence within the data sequence, removes the preset sequence from the data sequence, and then decodes the data sequence.

[0004] However, due to the influence of channel loss and noise, bit errors are inevitable in the process of transmitting the data sequence from the sending end to the receiving end. Bit errors are inevitable in the data sequence received by the receiving end. These bit errors can easily increase the time taken by the receiving end to search for the preset sequence in the data sequence, and even cause the receiving end to be unable to find the true preset sequence in the data sequence, affecting the data processing of the receiving end.

[0005] Summary of the Invention

[0006] The present application provides a method and device for processing data, and a communication system, which can shorten the time spent searching for a preset sequence in a data sequence and improve the efficiency, accuracy, and reliability of searching for a preset sequence in a data sequence. The technical solution of the present application is as follows.

[0007] In a first aspect, a method for processing data is provided, the method comprising: obtaining a data sequence, the data sequence comprising a plurality of forward error correction (FEC) codewords; performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; and finding a preset sequence in the at least one decoded codeword.

[0008] The technical solution provided in the present application searches for a preset sequence based on decoded data. Since error detection and correction can be performed on at least one FEC codeword in a data sequence during FEC decoding of the at least one FEC codeword, the at least one decoded codeword obtained by FEC decoding of the at least one FEC codeword has a low bit error rate or may even have no bit errors. This shortens the time spent searching for the preset sequence in the at least one decoded codeword, and increases efficiency, accuracy, and reliability, thereby ensuring the transmission efficiency and reliability of the communication system.

[0009] Optionally, the preset sequence is a sequence that appears periodically in the data sequence. The period in which the preset sequence appears in the data sequence may be a strict period or a non-strict period, with different strict periods being strictly equal, and different non-strict periods being unequal, with the difference between different non-strict periods being less than a preset difference. Optionally, the period in which the preset sequence appears in the data sequence is a non-strict period, and the regularity with which the preset sequence appears in the data sequence is generally periodic.

[0010] Optionally, the method includes: if a preset condition is met, deleting a padding sequence associated with the preset sequence in the data sequence based on the position of the found preset sequence in the data sequence, the preset condition including that the number of the preset sequence included in n codewords of the at least one decoded codeword reaches a first threshold, where n is a positive integer, and the interval between adjacent codewords in the n codewords is the period during which the preset sequence appears in the data sequence. The padding sequence associated with the preset sequence may be a padding sequence that includes the preset sequence.

[0011] Optionally, the method includes: if a loss of lock condition is met, re-searching the FEC codeword boundary in the data sequence, the loss of lock condition including that the number of m codewords in the at least one decoded codeword that do not include codewords of the preset sequence reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period of appearance of the preset sequence in the data sequence.

[0012] The technical solution provided by the present application is that, when the number of codewords that do not include a preset sequence among the m codewords in the at least one decoded codeword reaches a second threshold, it can be considered that the locked FEC codeword boundary is incorrect and the locked FEC codeword boundary is lost, so the FEC codeword boundary in the data sequence is re-searched to facilitate FEC decoding of the data sequence based on the re-found FEC codeword boundary.

[0013] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword includes: performing FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; correspondingly, finding a preset sequence in the at least one decoded codeword includes: finding the preset sequence in the multiple decoded codewords. Optionally, searching for the preset sequence in the multiple decoded codewords sequentially according to the arrangement order of the multiple decoded codewords until the first preset sequence is found; after finding the first preset sequence, searching for the preset sequence in the codewords following the codeword containing the first preset sequence according to the period at which the preset sequence appears in the data sequence. That is, searching for the first preset sequence in the multiple decoded codewords codeword by codeword, and after finding the first preset sequence, no longer searching for the preset sequence codeword by codeword, but searching for the preset sequence in the multiple decoded codewords according to the period at which the preset sequence appears in the data sequence.

[0014] The technical solution provided by the present application searches for the first preset sequence codeword by codeword. After finding the first preset sequence, the preset sequence is searched in the multiple decoded codewords according to the period at which the preset sequence appears in the data sequence. This can improve the efficiency of searching for the preset sequence.

[0015] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, includes: performing FEC decoding on the first FEC codeword in the data sequence to obtain the first decoded codeword; if the first decoded codeword does not include the preset sequence, continuing to perform FEC decoding on FEC codewords subsequent to the first FEC codeword in the data sequence until the first preset sequence is found. For example, searching for the preset sequence in the first decoded codeword; if the preset sequence is not found in the first decoded codeword, sequentially performing FEC decoding on FEC codewords subsequent to the first FEC codeword in the data sequence according to the order in which the FEC codewords in the data sequence are arranged, and searching for the preset sequence in the decoded codewords until the first preset sequence is found. The first FEC codeword is an FEC codeword in the data sequence, for example, the first FEC codeword in the data sequence.

[0016] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, further includes: if the decoded first codeword includes the preset sequence, performing FEC decoding on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein the interval between the second FEC codeword and the first FEC codeword is the period during which the preset sequence appears in the data sequence; and attempting to find the preset sequence in the decoded second codeword. That is, searching for the first preset sequence in the data sequence FEC codeword by FEC codeword, and after finding the first preset sequence, no longer searching for the preset sequence FEC codeword by FEC codeword, but searching for the preset sequence in the data sequence according to the period during which the preset sequence appears in the data sequence.

[0017] The technical solution provided by the present application attempts to find a preset sequence in the data sequence according to the period at which the preset sequence appears in the data sequence after finding the first preset sequence in the data sequence, which can improve the efficiency of finding the preset sequence.

[0018] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence includes: performing FEC decoding on the first FEC codeword in the data sequence using a first decoding method; and performing FEC decoding on candidate FEC codewords following the first FEC codeword in the data sequence using a second decoding method. For example, during the process of locking the preset sequence, the FEC codewords in the data sequence (including the first FEC codeword and possibly the second FEC codeword) are FEC-decoded using the first decoding method, and after the preset sequence is locked, the candidate FEC codewords following the first FEC codeword in the data sequence are FEC-decoded using the second decoding method. The candidate FEC codewords include all undecoded FEC codewords in the data sequence after the preset sequence is locked.

[0019] The technical solution provided by the present application is that the first decoding method is different from the second decoding method, and the decoding method used during the preset sequence locking process is different from the decoding method used after the preset sequence is locked, which can increase the applicability of the present application.

[0020] Optionally, the first decoding method is soft-decision decoding (SDD), and the second decoding method is hard-decision decoding (HDD). Alternatively, the first decoding method is HDD, and the second decoding method is SDD. Optionally, SDD is used to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and HDD is used to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. Alternatively, HDD is used to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and SDD is used to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. The complexity of HDD decoding is low, and the decoding performance of SDD is better. After the preset sequence is locked, formal data processing is performed on the data sequence, and the formal data processing includes FEC decoding on the FEC codewords in the data sequence. That is, the process of performing FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked belongs to the process of performing formal data processing on the data sequence.

[0021] The technical solution provided by this application, when the first decoding mode is HDD and the second decoding mode is SDD, uses HDD to perform FEC decoding on FEC codewords in a data sequence during the preset sequence locking process, and uses SDD to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. This reduces the complexity of locking the preset sequence and ensures the error performance of formal data processing. When the first decoding mode is SDD and the second decoding mode is HDD, uses SDD to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and uses HDD to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. This improves the reliability of locking the preset sequence and reduces the complexity of formal data processing.

[0022] Optionally, the first decoding method and the second decoding method are implemented using the same hardware logic, thereby reducing implementation complexity and cost.

[0023] Optionally, before performing FEC decoding on at least one FEC codeword in the data sequence, the method further includes: determining an FEC codeword boundary in the data sequence by self-synchronization.

[0024] The technical solution provided in the present application determines the FEC codeword boundaries in the data sequence by self-synchronization, which can achieve the technical effect of high-precision codeword synchronization. The reliability of the FEC codeword boundaries determined by self-synchronization is high.

[0025] Optionally, the preset sequence is a frame sequence (FS) or the preset sequence is in an alignment marker (AM). This enables the technical solution of the present application to interoperate with the Institute of Electrical and Electronics Engineers (IEEE) 802.3dj standard and the 200 / 400 Gigabit Ethernet (GE) standard.

[0026] Optionally, the preset sequence is FS, the filling sequence associated with the preset sequence is the filling sequence in the IEEE802.3dj standard, the preset sequence is located at the beginning of the filling sequence associated with the preset sequence, and the length of the filling sequence is an integer multiple of the length of the FEC codeword in the data sequence.

[0027] Optionally, the method is performed by a host chip, an optical module, or a chip in the optical module. The optical module may be a pluggable optical module.

[0028] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0029] Optionally, the Ethernet signal is a Terabit Ethernet (TbE) signal.

[0030] In a second aspect, a device for processing data is provided, wherein the device is used to execute the method provided in the first aspect or any optional implementation of the first aspect.

[0031] Optionally, the device includes an Ethernet interface, which may be a Terabit Ethernet interface.

[0032] Optionally, the device is any one of the following: a forwarding device, a user terminal device or a server device, a host chip, an optical module or a chip in an optical module. The forwarding device may be a router or a switch.

[0033] In one implementation, the apparatus includes at least one module configured to execute the method provided in the first aspect or any optional aspect of the first aspect. The at least one module may be implemented based on software, hardware, or a combination of software and hardware, and the at least one module may be arbitrarily combined or divided based on the specific implementation.

[0034] Optionally, the device includes:

[0035] An acquisition module, configured to acquire a data sequence, wherein the data sequence includes a plurality of forward error correction (FEC) codewords;

[0036] a decoding module, configured to perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword;

[0037] A searching module is configured to find a preset sequence in the at least one decoded codeword.

[0038] Optionally, the preset sequence is a sequence that appears periodically in the data sequence.

[0039] Optionally, the device further includes: a deletion module, configured to delete a padding sequence related to the preset sequence in the data sequence based on the position of the preset sequence found in the data sequence if a preset condition is met, wherein the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, where n is a positive integer, and the interval between adjacent codewords in the n codewords is the period in which the preset sequence appears in the data sequence.

[0040] Optionally, the device further includes: a synchronization module, configured to re-search the FEC codeword boundary in the data sequence if a loss of lock condition is met, wherein the loss of lock condition includes that the number of m codewords in the at least one decoded codeword that do not include codewords of the preset sequence reaches a second threshold, where m is a positive integer, and the interval between adjacent codewords in the m codewords is the period in which the preset sequence appears in the data sequence.

[0041] Optionally, the decoding module is configured to perform FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords;

[0042] Correspondingly, the searching module is configured to find a preset sequence among the multiple decoded code words.

[0043] Optionally, the decoding module is used to:

[0044] Performing FEC decoding on a first FEC codeword in the data sequence to obtain a decoded first codeword;

[0045] If the decoded first codeword does not include the preset sequence, FEC decoding is continued on the FEC codewords following the first FEC codeword in the data sequence until a first preset sequence is found.

[0046] Optionally, the decoding module is further configured to: if the decoded first codeword includes the preset sequence, perform FEC decoding on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein an interval between the second FEC codeword and the first FEC codeword is a period during which the preset sequence appears in the data sequence;

[0047] Correspondingly, the searching module is configured to attempt to search for the preset sequence in the decoded second codeword.

[0048] Optionally, the decoding module is used to: perform FEC decoding on the first FEC codeword in the data sequence using a first decoding method; and perform FEC decoding on the candidate FEC codewords following the first FEC codeword in the data sequence using a second decoding method.

[0049] Optional; the first decoding mode is soft decision decoding, and the second decoding mode is hard decision decoding; or,

[0050] The first decoding mode is hard decision decoding, and the second decoding mode is soft decision decoding.

[0051] Optionally, the device further includes: a synchronization module, configured to determine the FEC codeword boundary in the data sequence by self-synchronization.

[0052] Optionally, the preset sequence is a frame sequence FS or the preset sequence is in an alignment mark AM.

[0053] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0054] Optionally, the Ethernet signal is a Terabit Ethernet signal.

[0055] In another implementation, the apparatus includes: a memory, a processor, and a communication interface, wherein the communication interface includes an Ethernet interface;

[0056] The memory is used to store computer programs; the processor is used to execute the computer programs stored in the memory so that the device performs relevant steps in the method provided in the first aspect or any optional manner of the first aspect.

[0057] Optionally, the processor is used to execute a computer program stored in the memory so that the device performs: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by performing FEC decoding on at least one forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

[0058] Optionally, the processor is used to execute the computer program stored in the memory and further causes the device to execute: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence based on the position of the preset sequence found in the data sequence, the preset condition including that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0059] In a third aspect, a chip is provided for executing the method provided in the first aspect or any optional manner of the first aspect.

[0060] Optionally, the chip is a main chip or a chip in an optical module, and the chip includes a programmable logic circuit and / or program instructions.

[0061] In a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed, it is implemented: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by performing FEC decoding on at least one forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

[0062] Optionally, when the computer program is executed, it further implements: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence based on the position of the preset sequence found in the data sequence, wherein the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0063] In a fifth aspect, a computer program product is provided, comprising a program or code, which, when executed, implements: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by performing FEC decoding on at least one forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

[0064] Optionally, when the program or code is executed, it further implements: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence based on the position of the preset sequence found in the data sequence, wherein the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0065] In the sixth aspect, a communication system is provided, comprising an optical module and a host, wherein the optical module is communicatively connected to the host, for example, the optical module is plugged into the host, and the optical module is used to execute the method provided in the first aspect or any optional method of the first aspect.

[0066] Optionally, the host is a forwarding device, a user terminal device or a server device. The forwarding device is a router or a switch.

[0067] The technical solution provided by the present application is that since the optical module is used to execute the method provided by the first aspect or any optional method of the first aspect mentioned above, the optical module can improve the efficiency, accuracy and reliability of searching for a preset sequence in a data sequence by executing the above method, thereby enabling the host connected to the optical module to obtain corresponding benefits, such as improving the host's processing efficiency and reliability of the data sequence.

[0068] The technical effects not described in the above-mentioned second to sixth aspects can refer to the technical effects of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG1 is a schematic diagram of a physical layer transmitting data;

[0070] FIG2 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0071] FIG3 is a schematic diagram of a data sequence provided in an embodiment of the present application;

[0072] FIG4 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0073] FIG5 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0074] FIG6 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0075] FIG7 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0076] FIG8 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0077] FIG9 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0078] FIG10 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0079] FIG11 is a flow chart of a method for processing data provided in an embodiment of the present application;

[0080] FIG12 is a flow chart of another method for processing data provided in an embodiment of the present application;

[0081] FIG13 is a schematic diagram of a method for processing data provided in an embodiment of the present application;

[0082] FIG14 is a state diagram of a preset sequence locking process provided by an embodiment of the present application;

[0083] FIG15 is a state diagram of a preset sequence monitoring process provided by an embodiment of the present application;

[0084] FIG16 is a schematic diagram of a data processing device provided in an embodiment of the present application;

[0085] FIG17 is a schematic diagram of another apparatus for processing data provided by an embodiment of the present application;

[0086] FIG18 is a schematic diagram of another data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0087] The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0088] Synchronization technology is a crucial technology in the communications field and is used in a wide variety of scenarios. Based on different goals, synchronization can be categorized into various types, including clock synchronization, carrier synchronization, bit synchronization, and frame synchronization. Clock synchronization ensures time consistency between different devices. Carrier synchronization refers to the process by which the receiver extracts a coherent carrier from the received signal in coherent optical transmission. Bit synchronization refers to the process by which the receiver extracts the clock signal from the received signal to correctly sample and determine the information symbols. Frame synchronization refers to the process by which the receiver identifies the beginning or end of a specific data block within a received data sequence (or data stream). For example, a data sequence received by a receiver includes multiple codewords (CWs). Frame synchronization is the process by which the receiver identifies the beginning or end of a codeword within the data sequence. The beginning and end of a codeword are also called codeword boundaries. Therefore, frame synchronization refers to the process by which the receiver identifies codeword boundaries within the received data sequence. Optionally, the data sequence received by the receiving end is a data sequence that has been encoded with forward error correction (FEC), and the codewords in the data sequence are FEC codewords. Frame synchronization refers to the process by which the receiving end identifies FEC codeword boundaries from the data sequence. FEC codeword boundaries are also referred to as FEC codeword boundaries. In some implementation scenarios, frame synchronization is also referred to as codeword synchronization, and the codeword boundaries in the data sequence are also referred to as synchronization positions.

[0089] In the field of communications, when an Ethernet transmitter sends data to a receiver, it periodically inserts a preset sequence into the data, and then sends a data sequence containing the preset sequence to the receiver. These periodic preset sequences may be used by the receiver to find codeword boundaries in the received data sequence, or to pad the data sequence to a specific length, etc. After receiving the data sequence, the receiver finds the preset sequence in the data sequence, deletes the preset sequence in the data sequence, and then decodes the data sequence. Figure 1 is a schematic diagram of physical layer data transmission adopted by the Institute of Electrical and Electronics Engineers (IEEE) 802.3dj standard project. As shown in Figure 1, the transmitting end includes a host chip and an optical module. The host chip and the optical module are connected via an attachment unit interface (AUI). When the transmitting end sends data sequence A0, the host chip first performs a first FEC encoding on data sequence A0 to obtain data sequence A1. The host chip sends data sequence A1 to the optical module via the AUI. The optical module performs a second FEC encoding on data sequence A1 and periodically inserts a padding sequence into data sequence A1 to obtain data sequence A2. The optical module sends data sequence A2 to the receiving end. Data sequence A2 includes multiple codewords (CWs) and multiple padding sequences. Each CW in the multiple CWs is an FEC codeword obtained by the second FEC encoding. Optionally, the optical module also interleaves the FEC codewords obtained by the second FEC encoding. In this case, each CW in data sequence A2 is an interleaved codeword block obtained after the FEC codewords are interleaved (that is, an equal-length data block obtained after the FEC codewords are interleaved). The optical module may also not interleave the FEC codewords obtained by the second FEC encoding, which is not limited in the embodiments of the present application. The multiple filling sequences appear periodically in the data sequence A2, and each of the multiple filling sequences includes a preset sequence known to both the transmitting end and the receiving end. For example, the preset sequence is referred to as a frame sequence (FS) in the IEEE802.3dj standard discussion. The preset sequence in each filling sequence is located at the beginning of the filling sequence, and the starting position of the preset sequence in each filling sequence is the same as the starting position of the filling sequence.The padding sequence also undergoes the second FEC encoding and possible interleaving. The length of each padding sequence is an integer multiple of the length of the CW (Figure 1 uses k times as an example, where k is a positive integer, e.g., k = 2). Therefore, each padding sequence can be considered to include an integer number of padding CWs (padding CWs), which can also be called virtual CWs or simulated CWs. These integer number of padding CWs are additionally inserted by the transmitter into the data sequence to be transmitted. For example, if the CW is an FEC codeword obtained through the second FEC encoding, the optical module inserts three padding codewords every 3264 FEC codewords (the padding codewords are also FEC codewords, meaning the padding sequence length is three times the FEC codeword length), or inserts eight padding codewords every 8704 FEC codewords (the padding codewords are also FEC codewords, meaning the padding sequence length is eight times the FEC codeword length).

[0090] After receiving data sequence A2, the receiver needs to locate codeword boundaries in data sequence A2 to perform the second FEC decoding (i.e., FEC decoding corresponding to the second FEC encoding) on ​​data sequence A2. For example, if the CW in data sequence A2 is an FEC codeword obtained through the second FEC encoding, the codeword boundary is the CW boundary in Figure 1, which is also an FEC codeword boundary. If the CW in data sequence A2 is an interleaved codeword block obtained by interleaving the FEC codeword obtained through the second FEC encoding, the receiver first deinterleaves data sequence A2 and then locates codeword boundaries in data sequence A2. Because the padding sequence is additionally inserted non-media access control (MAC) data, the receiver also needs to locate the padding sequence in data sequence A2 and remove it. The receiver can locate the padding sequence in data sequence A2 by searching for a preset sequence known to the receiver in data sequence A2. The receiver can locate the codeword boundaries in data sequence A2 by performing codeword synchronization on data sequence A2. Here, the example in which the CW in data sequence A2 is an FEC codeword obtained through second FEC encoding without interleaving is used for illustration. After the receiving end finds the codeword boundary in data sequence A2, it determines the CW in data sequence A2 based on the codeword boundary and performs second FEC decoding on the CW in data sequence A2. Optionally, after performing second FEC decoding on data sequence A2, the receiving end obtains data sequence A1. The receiving end also performs first FEC decoding (i.e., FEC decoding corresponding to the first FEC encoding) on ​​data sequence A1 to obtain data sequence A0. It should be noted that the description herein uses first FEC encoding, second FEC encoding, first FEC decoding, and second FEC decoding as examples. In some implementation scenarios or documents, the first FEC encoding is also described as outer FEC encoding or outer code encoding, the second FEC encoding is also described as inner FEC encoding or inner code encoding, the first FEC decoding is also described as outer FEC decoding or outer code decoding, and the second FEC decoding is also described as inner FEC decoding or inner code decoding. This is not limited in the present embodiment.

[0091] The IEEE 802.3dj standard discusses a codeword synchronization scheme. The following describes a receiver using this codeword synchronization scheme to search for codeword boundaries in data sequence A2. Furthermore, the CW in data sequence A2 is an FEC codeword obtained through second FEC encoding without interleaving. The default sequence in data sequence A2 is described as the FS. The receiver first searches for the FS in data sequence A2 based on a known FS. Then, based on the FS found in data sequence A2, it determines the codeword boundaries in data sequence A2. This process involves both FS locking and FS monitoring. Specifically, the FS locking process includes: the receiver compares the FS known to the receiver bit by bit with data sequence A2 to search for a FS in data sequence A2. After the receiver finds the first FS in data sequence A2, the receiver searches for FSs in data sequence A2 based on the first FS and the periodicity of the FS in data sequence A2. If the receiver finds a specified number of FSs in data sequence A2 consecutively (e.g., 3), the receiver considers the first FS found to be the true FS and locks the first FS. The FS monitoring process includes: after the receiver locks the first FS, the receiver determines the potential FS locations in data sequence A2 based on the target FS found during the FS locking process (e.g., the target FS is the last FS found during the FS locking process) and the periodicity of the FS in data sequence A2. The receiver verifies whether the data content of the potential FS locations matches the content of the FSs known to the receiver. If the data content of a potential FS location matches the content of the known FS, the receiver determines that the data content of the potential FS location is a FS (i.e., the receiver has found a FS), and the receiver successfully verifies the potential FS location. If the receiving end fails to verify multiple potential FS positions that appear consecutively, the receiving end determines that the first locked FS has lost lock. The receiving end then re-locks the FS on data sequence A2 (i.e., re-executes the FS locking process) and performs FS monitoring on data sequence A2 based on the re-locked FS (i.e., re-executes the FS monitoring process). This forms a closed-loop process of FS locking, FS monitoring, and FS locking. After the receiving end locks the FS in data sequence A2, it determines the codeword boundaries in data sequence A2 based on the locked FS in data sequence A2. A potential FS position is a location where the FS may appear. A potential FS position is a region in data sequence A2 with a length equal to the FS length.For example, if the target FS is in bits a1 to (a1+48), and the period of FS appearance is (3264*128+3*128) bits, then the potential FS positions are bits [a1+(3264*128+3*128)] to [(a1+48)+(3264*128+3*128)], bits [a1+2*(3264*128+3*128)] to [(a1+48)+2*(3264*128+3*128)], ..., 3264*128 bits is the period of the filling sequence appearing in data sequence A2, and 3*128 is the length of the filling sequence. For another example, if the period of FS occurrence is (8704*128+8*128) bits, then the potential FS positions are bits [a1+(8704*128+8*128)] to [(a1+48)+(8704*128+8*128)], bits [a1+2*(8704*128+8*128)] to [(a1+48)+2*(8704*128+8*128)], ..., where 8704*128 bits is the interval of the padding sequence, and 8*128 is the length of the padding sequence.

[0092] The 200 / 400 Gigabit Ethernet (GE) standard defined by the IEEE802.3bs project also mentions a codeword synchronization scheme. This codeword synchronization scheme differs from the codeword synchronization scheme discussed in the IEEE802.3dj standard in that the padding sequence is replaced with an alignment marker (AM). Specifically, when the transmitter sends data sequence B0, the transmitter performs FEC encoding on data sequence B0 and periodically inserts AM into data sequence B0 to obtain data sequence B1. The transmitter sends data sequence B1 to the receiver. Data sequence B1 includes multiple CWs and multiple AMs, and each CW in the multiple CWs is an FEC codeword obtained through the FEC encoding. Optionally, the transmitter also interleaves the FEC codewords obtained through the FEC encoding. In this case, each CW in data sequence B1 is an interleaved codeword block obtained after the FEC codewords are interleaved. The transmitter may also not interleave the FEC codewords obtained through the FEC encoding, and this embodiment of the present application does not limit this. These multiple AMs appear periodically in data sequence B1. Each of these multiple AMs includes a preset sequence known to both the transmitter and receiver. The AM has also undergone FEC encoding and possibly interleaving. For example, taking the example of a CW in data sequence B1 being an FEC codeword obtained through FEC encoding but not interleaving, after receiving data sequence B1, the receiver searches for the AM in data sequence B1 based on the preset sequence known to the receiver. For example, the receiver searches for the preset sequence in data sequence B1 based on the preset sequence known to the receiver. Based on the preset sequence found, the receiver finds the AM that includes the preset sequence. Based on the AM found in data sequence B1, the receiver determines the codeword boundary in data sequence B1. The process of the receiver searching for the AM in data sequence A2 based on the preset sequence known to the receiver includes an AM locking process and an AM monitoring process. Specifically, the AM locking process includes: the receiving end compares the preset sequence known to the receiving end and the data sequence B1 bit by bit to search for AM in the data sequence B1. After the receiving end finds the first AM in the data sequence B1, the receiving end searches for AM in the data sequence B1 based on the first AM and the period at which AM appears in the data sequence B1. If the number of AMs found continuously in the data sequence B1 by the receiving end reaches a specified number (for example, 3), the receiving end considers that the first AM found is the real AM, and the receiving end locks the first AM.The AM monitoring process includes: after the receiving end locks onto the first AM, the receiving end determines the potential AM position in data sequence B1 based on the target AM found during the AM locking process (for example, the target AM is the last AM found during the AM locking process) and the periodicity of the AM appearance in data sequence B1. The receiving end verifies whether the data content of the potential AM position matches the content of a preset sequence known to the receiving end. If the data content of a potential AM position matches the content of the known preset sequence, the receiving end determines that the data content of the potential AM position is an AM (i.e., the receiving end has found an AM in data sequence B1), and the receiving end has successfully verified the potential AM position. If the receiving end fails to verify multiple potential AM positions that appear consecutively, the receiving end determines that the first AM locked has lost lock, and the receiving end re-AM locks data sequence B1 (i.e., re-executes the AM locking process). The receiving end then performs AM monitoring on data sequence B1 based on the re-locked AM (i.e., re-executes the AM monitoring process), thus forming a closed-loop process of AM locking, AM monitoring, and AM locking. After the receiver locks the AM in data sequence B1, it determines the codeword boundaries in data sequence B1 based on the locked AM in data sequence B1. A potential AM position is a location where AM may appear. A potential AM position is a region in data sequence B1 with a length equal to the AM length. For example, if the target AM is between bits b1 and (b1+1028), and the AM occurrence period is 4096*5440 bits, then the potential AM positions are bits (b1+4096*5440) to [(b1+1028)+4096*5440], bits (b1+2*4096*5440) to [(b1+1028)+2*4096*5440], and so on, where 1028 is the AM length. For another example, if the target AM occurs in bits b1 to (b1+1028), and the AM occurrence period is 2*4096*5440 bits, then the potential AM positions are bits (b1+2*4096*5440) to [(b1+1028)+2*4096*5440], bits (b1+2*2*4096*5440) to [(b1+1028)+2*2*4096*5440], and so on. After the receiver finds the codeword boundary in data sequence B1, it determines the codeword in data sequence B1 (e.g., the aforementioned CW) based on the codeword boundary in data sequence B1 and performs FEC decoding on the codeword in data sequence B1.In the codeword synchronization scheme mentioned in the 200 / 400GE standard defined in the IEEE802.3bs project, the receiving end continuously monitors data sequence B1 for uncorrectable codewords during FEC decoding of the data sequence B1. If the number of uncorrectable codewords (i.e., uncorrectable codewords) that appear consecutively in data sequence B1 reaches a preset number, or the proportion of uncorrectable codewords that appear consecutively in data sequence B1 reaches a preset ratio, the receiving end considers that the currently locked AM has lost lock, and the receiving end re-locks the AM of the data sequence B1. The receiving end monitors the data sequence B1 based on the re-locked AM, re-determines the codeword boundaries in the data sequence B1 based on the re-locked AM, and performs FEC decoding on the data sequence B1 based on the re-determined codeword boundaries.

[0093] According to the above description, whether it is the above-mentioned codeword synchronization scheme mentioned in the IEEE802.3dj standard discussion or the above-mentioned codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project, it is necessary to use additional data inserted in the data sequence (such as FS in the IEEE802.3dj standard discussion, AM in the 200 / 400GE standard defined by the IEEE802.3bs project) to find the codeword boundary in the data sequence. According to the above description, the process of the receiving end finding (or identifying) the codeword boundary in the data sequence is called codeword synchronization (or frame synchronization). In the embodiment of the present application, the synchronization scheme that uses additional data such as FS and AM inserted in the data sequence to find or identify the codeword boundary in the data sequence is called a non-self-synchronization scheme. Therefore, the above-mentioned codeword synchronization scheme mentioned in the IEEE802.3dj standard discussion and the above-mentioned codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project are both non-self-synchronization schemes. Since the non-self-synchronization scheme requires additional data inserted into the data sequence to find the codeword boundary in the data sequence, the accuracy of finding the codeword boundary in the data sequence is low, the time consumption is long, the efficiency is low, and the reliability is low.

[0094] Specifically, in the codeword synchronization scheme discussed in the IEEE 802.3dj standard, both FS locking and FS monitoring are performed based on the pre-decoded data sequence. Specifically, the receiver searches for the FS in the pre-decoded data sequence and then searches for codeword boundaries based on the found FS. Because errors are inevitable during the transmission of a data sequence from a transmitter to a receiver, errors are inevitably present in the pre-decoded data sequence, and the pre-decoded data sequence may have a high bit error rate (BER), such as a high bit error rate (BER). This can increase the time it takes for the receiver to search for the FS, or even prevent it from finding the true FS. This, in turn, reduces the efficiency, stability, and reliability of the receiver's codeword boundary search. For example, errors in the FS in data sequence A2 can easily prevent the receiver from finding the true FS during the FS locking process, resulting in the receiver missing the true FS. This increases the time it takes to lock the FS and increases the probability that the receiver will incorrectly lock the FS. For example, bit errors in the FS of data sequence A2 can easily cause the receiver to fail to verify the correct FS position during FS monitoring, requiring re-locking and re-monitoring. Bit errors in data sequence A2 can easily cause the receiver to repeatedly lock and monitor the data sequence, hindering its ability to find codeword boundaries, affecting subsequent processing of the data sequence, and compromising the transmission efficiency of the communication system.

[0095] Specifically, in the codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project, AM locking and AM monitoring are both performed based on the pre-decoded data sequence. That is, the receiver searches for AM in the pre-decoded data sequence and then searches for codeword boundaries based on the found AM. Because bit errors are inevitable in the pre-decoded data sequence, and the bit error rate of the pre-decoded data sequence may be high, this increases the time it takes for the receiver to search for AM, and may even cause the receiver to be unable to find the actual AM. This, in turn, reduces the efficiency, stability, and reliability of the receiver's search for codeword boundaries. Furthermore, the codeword synchronization scheme mentioned in the 200 / 400GE standard requires additional verification logic (e.g., additional hardware circuitry) for uncorrectable codeword monitoring, making the implementation process complex and costly.

[0096] In addition to the two codeword synchronization schemes described above, a self-synchronization (self-sync) scheme can also be used to find codeword boundaries in a data sequence. Based on the codeword boundaries found in the data sequence using the self-synchronization scheme, the receiving end searches for a preset sequence (e.g., FS) in the data sequence, thereby finding a padding sequence that includes the preset sequence and deleting the padding sequence. Furthermore, the receiving end determines the codewords in the data sequence based on the codeword boundaries found in the data sequence, and then performs codeword decoding on the data sequence.

[0097] Self-synchronization refers to the process by which a receiving end searches for or identifies codeword boundaries in a data sequence based on the intrinsic features of the data sequence. In a self-synchronization scheme, the receiving end does not need to rely on additional data inserted into the data sequence, such as FS or AM, to search for or identify codeword boundaries in the data sequence. In one embodiment, after receiving a data sequence, the receiving end attempts to partition the data sequence based on the length of the codewords in the data sequence known to the receiving end (e.g., 128 bits) and decodes the resulting test data blocks, where the length of the test data blocks is the length of the codewords. The receiving end determines whether the location at which the data sequence is partitioned is a codeword boundary based on the decoding result of the test data blocks. It should be noted that since the receiving end attempts to divide the data sequence to obtain test data blocks with a length equal to the length of the codeword, the test data blocks obtained by the receiving end may be real codewords or not. For example, when the division position is exactly at the codeword boundary, the test data block obtained by the division is a real codeword, and when the division position is not at the codeword boundary, the test data block obtained by the division is not a real codeword. Since the length of the test data block obtained by the division is equal to the length of the codeword, for simplicity, the test data block obtained by the division is described as a "codeword" here. For example, the receiving end divides the data sequence into multiple codewords based on the codeword length known to the receiving end (that is, the length of the codeword in the data sequence), and the receiving end decodes the multiple codewords; the receiving end determines the number of uncorrectable codewords in the multiple codewords based on the decoding results; if the number of uncorrectable codewords in the multiple codewords does not reach a preset number, or the ratio of the number of uncorrectable codewords in the multiple codewords (for example, the ratio of the number of uncorrectable codewords in the multiple codewords to the number of the multiple codewords) does not reach a preset ratio, the receiving end determines that the codeword division of the data sequence is correct. The division position is a codeword boundary, that is, the receiving end has found a codeword boundary in the data sequence; if the number of uncorrectable codewords in the multiple codewords reaches a preset number, or the proportion of uncorrectable codewords in the multiple codewords reaches a preset ratio, the receiving end determines that the division position of the codeword division of the data sequence is not a codeword boundary, and the receiving end re-divides the data sequence into codewords based on the codeword length known to the receiving end, decodes the re-divided codewords, and determines whether the division position of the codeword division of the data sequence is a codeword boundary based on the decoding result. This process is repeated until a codeword boundary is found.In addition, the self-synchronization scheme is only described here as an example. For the specific implementation of the self-synchronization scheme, please refer to the patent application document "Codeword Synchronization Method, Receiver, Network Device and Network System" with publication number CN113517949A, and the reference standard document "Inner Codeword Self-sync Proposal" (address: https: / / www.ieee802.org / 3 / dj / public / 23_07 / he_3dj_03b_2307.pdf). The entire contents of them are incorporated herein by reference, as if all statements are made. This article does not elaborate on the self-synchronization scheme.

[0098] Specifically, in the self-synchronization scheme, after receiving the data sequence, the receiving end uses a self-synchronization method to find the codeword boundary in the data sequence. After finding the codeword boundary in the data sequence, the receiving end locks the codeword boundary in the data sequence. The receiving end searches for a preset sequence (such as FS) in the data sequence based on the locked codeword boundary. Specifically, the receiving end first performs a preset sequence lock on the data sequence based on the locked codeword boundary, and then performs a preset sequence monitoring on the data sequence based on the locked codeword boundary and the locked preset sequence. The receiving end can find the preset sequence that appears periodically in the data sequence by performing preset sequence locking and preset sequence monitoring on the data sequence, and the receiving end can delete the padding sequence including these preset sequences in the data sequence. The receiving end also determines the codeword in the data sequence based on the codeword boundary locked in the data sequence, and decodes the codeword in the data sequence. After locking the codeword boundary in the data sequence, the receiving end also monitors the codeword boundary of the data sequence to determine whether the locked codeword boundary is lost. If the locked codeword boundary is lost, the receiving end uses a self-synchronization method to re-search the codeword boundary in the data sequence, and re-searches the preset sequence in the data sequence based on the re-found codeword boundary, and so on.

[0099] Based on the above description of the self-synchronization scheme, it can be seen that the self-synchronization scheme can find codeword boundaries in a data sequence without the need for additional data inserted into the data sequence. Therefore, the codeword boundary search process is not affected by this additional data, resulting in higher accuracy, shorter time consumption, higher efficiency, and higher reliability. However, if the receiving end still searches for the preset sequence in the pre-decoded data sequence, bit errors in the pre-decoded data sequence can easily increase the time it takes to find the preset sequence, thereby affecting the receiving end's subsequent processing of the data sequence. For example, if the preset sequence is a FS, bit errors in the FS in the pre-decoded data sequence can easily prevent the receiving end from finding the true FS, increasing the probability of finding an erroneous FS and significantly reducing the reliability of the FS found by the receiving end. For another example, bit errors in the FS in the pre-decoded data sequence can easily cause the receiving end to fail to verify the correct FS position during FS monitoring, increasing the time it takes to find the true FS and reducing the efficiency of FS search in the data sequence.

[0100] Embodiments of the present application provide a method, apparatus, and communication system for processing data. These methods, apparatus, and communication system are based on the same inventive concept. In this method, after a receiving end obtains a data sequence including multiple FEC codewords, the receiving end performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword. The receiving end then finds a preset sequence in the at least one decoded codeword. For example, the preset sequence is the FS mentioned in the IEEE 802.3dj standard discussion, or the AM mentioned in the 200 / 400GE standard defined in the IEEE 802.3bs project. During the FEC decoding process, the receiving end can perform error detection and correction on the at least one FEC codeword in the data sequence. Most errors are corrected during the FEC decoding process. Therefore, the at least one decoded codeword obtained through FEC decoding has a low bit error rate or may even be error-free. This reduces the impact of errors on the efficiency of the receiving end in searching for the preset sequence. The time spent by the receiving end in searching for the preset sequence in the at least one decoded codeword is short, and efficiency, accuracy, and reliability are all high, thereby ensuring the transmission efficiency and reliability of the communication system. Since most bit errors are corrected during the FEC decoding process, the mean time to lock (MTTL) of a preset sequence (e.g., FS) can be significantly reduced, and the mean time to false-unlock (MTTFU) of a preset sequence (e.g., FS) can be significantly improved. MTTL is the average duration of the preset sequence locking process, which is determined based on the locking probability. For example, if a preset sequence locking process is performed p times (p is a positive integer) on a data sequence, and the duration of most of the locking processes during these p locking processes is the first duration (e.g., the number of locking processes with the first duration during these p locking processes is greater than the first number), then the MTTL of the data sequence is the first duration. MTTFU is the average duration of the preset sequence being locked during the preset sequence monitoring process (that is, the duration from the start of the preset sequence monitoring to the determination of the preset sequence being locked). MTTFU is a duration determined based on the locking probability. For example, a preset sequence monitoring process is performed q times (q is a positive integer) on a certain data sequence. During these q monitoring processes, the duration of the preset sequence being locked during most of the locking processes is the second duration (for example, the number of monitoring processes during which the duration of the lock loss during these q monitoring processes is the second duration is greater than the second number), then the MTTFU of the data sequence is the second duration. In addition, compared to the codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project, the technical solution of the embodiment of the present application can shorten the time taken by the receiving end to search for the preset sequence without adding additional verification logic (such as additional hardware circuits), thereby improving the efficiency, accuracy and reliability of the receiving end in searching for the preset sequence. The implementation process of the embodiment of the present application is simple and the implementation cost is low.

[0101] In an embodiment of the present application, a receiving end includes a host chip and an optical module, wherein the optical module includes a chip. The method of the embodiment of the present application is performed by the host chip in the receiving end, the optical module in the receiving end, or the chip in the optical module in the receiving end. The receiving end obtains a data sequence including multiple FEC codewords, performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and searches for a preset sequence in the at least one decoded codeword. The receiving end can be a forwarding device, a user terminal device, or a server device, and can include an Ethernet interface. The data sequence is obtained by the receiving end based on an Ethernet signal received from the Ethernet interface of the receiving end, and the Ethernet signal is sent by the transmitting end to the receiving end. The transmitting end can be a forwarding device, a user terminal device, or a server device, and can also include an Ethernet interface. The forwarding device can be a router or a switch. The Ethernet signal can be a Terabit Ethernet (TbE) signal. Terabit Ethernet is a high-speed Ethernet. Terabit Ethernet refers to Ethernet with a speed exceeding 100 Gigabits per second (100Gbit / s). The speed of Terabit Ethernet can reach or even exceed 200Gbit / s or 400Gbit / s, thus enabling high-speed data transmission.

[0102] The technical solutions of the embodiments of the present application can be applied to both cascaded FEC encoding scenarios and non-cascaded FEC encoding scenarios. In a cascaded FEC encoding scenario, the transmitter performs at least two levels of FEC encoding on the data to be transmitted and then transmits it to the receiver. The receiver then performs at least two levels of FEC decoding on the received data to obtain the original data. For example, the transmitter sequentially performs first and second FEC encoding on the data to be transmitted, and the receiver sequentially performs second FEC decoding and first FEC decoding on the received data. The second FEC decoding corresponds to the second FEC encoding, and the first FEC decoding corresponds to the first FEC encoding. The first FEC encoding and the second FEC encoding are each a first-level (or layer) FEC encoding, and the first FEC decoding and the second FEC decoding are each a first-level FEC decoding. In some embodiments or technical documents, the first FEC encoding is also described as outer FEC encoding or outer code encoding, the second FEC encoding is also described as inner FEC encoding or inner code encoding, the second FEC decoding is also described as inner FEC decoding or inner code decoding, and the first FEC decoding is also described as outer FEC decoding or outer code decoding. In a non-concatenated FEC coding scenario, the sender performs a first-level (or layer) FEC coding on the data to be sent and then sends it to the receiver. The receiver performs a first-level FEC coding on the received data to obtain the original data. Non-concatenated FEC coding is also called single-stage FEC coding, single-layer FEC coding, first-level FEC coding, or layer FEC coding. The FEC code used by the receiver to perform the corresponding FEC decoding on the received data is the same as the FEC code used by the sender to perform FEC coding on the data. For example, in a concatenated FEC coding scenario, the FEC code used by the receiver to perform the first FEC decoding on the received data is the same as the FEC code used by the sender to perform the first FEC coding on the data, and the FEC code used by the receiver to perform the second FEC decoding on the received data is the same as the FEC code used by the sender to perform the second FEC coding on the data. In the embodiment of the present application, the FEC code can be a Reed-Solomon code (RS code), a Bose-Chaudhuri-Hocquenghem code (BCH code), an extended BCH code, a low-density parity-check code (LDPC code), a Hamming code, an extended Hamming code, a Golay code, a Reed-Muller code, a staircase code, a turbo code, or a turbo product code (TPC), etc.For example, the transmitting end first uses the RS (544, 514) code to perform a first FEC encoding on the data to be transmitted, and then uses the Hamming (128, 120) code or the Hamming (68, 60) code to perform a second FEC encoding on the data. The transmitting end then sends the data sequence obtained by the first FEC encoding and the second FEC encoding to the receiving end; after the receiving end receives the data sequence, the receiving end first uses the Hamming (128, 120) code or the Hamming (68, 60) code to perform a second FEC decoding on the data sequence, and then uses the RS (544, 514) code to perform the first FEC decoding on the data sequence. In an embodiment of the present application, when the transmitting end inserts a preset sequence into the data, the receiving end also needs to find the preset sequence in the received data sequence and delete the padding sequence including the preset sequence. Before deleting the padding sequence, the receiving end can also extract the information carried by the padding sequence for use by the physical layer. In which, the filling sequence is the filling sequence in the IEEE802.3dj standard, and the preset sequence is the FS mentioned in the IEEE802.3dj standard discussion; or, the filling sequence is the AM in the 200 / 400GE standard defined by the IEEE802.3bs project, and the preset sequence is in the AM, for example, the preset sequence is the AM or a fixed part in the AM, and this embodiment of the present application does not limit this.

[0103] The following describes the application scenarios of the technical solutions provided by the embodiments of the present application in conjunction with the accompanying drawings.

[0104] The application scenario of the embodiment of the present application includes a transmitting end and a receiving end, and the transmitting end is communicatively connected to the receiving end, for example, the transmitting end and the receiving end are connected via an optical fiber. Specifically, the transmitting end and the receiving end may both include an Ethernet interface, and the Ethernet interface of the transmitting end is connected to the Ethernet interface of the receiving end via an optical fiber. Wherein, the transmitting end includes a host chip and / or an optical module, and the receiving end includes a host chip and / or an optical module. For example, the transmitting end and the receiving end both include a host chip and an optical module, and in the transmitting end and / or the receiving end, the host chip and the optical module can be connected via an interface such as AUI. For ease of description, the host chip in the transmitting end is referred to as host chip 1, the optical module in the transmitting end is referred to as optical module 1, the host chip in the receiving end is referred to as host chip 2, and the optical module in the receiving end is referred to as optical module 2.

[0105] Please refer to Figure 2, which shows a schematic diagram of an application scenario provided by an embodiment of the present application. The application scenario is a non-cascaded FEC coding scenario. In this application scenario, the transmitting end includes a main chip 1 and / or an optical module 1, and the receiving end includes a main chip 2 and / or an optical module 2. When the transmitting end sends a data sequence C0 to the receiving end, the main chip 1 or the optical module 1 performs FEC encoding on the data sequence C0 and periodically inserts a padding sequence including a preset sequence into the data sequence C0 to obtain a data sequence C1, and the data sequence C1 includes multiple FEC codewords obtained by FEC encoding (the padding sequence has also been FEC encoded, and the padding sequence may include at least one FEC codeword obtained by FEC encoding, and the FEC codewords in the padding sequence may be called padding codewords), and the transmitting end sends the data sequence C1 to the receiving end. For example, Figure 3 shows a schematic diagram of a data sequence C1. Figure 3 takes the preset sequence FS as an example. The data sequence C1 includes multiple FEC codewords and periodically appearing filling sequences. Each filling sequence includes FS. The length of the filling sequence is 3 times the length of the FEC codeword. The length of FS is 48 bits. The filling sequence appears in the data sequence C1 for a period of 3264 FEC codewords (3264*128 bits), and the FS appears in the data sequence C1 for a period of 3264+3=3267 FEC codewords (3267*128 bits). For another example, FIG4 shows a schematic diagram of another data sequence C1. FIG4 takes the preset sequence FS as an example. Data sequence C1 includes multiple FEC codewords and periodically appearing padding sequences. Each padding sequence includes FS. The length of the padding sequence is 8 times the length of the FEC codeword, and the length of FS is 48 bits. The padding sequence appears in data sequence C1 for a period of 8704 FEC codewords (8704*128 bits). The FS appears in data sequence C1 for a period of 8704+8=8712 FEC codewords (8712*128 bits). For another example, FIG5 shows a schematic diagram of yet another data sequence C1. FIG5 takes the padding sequence AM as an example. Data sequence C1 includes multiple RS codewords and periodically appearing AM. Each AM includes a preset sequence. The length of the AM is 1028 bits. The AM appears in data sequence C1 for a period of 4096 RS codewords (4096*5440 bits). FIG6 shows a schematic diagram of another data sequence C1. FIG6 uses AM as an example of a padding sequence. Data sequence C1 includes multiple RS codewords and periodically occurring AMs. Each AM includes a preset sequence. The AM is 2056 bits long, and the period of occurrence of the AM in data sequence C1 is 8192 RS codewords (8192*5440 bits). The data sequence C1 shown in FIG5 and FIG6 is a data sequence obtained by RS encoding. RS encoding is also a type of FEC encoding. Therefore, the RS codewords in the data sequence C1 shown in FIG5 and FIG6 are also FEC codewords.After the receiving end receives data sequence C1, the main chip 2 or optical module 2 performs codeword synchronization on the data sequence C1 (for example, using a self-synchronization method to perform codeword synchronization on the data sequence C1) to determine the FEC codeword boundary in the data sequence C1. The main chip 2 or optical module 2 determines the FEC codeword in the data sequence C1 based on the FEC codeword boundary in the data sequence C1 (for the data sequence C1 shown in Figures 5 and 6, the FEC codeword boundary is the RS codeword boundary, and the FEC codeword is the RS codeword). The main chip 2 or optical module 2 performs FEC decoding on at least one FEC codeword in the data sequence C1 to obtain at least one decoded codeword. The main chip 2 or optical module 2 searches for a preset sequence in the at least one decoded codeword, and the main chip 2 or optical module 2 deletes the padding sequence in the data sequence C1 that includes the preset sequence. The main chip 2 or optical module 2 performs FEC decoding on all FEC codewords in the data sequence C1 and deletes the padding sequence in the data sequence C1 to obtain data sequence C0.

[0106] Please refer to Figure 7, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. This application scenario is a cascade FEC encoding scenario, in which the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends a data sequence D0 to the receiving end, the main chip 1 performs a first FEC encoding on the data sequence D0 to obtain a data sequence D1. The data sequence D1 includes multiple FEC codewords obtained through the first FEC encoding (for ease of description, the FEC codewords obtained through the first FEC encoding are referred to as FEC codewords 1). The main chip 1 sends the data sequence D1 to the optical module 1. The optical module 1 performs a second FEC encoding on the data sequence D1 and periodically inserts a padding sequence including a preset sequence into the data sequence D1 to obtain a data sequence D2. The data sequence D2 includes multiple FEC codewords obtained through the second FEC encoding (for ease of description, the FEC codewords obtained through the second FEC encoding are referred to as FEC codewords 2. The padding sequence in the data sequence D2 also undergoes the second FEC encoding and may include at least one FEC codeword 2 obtained through the second FEC encoding). The distribution of the FEC codewords and padding sequences in the data sequence D2 can refer to the data sequence C1 shown in Figures 3 to 6. The transmitting end sends the data sequence D2 to the receiving end. After the receiving end receives data sequence D2, optical module 2 performs a second codeword synchronization on data sequence D2 (for example, performing a second codeword synchronization on data sequence D2 using a self-synchronization method) to determine an FEC codeword boundary in data sequence D2. Optical module 2 determines multiple FEC codewords 2 in data sequence D2 based on the FEC codeword boundary in data sequence D2. Optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in data sequence D2 to obtain at least one decoded codeword. Optical module 2 searches for a preset sequence in the at least one decoded codeword, and optical module 2 deletes a padding sequence from data sequence D2 that includes the found preset sequence. Optical module 2 performs a second FEC decoding on all FEC codewords 2 in data sequence D2 and deletes the padding sequence in data sequence D2 to obtain data sequence D1. The optical module 2 sends the data sequence D1 to the main chip 2. The main chip 2 performs a first codeword synchronization on the data sequence D1 (for example, using a self-synchronization method to perform the first codeword synchronization) to determine the FEC codeword boundary in the data sequence D1. The main chip 2 determines multiple FEC codewords 1 in the data sequence D1 based on the FEC codeword boundary in the data sequence D1. The main chip 2 performs a first FEC decoding on the multiple FEC codewords 1 to obtain multiple decoded codewords. The multiple decoded codewords constitute the data sequence D0.

[0107] Please refer to Figure 8, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. This application scenario is a cascade FEC encoding scenario. In this application scenario, the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends a data sequence E0 to the receiving end, the main chip 1 performs a first FEC encoding on the data sequence E0 and periodically inserts a padding sequence including a preset sequence into the data sequence E0 to obtain a data sequence E1. The data sequence E1 includes multiple FEC codewords obtained by the first FEC encoding (for ease of description, the FEC codeword obtained by the first FEC encoding is referred to as FEC codeword 1, the padding sequence inserted by the main chip 1 in the data sequence E0 is referred to as padding sequence 1, and the preset sequence included in the padding sequence 1 is referred to as preset sequence 1. The padding sequence 1 also undergoes the first FEC encoding, and the padding sequence 1 may include at least one FEC codeword 1 obtained by the first FEC encoding). The distribution of the FEC codewords and padding sequences in the data sequence E1 can refer to the data sequence C1 shown in Figures 3 to 6. The main chip 1 sends the data sequence E1 to the optical module 1. The optical module 1 performs a second FEC encoding on the data sequence E1 and periodically inserts a padding sequence including a preset sequence into the data sequence E1 to obtain a data sequence E2. The data sequence E2 includes multiple FEC codewords obtained through the second FEC encoding (for ease of description, the FEC codeword obtained through the second FEC encoding is referred to as FEC codeword 2, the padding sequence inserted by the optical module 1 into the data sequence E1 is referred to as padding sequence 2, the preset sequence included in the padding sequence 2 is referred to as preset sequence 2, the padding sequence 2 is also subjected to the second FEC encoding, and the padding sequence 2 may include at least one FEC codeword 2 obtained through the second FEC encoding). The distribution of the FEC codewords and padding sequences in the data sequence E2 can refer to the data sequence C1 shown in Figures 3 to 6. The transmitting end sends the data sequence E2 to the receiving end. After the receiving end receives data sequence E2, optical module 2 performs a second codeword synchronization on data sequence E2 (for example, using a self-synchronization method to perform a second codeword synchronization on data sequence E2) to determine an FEC codeword boundary in data sequence E2. Optical module 2 determines multiple FEC codewords 2 in data sequence E2 based on the FEC codeword boundary in data sequence E2. Optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in data sequence E2 to obtain at least one decoded codeword. Optical module 2 searches for a preset sequence 2 in the at least one decoded codeword and deletes a padding sequence 2 in data sequence E2 that includes the preset sequence 2. Optical module 2 performs a second FEC decoding on all FEC codewords 2 in data sequence E2 and deletes the padding sequence 2 in data sequence E2 to obtain data sequence E1.Optical module 2 sends data sequence E1 to main chip 2. Main chip 2 performs first codeword synchronization on data sequence E1 (for example, using self-synchronization to perform first codeword synchronization on data sequence E1) to determine FEC codeword boundaries in data sequence E1. Main chip 2 determines multiple FEC codewords 1 in data sequence E1 based on the FEC codeword boundaries in data sequence E1. Main chip 2 performs first FEC decoding on at least one FEC codeword 1 in data sequence E1 to obtain at least one decoded codeword. Main chip 2 searches for a preset sequence 1 in the at least one decoded codeword and deletes padding sequence 1 in data sequence E1, including the preset sequence 1. Main chip 2 performs first FEC decoding on all FEC codewords 1 in data sequence E1 and deletes padding sequence 1 in data sequence E1 to obtain data sequence E0.

[0108] Please refer to Figure 9, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. This application scenario is a cascade FEC coding scenario. In this application scenario, the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends a data sequence F0 to the receiving end, the main chip 1 performs a first FEC coding on the data sequence F0 and periodically inserts a padding sequence including a preset sequence into the data sequence F0 to obtain a data sequence F1. The data sequence F1 includes multiple FEC codewords obtained by the first FEC coding (for ease of description, the FEC codeword obtained by the first FEC coding is referred to as FEC codeword 1, and the padding sequence in the data sequence F1 has also undergone the first FEC coding. The padding sequence may include at least one FEC codeword 1 obtained by the first FEC coding). The distribution of the FEC codewords and padding sequences in the data sequence F1 can refer to the data sequence C1 shown in Figures 3 to 6. The main chip 1 sends the data sequence F1 to the optical module 1. Optical module 1 performs a second FEC encoding on data sequence F1 to obtain data sequence F2. Data sequence F2 includes multiple FEC codewords obtained through the second FEC encoding (for ease of description, the FEC codewords obtained through the second FEC encoding are referred to as FEC codewords 2). The transmitting end transmits data sequence F2 to the receiving end. After the receiving end receives data sequence F2, optical module 2 performs a second codeword synchronization on data sequence F2 (for example, using a self-synchronization method to perform second codeword synchronization on data sequence F2) to determine FEC codeword boundaries in data sequence F2. Optical module 2 determines multiple FEC codewords 2 in data sequence F2 based on the FEC codeword boundaries in data sequence F2. Optical module 2 performs a second FEC decoding on the multiple FEC codewords 2 to obtain multiple decoded codewords. The multiple decoded codewords constitute data sequence F1. Optical module 2 sends data sequence F1 to main chip 2. Main chip 2 performs first codeword synchronization on data sequence F1 (for example, using self-synchronization to perform first codeword synchronization on data sequence F1) to determine the FEC codeword boundary in data sequence F1. Main chip 2 determines multiple FEC codewords 1 in data sequence F1 based on the FEC codeword boundary in data sequence F1. Main chip 2 performs first FEC decoding on at least one FEC codeword 1 in data sequence F1 to obtain at least one decoded codeword. Main chip 2 searches for a preset sequence in the at least one decoded codeword and deletes the padding sequence in data sequence F1, including the preset sequence. Main chip 2 performs first FEC decoding on all FEC codewords 1 in data sequence F1 and deletes the padding sequence in data sequence F1 to obtain data sequence F0.

[0109] Please refer to Figure 10, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. This application scenario is a cascade FEC encoding scenario. In this application scenario, the transmitting end includes a main chip 1 and / or an optical module 1, and the receiving end includes a main chip 2 and / or an optical module 2. When the transmitting end sends a data sequence G0 to the receiving end, first, the main chip 1 or the optical module 1 performs a first FEC encoding on the data sequence G0 to obtain a data sequence G1. The data sequence G1 includes multiple FEC codewords obtained by the first FEC encoding (for ease of description, the FEC codeword obtained by the first FEC encoding is referred to as FEC codeword 1). Then, the main chip 1 or optical module 1 performs a second FEC encoding on the data sequence G1 and periodically inserts a padding sequence including a preset sequence into the data sequence G1 to obtain a data sequence G2. The data sequence G2 includes multiple FEC codewords obtained through the second FEC encoding (for ease of description, the FEC codewords obtained through the second FEC encoding are referred to as FEC codewords 2. The padding sequence in the data sequence G2 also undergoes the second FEC encoding and may include at least one FEC codeword 2 obtained through the second FEC encoding). The distribution of the FEC codewords and padding sequences in the data sequence G2 can be referred to as the data sequence C1 shown in Figures 3 to 6. Finally, the transmitting end sends the data sequence G2 to the receiving end. After the receiving end receives the data sequence G2, the main chip 2 or optical module 2 performs a second codeword synchronization on the data sequence G2 (for example, using a self-synchronization method to perform a second codeword synchronization on the data sequence G2) to determine the FEC codeword boundary in the data sequence G2. The main chip 2 or optical module 2 determines multiple FEC codewords 2 in the data sequence G2 based on the FEC codeword boundary in the data sequence G2. The main chip 2 or optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in the data sequence G2 to obtain at least one decoded codeword. The main chip 2 or optical module 2 searches for a preset sequence in the at least one decoded codeword and deletes the padding sequence in the data sequence G2 including the preset sequence. The main chip 2 or optical module 2 performs a second FEC decoding on all FEC codewords 2 in the data sequence G2 and deletes the padding sequence in the data sequence G2 to obtain the data sequence G1. The main chip 2 or optical module 2 performs a first codeword synchronization on the data sequence G1 (for example, a self-synchronization method is used to perform the first codeword synchronization) to determine the FEC codeword boundary in the data sequence G1. The main chip 2 or optical module 2 determines multiple FEC codewords 1 in the data sequence G1 according to the FEC codeword boundary in the data sequence G1. The main chip 2 or optical module 2 performs a first FEC decoding on the multiple FEC codewords 1 to obtain multiple decoded codewords. The multiple decoded codewords constitute the data sequence G0.

[0110] It should be noted that the padding sequence used in the application scenarios shown in Figures 2, 7, and 10 may be the padding sequence in the IEEE 802.3dj standard, and the preset sequence may be the FS mentioned in the IEEE 802.3dj standard discussion. Alternatively, the padding sequence may be the AM in the 200 / 400GE standard defined in the IEEE 802.3bs project, and the preset sequence may be within the AM, for example, the preset sequence being the AM or a fixed portion of the AM. In addition, the above-mentioned FEC coding can be Reed-Solomon (RS) coding, Bose-Chaudhuri-Hocquenghem (BCH) coding, low-density parity-check (LDPC) coding, Hamming coding, Golay coding, Reed-Muller coding, staircase coding, turbo coding or turbo product code (TPC) coding, and correspondingly, the above-mentioned FEC decoding can be Reed-Solomon (RS) decoding, Bose-Chaudhuri-Hocquenghem (BCH) decoding, low-density parity-check (LDPC) coding, Hamming coding, Golay coding, Reed-Muller coding, staircase coding, turbo coding or turbo product code (TPC) coding. The FEC decoding method may be LDPC (low-density parity check) decoding, Hamming decoding, Golay decoding, Reed-Muller decoding, staircase decoding, turbo decoding, or turbo product code (TPC) decoding. The FEC code used for FEC decoding is the same as the FEC code used for the corresponding FEC encoding. For example, for the application scenarios shown in Figures 7 to 10, the FEC code used for the first FEC encoding is the same as the FEC code used for the first FEC decoding, and the FEC code used for the second FEC encoding is the same as the FEC code used for the second FEC decoding. For example, the FEC code used for the first FEC encoding and the FEC code used for the first FEC decoding are both RS (544, 514) codes, and the FEC code used for the second FEC encoding and the FEC code used for the second FEC decoding are both Hamming (128, 120) codes or Hamming (68, 60) codes. For the application scenario shown in FIG2 , the FEC code used for FEC encoding and the FEC code used for FEC decoding are the same. For example, the FEC code used for FEC encoding and the FEC code used for FEC decoding are both RS (544, 514) code, Hamming (128, 120) code, or Hamming (68, 60) code.

[0111] In addition, for a data sequence that needs to be FEC encoded and a padding sequence inserted at the transmitting end, the embodiment of the present application does not limit the order in which the transmitting end performs FEC encoding on the data sequence and inserts the padding sequence into the data sequence. For a data sequence that needs to be FEC decoded and a padding sequence needs to be deleted at the receiving end, the embodiment of the present application does not limit the order in which the receiving end performs FEC decoding on the data sequence and deletes the padding sequence from the data sequence, and the process of the receiving end performing FEC decoding on the data sequence and the process of the receiving end deleting the padding sequence from the data sequence can be executed alternately. For example, with reference to Figure 2 and its related description, the embodiment of the present application does not limit the order in which the main chip 1 or optical module 1 performs FEC encoding on the data sequence C0 and inserts the padding sequence into the data sequence C0. The main chip 1 or optical module 1 can first perform FEC encoding on the data sequence C0 and then insert the padding sequence into the data sequence C0, or can first insert the padding sequence into the data sequence C0 and then perform FEC encoding on the data sequence C0. In an optional implementation, the main chip 1 or optical module 1 first inserts a filling sequence into the data sequence C0, and then performs FEC encoding on the data sequence C0, thereby causing the filling sequence to be FEC encoded as well. In an optional implementation, the main chip 1 or optical module 1 first performs FEC encoding on the data sequence C0, and then inserts a filling sequence into the data sequence C0. The main chip 1 or optical module 1 may also perform FEC encoding on the inserted filling sequence. Continuing to refer to Figure 2 and its related description, the embodiment of the present application does not limit the main chip 2 or optical module 2 to performing FEC decoding on the data sequence C1 and deleting the filling sequence of the preset sequence in the data sequence C1. The main chip 2 or optical module 2 may first perform FEC decoding on all FEC codewords in the data sequence C1, and then delete the filling sequence including the preset sequence in the data sequence C1, or may perform FEC decoding on the FEC codewords in the data sequence C1 while deleting the filling sequence in the data sequence C1. For example, the main chip 2 or optical module 2 first performs FEC decoding on a portion of the FEC codewords in the data sequence C1, and then deletes the padding sequence in this portion of the FEC codewords. Then, the main chip 2 or optical module 2 first performs FEC decoding on another portion of the FEC codewords in the data sequence C1, and deletes the padding sequence in this other portion of the FEC codewords, and so on.

[0112] The above description of the sender and receiver is merely exemplary. In some embodiments, the sender is also referred to as a sender device, and the receiver is also referred to as a receiver device. Both the sender and the receiver can be forwarding devices, user terminal devices, or server devices.

[0113] The above is an introduction to the application scenarios of the embodiments of the present application. The following introduces the method embodiments of the present application.

[0114] Please refer to Figure 11, which shows a flow chart of a method for processing data provided by an embodiment of the present application. The method is executed by a main chip in a receiving end, an optical module in a receiving end, or a chip in an optical module in a receiving end. For ease of description, the following description uses the method executed by the receiving end as an example. It is understood that the method is specifically executed by the main chip in a receiving end, an optical module in a receiving end, or a chip in an optical module in a receiving end. As shown in Figure 11, the method includes the following steps S1101 to S1103.

[0115] S1101. Obtain a data sequence X, where the data sequence X includes multiple FEC codewords.

[0116] The data sequence X is obtained according to an Ethernet signal received from an Ethernet interface of the receiving end. The Ethernet interface may be a Terabit Ethernet interface, and the Ethernet signal may be a Terabit Ethernet signal.

[0117] In one embodiment, a receiving end receives an Ethernet signal sent by a transmitting end through an Ethernet interface. The Ethernet signal carries a data sequence X, and the receiving end extracts the data sequence X from the Ethernet signal. In another embodiment, the Ethernet signal carries an interleaved sequence of the data sequence X. The receiving end extracts the interleaved sequence from the Ethernet signal and deinterleaves the interleaved sequence to obtain the data sequence X.

[0118] The data sequence X is obtained by performing target FEC encoding on the initial data sequence by the transmitter, and the FEC codewords included in the data sequence X are FEC codewords obtained by performing the target FEC encoding. The multiple FEC codewords have equal lengths, and the length of each FEC codeword in the multiple FEC codewords depends on the FEC code used by the transmitter for the target FEC encoding. For example, the length of the multiple FEC codewords is 128 bits.

[0119] In which, data sequence X includes a preset sequence Z, which appears periodically in data sequence X, and preset sequence Z is periodically inserted by the transmitter into the initial data sequence. For example, data sequence X includes a periodically appearing padding sequence, each padding sequence including the preset sequence Z. Optionally, the padding sequence periodically inserted by the transmitter into the initial data sequence includes a padding sequence including the preset sequence Z. The padding sequence described in the embodiment of the present application can be a padding sequence in the IEEE802.3dj standard or an AM in the 200 / 400GE standard defined in the IEEE802.3bs project. The preset sequence Z can be the FS mentioned in the discussion of the IEEE802.3dj standard, or the preset sequence Z in the AM in the 200 / 400GE standard defined in the IEEE802.3bs project. The preset sequence Z in the AM can be understood as the preset sequence Z being all or part of the AM, for example, the preset sequence Z being the AM, or the preset sequence Z being a fixed part of the AM known to both the transmitter and the receiver. The padding sequence in data sequence X is also encoded with the target FEC. Optionally, the padding sequence is a padding sequence in the IEEE802.3dj standard, the length of the padding sequence is an integer multiple of the length of the FEC codeword in the data sequence X, and the padding sequence includes an integer number of the FEC codewords. In an embodiment of the present application, the periodic appearance of the preset sequence Z in the data sequence X may be that the preset sequence Z appears in the data sequence X according to a strict period, that is, the period of the preset sequence Z appearing in the data sequence X is a strict period, and different periods of the preset sequence Z are strictly equal. Alternatively, the periodic appearance of the preset sequence Z in the data sequence X may be that the preset sequence Z appears in the data sequence X according to a non-strict period, that is, the period of the preset sequence Z appearing in the data sequence X is a non-strict period, different non-strict periods of the preset sequence Z may not be equal, the difference between different non-strict periods is less than the preset difference, and the regularity of the appearance of the preset sequence Z is roughly periodic. This embodiment of the present application is not limited to this.

[0120] The initial data sequence is the data sequence before the transmitter performs target FEC encoding. In other words, the initial data sequence is the target FEC encoding target. The transmitter may first insert a padding sequence including a preset sequence Z into the initial data sequence and then perform target FEC encoding on the initial data sequence, or may first perform target FEC encoding on the initial data sequence and then insert a padding sequence including the preset sequence Z into the initial data sequence. The present embodiment does not limit the order in which the transmitter performs target FEC encoding on the initial data sequence and inserts the padding sequence into the initial data sequence. If the transmitter first inserts the padding sequence into the initial data sequence, the transmitter may perform target FEC encoding on the padding sequence during the target FEC encoding process. If the transmitter first performs target FEC encoding on the initial data sequence, the transmitter may also perform target FEC encoding on the inserted padding sequence after inserting the padding sequence into the initial data sequence. In the present embodiment, the initial data sequence may not have been FEC-encoded or may have been encoded with other FEC codes. The initial data sequence may or may not have been inserted with a padding sequence. For example, in a non-concatenated FEC encoding scenario, the initial data sequence has not undergone FEC encoding. In a concatenated FEC encoding scenario, the initial data sequence may have undergone other FEC encodings or may have a padding sequence inserted. In one example, referring to FIG. 2 and its related description, FIG. 2 illustrates a non-concatenated FEC encoding scenario, where the initial data sequence is data sequence C0, data sequence X is data sequence C1, and the initial data sequence has not undergone FEC encoding and has no padding sequence inserted. In another example, referring to FIG. 7 and its related description, FIG. 7 illustrates a concatenated FEC encoding scenario, where the initial data sequence is data sequence D1, data sequence X is data sequence D2, the initial data sequence has undergone a first FEC encoding, no padding sequence is inserted into the initial data sequence, and the target FEC encoding is a second FEC encoding. In another example, referring to FIG8 and its related description, FIG8 illustrates a cascaded FEC encoding scenario, where the initial data sequence is data sequence E0, data sequence X is data sequence E1, the initial data sequence has not been FEC-encoded and has no padding sequence inserted, and the target FEC encoding is the first FEC encoding; alternatively, the initial data sequence is data sequence E1, data sequence X is data sequence E2, the initial data sequence has been first FEC-encoded and has padding sequence 1 inserted, and the target FEC encoding is the second FEC encoding. In another example, referring to FIG9 and its related description, FIG9 illustrates a cascaded FEC encoding scenario, where the initial data sequence is data sequence F0, data sequence X is data sequence F1, the initial data sequence has not been FEC-encoded and has no padding sequence inserted, and the target FEC encoding is the first FEC encoding.In another example, referring to Figure 10 and its related description, Figure 10 shows a cascade FEC encoding scenario, the initial data sequence is data sequence G1, data sequence X is data sequence G2, the initial data sequence has undergone the first FEC encoding, the initial data sequence has not been inserted with a padding sequence, and the target FEC encoding is the second FEC encoding.

[0121] S1102. Perform FEC decoding on at least one FEC codeword in the data sequence X to obtain at least one decoded codeword Y.

[0122] This step and the FEC decoding of the FEC codewords in the data sequence X described later refer to target FEC decoding of the FEC codewords in the data sequence X. The target FEC decoding is the FEC decoding corresponding to the target FEC encoding described in S1101. The FEC code used in the target FEC decoding is the same as the FEC code used in the target FEC encoding.

[0123] The at least one FEC codeword in the data sequence X may be all FEC codewords in the data sequence X, or may be part of the FEC codewords in the data sequence X. The at least one decoded codeword Y corresponds one-to-one to the at least one FEC codeword. The at least one decoded codeword Y may be a decoded codeword obtained by performing target FEC decoding on all FEC codewords in the data sequence X, or may be a decoded codeword obtained by performing target FEC decoding on part of the FEC codewords in the data sequence X. This embodiment of the present application is not limited to this.

[0124] This document only describes the receiver's target FEC decoding of the FEC codewords in the data sequence X. The detailed decoding process is not detailed here. For the implementation of the receiver's target FEC decoding of any FEC codeword in the data sequence X, please refer to the relevant technical documents on FEC decoding.

[0125] S1103 . Find a preset sequence Z in the at least one decoded codeword Y.

[0126] The receiving end searches for the preset sequence Z in the at least one decoded codeword Y based on the preset sequence Z known to the receiving end. The receiving end may find the preset sequence Z in the at least one decoded codeword Y. Optionally, the receiving end compares the preset sequence Z known to the receiving end with the at least one decoded codeword Y (e.g., bit by bit) to find the preset sequence Z in the at least one decoded codeword Y.

[0127] In one embodiment, the preset sequence Z includes multiple nibbles, i.e., each nibble is 4 bits long. During a comparison between the preset sequence Z known to the receiving end and any codeword Y in the at least one decoded codeword Y, if the number of nibbles in the codeword Y that match the multiple nibbles in the preset sequence Z reaches a set number, the receiving end determines that the codeword Y matches the preset sequence Z, and the receiving end determines that the preset sequence Z is found in the codeword Y. In one example, the preset sequence Z is 48 bits long, includes 12 nibbles, and the set number is 9. That is, if the number of nibbles in the codeword Y that match the multiple nibbles in the preset sequence Z reaches 9, the codeword Y is considered to match the preset sequence Z, and the receiving end determines that the preset sequence Z is found in the codeword Y.

[0128] The at least one decoded codeword Y may be a decoded codeword obtained by the receiving end performing target FEC decoding on all FEC codewords in the data sequence X, or may be a decoded codeword obtained by the receiving end performing target FEC decoding on a portion of the FEC codewords in the data sequence X. Therefore, in conjunction with S1102 and S1103, it can be seen that the receiving end may first perform target FEC decoding on all FEC codewords in the data sequence X and then search for the preset sequence Z among all decoded codewords Y. Alternatively, the receiving end may perform target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z among the decoded codewords Y. For example, the receiving end may first perform target FEC decoding on a portion of the FEC codewords in the data sequence X and search for the preset sequence Z among the decoded codewords; then, the receiving end may perform target FEC decoding on another portion of the FEC codewords in the data sequence X and search for the preset sequence Z among the decoded codewords, and so on. Optionally, the receiving end groups the FEC codewords in the data sequence X to obtain multiple codeword groups, each codeword group in the multiple codeword groups includes at least one FEC codeword in the data sequence X, and the FEC codewords in any two codeword groups in the multiple codeword groups do not overlap. The receiving end performs target FEC decoding on the FEC codewords in the data sequence X group by group. The receiving end can obtain a group of decoded codewords after decoding each FEC codeword in a codeword group. The receiving end searches for a preset sequence Z in the group of decoded codewords. This embodiment of the present application is not limited to this.

[0129] The implementation process of S1102 and S1103 is described below in two embodiments.

[0130] First embodiment: A receiving end performs target FEC decoding on all FEC codewords in a data sequence X, and searches for a preset sequence Z among all decoded codewords Y. Optionally, the receiving end performs FEC decoding (i.e., target FEC decoding) on ​​the multiple FEC codewords (i.e., all FEC codewords) in the data sequence X to obtain multiple decoded codewords Y, where the multiple decoded codewords Y may correspond one-to-one with the multiple FEC codewords. The receiving end searches for the preset sequence Z among the multiple decoded codewords Y, and the receiving end may find the preset sequence Z among the multiple decoded codewords Y. For example, the receiving end may find multiple preset sequences Z among the multiple decoded codewords Y.

[0131] In a specific embodiment, the arrangement order of the multiple decoded codewords Y is the same as the arrangement order of the multiple FEC codewords. The receiving end sequentially searches for the preset sequence Z in the multiple decoded codewords Y according to the arrangement order of the multiple decoded codewords Y until the first preset sequence Z is found. For example, the multiple decoded codewords Y are codeword Y1, codeword Y2, codeword Y3, etc., arranged sequentially. The receiving end first searches for the preset sequence Z in codeword Y1. If the receiving end finds the preset sequence Z in codeword Y1, the receiving end has found the first preset sequence Z. If the receiving end does not find the preset sequence Z in codeword Y1, the receiving end continues to search for the preset sequence Z in codeword Y2. If the receiving end finds the preset sequence Z in codeword Y2, the receiving end has found the first preset sequence Z. If the receiving end does not find the preset sequence Z in codeword Y2, the receiving end continues to search for the preset sequence Z in codeword Y3, and so on, until the first preset sequence Z is found. After the receiving end finds the first preset sequence Z in the multiple decoded codewords Y, for example, the receiving end finds the first preset sequence Z in codeword Y1, the receiving end determines at least one codeword from the codewords following codeword Y1 in the multiple decoded codewords Y according to the period at which the preset sequence Z appears in the data sequence X (for ease of description, the period at which the preset sequence Z appears in the data sequence X is referred to as the target period). The interval between adjacent codewords in the at least one codeword is the target period, and the interval between the first codeword in the at least one codeword and codeword Y1 is the target period. The receiving end searches for the preset sequence Z in the at least one codeword until the at least one codeword is found. That is, the receiving end searches for the first preset sequence Z in the multiple decoded codewords Y codeword by codeword. After finding the first preset sequence Z in the multiple decoded codewords Y, the receiving end no longer searches for the preset sequence Z codeword by codeword, but instead searches for the preset sequence Z in the multiple decoded codewords Y according to the target period, thereby improving the efficiency of searching for the preset sequence Z.

[0132] Optionally, after the receiving end finds the first preset sequence Z among the multiple decoded codewords Y, the receiving end searches for the preset sequence Z among the multiple decoded codewords Y according to a target period. If the number of preset sequences Z found consecutively by the receiving end in the multiple decoded codewords Y reaches a specified number (for example, the specified number is 3, and the interval between the preset sequences Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z include the first preset sequence Z), the receiving end locks the first preset sequence Z found. The process from the receiving end starting to search for the first preset sequence Z to locking the first preset sequence Z found can be referred to as a preset sequence locking process. After the receiving end locks the first preset sequence Z, the receiving end performs a preset sequence monitoring process. Specifically, the receiving end continues to search for the preset sequence Z in the multiple decoded codewords Y according to the target period based on the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process), until all the codewords Y distributed according to the target period in the multiple decoded codewords Y are found, or until the locked preset sequence is lost (the preset sequence monitoring process fails). For example, the preset sequence is the FS mentioned in the IEEE802.3dj standard discussion, the preset sequence locking process can be called the FS locking process, and the preset sequence monitoring process can be called the FS monitoring process. For another example, the preset sequence is the AM mentioned in the 200 / 400GE standard, the preset sequence locking process can be called the AM locking process, and the preset sequence monitoring process can be called the AM monitoring process. Since the receiving end performs preset sequence locking and preset sequence monitoring based on the decoded codewords of the data sequence X, and the bit error rate of the decoded codewords is low, the probability of the preset sequence losing lock can be reduced. Among them, the preset sequence false lock loss means that the preset sequence is locked correctly but the preset sequence monitoring process fails. For example, during the preset sequence monitoring process, the preset sequence Z is not found in multiple consecutive target cycles, or the proportion of cycles in which the data sequence X is not found in multiple consecutive target cycles reaches the preset proportion, and the preset sequence monitoring process is considered to have failed.

[0133] Second embodiment: The receiving end performs target FEC decoding on FEC codewords in data sequence X while searching for a preset sequence Z in the decoded codewords Y. In one implementation, the receiving end performs FEC decoding on the first FEC codeword in data sequence X (also known as target FEC decoding) to obtain the first decoded codeword, and then searches for the preset sequence Z in the first decoded codeword. If the first decoded codeword does not include the preset sequence Z, that is, the receiving end does not find the preset sequence Z in the first decoded codeword, the receiving end continues to perform FEC decoding on FEC codewords following the first FEC codeword in data sequence X (also known as target FEC decoding) and searches for the preset sequence Z in the decoded codewords until the first preset sequence Z is found. If the first decoded codeword includes the preset sequence Z, that is, the receiving end finds the preset sequence Z in the first decoded codeword, the receiving end performs FEC decoding on the second FEC codeword following the first FEC codeword in data sequence X (also known as target FEC decoding) to obtain the second decoded codeword, and then attempts to search for the preset sequence Z in the second decoded codeword. The first FEC codeword is an FEC codeword in the data sequence X, for example, the first FEC codeword is the first FEC codeword in the data sequence X, and the interval between the second FEC codeword and the first FEC codeword is the period of the preset sequence Z appearing in the data sequence X.

[0134] In a specific embodiment, if the receiving end finds the preset sequence Z in the decoded first codeword, the receiving end determines a second FEC codeword following the first FEC codeword in the data sequence X, with the interval between the second FEC codeword and the first FEC codeword being the target period (i.e., the period during which the preset sequence Z appears in the data sequence X). The receiving end performs target FEC decoding on the second FEC codeword to obtain a decoded second codeword, and the receiving end attempts to find the preset sequence Z in the decoded second codeword. Furthermore, the receiving end determines a third FEC codeword following the second FEC codeword in the data sequence X, with the interval between the third FEC codeword and the second FEC codeword being the target period. The receiving end performs target FEC decoding on the third FEC codeword to obtain a decoded third codeword, and the receiving end attempts to find the preset sequence Z in the decoded third codeword. Furthermore, the receiving end determines the fourth FEC codeword following the third FEC codeword in the data sequence X, with the interval between the fourth FEC codeword and the third FEC codeword being the target period. The receiving end performs target FEC decoding on the fourth FEC codeword to obtain a decoded fourth codeword, and then attempts to find the preset sequence Z in the decoded fourth codeword. This continues in this manner. That is, if the receiving end finds the preset sequence Z in the first decoded codeword, the receiving end traverses the FEC codewords following the first FEC codeword in the data sequence X according to the target period (the interval between two adjacent FEC codewords traversed according to the target period being the target period), performs target FEC decoding on the traversed FEC codewords, and attempts to find the preset sequence Z in the decoded codewords. In other words, if the receiving end finds the preset sequence Z in the first decoded codeword, the receiving end attempts to find the preset sequence Z in the FEC codewords following the first FEC codeword in the data sequence X according to the target period. Optionally, the preset sequence Z found by the receiving end in the first decoded codeword is the first preset sequence Z found by the receiving end. After the receiving end finds the first preset sequence Z, the receiving end traverses the FEC codewords after the first FEC codeword in the data sequence X according to the target period. The receiving end performs target FEC decoding on the traversed FEC codewords and attempts to find the preset sequence Z in the decoded codewords. If the number of preset sequences Z found consecutively in the data sequence X by the receiving end reaches a specified number (for example, the specified number is 3, and the interval between the preset sequences Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z include the first preset sequence Z), the receiving end locks the first preset sequence Z found. The process from the receiving end starting to search for the first preset sequence Z to locking the first preset sequence Z found by the receiving end can be referred to as a preset sequence locking process. After the receiving end locks the first preset sequence Z, the receiving end performs a preset sequence monitoring process.Specifically, the receiving end continues to traverse the FEC codewords of data sequence X according to the target period based on the position of the target preset sequence found during the preset sequence locking process (for example, the target preset sequence is the last preset sequence found during the preset sequence locking process). The receiving end performs target FEC decoding on the traversed FEC codewords and searches for the preset sequence Z in the decoded codewords until all FEC codewords distributed according to the target period in data sequence X are found, or until the locked preset sequence is lost (the preset sequence monitoring process fails). Because the receiving end performs preset sequence locking and preset sequence monitoring on data sequence X based on the decoded codewords of data sequence X, and the bit error rate of the decoded codewords is low, the probability of falsely losing the preset sequence lock can be reduced.

[0135] In a specific embodiment, if the receiving end does not find the preset sequence Z in the first decoded codeword, the receiving end sequentially performs target FEC decoding on multiple FEC codewords following the first FEC codeword in the data sequence X according to the arrangement order of the FEC codewords in the data sequence X, and sequentially searches for the preset sequence Z in the decoded codewords. Specifically, for each decoded codeword obtained by the receiving end, the receiving end searches for the preset sequence Z in the decoded codeword. If the preset sequence Z is not found in the decoded codeword, the receiving end performs target FEC decoding on the next FEC codeword and searches for the preset sequence Z in the next decoded codeword, and so on, until the first preset sequence Z is found. The codeword boundaries of any two adjacent FEC codewords in the multiple FEC codewords following the first FEC codeword are adjacent, and the codeword boundary of the FEC codeword adjacent to the first FEC codeword in the multiple FEC codewords is adjacent to the codeword boundary of the first FEC codeword. The adjacent codeword boundaries of the two FEC codewords mentioned here means that: in the two FEC codewords, the end of the previous FEC codeword (for example, the last bit of the previous FEC codeword) is adjacent to the beginning of the next FEC codeword (for example, the first bit of the next FEC codeword), there are no other bits between the end of the previous FEC codeword and the beginning of the next FEC codeword, and the next bit after the last bit of the previous FEC codeword is the first bit of the next FEC codeword. Optionally, after the receiving end finds the first preset sequence Z, for example, the receiving end finds the first preset sequence Z in the decoded codeword of the target FEC codeword in the data sequence X, the receiving end traverses the FEC codewords following the target FEC codeword in the data sequence X according to the target period (i.e., the period during which the preset sequence Z appears in the data sequence X), performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords. That is, before finding the first preset sequence Z, the receiving end searches for the preset sequence Z in the data sequence X in sequence according to the order in which the FEC codewords in the data sequence X are arranged (i.e., searches for the preset sequence Z FEC codeword by FEC codeword). After finding the first preset sequence Z, the receiving end no longer searches for the preset sequence Z FEC codeword by FEC codeword, but instead searches for the preset sequence Z in the data sequence X according to the target period. This improves the efficiency of searching for the preset sequence Z.

[0136] Optionally, after the receiving end finds the first preset sequence Z in the data sequence X, the receiving end searches for the preset sequence Z in the data sequence X according to a target period. If the number of preset sequences Z found consecutively by the receiving end in multiple FEC codewords reaches a specified number (e.g., the specified number is 3, and the interval between the preset sequences Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z includes the first preset sequence Z), the receiving end locks onto the first preset sequence Z found. The process from the receiving end starting to search for the first preset sequence Z to locking onto the first preset sequence Z found can be referred to as a preset sequence locking process. After the receiving end locks onto the first preset sequence Z, the receiving end performs a preset sequence monitoring process. Specifically, based on the position of the target preset sequence found during the preset sequence locking process (e.g., the target preset sequence is the last preset sequence found during the preset sequence locking process) in the data sequence X, the receiving end continues searching for the preset sequence Z in the data sequence X according to the target period until all FEC codewords distributed according to the target period in the data sequence X are found, or until the locked preset sequence is lost (the preset sequence monitoring process fails). Since the receiving end performs preset sequence locking and preset sequence monitoring on the data sequence X based on the decoded codeword of the data sequence X, and the bit error rate of the decoded codeword is low, the probability of losing the preset sequence lock can be reduced.

[0137] In an optional embodiment, the receiving end uses a first decoding method to perform FEC decoding on the first FEC codeword in the data sequence X (i.e., target FEC decoding), and the receiving end uses a second decoding method to perform FEC decoding on the candidate FEC codewords after the first FEC codeword in the data sequence X (i.e., target FEC decoding). The receiving end may also use the first decoding method to perform FEC decoding on the second FEC codeword in the data sequence X (i.e., target FEC decoding). One of the first decoding method and the second decoding method is soft-decision decoding (SDD), and the other is hard-decision decoding (HDD). That is, the first decoding method is SDD and the second decoding method is HDD; or, the first decoding method is HDD and the second decoding method is SDD. The candidate FEC codewords described here may include all undecoded FEC codewords in the data sequence X after the receiving end locks the preset sequence. In one embodiment, a receiving end uses a first decoding method to perform target FEC decoding on FEC codewords in data sequence X during the process of locking a preset sequence. After locking the preset sequence, the receiving end uses a second decoding method to perform target FEC decoding on the FEC codewords in data sequence X. After locking the preset sequence, the receiving end performs formal data processing on data sequence X, which includes performing target FEC decoding on the FEC codewords in data sequence X. In one example, the first decoding method is HDD and the second decoding method is SDD. Because HDD has lower decoding complexity and SDD has better decoding performance (e.g., fewer bit errors in the decoded codewords), the receiving end uses the first decoding method (i.e., HDD) to perform target FEC decoding on the FEC codewords in data sequence X during the process of locking the preset sequence, thereby reducing the complexity of locking the preset sequence. After locking the preset sequence, the receiving end uses the second decoding method (i.e., SDD) to perform target FEC decoding on the FEC codewords in data sequence X, thereby ensuring the bit error performance of the receiving end's formal data processing. In another example, the first decoding method is SDD and the second decoding method is HDD. During the preset sequence locking process, the receiving end uses the first decoding method (i.e., SDD) to perform target FEC decoding on the FEC codewords in the data sequence X, which can improve the reliability of the receiving end locking the preset sequence. After the preset sequence is locked, the receiving end uses the second decoding method (i.e., HDD) to perform target FEC decoding on the FEC codewords in the data sequence X, which can reduce the complexity of the receiving end's formal data processing. In an embodiment of the present application, the first decoding method and the second decoding method are implemented using the same hardware logic, that is, SDD and HDD are implemented using the same hardware logic. For example, SDD is implemented by a specific hardware circuit, and HDD is implemented by a portion of the specific hardware circuit. This can reduce the implementation complexity and cost of the technical solution of the present application.

[0138] In summary, the technical solution provided by the embodiments of the present application is that, after a receiving end obtains a data sequence including multiple FEC codewords, the receiving end performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and the receiving end finds a preset sequence in the at least one decoded codeword. Because the receiving end can perform error detection and error correction on the at least one FEC codeword during FEC decoding, the at least one decoded codeword has a low bit error rate or may even be error-free, which can reduce the impact of bit errors on the efficiency of the receiving end in searching for the preset sequence. The time consumed by the receiving end in searching for the preset sequence in the at least one decoded codeword is short, and the efficiency, accuracy, and reliability are all high, thereby ensuring the transmission efficiency and reliability of the communication system. In particular, when the bit error rate of the data sequence obtained by the receiving end is high, the technical solution of the embodiments of the present application can achieve significant benefits. In addition, the FEC decoding process performed by the receiving end on the data sequence during the preset sequence locking process and the FEC decoding process performed by the receiving end on the data sequence during the formal data processing process are implemented using the same hardware logic. Without adding additional verification logic, the time taken by the receiving end to search for the preset sequence can be shortened, thereby improving the efficiency, accuracy and reliability of the receiving end in searching for the preset sequence. The implementation process of the embodiment of the present application is simple, the implementation cost is low, and the applicability is wide.

[0139] In an optional embodiment, please refer to Figure 12, which shows a flow chart of another method for processing data provided by an embodiment of the present application. Before S1102, the method for processing data further includes the following step S1104.

[0140] S1104. Determine the FEC codeword boundary in the data sequence X by self-synchronization.

[0141] For a method of determining the FEC codeword boundaries in the data sequence X by self-synchronization, reference may be made to the patent application document "Codeword Synchronization Method, Receiver, Network Device, and Network System" with publication number CN113517949A, and the reference standard document "Inner Codeword Self-sync Proposal" (address: https: / / www.ieee802.org / 3 / dj / public / 23_07 / he_3dj_03b_2307.pdf), the entire contents of which are incorporated herein by reference as if fully set forth and are not repeated here.

[0142] After the receiving end determines the FEC codeword boundary in the data sequence X, the receiving end locks the FEC codeword boundary in the data sequence X. Furthermore, after the receiving end determines the FEC codeword boundary in the data sequence X (e.g., after the receiving end locks the FEC codeword boundary in the data sequence X), the receiving end determines multiple FEC codewords included in the data sequence X based on the FEC codeword boundary in the data sequence X, then performs FEC decoding on at least one of the multiple FEC codewords and searches for the preset sequence Z in the decoded codeword, that is, executing S1102 to S1103.

[0143] In an optional embodiment, please refer to FIG. 12 , after S1103 , the method for processing data further includes the following step S1105 .

[0144] S1105. If a preset condition is met, a padding sequence related to the preset sequence Z in the data sequence X is deleted according to the position of the preset sequence Z found in the data sequence X. The preset condition includes that the number of the preset sequence Z included in n codewords in the at least one decoded codeword Y reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence Z in the data sequence X.

[0145] The number of preset sequences Z included in the n codewords reaching the first threshold can mean that the number of preset sequences Z included in the n codewords is greater than the first threshold, or that the number of preset sequences Z included in the n codewords is greater than or equal to the first threshold. The interval between adjacent codewords in the n codewords is the period during which the preset sequence Z appears in the data sequence X, and the n codewords are continuous, that is, the n codewords are continuous according to the period during which the preset sequence Z appears in the data sequence X. All or some of the n codewords include the preset sequence Z. A codeword typically includes one preset sequence Z, while some codewords may not include the preset sequence Z. The value of n and the first threshold can be set according to actual circumstances. For example, if n = 3, the first threshold is 3.

[0146] The padding sequence associated with the preset sequence Z in the data sequence X is the padding sequence in the data sequence X that includes the preset sequence Z. For example, if a certain padding sequence includes the preset sequence Z, then the certain padding sequence is associated with the preset sequence Z, and the certain padding sequence is the padding sequence associated with the preset sequence Z. In one embodiment, the preset sequence Z is the FS mentioned in the discussion of the IEEE802.3dj standard, and the padding sequence associated with the preset sequence Z is the padding sequence in the IEEE802.3dj standard that includes the FS. In another embodiment, the preset sequence Z is the AM defined in the 200 / 400GE standard defined in the IEEE802.3bs project, and the padding sequence associated with the preset sequence Z is the AM.

[0147] During the process of searching for the preset sequence Z in the at least one decoded codeword Y by the receiving end, for example, during the preset sequence locking process, the receiving end monitors whether a preset condition is satisfied. For example, the receiving end checks in real time or periodically whether the preset condition is satisfied. If the receiving end determines that the preset condition is satisfied, the receiving end obtains the preset sequence Z that the receiving end has found in the at least one decoded codeword Y when the preset condition is satisfied. For each preset sequence Z that the receiving end has found in the at least one decoded codeword Y when the preset condition is satisfied, the receiving end determines, based on the position of each preset sequence Z in the data sequence X, a padding sequence associated with each preset sequence Z in the data sequence X, and deletes the padding sequence associated with each preset sequence Z in the data sequence X. Optionally, during the preset sequence locking process, the receiving end monitors whether the preset condition is satisfied. If the receiving end determines that the preset condition is satisfied, the receiving end locks on the first preset sequence Z found and then performs the preset sequence detection process. Specifically, the receiving end continues searching for the preset sequence Z in the at least one decoded codeword Y based on the position of the target preset sequence found in the preset sequence locking process (e.g., the target preset sequence is the last preset sequence found in the preset sequence locking process) in the data sequence X, and deletes the padding sequence associated with the preset sequence Z in the data sequence X according to the position of the found preset sequence Z in the data sequence X, until all FEC codewords distributed according to the target period in the data sequence X are found, or until the locked preset sequence is lost (the preset sequence monitoring process fails). The preset conditions include that the number of preset sequence Z included in n codewords in the at least one decoded codeword Y reaches a first threshold, and the interval between adjacent codewords in the n codewords is the period during which the preset sequence Z appears in the data sequence X (i.e., the target period described above). The fact that the number of preset sequences Z included in the n codewords reaches the first threshold indicates that the number of preset sequences Z included in the n codewords is relatively large, further indicating that there is no problem with the preset sequence found by the receiving end (for example, the found preset sequence is a true preset sequence). Therefore, when the number of preset sequences Z included in the n codewords reaches the first threshold, the receiving end deletes the padding sequence related to the preset sequence Z in the data sequence X according to the position of the found preset sequence Z in the data sequence X.

[0148] In one embodiment, a receiving end performs target FEC decoding on the multiple FEC codewords (i.e., all FEC codewords) in a data sequence X to obtain multiple decoded codewords Y. The receiving end then searches for a preset sequence Z in the multiple decoded codewords Y. During the process of searching for the preset sequence Z in the multiple decoded codewords Y, the receiving end monitors whether a preset condition is satisfied. If the receiving end determines that the preset condition is satisfied, the receiving end locks onto the first preset sequence Z found. Thereafter, based on a target preset sequence found during the preset sequence locking process (e.g., the target preset sequence is the last preset sequence found during the preset sequence locking process), the receiving end continues to search for the preset sequence Z in the multiple decoded codewords Y following the currently searched codeword according to a target period. The receiving end then deletes the padding sequence associated with the preset sequence Z in the data sequence X based on the position of the found preset sequence Z in the data sequence X.

[0149] In another embodiment, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X while searching for a preset sequence Z in the decoded codewords Y. The receiving end monitors whether a preset condition is satisfied during the search for the preset sequence Z in the data sequence X. If the receiving end determines that the preset condition is satisfied, the receiving end locks onto the first preset sequence Z found. Thereafter, based on the target preset sequence found during the preset sequence locking process (e.g., the target preset sequence is the last preset sequence found during the preset sequence locking process), the receiving end continues to search for the preset sequence Z in the FEC codewords following the currently searched FEC codeword in the data sequence X according to the target period. The receiving end then deletes the padding sequence associated with the preset sequence Z from the data sequence X based on the position of the found preset sequence Z in the data sequence X. Optionally, after the receiving end determines that the preset conditions are met, the receiving end traverses the FEC codewords after the currently decoded FEC codeword in the data sequence X according to the target period, performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords until the FEC codewords distributed according to the target period after the currently decoded FEC codeword are traversed.

[0150] In an optional embodiment, please continue to refer to FIG. 12 , after S1103 , the method for processing data further includes the following step S1106 .

[0151] S1106. If the loss of lock condition is met, re-search for FEC codeword boundaries in the data sequence X. The loss of lock condition includes that the number of m codewords in the at least one decoded codeword Y that does not include codewords of the preset sequence Z reaches a second threshold, where m is a positive integer, and the interval between adjacent codewords in the m codewords is the period during which the preset sequence Z appears in the data sequence X.

[0152] The number of codewords in the m codewords that do not include the preset sequence Z reaches the second threshold, which can be that the number of codewords in the m codewords that do not include the preset sequence Z is greater than the second threshold, or the number of codewords in the m codewords that do not include the preset sequence Z is greater than or equal to the second threshold. The interval between adjacent codewords in the m codewords is the period during which the preset sequence Z appears in the data sequence X. Optionally, the m codewords are continuous, that is, the m codewords are continuous according to the period during which the preset sequence Z appears in the data sequence X. All or some of the m codewords include the preset sequence Z. A codeword typically includes one preset sequence Z, while some codewords may not include the preset sequence Z. The value of m and the second threshold are both set according to actual circumstances. For example, if m = 12, the second threshold is 12. The loss of lock condition described herein can also be described as "the number of codewords in the at least one decoded codeword Y that include an incorrect (bad) preset sequence Z reaches the second threshold." An incorrect (bad) preset sequence is also referred to as a poor preset sequence, an incorrect preset sequence, or an invalid preset sequence.

[0153] In an embodiment of the present application, after the receiving end locks onto an FEC codeword boundary in a data sequence X, the receiving end determines multiple FEC codewords included in the data sequence X based on the FEC codeword boundary in the data sequence X, and then performs FEC decoding on at least one of the multiple FEC codewords to obtain the at least one decoded codeword Y. During the process of the receiving end searching for the preset sequence Z in the at least one decoded codeword Y, for example, during a preset sequence monitoring process, the receiving end monitors whether a loss-of-lock condition is satisfied. For example, the receiving end detects whether the loss-of-lock condition is satisfied in real time or periodically. If the receiving end determines that the lock-out condition is met, the receiving end determines that the locked FEC codeword boundary is incorrect, and the locked FEC codeword boundary is locked (or data sequence X is locked). The receiving end re-searches the FEC codeword boundary in the data sequence X. For example, the receiving end re-searches the FEC codeword boundary in the data sequence X through self-synchronization (or re-determines the FEC codeword boundary in the data sequence X). The receiving end re-determines the multiple FEC codewords included in the data sequence X based on the re-found FEC codeword boundary, and then performs FEC decoding on at least one FEC codeword among the re-determined multiple FEC codewords and searches for the preset sequence Z. For example, the receiving end executes the above-mentioned S1102, S1103, and S1105 based on the re-found FEC codeword boundary. Optionally, if the receiving end determines that the loss of lock condition is not met, the receiving end determines that the locked FEC codeword has not lost lock (or that the data sequence X has not lost lock), and the receiving end continues to search for the preset sequence Z in the original at least one decoded codeword Y, and continues to monitor whether the loss of lock condition is met until the loss of lock condition is met or until the at least one decoded codeword Y is completely searched. The loss of lock condition includes the number of codewords in the at least one decoded codeword Y that do not include the preset sequence Z reaching a second threshold, where the interval between adjacent codewords in the m codewords is a target period. The number of codewords in the m codewords that do not include the preset sequence Z reaching the second threshold indicates that the m codewords include a small number of the preset sequence Z, further indicating that the FEC codeword boundary locked by the receiving end is incorrect. Therefore, when the number of codewords in the m codewords that include the preset sequence Z reaches the second threshold, the receiving end re-searches for the FEC codeword boundary in the data sequence X.

[0154] In one embodiment, in S1102, the receiving end performs target FEC decoding on the multiple FEC codewords (i.e., all FEC codewords) in the data sequence X to obtain multiple decoded codewords Y. In S1103, the receiving end searches for a preset sequence Z in the multiple decoded codewords Y. If the loss-of-lock condition is not met, the receiving end continues to search for the preset sequence in the codewords following the currently searched codeword in the multiple decoded codewords Y according to the target period, and continues to monitor whether the loss-of-lock condition is met until the loss-of-lock condition is met or until the multiple decoded codewords Y are completely searched according to the target period. For example, the receiving end continues to traverse the codewords following the currently searched codeword in the multiple decoded codewords Y according to the target period, and the interval between two adjacent codewords traversed by the receiving end according to the target period is the target period.

[0155] In another embodiment, in S1102 and S1103, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z in the decoded codewords Y. If the loss-of-lock condition is not met, the receiving end continues to search for the preset sequence Z in the FEC codewords following the currently searched FEC codeword in the data sequence X according to the target period, and continues to monitor whether the loss-of-lock condition is met until the loss-of-lock condition is met or until all FEC codewords in the data sequence X are searched according to the target period. Optionally, if the loss-of-lock condition is not met, the receiving end traverses the FEC codewords following the currently decoded FEC codeword in the data sequence X according to the target period, performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords.

[0156] In the embodiment of the present application, the example of a loss of lock condition includes the number of codewords not including the preset sequence Z among the m codewords in the at least one decoded codeword Y reaching a second threshold. That is, the number of preset sequences Z found by the receiving end from the decoded codewords Y serves as the criterion for determining whether the lock has been lost. The loss of lock condition may also include other conditions. In an optional embodiment, after the receiving end locks onto the FEC codeword boundary in the data sequence X, it further monitors the codeword boundary of the data sequence X to determine whether the loss of lock condition is met. In this embodiment, the loss of lock condition may include the number of consecutive uncorrectable codewords in the data sequence X reaching a preset number, the proportion of consecutive uncorrectable codewords in the data sequence X reaching a preset ratio, etc. In these cases, the receiving end deems the locked FEC codeword boundary to be incorrect and re-searches for the FEC codeword boundary in the data sequence X. Among them, the preset number and the preset ratio can be set according to actual conditions. The continuously appearing uncorrectable codewords are uncorrectable codewords that appear continuously in multiple FEC codewords that the receiving end continuously performs target FEC decoding. The multiple FEC codewords can be continuous or discontinuous (for example, there may be some FEC codewords in the multiple FEC codewords with the interval between them being the target period). Optionally, the data sequence X includes FEC codeword X1, FEC codeword X2, FEC codeword X3...FEC codeword Xh, and the receiving end continuously performs target FEC decoding on FEC codeword X1, FEC codeword X4, and FEC codeword X7. Then, FEC codeword X1, FEC codeword X4, and FEC codeword X7 are multiple FEC codewords on which the receiving end continuously performs target FEC decoding. The continuously appearing uncorrectable codewords are the continuously appearing uncorrectable codewords in FEC codeword X1, FEC codeword X4, and FEC codeword X7. For example, the receiving end determines through target FEC decoding that FEC codeword X1 and FEC codeword X4 are both uncorrectable codewords. Then, FEC codeword X1 and FEC codeword X4 are the "continuously appearing uncorrectable codewords" described in the embodiment of the present application. The proportion of uncorrectable codewords that appear continuously in the data sequence X is the proportion of uncorrectable codewords that appear continuously in multiple FEC codewords that the receiving end continuously performs target FEC decoding on, specifically, the ratio of the number of uncorrectable codewords that appear continuously in the multiple FEC codewords to the number of the multiple FEC codewords. For example, if the receiving end continuously performs target FEC decoding on FEC codeword X1, FEC codeword X4, and FEC codeword X7 and determines that FEC codeword X1 and FEC codeword X4 are both uncorrectable codewords, then the receiving end determines that the proportion of uncorrectable codewords that appear continuously is 0.5.In a specific embodiment, during codeword boundary monitoring of a data sequence X by a receiving end, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X based on the locked FEC codeword boundaries. Based on the decoding result, the receiving end determines whether the FEC codeword is an uncorrectable codeword to perform uncorrectable codeword monitoring. If, during the monitoring process, the receiving end determines that the number of consecutive uncorrectable codewords has reached a preset number or the proportion of consecutive uncorrectable codewords has reached a preset ratio, the receiving end determines that a loss of lock condition has been met, that the locked FEC codeword boundary has been lost, and that the FEC codeword boundary in the data sequence X is re-searched. It can be seen that in the embodiments of the present application, there may be multiple loss of lock conditions. Setting multiple loss of lock conditions to monitor whether the locked FEC codeword boundary has been lost can improve the reliability of the loss of lock monitoring performed by the receiving end.

[0157] As previously described, in an embodiment of the present application, the receiving end determines the FEC codeword boundary in the data sequence X by self-synchronization. After determining the FEC codeword boundary in the data sequence X, the receiving end locks the FEC codeword boundary in the data sequence X. After locking the FEC codeword boundary in the data sequence X, the receiving end also monitors the FEC codeword boundary of the data sequence X to determine whether the locked FEC codeword boundary is lost. Since the receiving end determines the FEC codeword boundary in the data sequence X and locks the FEC codeword boundary in the data sequence X by self-synchronization, the process of the receiving end locking the FEC codeword boundary (the process from the receiving end starting to search for the FEC codeword boundary in the data sequence X to the receiving end locking the FEC codeword boundary in the data sequence X) can be called a self-synchronization locking process or a codeword boundary locking process, and the process of the receiving end monitoring the FEC codeword boundary of the data sequence X can be called a self-synchronization monitoring process or a codeword boundary monitoring process. In an optional embodiment, Figure 13 is a schematic diagram of a method for processing data provided in an embodiment of the present application. As shown in Figure 13, the receiving end first performs a self-synchronization locking process to lock the FEC codeword boundary of the data sequence X, and then performs a self-synchronization monitoring process based on the locked FEC codeword boundary to monitor the FEC codeword boundary of the data sequence X. Specifically, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X according to the locked FEC codeword boundary, and the receiving end monitors the data sequence X for uncorrectable codewords based on the decoding results. During the self-synchronization monitoring process of the receiving end, if the receiving end determines that the self-synchronization monitoring has failed (for example, the number of uncorrectable codewords appearing consecutively in the data sequence X reaches a preset number, the proportion of uncorrectable codewords appearing consecutively in the data sequence X reaches a preset ratio, etc.), the receiving end determines that the locked FEC codeword boundary has lost lock, and the receiving end re-executes the self-synchronization locking process to lock the FEC codeword boundary of the data sequence X. The receiving end performs the self-synchronization monitoring process based on the re-locked FEC codeword boundary, thus forming a closed-loop process of self-synchronization locking-self-synchronization monitoring-self-synchronization locking.

[0158] As shown in FIG13 , after locking the FEC codeword boundary in the data sequence X, the receiving end also performs a preset sequence locking process based on the locked FEC codeword boundary to lock the preset sequence Z in the data sequence X. The receiving end then performs a preset sequence monitoring process based on the locked preset sequence Z. Specifically, the receiving end performs target FEC decoding on at least one FEC codeword in the data sequence X based on the locked FEC codeword boundary to obtain at least one decoded codeword Y. The receiving end searches for the preset sequence Z in the at least one decoded codeword Y. If the number of preset sequences Z consecutively found by the receiving end in the at least one decoded codeword Y reaches a first threshold (e.g., 3), for example, if the receiving end determines that the preset condition described in S1105 is satisfied, the receiving end locks the first preset sequence Z found. Specifically, during the preset sequence monitoring process, the receiving end searches for the preset sequence Z in the at least one decoded codeword Y according to a target period based on the position of the target preset sequence found during the preset sequence locking process (for example, the target preset sequence is the last preset sequence found during the preset sequence locking process) in the data sequence X, until it is determined that the number of codewords in the at least one decoded codeword Y that do not include the preset sequence Z reaches a second threshold (that is, until the loss of lock condition described in S1106 is satisfied), and the receiving end determines that the preset sequence monitoring process has failed, or until the receiving end completes searching for the at least one decoded codeword Y according to the target period. If the receiving end determines that the preset sequence monitoring has failed, the receiving end determines that the locked preset sequence has lost lock. Since the locked preset sequence is locked based on the locked FEC codeword boundary, if the locked preset sequence loses lock, it can be considered that the locked FEC codeword boundary has lost lock. Therefore, as shown in Figure 13, if the receiving end determines that the preset sequence monitoring has failed, the receiving end re-executes the self-synchronization locking process to lock the FEC codeword boundary of data sequence X, the receiving end performs the self-synchronization monitoring process based on the re-locked FEC codeword boundary, the receiving end performs target decoding on the FEC codeword in data sequence X based on the re-locked FEC codeword boundary and performs the preset sequence locking process, and performs the preset sequence monitoring process based on the re-locked preset sequence Z, thus forming a closed-loop process of self-synchronization locking-preset sequence locking-preset sequence monitoring-self-synchronization locking. Optionally, if the receiving end determines that the preset sequence monitoring has failed, the receiving end can also skip the self-synchronization locking process and directly re-execute the preset sequence locking process, thus forming a closed-loop process of preset sequence locking-preset sequence monitoring-preset sequence locking, which is not limited in this embodiment of the present application.

[0159] The following describes the preset sequence locking process and the preset sequence monitoring process, taking the preset sequence Z as an example where the preset sequence Z is FS. As shown in Figures 14 and 15, Figure 14 is a state diagram of a preset sequence locking process provided by an embodiment of the present application, and Figure 15 is a state diagram of a preset sequence monitoring process provided by an embodiment of the present application. Figure 14 illustrates the case where the number of FS found by the receiving end in at least one decoded codeword Y reaches a first threshold, i.e., the receiving end locks the FS in data sequence X when the preset conditions described in S1105 are met. Figure 14 illustrates the case where the first threshold is 3. Figure 15 illustrates the case where the loss of lock condition is that the number of codewords that do not include FS in at least one decoded codeword of data sequence X reaches a second threshold. Figure 15 illustrates the case where the second threshold is 12. For example, the loss of lock condition is that the number of bad FS in at least one decoded codeword of data sequence X reaches 12. In Figures 14 and 15, a large rectangular box formed by two overlapping small rectangular boxes represents the state of the state machine. In each large rectangular box, the small rectangular box located above records the state name, and the small rectangular box located below records the operation performed by the state machine in the corresponding state. For example, in Figure 14, "FS_LOCK_INIT" is the state name, and the small rectangular box below the small rectangular box containing "FS_LOCK_INIT" records "test_fs <= false" indicating that the operation performed by the state machine in the "FS_LOCK_INIT" state is to assign the value "false" to the variable "test_fs". In the arrows connected to each large rectangular box used to represent a state, the arrow at the end connected to the large rectangular box records the transition condition for the state machine to enter the state represented by the large rectangular box, and the arrow at the beginning connected to the large rectangular box records the transition condition for the state machine to exit the state represented by the large rectangular box. For example, in Figure 14, the transition condition for the state machine to enter the state "FS_LOCK_INIT" is all_locked* and! fs_lock. The transition condition for the state machine to exit the "FS_LOCK_INIT" state is UCT, which represents an unconditional transition. This means the state machine can exit the "FS_LOCK_INIT" state without any conditional transition. The same applies to other states. Figure 14 shows that during the FS lock process, the receiver continuously searches for the FS. It locks the FS when it finds three consecutive FSs. Figure 15 shows that after locking the FS, the receiver enters the FS monitoring process. During the FS monitoring process, the receiver determines that the FS has lost lock when it finds 12 consecutive bad FSs. The receiver then searches again for FEC codeword boundaries in data sequence X.

[0160] The data processing method provided in the embodiment of the present application can be executed entirely by hardware or by a combination of software and hardware. For example, the steps of performing FEC decoding on the FEC codewords in the data sequence X and the steps before decoding can be performed by hardware, and the steps after decoding the FEC codewords in the data sequence X can be performed by software. Optionally, the receiving end includes an acquisition module, a synchronization module, a decoding module, a search module, and a deletion module. The acquisition module, the synchronization module, and the decoding module are all hardware modules, and the search module and the deletion module are all software modules. For example, the acquisition module is also called an acquisition circuit, the synchronization module is also called a synchronization circuit, and the decoding module is also called a decoding circuit (or called an FEC decoding circuit, an FEC decoder, etc.). The acquisition module extracts the data sequence X from the Ethernet signal received by the receiving end, the synchronization module searches for the FEC codeword boundary in the data sequence X, the decoding module performs FEC decoding on the FEC codewords in the data sequence X, the search module finds the preset sequence Y in the decoded codewords, and the deletion module monitors whether a preset condition is met and deletes the padding sequence related to the preset sequence Z in the data sequence X if the preset condition is met. In an optional embodiment, the decoding module may send all decoded codewords to the search module, and the search module searches for the preset sequence in all decoded codewords; or the decoding module may send part of the decoded codewords to the search module, and the search module searches for the preset sequence in this part of the decoded codewords. For example, the decoding module filters the decoding results, and the decoding module sends the filtered part of the codewords to the search module. Optionally, the decoding module filters the decoding results according to the target period (that is, the period in which the preset sequence Z appears in the data sequence X) and sends the filtered part of the codewords to the search module, which is not limited in this embodiment of the present application.

[0161] The length and content of the preset sequence described in the embodiments of the present application are fixed. In some technical documents, the preset sequence is also referred to as a fixed sequence or a similar term.

[0162] The above embodiments are described using the application of the present application to Ethernet as an example. The application scenarios of the embodiments of the present application are not limited to Ethernet. The embodiments of the present application can also be applied to network systems such as optical transport network (OTN), secret private network (SPN), fiber channel, and infinite bandwidth (Infiniband).

[0163] The above is an introduction to the method embodiments of the present application. The following describes the device embodiments of the present application. The device of the present application can be used to perform the method of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments.

[0164] An embodiment of the present application provides a device for processing data, which is used to execute the method embodiment shown in Figure 10 or Figure 11.

[0165] Optionally, the device includes an Ethernet interface, which may be a Terabit Ethernet interface.

[0166] Optionally, the device is any one of the following: a forwarding device, a user terminal device or a server device, a main chip, an optical module or a chip in an optical module. The forwarding device may be a router or a switch.

[0167] In one implementation, the apparatus includes at least one module configured to execute the method shown in FIG10 or FIG11. The at least one module may be implemented based on software, hardware, or a combination of software and hardware, and may be arbitrarily combined or divided based on the specific implementation.

[0168] Optionally, please refer to Figure 16, which shows a schematic diagram of a device 1600 for processing data provided in an embodiment of the present application. The device 1600 includes: an acquisition module 1610, a decoding module 1620 and a search module 1630.

[0169] Acquisition module 1610 is configured to acquire a data sequence comprising multiple FEC codewords. Decoding module 1620 is configured to perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword. Search module 1630 is configured to search for a preset sequence within the at least one decoded codeword. For the functional implementation of acquisition module 1610, please refer to the description in S1101. For the functional implementation of decoding module 1620, please refer to the description in S1102. For the functional implementation of search module 1630, please refer to the description in S1103.

[0170] Optionally, the preset sequence is a sequence that appears periodically in the data sequence.

[0171] Optionally, referring again to FIG. 16 , apparatus 1600 further includes a deletion module 1640 configured to delete a padding sequence associated with the found preset sequence in the data sequence based on the position of the preset sequence in the data sequence, if a preset condition is met. The preset condition includes that the number of preset sequences included in n codewords of the at least one decoded codeword reaches a first threshold, where n is a positive integer, and the interval between adjacent codewords in the n codewords is the period during which the preset sequence appears in the data sequence. For the functional implementation of deletion module 1640, please refer to the description in S1105.

[0172] Optionally, referring again to FIG. 16 , apparatus 1600 further includes a synchronization module 1650 configured to re-search an FEC codeword boundary in the data sequence if a loss-of-lock condition is met. The loss-of-lock condition includes the number of m codewords in the at least one decoded codeword that do not include a preset sequence reaching a second threshold, where m is a positive integer and the interval between adjacent codewords in the m codewords is the period during which the preset sequence appears in the data sequence. For the functional implementation of synchronization module 1650, please refer to the relevant description in S1106.

[0173] Optionally, the decoding module 1620 is configured to perform FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; correspondingly, the searching module 1630 is configured to find a preset sequence in the multiple decoded codewords.

[0174] Optionally, the decoding module 1620 is used to: perform FEC decoding on the first FEC codeword in the data sequence to obtain a decoded first codeword; if the decoded first codeword does not include a preset sequence, continue to perform FEC decoding on the FEC codewords after the first FEC codeword in the data sequence until the first preset sequence is found.

[0175] Optionally, the decoding module 1620 is further configured to: if the decoded first codeword includes a preset sequence, perform FEC decoding on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, where an interval between the second FEC codeword and the first FEC codeword is a period during which the preset sequence appears in the data sequence;

[0176] The searching module 1630 is further configured to attempt to search for a preset sequence in the decoded second codeword.

[0177] Optionally, the decoding module 1620 is configured to: perform FEC decoding on the first FEC codeword in the data sequence using a first decoding method; and perform FEC decoding on the candidate FEC codewords following the first FEC codeword in the data sequence using a second decoding method.

[0178] Optional; the first decoding method is soft decision decoding, and the second decoding method is hard decision decoding; or, the first decoding method is hard decision decoding, and the second decoding method is soft decision decoding.

[0179] Optionally, the apparatus 1600 further includes a synchronization module 1650, configured to determine the FEC codeword boundary in the data sequence by self-synchronization.

[0180] Optionally, the preset sequence is FS or the preset sequence is in AM.

[0181] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0182] Optionally, the Ethernet signal is a Terabit Ethernet signal.

[0183] The data processing device 1600 provided in the embodiment of the present application can also be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above-mentioned PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. Some steps of the data processing method provided in the above-mentioned method embodiment can also be implemented by software. When some steps of the data processing method provided in the above-mentioned method embodiment are implemented by software, some modules in the data processing device 1600 are software modules. Optionally, the acquisition module 1610, the decoding module 1620 and the synchronization module 1650 are all hardware modules, and the search module 1630 and the deletion module 1640 are both software modules.

[0184] In another implementation, the apparatus includes: a memory, a processor, and a communication interface. The communication interface includes an Ethernet interface; the memory is configured to store a computer program; and the processor is configured to execute the computer program stored in the memory to cause the apparatus to perform the relevant steps in the method embodiment shown in FIG11 or FIG12 , for example, causing the apparatus to perform steps S1103 and S1105.

[0185] In one embodiment, please refer to Figure 17, which shows a schematic diagram of another device 1700 for processing data provided in an embodiment of the present application. Device 1700 can be a forwarding device, a user terminal device, or a server device. Device 1700 includes at least one processor 1701 (Figure 17 uses two processors 1701 as an example), a communication bus 1702, a memory 1703, and at least one communication interface 1704. The at least one processor 1701, the memory 1703, and the at least one communication interface 1704 are connected via the communication bus 1702. The at least one processor 1701, the memory 1703, and the at least one communication interface 1704 can also be connected using other connection methods besides the communication bus 1702.

[0186] The memory 1703 is used to store computer programs for executing the technical solutions of the present application and is controlled by the processor 1701. The computer programs stored in the memory 1703 include but are not limited to program codes, program instructions, data, etc. The memory 1703 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or may be a non-volatile random access memory (NVRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these. The memory 1703 may be independent and connected to the processor 1701 via the communication bus 1702. The memory 1703 may also be integrated with the processor 1701, which is not limited in the embodiment of the present application.

[0187] Processor 1701 can be a general-purpose processor or a dedicated processor. A general-purpose processor is a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 1703). The general-purpose processor may use a computer program stored in a memory (e.g., memory 1703) in the process of performing the above steps and / or operations. The stored computer program can be executed to implement the related functions of the aforementioned search module 1630, deletion module 1650, etc. A general-purpose processor is, for example, but not limited to, a central processing unit (CPU). A dedicated processor is a processor specially designed to perform specific steps and / or operations. A dedicated processor is, for example, but not limited to, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Processor 1701 can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. Processor 1701 can also be a combination that implements computing functions, for example, including a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The processor can be configured to: find a preset sequence in at least one decoded codeword, where the at least one decoded codeword is obtained by performing FEC decoding on at least one FEC codeword in a data sequence, where the data sequence includes multiple FEC codewords; and, if a preset condition is satisfied, delete a padding sequence associated with the preset sequence in the data sequence based on a position of the found preset sequence in the data sequence, where the preset condition includes that the number of the preset sequence included in n codewords in the at least one decoded codeword reaches a first threshold, where n is a positive integer, and an interval between adjacent codewords in the n codewords is a period during which the preset sequence appears in the data sequence.

[0188] Communication bus 1702 is used to transmit information between processor 1701, communication interface 1704, and memory 1703. Communication bus 1702 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Communication bus 1702 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, FIG17 shows only one thick line, but this does not indicate that there is only one bus or only one type of bus.

[0189] Communication interface 1704 includes input / output (I / O) interfaces, physical interfaces, and logical interfaces, which are used to interconnect devices within device 1700, as well as interfaces for interconnecting device 1700 with other communication devices. Physical interfaces can be Ethernet interfaces, Fast Ethernet (FE) interfaces, Gigabit Ethernet (GE) interfaces, Terabit Ethernet (TbE) interfaces, 400G Ethernet interfaces, Asynchronous Transfer Mode (ATM) interfaces, etc., which are used to interconnect device 1700 with other devices. Logical interfaces are interfaces within device 1700 that are used to interconnect devices within device 1700. It is easy to understand that communication interface 1704 is used for communication between device 1700 and other devices. For example, communication interface 1704 is used to send and receive Ethernet signals between device 1700 and other devices or communication networks. The communication interface 1704 may be a device using any transceiver, and the communication network may be Ethernet, optical transport network (OTN), secret private network (SPN), fiber channel, infiniband, etc.

[0190] In a specific implementation, as an embodiment, the apparatus 1700 includes multiple processors 1701. Each of the multiple processors 1701 can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0191] In a specific embodiment, communication interface 1704 in apparatus 1700 is configured to receive an Ethernet signal carrying a data sequence, and processor 1701 is configured to obtain the data sequence from the Ethernet signal, perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and search for a predetermined sequence in the at least one decoded codeword. The detailed processing of processor 1701 is described in the method embodiments illustrated in Figures 11 and 12 above and is not further described here.

[0192] In another embodiment, please refer to Figure 18, which shows a schematic diagram of another data processing device 1800 provided in an embodiment of the present application. Device 1800 can be a forwarding device, such as a switch or router. As shown in Figure 18, device 1800 includes a main control board and one or more interface boards, and the main control board is communicatively connected to the interface boards. The main control board is also called a main processing unit (MPU) or a route processor card. The main control board is responsible for controlling and managing various components in device 1800, including routing calculation, device management, and maintenance functions. The interface board is also called a line processing unit (LPU) or a line card. The interface board is used to forward data. In some embodiments, device 1800 may also include a switching fabric board, which is communicatively connected to the main control board and the interface board. The switching fabric board is used to forward data between the interface boards. The switching fabric board may also be called a switch fabric unit (SFU). The interface board includes a central processing unit, memory, a forwarding chip, and a physical interface card (PIC). The central processing unit is communicatively connected to the memory, the forwarding chip, and the physical interface card. The memory is used to store the forwarding table. The forwarding chip is used to forward the received data frame based on the forwarding table stored in the memory. If the destination address of the data frame is the address of device 1800, the data frame is sent to the CPU for processing; if the destination address of the data frame is not the address of device 1800, the next hop and output interface corresponding to the destination address are found in the forwarding table according to the destination address, and the data frame is forwarded to the output interface corresponding to the destination address. The forwarding chip can be a network processor (NP). The PIC, also known as a daughter card, can be installed on the interface board and is responsible for converting the photoelectric signal into a data frame and forwarding the data frame to the forwarding chip for processing after performing a validity check on the data frame. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board. The communication connection between the main control board, the interface board, and the switching network board can be achieved through a bus. The forwarding chip can be implemented by ASIC or FPGA.

[0193] Logically, device 1800 comprises a control plane and a forwarding plane. The control plane includes the main control board and central processing unit (CPU), while the forwarding plane includes various components that perform forwarding, such as memory, PIC, and network router (NP). The control plane performs functions such as generating a forwarding table for the router, processing signaling and protocol messages, and configuring and maintaining status. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the NP forwards messages received by the PIC of device 1800 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in memory. In some embodiments, the control plane and forwarding plane can be completely separate and not located on the same device.

[0194] In a specific embodiment, the interface board is configured to receive an Ethernet signal, obtain a data sequence from the Ethernet signal, the data sequence including multiple FEC codewords, and perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword. For details, refer to the description of S1101 to S1102 above. The main control board is configured to search for a preset sequence in the at least one decoded codeword. For details, refer to the description of S1103 above and are not further described here.

[0195] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate with each other through the IPC channel.

[0196] Based on the same inventive concept, an embodiment of the present application provides a chip for executing the method provided in the embodiment shown in Figure 11 or Figure 12.

[0197] Optionally, the chip is a main chip or a chip in an optical module. The chip includes a programmable logic circuit and / or program instructions.

[0198] Optionally, the chip can be used in both cascaded FEC encoding and non-cascaded FEC encoding scenarios. Specifically, cascaded FEC encoding includes outer FEC encoding and inner FEC encoding, and the corresponding FEC decoding includes inner FEC decoding and outer FEC decoding. The chip provided in this embodiment of the application is used for inner FEC decoding and / or outer FEC decoding. Non-cascaded FEC encoding scenarios include one layer of FEC encoding, and the corresponding FEC decoding includes one layer of FEC decoding. The chip provided in this embodiment of the application is used for this layer of FEC decoding.

[0199] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed (e.g., by a forwarding device, a user terminal device, a server device, a main chip, an optical module, or a chip in an optical module), the steps of the method embodiments shown in Figures 11 and 12 are implemented. For example, steps S1103 and S1105 are implemented.

[0200] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes a program or code. When the program or code is executed (for example, by a forwarding device, a user terminal device, a server device, a main chip, an optical module, or a chip in an optical module), the steps of the method embodiments shown in Figures 11 and 12 are implemented. For example, steps S1103 and S1105 are implemented.

[0201] Based on the same inventive concept, an embodiment of the present application provides a communication system, which includes an optical module and a host. The optical module is communicatively connected to the host, for example, the optical module is plugged into the host, and the optical module is used to execute the method embodiments shown in Figures 11 and 12.

[0202] Optionally, the host is a forwarding device, a user terminal device or a server device. The forwarding device is a router or a switch.

[0203] Optionally, the communication system is a network system such as Ethernet, optical transport network (OTN), secret private network (SPN), fiber channel, or infiniband.

[0204] The technical solution provided by the embodiments of the present application is that the optical module is used to execute the method embodiments shown in Figures 11 and 12. The optical module executing the method embodiments shown in Figures 11 and 12 can improve the efficiency, accuracy and reliability of finding a preset sequence in a data sequence, thereby enabling the host connected to the optical module to obtain corresponding benefits, such as improving the host's processing efficiency and reliability of the data sequence.

[0205] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium (e.g., a solid-state hard disk).

[0206] It should be understood that the term "at least one" in this application refers to one or more, and "a plurality of" refers to two or more. In this application, unless otherwise specified, the symbol " / " generally means or, for example, A / B can mean A or B. The term "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. For the sake of clarity of description, in this application, words such as "first", "second", and "third" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first", "second", and "third" do not limit the quantity and order of execution.

[0207] The different types of embodiments, such as the method embodiments and device embodiments provided in the embodiments of this application, can refer to each other, and the embodiments of this application are not limited thereto. The order of the operations of the method embodiments provided in the embodiments of this application can be appropriately adjusted, and the operations can be increased or decreased in response to the circumstances. Any person skilled in the art who can easily think of a method of variation within the technical scope disclosed in this application should be included in the scope of protection of this application, and therefore will not be described in detail.

[0208] In the corresponding embodiments provided in this application, it should be understood that the disclosed devices, etc. can be implemented through other structural methods. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0209] The units described as separate components may or may not be physically separate, and the components described as units may or may not be physical units, and may be located in one place or distributed across multiple network nodes. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0210] The above description is merely an exemplary embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for processing data, characterized in that: The method comprises: Acquire a data sequence, wherein the data sequence includes a plurality of forward error correction (FEC) code words; Performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; A preset sequence is found in the at least one decoded codeword.

2. The method according to claim 1, characterized in that The preset sequence is a sequence that appears periodically in the data sequence.

3. The method according to claim 2, characterized in that The method comprises: If a preset condition is met, a padding sequence related to the preset sequence in the data sequence is deleted according to the position of the preset sequence found in the data sequence, wherein the preset condition includes that the number of the preset sequences included in n codewords of the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

4. The method according to claim 2 or 3, characterized in that: The method comprises: If the lock-loss condition is met, the FEC codeword boundary in the data sequence is searched again, and the lock-loss condition includes that the number of m codewords in the at least one decoded codeword that do not include the preset sequence reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period of the preset sequence appearing in the data sequence.

5. The method according to any one of claims 2 to 4, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword comprises: performing FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; The finding a preset sequence in the at least one decoded codeword includes: finding a preset sequence in the multiple decoded codewords.

6. The method according to any one of claims 2 to 4, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, comprises: Performing FEC decoding on a first FEC codeword in the data sequence to obtain a decoded first codeword; If the decoded first codeword does not include the preset sequence, FEC decoding is continued on the FEC codewords after the first FEC codeword in the data sequence until a first preset sequence is found.

7. The method according to claim 6, characterized in that The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, further comprises: If the decoded first codeword includes the preset sequence, FEC decoding is performed on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein an interval between the second FEC codeword and the first FEC codeword is a period during which the preset sequence appears in the data sequence; Try to find the preset sequence in the decoded second codeword.

8. The method according to claim 6 or 7, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence comprises: Performing FEC decoding on the first FEC codeword in the data sequence using a first decoding method; The candidate FEC codewords following the first FEC codeword in the data sequence are FEC decoded using a second decoding method.

9. The method according to claim 8, It is characterized by: The first decoding mode is soft decision decoding, and the second decoding mode is hard decision decoding; or, The first decoding mode is hard decision decoding, and the second decoding mode is soft decision decoding.

10. The method according to any one of claims 1 to 9, characterized in that: Before performing FEC decoding on at least one FEC codeword in the data sequence, the method further includes: determining a FEC codeword boundary in the data sequence by self-synchronization.

11. The method according to any one of claims 1 to 10, characterized in that: The preset sequence is a frame sequence FS or the preset sequence is in an alignment mark AM.

12. The method according to any one of claims 1 to 11, characterized in that: The method is executed by a main chip, an optical module or a chip in an optical module.

13. The method according to any one of claims 1 to 12, characterized in that: The data sequence is obtained according to an Ethernet signal received from an Ethernet interface.

14. The method according to claim 13, characterized in that The Ethernet signal is a Terabit Ethernet signal.

15. A device for processing data, characterized in that: Used to perform the method according to any one of claims 1 to 14.

16. The device according to claim 15, characterized in that The device comprises an Ethernet interface.

17. The device according to claim 15 or 16, characterized in that The device is any one of the following: a forwarding device, a user terminal device or a server device, a main chip, an optical module or a chip in an optical module.

18. A chip, characterized in that: Used to perform the method according to any one of claims 1 to 14.

19. The chip according to claim 18, characterized in that: The chip is a main chip or a chip in an optical module.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed, implements: finding a preset sequence in a decoded codeword; wherein the decoded codeword is obtained by performing FEC decoding on a forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

21. A communication system, characterized in that: It comprises an optical module and a host, and the optical module is used to execute the method according to any one of claims 1 to 14.

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