Wiring method, apparatus and device for quantum chip, and computer-readable storage medium

Abstract

A wiring method, apparatus and device for a quantum chip, and a computer-readable storage medium. The method comprises: on the basis of the positions of quantum bits on a quantum chip, determining starting interfaces corresponding to the quantum bits; determining first virtual pins on the basis of the starting interfaces, so that control lines in the quantum bits are connected to first external pins of the quantum chip by means of the starting interfaces and the first virtual pins, wherein a first spacing between the first virtual pins corresponding to any two starting interfaces is not smaller than a preset minimum line spacing; and on the basis of the starting interfaces, the first virtual pins and a Monte Carlo tree model, determining a first optimal connecting line path from the starting interfaces to the corresponding first virtual pins, wherein the Monte Carlo tree model is a mathematical model trained on the basis of wiring results obtained after performing wiring on different quantum bits.

Description

Quantum chip wiring method, device, equipment, and computer-readable storage medium Technical Field

[0001] The present invention relates to the field of quantum chip technology, and in particular to a quantum chip wiring method, device, equipment, and computer-readable storage medium. Background Art

[0002] Quantum chips are the core components of quantum computers. They integrate quantum bits and related circuits on a substrate, thereby carrying the function of quantum information processing. Typically, a quantum chip includes multiple quantum bits and quantum devices such as resonant cavities. As the number of quantum chip bits increases, the difficulty of quantum chip design increases exponentially. In the large-scale quantum chip design process, the issue of wiring consumes the most time and energy. For example, to achieve the driving of quantum bits, two control lines are usually relied on. The first is the xy control line of the microwave signal, and the second is the z control line of the magnetic flux signal. The control line interface on the quantum bit is connected to the external pin of the quantum chip through a connecting wire. The control signal is obtained from the outside through the control channel corresponding to the external pin, realizing the driving and frequency control of the quantum bit.

[0003] Due to the exponential annual growth of qubits in quantum chips today, manual wiring cannot meet the requirements of efficient layout design and iteration. Existing technologies for quantum chip wiring are generally achieved through automated wiring. Existing automated wiring methods generally use greedy algorithms to automatically select the shortest path between qubits and external pins for connection. They do not consider the problem from the perspective of overall optimization, nor do they consider the spacing between connecting wires. For more complex wiring scenarios such as two-dimensional quantum chip structures, since the two-dimensional quantum chip structure includes multiple qubit rows, each of which includes multiple qubits, the existing automated wiring method is still used for wiring. The spacing between connecting wires is often too close, resulting in problems such as signal crosstalk. The wiring success rate is low, and the application has great limitations. It cannot meet the complex layout and wiring conditions after the exponential growth of qubits in the future.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to provide a quantum chip wiring method, device, equipment, and computer-readable storage medium to achieve efficient and accurate automatic wiring of two-dimensional quantum chips, maximize the wiring efficiency of quantum chips, ensure that the line spacing between the connecting lines from the starting interface to the external pins of the quantum chip is not less than a preset minimum line spacing, and reduce the probability of problems such as signal crosstalk.

[0006] To solve the above technical problems, the present invention provides a wiring method for a quantum chip, wherein the quantum chip includes m qubit rows, and one qubit row includes n qubits, wherein m and n are both positive integers not less than 1. For any qubit, the wiring method includes:

[0007] Determining a starting interface corresponding to the quantum bit according to a position of the quantum bit on the quantum chip;

[0008] Determining a first virtual pin according to the starting interface, so that a control line in the quantum bit is connected to a first external pin of the quantum chip through the starting interface and the first virtual pin, and a first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing;

[0009] A first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin is determined based on the starting interface, the first virtual pin, and a Monte Carlo tree model, wherein the Monte Carlo tree model is a mathematical model trained based on wiring results after wiring different quantum bits.

[0010] On the one hand, after determining the first virtual pin according to the starting interface, the method further includes:

[0011] A second virtual pin is determined based on the first virtual pin, so that the control line in the quantum bit is connected to the second external pin of the quantum chip through the starting interface, the first virtual pin, and the second virtual pin, and a second spacing between the second virtual pins corresponding to any two of the first virtual pins is not less than the product of the first spacing and a preset expansion parameter, and the expansion parameter is greater than 1.

[0012] On the one hand, the first abscissa formula of the abscissa of the second virtual pin is The first ordinate formula of the ordinate of the second virtual pin is:

[0013] in, is the horizontal coordinate of the i-th first virtual pin, is the horizontal coordinate of the i-th second virtual pin, d is the distance between the second virtual pin and the first virtual pin, is the ordinate of the i-th second virtual pin, b is the number of the first virtual pins in the quantum bit row, is the vertical coordinate of the b / 2th second virtual pin, is the vertical coordinate of the b / 2th virtual pin, s 2 is the second distance between the second virtual pins.

[0014] On the one hand, after determining the first virtual pin according to the starting interface, the method further includes:

[0015] Determining a third virtual pin based on the first virtual pin, so that the control line in the quantum bit is connected to the third external pin of the quantum chip through the starting interface, the first virtual pin, and the third virtual pin, and a third spacing between the third virtual pins corresponding to any two of the first virtual pins is not less than a preset minimum line spacing;

[0016] The third virtual pin includes an upper virtual pin and a lower virtual pin, the first virtual pin of the quantum bit row in the first row corresponds to the upper virtual pin one-to-one, and the first virtual pin of the quantum bit row in the last row corresponds to the lower virtual pin one-to-one, the upper virtual pin is set above the quantum bit row in the first row, and the lower virtual pin is set below the quantum bit row in the last row, and the first distance between the upper virtual pin and the quantum bit row in the first row and the second distance between the lower virtual pin and the quantum bit row in the last row are both preset optimal pin distances.

[0017] On the one hand, the calculation formula of the optimal pin distance is:

[0018] Wherein, d is the optimal pin distance, n is the total number of connection lines connecting each first virtual pin to the corresponding third virtual pin, L 1i is the distance from the ith first virtual pin to the corresponding ith third virtual pin, L 2i is the distance from the i-th third virtual pin to the peripheral pin.

[0019] On the one hand, the second abscissa formula of the abscissa of the third virtual pin is The second ordinate formula of the ordinate of the third virtual pin is:

[0020] in, is the horizontal coordinate of the third virtual pin i, x q1 is the abscissa of the starting qubit of the first qubit row or the last qubit row, x qm is the horizontal coordinate of the middle qubit of the first qubit row or the last qubit row, n 3 is the number of the third virtual pins, is the vertical coordinate of the third virtual pin, y q1is the ordinate of the starting qubit of the first qubit row or the last qubit row, and d is the preset optimal pin distance.

[0021] On the one hand, after determining the third virtual pin according to the first virtual pin, the method further includes:

[0022] A second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin is determined according to the first virtual pin, the third virtual pin, and the Monte Carlo tree model.

[0023] On the one hand, after determining a second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin based on the first virtual pin, the third virtual pin, and the Monte Carlo tree model, the method further includes:

[0024] According to the third virtual pin, the third external pin of the quantum chip and the A* algorithm, the third virtual pin is connected to the corresponding third external pin, and the third external pin corresponds to the third virtual pin one by one.

[0025] On the one hand, after determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin, and the Monte Carlo tree model, the method further includes:

[0026] According to the first virtual pin, the first external pin of the quantum chip and the A* algorithm, the first virtual pin is connected to the corresponding first external pin, and the first external pin corresponds to the first virtual pin one by one.

[0027] In one aspect, the first virtual pins include a left-half portion of first virtual pins arranged on the left side of each of the qubit rows and a right-half portion of first virtual pins arranged on the right side of each of the qubit rows. The number of the left-half portion of first virtual pins is calculated as follows:

[0028] Among them, n l1 (k) is the number of first virtual pins in the left half, is the number of xy control lines provided on the left side of each of the qubit rows, is the number of z control lines arranged on the left side of each of the qubit rows;

[0029] The calculation formula for the number of first virtual pins in the right half is:

[0030] Among them, n r1 (k) is the number of first virtual pins in the right half, is the number of xy control lines provided to the right of each of the qubit rows, is the number of z control lines set to the right of each of the qubit rows, δ l is 0 or 1, δ r is 0 or 1, and δ l +δ r =1.

[0031] On the one hand, after determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin, and the Monte Carlo tree model, the method further includes:

[0032] Score the wiring result of the first optimal connection path according to a reward function;

[0033] The Monte Carlo tree model is updated according to the scoring results and the neural network model.

[0034] On the one hand, the reward function is defined as:

[0035] Wherein, s is the wiring state of the first optimal wiring path during the wiring process, a is the wiring behavior of the first optimal wiring path during the wiring process, L i is the wiring length of the first optimal connection path, L ri is the Manhattan length between the i-th unwired starting interface, N i is the number of right angles in the wiring process of the first optimal connection path, α, β, γ are the weight coefficients in front of each item, s′ is the wiring state after performing the wiring behavior a, and t is the state of completing the wiring of all the starting interfaces or encountering a state where wiring cannot continue.

[0036] On the one hand, the loss function of the neural network model is: L = (Rv) 2 +E p [log(p θ (s, a)·v(s, a)]+α|θ| 2 ;

[0037] Wherein, L is the loss function, s is the wiring state during the wiring process of the first optimal wiring path, a is the wiring behavior during the wiring process of the first optimal wiring path, R is the reward function, v is the value function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, and p θis the strategy function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, α is the regularization parameter of the neural network model, and θ is the parameter of the neural network model.

[0038] To solve the above technical problems, the present invention further provides a wiring device for a quantum chip, wherein the quantum chip includes m qubit rows, each of which includes n qubits, wherein m and n are both positive integers not less than 1. For any of the qubits, the wiring device includes:

[0039] a starting interface determination module, configured to determine a starting interface corresponding to the quantum bit according to a position of the quantum bit on the quantum chip;

[0040] a first virtual pin interface determining module, configured to determine a first virtual pin according to the starting interface, so that a control line within the qubit is connected to a first external pin of the quantum chip through the starting interface and the first virtual pin, and a first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing;

[0041] A first wiring module is used to determine a first optimal connection path for a connection line from the starting interface to the corresponding first virtual pin based on the starting interface, the first virtual pin, and a Monte Carlo tree model, wherein the Monte Carlo tree model is a mathematical model trained based on wiring results after wiring different quantum bits.

[0042] To solve the above technical problems, the present invention further provides a wiring device for a quantum chip, wherein the quantum chip includes m qubit rows, and one qubit row includes n qubits, wherein m and n are both positive integers not less than 1, and the wiring device includes:

[0043] memory for storing computer programs;

[0044] A processor is configured to implement the steps of any of the above-described quantum chip wiring methods when executing the computer program.

[0045] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the target computer program is executed by a processor, the steps of the quantum chip wiring method as described in any one of the above items are implemented.

[0046] The present invention provides a wiring method for a quantum chip, which uses a Monte Carlo tree model to calculate the optimal connection path between a starting interface and a corresponding first virtual pin. Since the Monte Carlo tree model can perform mathematical model training based on wiring results after previous wiring, and perform self-learning to obtain the optimal wiring result at the overall level, efficient and accurate automatic wiring of a two-dimensional quantum chip is achieved, thereby maximizing the wiring efficiency of the quantum chip. Moreover, through the setting of the first virtual pin, the control line within the quantum bit is connected to the external pin of the quantum chip through the starting interface and the first virtual pin. Since the first spacing between the first virtual pins is not less than a preset minimum line spacing, it is ensured that the line spacing of the connecting line from the starting interface to the external pin of the quantum chip is not less than the preset minimum line spacing, thereby reducing the probability of problems such as signal crosstalk.

[0047] The present invention also provides a wiring device, equipment, and computer-readable storage medium for a quantum chip, which have the above-mentioned beneficial effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] FIG1 is a flow chart of a quantum chip wiring method provided by an embodiment of the present invention;

[0050] FIG2 is a schematic diagram of the wiring of a greedy algorithm provided by an embodiment of the present invention;

[0051] FIG3 is a schematic diagram of Monte Carlo tree model wiring according to an embodiment of the present invention;

[0052] FIG4 is a schematic diagram of wiring from a first virtual pin to a second virtual pin according to an embodiment of the present invention;

[0053] FIG5 is a schematic diagram of wiring from a second virtual pin to a second external pin according to an embodiment of the present invention;

[0054] FIG6 is a schematic diagram of wiring from a first virtual pin to an upper virtual pin according to an embodiment of the present invention;

[0055] FIG7 is a schematic diagram of wiring from a first virtual pin to a lower virtual pin according to an embodiment of the present invention;

[0056] FIG8 is a schematic diagram of wiring area division provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The core of the present invention is to provide a quantum chip wiring method, device, equipment, and computer-readable storage medium to achieve efficient and accurate automatic wiring of two-dimensional quantum chips, maximize the wiring efficiency of quantum chips, ensure that the line spacing between the connecting lines from the starting interface to the external pins of the quantum chip is not less than the preset minimum line spacing, and reduce the probability of problems such as signal crosstalk.

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] Please refer to FIG1 , which is a flow chart of a wiring method for a quantum chip provided by an embodiment of the present invention. The quantum chip includes m qubit rows, and a qubit row includes n qubits, where m and n are both positive integers not less than 1. For any qubit, the wiring method includes:

[0060] S101: Determine the starting interface corresponding to the quantum bit based on the position of the quantum bit on the quantum chip.

[0061] In a specific embodiment, a parameterized quantum device library is first established. The quantum device library specifically includes quantum devices such as quantum bits and resonant cavities. Then, based on the requirements of the quantum chip, the quantum devices in the established quantum device library are arranged at specific locations on the chip according to a certain structure. In order to connect the control line interface on the quantum bit with the external pin of the quantum chip, so as to obtain external control signals through the control channel corresponding to the external pin and realize the driving and frequency control of the quantum bit, it is necessary to first determine the interface between the control line on the quantum bit and the quantum bit, that is, the starting interface corresponding to the quantum bit.

[0062] S102: Determine a first virtual pin according to the starting interface, so that the control line in the quantum bit is connected to the first external pin of the quantum chip through the starting interface and the first virtual pin, and a first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing.

[0063] In a specific embodiment, in order to facilitate wiring, virtual pins are used to divide the wiring of the entire quantum chip into several steps and perform wiring tasks separately. First, a first virtual pin is set at the edge of each row of quantum bit layout. The wiring task is divided into two tasks: on-chip wiring and off-chip wiring through the first virtual pin of each row, that is, the wiring is led from the inside of the quantum bit to the outside of the quantum bit through the first virtual pin of each row.

[0064] The position of the first virtual pin can be set by the user. The first virtual pin can be arranged near the bit edge.

[0065] S103: Determine a first optimal connection path for a connection line from the starting interface to the corresponding first virtual pin based on the starting interface, the first virtual pin, and a Monte Carlo tree model. The Monte Carlo tree model is a mathematical model trained based on wiring results after wiring different quantum bits.

[0066] When using the traditional greedy algorithm for traditional wiring, you will encounter the problem of blocking the second line after the previous line is laid, as shown in Figure 2 (the shaded area shown in Figure 2 is the area where wiring cannot be performed at present, for example, there is an obstacle), thus terminating the wiring. Figure 2 is a schematic diagram of the greedy algorithm wiring provided by an embodiment of the present invention. To solve the above problems, the present invention adopts a reinforcement learning method to allow the intelligent agent to automatically learn the optimal wiring strategy and learn to automatically explore the global wiring solution in various complex situations. In a specific embodiment, first, a grid is divided in the area where wiring is required, and the width of the grid is equal to the minimum constraint width between the lines in the wiring, so as to convert the wiring problem into a graph problem, that is, given G = (V, E), find a path P i And any two paths State s is defined as the set contained in graph G, including the starting interface and target interface information, the serial number being wired (serial wiring), the wiring head coordinates, etc.; the wiring behavior a is defined as a vector in the four directions of up, down, left and right. For the specific wiring process, please refer to state 0, state 1, state 2 to state n in Figure 3. Figure 3 is a schematic diagram of the Monte Carlo tree model wiring provided by an embodiment of the present invention. The shaded area in Figure 3 is the area where wiring is currently unavailable, for example, there are obstacles.

[0067] An embodiment of the present invention provides a wiring method for a quantum chip, which uses a Monte Carlo tree model to calculate the optimal connection path between a starting interface and a corresponding first virtual pin. Since the Monte Carlo tree model can perform mathematical model training based on the wiring results after previous wiring, and perform self-learning to obtain the optimal wiring result at the overall level, efficient and accurate automatic wiring of a two-dimensional quantum chip is achieved, thereby maximizing the wiring efficiency of the quantum chip; and through the setting of the first virtual pin, the control line within the quantum bit is connected to the external pin of the quantum chip through the starting interface and the first virtual pin. Since the first spacing between the first virtual pins is not less than the preset minimum line spacing, it is ensured that the line spacing of the connecting line from the starting interface to the external pin of the quantum chip is not less than the preset minimum line spacing, thereby reducing the probability of problems such as signal crosstalk.

[0068] Based on the above embodiment, in some embodiments, after determining the first virtual pin according to the starting interface, the method further includes:

[0069] The second virtual pin is determined based on the first virtual pin, so that the control line in the quantum bit is connected to the second external pin of the quantum chip through the starting interface, the first virtual pin and the second virtual pin, and the second spacing between the second virtual pins corresponding to any two first virtual pins is not less than the product of the first spacing and a preset expansion parameter, and the expansion parameter is greater than 1.

[0070] When the wiring is led out from the chip through the first virtual pin of each row, the first spacing between the lines is not less than the preset minimum line spacing. In order to reduce the crosstalk between signals and for the purpose of expanding impedance matching in the future, it is necessary to increase the spacing between the lines led out from the first virtual pin, that is, determine the second virtual pin according to the first virtual pin. Please refer to Figures 4 and 5 for details. Figure 4 is a wiring diagram from the first virtual pin to the second virtual pin provided in an embodiment of the present invention, and Figure 5 is a wiring diagram from the second virtual pin to the second external pin provided in an embodiment of the present invention. In a specific embodiment, a second virtual pin is set at a distance d from the first virtual pin. d can be adjusted as a parameter, usually d≈10~20w min , where w min The second spacing between the second virtual pins is a preset minimum spacing, and the second spacing between the second virtual pins is generally 1.5 to 2.5 times the spacing between the first virtual pins.

[0071] In some embodiments, the first virtual pin and the second virtual pin correspond one-to-one, that is, for each first virtual pin, there is a corresponding second virtual pin, and each first virtual pin must be connected to the corresponding external pin after being connected to the second virtual pin, so that the line spacing between each connection line is equal, which facilitates subsequent expansion.

[0072] In some embodiments, the first abscissa formula of the abscissa of the second virtual pin is: The first ordinate formula of the ordinate of the second virtual pin is

[0073] in, is the horizontal coordinate of the first virtual pin of the i-th node, is the horizontal coordinate of the i-th second virtual pin, d is the distance between the second virtual pin and the first virtual pin, is the ordinate of the second virtual pin of the ith qubit, b is the number of first virtual pins in the qubit row, is the vertical coordinate of the b / 2th second virtual pin, is the vertical coordinate of the b / 2th first virtual pin, s 2is the second distance between the second virtual pins.

[0074] It should be noted that in the above formula, [] means rounding up.

[0075] The horizontal coordinate and the vertical coordinate of the first virtual pin can both be user-set values. The first virtual pin can be set near a bit edge.

[0076] This embodiment determines the specific position of the second virtual pin through a formula, which ensures accurate positioning, reduces crosstalk between signals, and facilitates future expansion of impedance matching.

[0077] In some embodiments, after determining the first virtual pin according to the starting interface, the method further includes:

[0078] Determining a third virtual pin based on the first virtual pin, so that the control line in the quantum bit is connected to the third external pin of the quantum chip through the starting interface, the first virtual pin, and the third virtual pin, and a third spacing between the third virtual pins corresponding to any two first virtual pins is not less than a preset minimum line spacing;

[0079] The third virtual pin includes an upper virtual pin and a lower virtual pin. The first virtual pin of the first row of quantum bit rows corresponds one-to-one to the upper virtual pin, and the first virtual pin of the last row of quantum bit rows corresponds one-to-one to the lower virtual pin. The upper virtual pin is set above the quantum bit rows in the first row, and the lower virtual pin is set below the quantum bit rows in the last row. The first distance between the upper virtual pin and the quantum bit rows in the first row and the second distance between the lower virtual pin and the quantum bit rows in the last row are both preset optimal pin distances.

[0080] In a specific embodiment, for the two-dimensional structure commonly used today, for the first two rows and the last two rows of quantum bit rows in multiple quantum bit rows, the process of wiring from the first virtual pin to the third external pin corresponding to the quantum bits in the first row and the last row is relatively complex. Therefore, a third virtual pin is set between the first virtual pin and the third external pin. Please refer to Figures 6 and 7 for details. Figure 6 is a wiring diagram from the first virtual pin to the upper virtual pin provided in an embodiment of the present invention, and Figure 7 is a wiring diagram from the first virtual pin to the lower virtual pin provided in an embodiment of the present invention.

[0081] In some embodiments, the optimal pin distance is calculated as follows:

[0082] Where d is the optimal pin distance, n is the total number of connection lines connecting each first virtual pin to the corresponding third virtual pin, L 1i is the distance from the ith first virtual pin to the corresponding ith third virtual pin, L2i is the distance from the i-th third virtual pin to the peripheral pin.

[0083] To simplify reinforcement learning wiring, the third type of virtual pin is used as a wiring relay station for the quantum bits in the first and last rows, ensuring that the distance from the first virtual pin to the corresponding third virtual pin and then to the corresponding third external pin is appropriate. This embodiment uses a formula to determine the optimal pin distance for accurate positioning.

[0084] In some embodiments, the second abscissa formula of the abscissa of the third virtual pin is: The second ordinate formula of the ordinate of the third virtual pin is:

[0085] in, is the horizontal coordinate of the third virtual pin of the i-th node, x q1 is the horizontal coordinate of the starting qubit of the first or last qubit row, x qm is the horizontal coordinate of the middle qubit in the first or last qubit row, n 3 is the number of the third virtual pins, is the vertical coordinate of the third virtual pin of the i-th node, y q1 is the ordinate of the starting qubit of the first qubit row or the last qubit row, and d is the preset optimal pin distance.

[0086] This embodiment determines the specific position of the third virtual pin through a formula, and the positioning is accurate, wherein the start qubit is the qubit at the outermost position in the corresponding qubit row, and the middle qubit is the qubit at the middle position in the corresponding qubit row.

[0087] In some embodiments, after determining the third virtual pin according to the first virtual pin, the method further includes:

[0088] A second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin is determined according to the first virtual pin, the third virtual pin, and the Monte Carlo tree model.

[0089] In this embodiment, due to the complexity of the wiring scenario, a Monte Carlo search tree combined with a reinforcement learning algorithm is used to route the connection line from the first virtual pin to the corresponding third virtual pin, thereby improving the intelligence of the wiring process.

[0090] In some embodiments, after determining a second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin based on the first virtual pin, the third virtual pin, and the Monte Carlo tree model, the method further includes:

[0091] According to the third virtual pin, the third external pin of the quantum chip and the A* algorithm, the third virtual pin is connected to the corresponding third external pin, and the third external pin corresponds to the third virtual pin one by one.

[0092] In this embodiment, due to the simplicity of the wiring scenario, a traditional greedy algorithm, namely the A* algorithm, is directly used to perform wiring between the third virtual pin and the third external pin of the quantum chip, thereby improving wiring efficiency.

[0093] In some embodiments, after determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin, and the Monte Carlo tree model, the method further includes:

[0094] According to the first virtual pin, the first external pin of the quantum chip and the A* algorithm, the first virtual pin is connected to the corresponding first external pin, and the first external pin corresponds to the first virtual pin one by one.

[0095] In this embodiment, due to the simplicity of the wiring scenario, a traditional greedy algorithm, namely the A* algorithm, is directly used to perform wiring between the first virtual pin and the first external pin of the quantum chip, thereby improving wiring efficiency.

[0096] In a specific embodiment, the quantum chip is divided into a reinforcement learning wiring area and a non-reinforcement learning wiring area according to the complexity of the wiring. For the non-reinforcement learning wiring area, since the wiring scenario is simple and direct, the traditional greedy algorithm will be used for wiring to improve wiring efficiency. For the reinforcement learning wiring area, since the wiring scenario is complex, the Monte Carlo search tree combined with the reinforcement learning algorithm will be used for wiring. Please refer to Figure 8 for details. Figure 8 is a schematic diagram of wiring area division provided by an embodiment of the present invention.

[0097] In some embodiments, the first virtual pins include a left-half portion of first virtual pins disposed on the left side of each qubit row and a right-half portion of first virtual pins disposed on the right side of each qubit row. The number of the left-half portion of first virtual pins is calculated as follows:

[0098] Among them, n l1 (k) is the number of the first virtual pins in the left half, is the number of xy control lines placed on the left side of each qubit row, is the number of z control lines set to the left of each qubit row;

[0099] The formula for calculating the number of first virtual pins in the right half is:

[0100] Among them, n r1(k) is the number of the first virtual pins in the right half, is the number of xy control lines set to the right of each qubit row, is the number of z control lines set to the right of each qubit row, δ l is 0 or 1, δ r is 0 or 1, and δ l +δ r =1.

[0101] It should be noted that when the first virtual pin includes the left half of the first virtual pin arranged on the left side of each qubit row and the right half of the first virtual pin arranged on the right side of each qubit row, combined with the formula for the wiring position of the second virtual pin provided in the above embodiment, b=n l1 (k) or b=n r1 (k).

[0102] To balance the number of wirings in the left and right halves of each quantum chip layer and prevent local congestion of connection lines in the quantum chip, this embodiment uses a formula to determine the number of first virtual pins in the left and right halves, ensuring that the number of virtual pins on both sides is even, thereby adjusting the number of connection lines on both sides.

[0103] In some embodiments, after determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin, and the Monte Carlo tree model, the method further includes:

[0104] Scoring the wiring result of the first best connection path according to the reward function;

[0105] The Monte Carlo tree model is updated according to the scoring results and the neural network model.

[0106] This embodiment updates the Monte Carlo tree model through a reward function. Specifically, when the termination condition is met during the wiring process, the wiring is stopped, and the wiring results are scored using the reward function to guide the search process of the Monte Carlo tree and improve the wiring capability.

[0107] In some embodiments, the reward function is defined as:

[0108] Among them, s is the wiring state of the first best wiring path during the wiring process, a is the wiring behavior of the first best wiring path during the wiring process, L i is the wiring length of the first optimal connection path, L ri is the Manhattan length between the i-th unwired starting interface, N iis the number of right angles in the wiring process of the first optimal connection path, α, β, γ are the weight coefficients in front of each item, s′ is the wiring state after the wiring behavior a is performed, and t is the state of completing the wiring of all starting interfaces or encountering a state where wiring cannot continue.

[0109] This embodiment provides a reward function. Specifically, if the existing wiring length is smaller, the remaining wiring length is smaller, and the number of right-angle wirings is smaller, the intelligent agent will have a higher score, making the exploration strategy learned during the test more comprehensive and detailed, and providing an opportunity for long-term exploration of better wiring strategies.

[0110] In some embodiments, the loss function of the neural network model is: L = (Rv) 2 +Ep[log(p θ (s,a)·v(s,a)]+α|θ| 2 ;

[0111] Where L is the loss function, s is the wiring state during the wiring process of the first optimal wiring path, a is the wiring behavior during the wiring process of the first optimal wiring path, R is the reward function, v is the value function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, and p θ is the strategy function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, α is the regularization parameter of the neural network model, and θ is the parameter of the neural network model.

[0112] In a specific embodiment, the agent generates a large number of samples through the Monte Carlo tree to obtain training data for neural network training. The Monte Carlo tree will save four main pieces of information for each action a in the wiring: the number of edge visits N(s, a), the total action value W(s, a), the average action value Q(s, a) and the prior strategy probability P(s, a), where both the action value and the prior strategy probability are output by the neural network. Like the traditional Monte Carlo tree search method, the search process is divided into four stages: the first is the selection stage, where the selected action a combines the UCT and the judgment a of the optimal action value. t =arg max(Q(s t ,a)+U(s t ,a)), where Select a strategy for the UCT. Action selection continues until the final node or leaf node. The second stage is the expansion simulation stage. When a new leaf node that has not been searched is reached, the leaf node state s is input into the neural network for prediction to obtain the strategy action probability P and action value v and initialize the stored information to [N(s,a)=0,W(s,a)=0,Q(s,a)=0,P(s,a)=P]. Finally, there is the backtracking stage, which traces the information on the new node back to the parent node, N(s,a)=N(s,a)+1,W(s,a)=W(s,a)+v,Q(s,a)=W(s,a) / N(s,a). After hundreds or thousands of searches, the agent selects the branch π(a|s)=N(s,a) through the Monte Carlo tree strategy. 1 / τ / ∑ b N(s,b) 1 / τ , τ is a parameter that controls the degree of exploration. In order to reduce the search space of the Monte Carlo search tree, the present invention adopts a rollback method for search, that is, when encountering a terminal state (not to mention the final wiring state), try to move forward one step and reselect a new action to continue.

[0113] The agent's neural network is a ResNet (residual network) convolutional neural network (other convolutional neural networks such as VGGNet and AlexNet are also possible). The sample set obtained during the agent's Monte Carlo search tree search phase is used to train the neural network's model parameters. For each input state s, the neural network outputs p and v that minimize the loss function. The first part of the loss function is the difference between the actual reward and the neural network's predicted value. The second part is the expected value of the reward, which is the optimization objective of the policy gradient. The third part is a regularization term set to prevent overfitting. By optimizing the deep reinforcement learning neural network, the Monte Carlo search tree search process can be guided.

[0114] It should be noted that the reinforcement learning wiring in this embodiment adopts serial wiring, that is, sequential wiring. Of course, parallel wiring can also be used to increase the speed.

[0115] The above describes in detail various embodiments corresponding to the quantum chip wiring method. On this basis, the present invention also discloses a quantum chip wiring device, equipment and computer-readable storage medium corresponding to the above method.

[0116] The present invention further provides a wiring device for a quantum chip, wherein the quantum chip includes m qubit rows, each qubit row includes n qubits, wherein m and n are both positive integers not less than 1. For any qubit, the wiring device includes:

[0117] A starting interface determination module is used to determine the starting interface corresponding to the quantum bit according to the position of the quantum bit on the quantum chip;

[0118] a first virtual pin interface determining module, configured to determine a first virtual pin based on a starting interface, such that a control line within a quantum bit is connected to a first external pin of the quantum chip via the starting interface and the first virtual pin, and a first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing;

[0119] The first wiring module is used to determine the first optimal connection path of the connection line from the starting interface to the corresponding first virtual pin based on the starting interface, the first virtual pin and the Monte Carlo tree model. The Monte Carlo tree model is a mathematical model trained based on the wiring results after wiring different quantum bits.

[0120] In some embodiments, further comprising:

[0121] A second virtual pin interface determination module is configured to determine a second virtual pin based on the first virtual pin, so that a control line within the quantum bit is connected to a second external pin of the quantum chip through the starting interface, the first virtual pin, and the second virtual pin, and a second spacing between the second virtual pins corresponding to any two first virtual pins is not less than the product of the first spacing and a preset extension parameter, and the extension parameter is greater than 1.

[0122] In some embodiments, the first abscissa formula of the abscissa of the second virtual pin is: The first ordinate formula of the ordinate of the second virtual pin is

[0123] in, is the horizontal coordinate of the first virtual pin of the i-th node, is the horizontal coordinate of the i-th second virtual pin, d is the distance between the second virtual pin and the first virtual pin, is the ordinate of the second virtual pin of the ith qubit, b is the number of first virtual pins in the qubit row, is the vertical coordinate of the b / 2th second virtual pin, is the vertical coordinate of the b / 2th first virtual pin, s 2 is the second distance between the second virtual pins.

[0124] In some embodiments, further comprising:

[0125] a third virtual pin interface determination module, configured to determine a third virtual pin based on the first virtual pin, so that a control line within the quantum bit is connected to a third external pin of the quantum chip through the starting interface, the first virtual pin, and the third virtual pin, and a third spacing between the third virtual pins corresponding to any two first virtual pins is not less than a preset minimum line spacing;

[0126] The third virtual pin includes an upper virtual pin and a lower virtual pin. The first virtual pin of the first row of quantum bit rows corresponds one-to-one to the upper virtual pin, and the first virtual pin of the last row of quantum bit rows corresponds one-to-one to the lower virtual pin. The upper virtual pin is set above the quantum bit rows in the first row, and the lower virtual pin is set below the quantum bit rows in the last row. The first distance between the upper virtual pin and the quantum bit rows in the first row and the second distance between the lower virtual pin and the quantum bit rows in the last row are both preset optimal pin distances.

[0127] In some embodiments, the optimal pin distance is calculated as follows:

[0128] Where d is the optimal pin distance, n is the total number of connection lines connecting each first virtual pin to the corresponding third virtual pin, L 1i is the distance from the ith first virtual pin to the corresponding ith third virtual pin, L 2i is the distance from the i-th third virtual pin to the peripheral pin.

[0129] In some embodiments, the second abscissa formula of the abscissa of the third virtual pin is: The second ordinate formula of the ordinate of the third virtual pin is:

[0130] in, is the horizontal coordinate of the third virtual pin of the i-th node, x q1 is the horizontal coordinate of the starting qubit of the first or last qubit row, x qm is the horizontal coordinate of the middle qubit in the first or last qubit row, n 3 is the number of the third virtual pins, is the vertical coordinate of the third virtual pin of the i-th node, y q1 is the ordinate of the starting qubit of the first qubit row or the last qubit row, and d is the preset optimal pin distance.

[0131] In some embodiments, further comprising:

[0132] The second routing module is configured to determine a second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin based on the first virtual pin, the third virtual pin, and the Monte Carlo tree model.

[0133] In some embodiments, further comprising:

[0134] The third wiring module is used to connect the third virtual pin with the corresponding third external pin according to the third virtual pin, the third external pin of the quantum chip and the A* algorithm, and the third external pin corresponds to the third virtual pin one by one.

[0135] In some embodiments, further comprising:

[0136] The fourth wiring module is used to connect the first virtual pin with the corresponding first external pin according to the first virtual pin, the first external pin of the quantum chip and the A* algorithm, and the first external pin corresponds to the first virtual pin one by one.

[0137] In some embodiments, the first virtual pins include a left-half portion of first virtual pins disposed on the left side of each qubit row and a right-half portion of first virtual pins disposed on the right side of each qubit row. The number of the left-half portion of first virtual pins is calculated as follows:

[0138] Among them, n l1 (k) is the number of the first virtual pins in the left half, is the number of xy control lines placed on the left side of each qubit row, is the number of z control lines set to the left of each qubit row;

[0139] The formula for calculating the number of first virtual pins in the right half is:

[0140] Among them, n r1 (k) is the number of the first virtual pins in the right half, is the number of xy control lines set to the right of each qubit row, is the number of z control lines set to the right of each qubit row, δ l is 0 or 1, δ r is 0 or 1, and δ l +δ r =1.

[0141] In some embodiments, further comprising:

[0142] A reward function module, configured to score the wiring result of the first optimal connection path according to the reward function;

[0143] The Monte Carlo tree update module is used to update the Monte Carlo tree model based on the scoring results and the neural network model.

[0144] In some embodiments, the reward function is defined as:

[0145] Among them, s is the wiring state of the first best wiring path during the wiring process, a is the wiring behavior of the first best wiring path during the wiring process, L i is the wiring length of the first optimal connection path, L ri is the Manhattan length between the i-th unwired starting interface, N i is the number of right angles in the wiring process of the first optimal connection path, α, β, γ are the weight coefficients in front of each item, s′ is the wiring state after the wiring behavior a is performed, and t is the state of completing the wiring of all starting interfaces or encountering a state where wiring cannot continue.

[0146] In some embodiments, the loss function of the neural network model is: L = (Rv) 2 +E p [log(p θ (s, a)·v(s, a)]+α|θ| 2 ;

[0147] Where L is the loss function, s is the wiring state during the wiring process of the first optimal wiring path, a is the wiring behavior during the wiring process of the first optimal wiring path, R is the reward function, v is the value function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, and p θ is the strategy function output by the neural network model when the wiring state s and wiring behavior a are input to the neural network model, α is the regularization parameter of the neural network model, and θ is the parameter of the neural network model.

[0148] For an introduction to a wiring device for a quantum chip provided by the present invention, please refer to the above embodiment, and the present invention will not be elaborated here.

[0149] The present invention further provides a wiring device for a quantum chip, wherein the quantum chip includes m qubit rows, each qubit row includes n qubits, wherein m and n are both positive integers not less than 1, and the wiring device includes:

[0150] memory for storing computer programs;

[0151] A processor is used to implement the steps of the above-mentioned quantum chip wiring method when executing a computer program.

[0152] For an introduction to a wiring device for a quantum chip provided by the present invention, please refer to the above embodiment, and the present invention will not be elaborated here.

[0153] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the target computer program is executed by a processor, the steps of the quantum chip wiring method as described above are implemented.

[0154] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above embodiments, and the present invention will not be elaborated here.

[0155] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0156] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0157] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Claims

1. A quantum chip wiring method, characterized in that: The quantum chip includes m quantum bit rows, one of which includes n quantum bits, wherein m and n are both positive integers not less than 1, and for any of the quantum bits, the wiring method includes: Determining a starting interface corresponding to the quantum bit according to a position of the quantum bit on the quantum chip; Determine a first virtual pin according to the starting interface, so that the control line in the quantum bit is connected to the first external pin of the quantum chip through the starting interface and the first virtual pin, and the first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing; According to the starting interface, the first virtual pin and the Monte Carlo tree model, a first optimal connection path of the connection line from the starting interface to the corresponding first virtual pin is determined, and the Monte Carlo tree model is a mathematical model trained according to the wiring results after wiring different quantum bits.

2. The quantum chip wiring method according to claim 1, characterized in that: After determining the first virtual pin according to the starting interface, the method further includes: The second virtual pin is determined according to the first virtual pin, so that the control line in the quantum bit is connected to the second external pin of the quantum chip through the starting interface, the first virtual pin and the second virtual pin, and the second spacing between the second virtual pins corresponding to any two of the first virtual pins is not less than the product of the first spacing and a preset extension parameter, and the extension parameter is greater than 1.

3. The quantum chip wiring method according to claim 2, characterized in that: The first abscissa formula of the abscissa of the second virtual pin is: The first ordinate formula of the ordinate of the second virtual pin is: in, is the horizontal coordinate of the i-th first virtual pin, is the horizontal coordinate of the i-th second virtual pin, d is the distance between the second virtual pin and the first virtual pin, is the ordinate of the i-th second virtual pin, b is the number of the first virtual pins in the quantum bit row, is the ordinate of the b / 2th second virtual pin, is the ordinate of the b / 2th virtual pin, s 2 is a second distance between the second virtual pins.

4. The quantum chip wiring method according to claim 1, characterized in that: After determining the first virtual pin according to the starting interface, the method further includes: Determine a third virtual pin according to the first virtual pin, so that the control line in the quantum bit is connected to the third external pin of the quantum chip through the starting interface, the first virtual pin and the third virtual pin, and the third spacing between the third virtual pins corresponding to any two of the first virtual pins is not less than a preset minimum line spacing; The third virtual pin includes an upper virtual pin and a lower virtual pin, the first virtual pin of the quantum bit row in the first row corresponds to the upper virtual pin one-to-one, the first virtual pin of the quantum bit row in the last row corresponds to the lower virtual pin one-to-one, the upper virtual pin is arranged above the quantum bit row in the first row, and the lower virtual pin is arranged below the quantum bit row in the last row, and the first distance between the upper virtual pin and the quantum bit row in the first row and the second distance between the lower virtual pin and the quantum bit row in the last row are both preset optimal pin distances.

5. The quantum chip wiring method according to claim 4, characterized in that: The calculation formula for the optimal pin distance is: Wherein, d is the optimal pin distance, n is the total number of connection lines connecting each of the first virtual pins with the corresponding third virtual pins, and L 1i is the distance from the ith first virtual pin to the corresponding ith third virtual pin, L 2i is the distance from the ith third virtual pin to the peripheral pin.

6. The quantum chip wiring method according to claim 4, characterized in that: The second abscissa formula of the abscissa of the third virtual pin is: The second ordinate formula of the ordinate of the third virtual pin is: in, is the horizontal coordinate of the third virtual pin of the ith q1 is the abscissa of the starting qubit of the first qubit row or the last qubit row, x qm is the abscissa of the middle qubit of the first qubit row or the last qubit row, n 3 for the number of the third virtual pins, is the ordinate of the third virtual pin of the ith q1 is the ordinate of the starting quantum bit of the first quantum bit row or the last quantum bit row, and d is the preset optimal pin distance.

7. The quantum chip wiring method according to claim 4, characterized in that: After determining the third virtual pin according to the first virtual pin, the method further includes: A second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin is determined according to the first virtual pin, the third virtual pin and the Monte Carlo tree model.

8. The quantum chip wiring method according to claim 7, characterized in that: After determining a second optimal connection path of a connection line from the first virtual pin to the corresponding third virtual pin according to the first virtual pin, the third virtual pin and the Monte Carlo tree model, the method further includes: According to the third virtual pin, the third external pin of the quantum chip and the A* algorithm, the third virtual pin is connected to the corresponding third external pin, and the third external pin corresponds to the third virtual pin one by one.

9. The quantum chip wiring method according to claim 7, characterized in that: After determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin and the Monte Carlo tree model, the method further includes: According to the first virtual pin, the first external pin of the quantum chip and the A* algorithm, the first virtual pin is connected to the corresponding first external pin, and the first external pin corresponds to the first virtual pin one by one.

10. The quantum chip wiring method according to claim 1, characterized in that: The first virtual pins include a left-half first virtual pin arranged on the left side of each of the qubit rows and a right-half first virtual pin arranged on the right side of each of the qubit rows. The number of the left-half first virtual pins is calculated as follows: Among them, n l1 (k) is the number of the first virtual pins in the left half, is the number of xy control lines arranged on the left side of each of the qubit rows, is the number of z control lines arranged on the left side of each of the qubit rows; The calculation formula for the number of first virtual pins in the right half is: Among them, n r1 (k) is the number of first virtual pins in the right half, is the number of xy control lines arranged on the right side of each of the qubit rows, is the number of z control lines arranged on the right side of each of the qubit rows, δ l is 0 or 1, δ r is 0 or 1, and δ l +δ r =1.

11. The quantum chip wiring method according to any one of claims 1 to 10, characterized in that: After determining a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin and the Monte Carlo tree model, the method further includes: Scoring the wiring result of the first optimal wiring path according to a reward function; The Monte Carlo tree model is updated according to the scoring results and the neural network model.

12. The quantum chip wiring method according to claim 11, characterized in that: The reward function is defined as: Wherein, s is the wiring state of the first optimal wiring path during the wiring process, a is the wiring behavior of the first optimal wiring path during the wiring process, and L i is the wiring length of the first optimal wiring path, L ri is the Manhattan length between the i-th starting interface that has not yet been routed, N i is the number of right angles in the wiring process of the first optimal connection path, α, β, γ are the weight coefficients in front of each item, s′ is the wiring state after performing the wiring behavior a, and t is the state of completing the wiring of all the starting interfaces or encountering a state where the wiring cannot continue.

13. The quantum chip wiring method according to claim 11, characterized in that: The loss function of the neural network model is: L = (Rv) 2 +E p [log(p θ (s,a)·v(s,a)]+α|θ| 2 ; Wherein, L is the loss function, s is the wiring state of the first optimal wiring path during the wiring process, a is the wiring behavior of the first optimal wiring path during the wiring process, R is the reward function, v is the value function output by the neural network model when the wiring state s and the wiring behavior a are input to the neural network model, and p θ is the strategy function output by the neural network model when the wiring state s and the wiring behavior a are input to the neural network model, α is the regularization parameter of the neural network model, and θ is the parameter of the neural network model.

14. A wiring device for a quantum chip, characterized in that: The quantum chip includes m quantum bit rows, one of the quantum bit rows includes n quantum bits, wherein m and n are both positive integers not less than 1, and for any of the quantum bits, the wiring device includes: A starting interface determination module, used to determine the starting interface corresponding to the quantum bit according to the position of the quantum bit on the quantum chip; A first virtual pin interface determination module, configured to determine a first virtual pin according to the starting interface, so that the control line in the quantum bit is connected to the first external pin of the quantum chip through the starting interface and the first virtual pin, and a first spacing between the first virtual pins corresponding to any two starting interfaces is not less than a preset minimum line spacing; The first wiring module is used to determine a first optimal connection path of a connection line from the starting interface to the corresponding first virtual pin according to the starting interface, the first virtual pin and a Monte Carlo tree model, wherein the Monte Carlo tree model is a mathematical model trained according to wiring results after wiring different quantum bits.

15. A wiring device for a quantum chip, characterized in that: The quantum chip includes m quantum bit rows, one of the quantum bit rows includes n quantum bits, wherein m and n are both positive integers not less than 1, and the wiring device includes: Memory for storing computer programs; A processor, configured to implement the steps of the quantum chip wiring method according to any one of claims 1 to 13 when executing the computer program.

16. A computer-readable storage medium, characterized in that: The target computer-readable storage medium stores a computer program, and when the target computer program is executed by a processor, the steps of the quantum chip wiring method according to any one of claims 1 to 13 are implemented.

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