Switching device, memory expansion module, and memory expansion system

Abstract

Provided in the embodiments of the present application are a switching device, a memory expansion module, and a memory expansion system. The switching device comprises: a connector and a controller, M uplink ports and N downlink ports being deployed on the connector, M being an integer greater than or equal to 1, and N being an integer greater than 1. The M uplink ports are configured to connect to a host end by means of compute express link protocol. The N downlink ports are configured to connect to a memory end by means of compute express link protocol, the memory end being an expanded memory of the host end. The controller is configured to control the binding between the M uplink ports and the N downlink ports, each uplink port being allowed to mapping to the N downlink ports. The present application solves the problem of low memory capacity, thereby achieving the effect of expanding the memory capacity.

Description

Switching devices, memory expansion modules, and memory expansion systems

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 6, 2023, with application number 202311144716.4, entitled “Switching Chip, Memory Expansion Module and Memory Expansion System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and in particular to a switching device, a memory expansion module, and a memory expansion system. Background Art

[0004] Artificial intelligence, deep learning, and high-performance computing have made significant progress in recent years. With the increasing amount of data generated by CPUs (Central Processing Units), GPUs (Graphics Processing Units), and other AI processors, this data needs to be seamlessly exchanged between processors to execute extremely intensive neural network algorithms and complete critical tasks such as data mining, vision, and speech processing. Currently, the capacity of memory systems used to exchange data between processors lags far behind the memory capacity required for data processing.

[0005] With regard to the problems of low memory capacity in related technologies, no effective solutions have been proposed yet.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a switching device, a memory expansion module, and a memory expansion system to at least solve the problem of low memory capacity in related technologies.

[0008] According to a first aspect, a switching device is provided, comprising: a connector and a controller, wherein the connector is deployed with M upstream ports and N downstream ports, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; the M upstream ports are configured to connect to a host side via a computing fast connection protocol; the N downstream ports are configured to connect to a memory side via a computing fast connection protocol, wherein the memory side is an extended memory of the host side; and the controller is configured to control binding between the M upstream ports and the N downstream ports, wherein each upstream port is allowed to be mapped to the N downstream ports.

[0009] In an exemplary embodiment, the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0010] In an exemplary embodiment, the switching device further includes: a target processor, wherein the controller includes: a structure management module and an in-band configuration port; the target processor is configured to send a target control signal to the structure management module through the in-band configuration port; the structure management module is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and the target uplink port and the target downlink port are bound according to the target mapping relationship.

[0011] In an exemplary embodiment, a universal asynchronous receiver / transmitter (UATS) interface is deployed on both the target processor and the controller, wherein the target processor is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0012] In an exemplary embodiment, universal asynchronous receiver / transmitter (UATS) interfaces are deployed on both the target processor and the controller. During the initialization phase of the switching device, the controller receives signals sent by the target processor via the UART interface, thereby configuring the types of the uplink port and the downlink port of the switching device. The target processor writes corresponding control signals and mapping relationships into the controller via the UART interface, and the controller receives and stores the corresponding relationship between the control signals and the mapping relationship, wherein the mapping relationship includes the corresponding relationship between the uplink port and the downlink port.

[0013] In an exemplary embodiment, the target upstream ports include m upstream ports, and the target downstream ports include n downstream ports, where m is less than or equal to M, and n is less than or equal to N.

[0014] In an exemplary embodiment, M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0015] In an exemplary embodiment, N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit.

[0016] In an exemplary embodiment, the uplink port of the switching device is connected to the host side via a computing fast connection protocol. The host side includes processor 0 and processor 1, and processor 0 and processor 1 are interconnected via a hyperpath interconnect bus, forming a dual-path server as the host side. When one processor performs memory expansion, the other processor can obtain the expanded memory via the hyperpath interconnect bus, and each processor can provide two sets of CXL x16 interfaces, which are respectively connected to the uplink port of the switching device; the downlink port of the switching device is connected to the memory expansion controller of the memory side via the computing fast connection protocol, and memory expansion is performed through the double rate controller inside the memory expansion controller.

[0017] According to a second aspect, a memory expansion module is provided, comprising: a switching device and a memory end, wherein M upstream ports and N downstream ports are deployed on the switching device, and the N downstream ports are connected to the memory end through a computing fast connection protocol, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; the M upstream ports are configured to connect to the host end through the computing fast connection protocol; the switching device is configured to control the binding between the M upstream ports and the N downstream ports, wherein each upstream port is allowed to be mapped to N downstream ports; and the memory end is configured to provide extended memory for the host end.

[0018] In an exemplary embodiment, a switching device includes: a connector and a controller, wherein M upstream ports and N downstream ports are deployed on the connector; the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0019] In an exemplary embodiment, the switching device further includes: a target processor, wherein the controller includes: a structure management module and an in-band configuration port; the target processor is configured to send a target control signal to the structure management module through the in-band configuration port; the structure management module is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and the target uplink port and the target downlink port are bound according to the target mapping relationship.

[0020] In an exemplary embodiment, a universal asynchronous receiver / transmitter (UATS) interface is deployed on both the target processor and the controller, wherein the target processor is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0021] In an exemplary embodiment, the target upstream ports include m upstream ports, and the target downstream ports include n downstream ports, where m is less than or equal to M, and n is less than or equal to N.

[0022] In an exemplary embodiment, M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0023] In an exemplary embodiment, N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit.

[0024] According to a third aspect, a memory expansion system is provided, comprising: a host side, a switching device, and a memory side, wherein M upstream ports and N downstream ports are deployed on the switching device, the N downstream ports are connected to the memory side via a computing fast connection protocol, and the M upstream ports are connected to the host side via a computing fast connection protocol, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; the switching device is configured to control the binding between the M upstream ports and the N downstream ports, wherein each upstream port is allowed to be mapped to N downstream ports; the memory side is configured to provide extended memory for the host side; and the host side is configured to use the memory side as extended memory.

[0025] In an exemplary embodiment, a switching device includes: a connector and a controller, wherein M upstream ports and N downstream ports are deployed on the connector; the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0026] In an exemplary embodiment, the switching device further includes: a target processor, wherein the controller includes: a structure management module and an in-band configuration port; the target processor is configured to send a target control signal to the structure management module through the in-band configuration port; the structure management module is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and the target uplink port and the target downlink port are bound according to the target mapping relationship.

[0027] In an exemplary embodiment, a universal asynchronous receiver / transmitter (UATS) interface is deployed on both the target processor and the controller, wherein the target processor is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0028] In an exemplary embodiment, the target upstream ports include m upstream ports, and the target downstream ports include n downstream ports, where m is less than or equal to M, and n is less than or equal to N.

[0029] In an exemplary embodiment, M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0030] In an exemplary embodiment, N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit.

[0031] Through this application, the M upstream ports deployed on the connector are connected to the host end through a computing fast connection protocol, and the N downstream ports deployed on the connector are connected to the memory end through a computing fast connection protocol. Since the controller realizes the control of binding between the M upstream ports and the N downstream ports, each host end connected to the upstream port can use the extended memory connected to the downstream port with which it has a mapping relationship, thereby expanding the memory for one or more host ends. Therefore, the problem of low memory capacity can be solved and the effect of expanding memory capacity can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram 1 of a switching device according to an embodiment of the present application;

[0033] FIG2 is a second schematic diagram of a switching device according to an embodiment of the present application;

[0034] FIG3 is a third schematic diagram of a switching device according to an embodiment of the present application;

[0035] FIG4 is a fourth schematic diagram of a switching device according to an embodiment of the present application;

[0036] FIG5 is a fifth schematic diagram of a switching device according to an embodiment of the present application;

[0037] FIG6 is a sixth schematic diagram of a switching device according to an embodiment of the present application;

[0038] FIG7 is a schematic diagram of a use process of a switching device according to an embodiment of the present application;

[0039] FIG8 is a schematic diagram of a memory expansion process of a switching device according to an embodiment of the present application;

[0040] FIG9 is a schematic diagram of a memory expansion module according to an embodiment of the present application;

[0041] FIG10 is a schematic diagram of an extended memory of a memory expansion module according to an embodiment of the present application;

[0042] FIG11 is a schematic diagram of a memory expansion system according to an embodiment of the present application;

[0043] FIG12 is a schematic diagram of an extended memory of a memory expansion system according to an embodiment of the present application;

[0044] FIG13 is a schematic diagram of an extended memory of a large memory expansion system according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] In this embodiment, a switching device is provided. FIG1 is a schematic diagram of a switching device according to an embodiment of the present application. As shown in FIG1 , the switching device includes: a connector 102 and a controller 104, wherein the connector 102 is deployed with M uplink ports (106-1 to 106-M) and N downlink ports (108-1 to 108-N), wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; the M uplink ports (106-1 to 106-M), It is configured to connect to the host side 110 through a computing fast connection protocol; N downstream ports (108-1 to 108-N) are configured to connect to the memory side 112 through a computing fast connection protocol, wherein the memory side 112 is the extended memory of the host side 110; the controller 104 is configured to control the binding between M upstream ports (106-1 to 106-M) and N downstream ports (108-1 to 108-N), wherein each upstream port is allowed to be mapped to N downstream ports.

[0048] Through the above-mentioned switching device, the M upstream ports deployed on the connector are connected to the host end through the computing fast connection protocol, and the N downstream ports deployed on the connector are connected to the memory end through the computing fast connection protocol. Since the controller realizes the control of binding between the M upstream ports and the N downstream ports, each host end connected to the upstream port can use the extended memory connected to the downstream port with which it has a mapping relationship, thereby expanding the memory for one or more host ends. Therefore, the problem of low memory capacity can be solved and the effect of expanding memory capacity can be achieved.

[0049] Optionally, in this embodiment, the switching device proposed in this application allows for application in a variety of scenarios where memory expansion is performed through computing fast connection protocols, including but not limited to: multi-scale data set processing, data centers and cloud computing, machine learning, etc. Any server that allows the deployment of devices can use the switching device proposed in this application, and any scenario that requires memory expansion can use the switching device proposed in this application for memory expansion.

[0050] Optionally, in this embodiment, the connector deploys one or more uplink ports and multiple downlink ports, and the connector may be, but is not limited to, a switch, a bridge, or an electronic device that allows deployment of uplink ports and downlink ports.

[0051] Optionally, in this embodiment, the uplink port is connected to a host device on the host side. The host device may be, but is not limited to, a single-way server including one CPU or a multi-way server consisting of multiple CPUs, etc. The multi-way server may be, but is not limited to, CPU0 and CPU1 interconnected by a UPI (Ultra Path Interconnect) bus to form a dual-way server, etc.

[0052] Optionally, in this embodiment, the uplink port is connected to the host device on the host side through the CXL (Compute Express Link) protocol. For example, each CPU supports two CXL interfaces with a bandwidth of x16 (i.e., CXL x16 interfaces), and the two CXL x16 interfaces of a single CPU are respectively connected to the two uplink ports (USP, UpStream Port) of the connector.

[0053] Optionally, in this embodiment, the memory side is extended memory on the host side, and may include, but is not limited to, extended memory space and devices that connect the extended memory to the downstream port. The extended memory space may include, but is not limited to, DIMMs (Dual Inline Memory Modules), SODIMMs (Small Outline Dual Inline Memory Modules), and UDIMMs (Unbuffered Dual Inline Memory Modules or Unregistered Dual In-Line Memory Modules). The devices that connect the extended memory to the downstream port may include, but are not limited to, MXCs (Memory Expander Controllers), HBM (High Bandwidth Memory) expansion modules, and HMC (Hybrid Memory Cube) expansion modules.

[0054] Optionally, in this embodiment, the controller may, but is not limited to, control the binding of the M upstream ports and the N downstream ports based on the correspondence between the upstream ports and the downstream ports. For example, the correspondence between the M upstream ports and the N downstream ports may be pre-set, and the M upstream ports and the N downstream ports may be bound according to the pre-set correspondence. Alternatively, the correspondence between the M upstream ports and the N downstream ports may be dynamically determined based on usage of the M upstream ports and the N downstream ports, and the M upstream ports and the N downstream ports may be bound according to the currently determined correspondence.

[0055] Optionally, in this embodiment, the upstream port and the downstream port may be bound by, but not limited to, connecting the upstream port and the downstream port. For example, the upstream port and the downstream port are conductively connected to each other to bind the upstream port and the downstream port. Alternatively, the upstream port and the downstream port may be bound by transmitting a signal transmitted by the upstream port to the corresponding downstream port.

[0056] Optionally, in this embodiment, each upstream port is allowed to be mapped to N downstream ports. A single upstream port can be bound to one or more downstream ports. That is, a single upstream port can use, but is not limited to, extended memory connected to one or more downstream ports based on the memory requirements of the host connected to the current upstream port. For example, if the memory requirements of the host connected to the current upstream port are large, multiple downstream ports can be connected to use the multiple extended memories connected thereto. Alternatively, if the memory requirements of the host connected to the current upstream port are small or non-existent, the number of connected downstream ports can be reduced, thereby reducing the amount of connected extended memory.

[0057] In an exemplary embodiment, the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0058] Optionally, in this embodiment, the target mapping relationship may be, but is not limited to, predetermined, or may change in real time based on the demand for extended memory by the host connected to the upstream port. For example, a target downstream port having a target mapping relationship with the target upstream port is obtained from a predetermined mapping relationship, and the target upstream port and the target downstream port are bound. Alternatively, based on the demand for extended memory by the host connected to the upstream port, some downstream ports are selected from all downstream ports as target downstream ports, and the target upstream port and the target downstream port are bound.

[0059] Optionally, in this embodiment, the target mapping relationship is used to indicate the binding relationship between the target upstream port and the target downstream port, which may include but is not limited to: a binding relationship between a target upstream port and a target downstream port, a binding relationship between a target upstream port and multiple target downstream ports, etc.

[0060] In an exemplary embodiment, Figure 2 is a second schematic diagram of a switching device according to an embodiment of the present application. As shown in Figure 2, the switching device further includes: a target processor 202, wherein the controller 104 includes: a structure management module 204 and an in-band configuration port 206; the target processor 202 is configured to send a target control signal to the structure management module 204 through the in-band configuration port 206; the structure management module 204 is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships with corresponding relationships; and bind the target uplink port and the target downlink port according to the target mapping relationship.

[0061] Optionally, in this embodiment, the structure management module of the controller is configured to control the binding between M uplink ports and N downlink ports, and may include but is not limited to: Fabric (in-band management controller), switch, router, network management system, etc.

[0062] Optionally, in this embodiment, the target processor sends a target control signal to the in-band configuration port. The target processor may include, but is not limited to, an mCPU (micro Central Processing Unit). The in-band configuration port may be configured to forward the target control signal sent by the target processor to the fabric management module. The fabric management module controls the binding of the target uplink port and the target downlink port based on the target control signal.

[0063] Optionally, in this embodiment, the in-band configuration port of the controller is configured to receive a target control signal sent by a target processor. The target control signal may include, but is not limited to: a target control signal carrying a target mapping relationship between a target upstream port and a target downstream port, and the fabric management module obtains the target mapping relationship between the target upstream port and the target downstream port by receiving the target control signal. Alternatively, the target control signal carries information indicating the target mapping relationship between the target upstream port and the target downstream port, and the fabric management module obtains the target mapping relationship between the target upstream port and the target downstream port by parsing the information indicated by the target control signal.

[0064] Optionally, in this embodiment, the connection method between the target processor and the in-band configuration port includes: connection through a group of PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard), connection through PCI (Peripheral Component Interconnect, a high-speed serial computer expansion bus standard), etc.

[0065] In an exemplary embodiment, Figure 3 is a third schematic diagram of a switching device according to an embodiment of the present application. As shown in Figure 3, a universal asynchronous receive / transmit transmission interface 302 is deployed on both the target processor 202 and the controller 104, wherein the target processor 202 is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0066] Optionally, in this embodiment, UART (Universal Asynchronous Receiver / Transmitter) is deployed on both the target processor and the controller. During the initialization phase of the switching device, the signal sent by the target processor can be received through the UART interface, but is not limited to, so as to configure the type of the upstream port and the downstream port of the switching device. For example, the target processor writes the control signal and the mapping relationship with the corresponding relationship into the controller, so that the controller receives and stores the corresponding relationship between the control signal and the mapping relationship, wherein the mapping relationship includes the corresponding relationship between the upstream port and the downstream port.

[0067] In an exemplary embodiment, Figure 4 is a fourth schematic diagram of a switching device according to an embodiment of the present application. As shown in Figure 4, the target uplink port 402 includes m uplink ports, and the target downlink port 404 includes n downlink ports, where m is less than or equal to M, and n is less than or equal to N.

[0068] Optionally, in this embodiment, one or more uplink ports may be determined as target uplink ports, but is not limited to being determined. Each target uplink port may have one or more corresponding target downlink ports, but is not limited to being determined. The number of target downlink ports for each target uplink port may be determined based on, but is not limited to being determined by, the amount of memory expansion required by the host connected to the target uplink port. For example:

[0069] Taking the example that the uplink ports include uplink port 1, uplink port 2, and uplink port 3, and the downlink ports include downlink port 1, downlink port 2, and downlink port 3, the target downlink port of the target uplink port may include, but is not limited to, the following:

[0070] When upstream port 1 is determined as the target upstream port, the target downstream ports corresponding to upstream port 1 include downstream port 1; or, the target downstream ports corresponding to upstream port 1 include downstream port 1 and downstream port 2.

[0071] When upstream port 1 and upstream port 2 are determined as target upstream ports, the target downstream ports corresponding to upstream port 1 include downstream port 1, and the target downstream ports corresponding to upstream port 2 include downstream port 2; or, the target downstream ports corresponding to upstream port 1 include downstream port 1 and downstream port 2 (the host end connected to upstream port 1 has a greater demand for extended memory, so more extended memory is connected), and the target downstream ports corresponding to upstream port 2 include downstream port 3.

[0072] Optionally, in this embodiment, the target processor sends different control signals to the in-band configuration port of the switching device. The in-band management port forwards the control signals to the structure management module. After the structure management module receives the control signals, the structure management module controls the mapping of the target uplink port and the target downlink port according to the control signals. Taking the uplink ports USP including USP-0, USP-1, USP-2, and USP-3, and the downlink ports (DSP) including DSP-0 and DSP-1 as an example, Table 1 is an example of a mapping relationship between a control signal and an uplink port and a downlink port. The target mapping relationship indicated by the target control signal may include, but is not limited to, the following:

[0073] Table 1

[0074] As shown in Table 1, when the control signal includes 0000, the downstream ports DSP-0 and DSP-1 are used as target downstream ports, and the memory ports connected to the target downstream ports are used to expand the memory of the target upstream port USP-0.

[0075] When the control signal includes 0001, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-0, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-0; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1.

[0076] When the control signal includes 0010, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-0, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-0; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-2, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-2.

[0077] When the control signal includes 0011, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-0, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-0; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-3, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-3.

[0078] When the control signal includes 0100, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-0, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-0.

[0079] When the control signal includes 0101, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1.

[0080] When the control signal includes 0110, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-2, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-2.

[0081] When the control signal includes 0111, the downstream port DSP-0 is used as the target downstream port of the upstream port USP-1, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-1; the downstream port DSP-1 is used as the target downstream port of the upstream port USP-3, and the memory end connected to the target downstream port is used to expand the memory of the target upstream port USP-3.

[0082] Similarly, the target mapping relationships indicated by other target control signals included in Table 1 are similar to the above description and will not be described in detail here.

[0083] The target control signal may include, but is not limited to, one or more control signals in Table 1. When the target control signal includes multiple control signals, the structure management module may, but is not limited to, mapping multiple target upstream ports to corresponding target downstream ports according to each control signal in the target control signal.

[0084] In an exemplary embodiment, Figure 5 is a schematic diagram 5 of a switching device according to an embodiment of the present application. As shown in Figure 5, M uplink ports (106-1 to 106-M) include: a first uplink port 502, a second uplink port 504, a third uplink port 506 and a fourth uplink port 508, and the host end 110 includes: a first processor 510 and a second processor 512, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0085] Optionally, in this embodiment, the first processor and the second processor can be, but are not limited to, respectively a server, or the first processor and the second processor are connected via a UPI bus to form a dual-way server as a host side. In the case where the first processor and the second processor are connected via a UPI bus to form a dual-way server as a host side, and when the first processor obtains extended memory, the second processor can, but is not limited to, occupy the extended memory of the first processor via the UPI bus.

[0086] Optionally, in this embodiment, the first upstream port and the second upstream port are both connected to the first processor, and the third upstream port and the fourth upstream port are both connected to the second processor. The controller can, but is not limited to, perform memory expansion for the first processor and the second processor by connecting the first upstream port, the second upstream port, the third upstream port, and the fourth upstream port.

[0087] In an exemplary embodiment, Figure 6 is a schematic diagram of a switching device according to an embodiment of the present application. As shown in Figure 6, N downstream ports (108-1 to 108-N) include: a first downstream port 602 and a second downstream port 604, and the memory end 112 includes: a first memory unit 606 and a second memory unit 608, wherein the first downstream port 602 is connected to the memory expansion controller in the first memory unit 606, and the second downstream port 604 is connected to the memory expansion controller in the second memory unit 608.

[0088] Optionally, in this embodiment, the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit. The memory expansion controller expands the memory through an internal DDR (Double Data Rate) controller.

[0089] In an exemplary embodiment, Figure 7 is a schematic diagram of the use process of a switching device according to an embodiment of the present application. As shown in Figure 7, the switching device includes a fabric management module (FMM), which is connected to an in-band configuration port. The in-band configuration port is connected to a target processor (mCPU) through a set of PCIe x16 buses and forwards the target control signal sent by the target processor to the fabric management module. The fabric management module is also connected to multiple upstream ports and downstream ports, wherein the upstream ports include USP-0, USP-1, USP-2 and USP-3, and the downstream ports include DSP-0 and DSP-1. Under the control of the target control signal sent by the mCPU, the fabric management module obtains the mapping of the target upstream port and the target downstream port, connects the CXL bus supporting a single host to different target downstream ports, and thereby expands a larger capacity memory for the host side connected to the target upstream port. The correspondence between the upstream port and the downstream port and the control signal is written into the fabric management module by the target processor via UART during the initialization phase of the switching device.

[0090] The uplink port of the switching device is connected to the host side through the computing fast connection protocol. The host side includes CPU0 and CPU1, and CPU0 and CPU1 are interconnected through the UPI bus, forming a dual-channel server as the host side. When one CPU has memory expansion, the other CPU can obtain the expanded memory through the UPI bus, and each CPU can provide two sets of CXL x16 interfaces, which are respectively connected to the uplink port of the switching device.

[0091] The downlink port of the switching device is connected to the MXC on the memory side through the computing fast connection protocol, and memory expansion is performed through the DDR controller inside the MXC.

[0092] For switching devices, GPIO (General-purpose input / output) is also included as a debugging interface. GPIO can output status information of each internal port, such as PLL status (Phase Locked Loop), Boot done (Bootstrap done), and Link up. If a problem occurs in the switching device, the GPIO port status can be checked to help locate the problem. For example:

[0093] PLL status: When the level is 1, it indicates that the clock frequency and phase of the phase-locked loop are stable. When the level is 0, it indicates that the phase-locked loop is not stable.

[0094] Boot done: When the level is 1, the port has completed initialization. When the level is 0, the port has not completed initialization.

[0095] Link up: When the level is 1, it indicates that the port is connected to the host or memory. When the level is 0, it indicates that the port is not connected or the connection fails.

[0096] Similarly, the switch device also supports JTAG (Joint Test Action Group) interface debugging, and a JTAG debugger is connected to the switch device to debug the device registers.

[0097] Use Flash (flash memory) to store the firmware information of the switching device. After the switching device is powered on, the switching device can read the firmware configuration information of the switching device through the SPI bus to complete the basic initialization configuration.

[0098] Use the CLK Generator to output a 100MHz clock to the switching equipment to provide basic clock requirements.

[0099] The switch also includes an I2C (Inter-Integrated Circuit) interface topology. For example, the mCPU acts as the I2C host, expanding the port through an I2C expander. This interface connects to the TS (Thermal Sensor) to read the switch's temperature in real time, and to the FRU (Field Replaceable Unit) to obtain basic board information such as the manufacturer, production date, and firmware version. The I2C interface also supports reading the switch's register information.

[0100] In an exemplary embodiment, Figure 8 is a schematic diagram of a memory expansion process of a switching device according to an embodiment of the present application. As shown in Figure 8, after the initialization work is completed on the memory side, the switching device reads the firmware information and performs basic configuration. The target processor communicates with the universal asynchronous receiver and transmitter transmission interface through the PCIe x16 bus to configure the uplink port and downlink port of the switching device. In the process of using the switching device for memory expansion, the structure management module deployed in the switching device receives the target control signal sent by the target processor, and binds the target uplink port and target downlink port of the switching device according to the target control signal, so that the host connected to the target uplink port can recognize the expanded memory connected to the target downlink port and complete the memory expansion.

[0101] In this embodiment, a memory expansion module is also provided, which is configured to implement the above-mentioned embodiments and optional implementations. Details already described will not be repeated here. As used below, the term "unit" may refer to a combination of software and / or hardware that implements a predetermined function. Although the memory expansion modules described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0102] FIG9 is a schematic diagram of a memory expansion module according to an embodiment of the present application. As shown in FIG9 , the memory expansion module includes: a switching device 902 and a memory terminal 904, wherein the switching device 902 is deployed with M uplink ports (906-1 to 906-M) and N downlink ports (908-1 to 908-N), and the N downlink ports (908-1 to 908-N) are connected to the memory terminal 904 through a computing fast connection protocol, wherein M is greater than or equal to 1, N is an integer greater than 1; the M uplink ports are configured to connect to the host end 910 through a computing fast connection protocol; the switching device 902 is configured to control the binding between the M uplink ports (906-1 to 906-M) and the N downlink ports (908-1 to 908-N), wherein each uplink port is allowed to be mapped to the N downlink ports (908-1 to 908-N); the memory end 904 is configured to provide extended memory for the host end 910.

[0103] Through the above-mentioned memory expansion module, the M upstream ports deployed on the connector are connected to the host end through the computing fast connection protocol, and the N downstream ports deployed on the connector are connected to the memory end through the computing fast connection protocol. Since the controller realizes the control of binding between the M upstream ports and the N downstream ports, each host end connected to the upstream port can use the extended memory connected to the downstream port with which it has a mapping relationship, thereby expanding the memory for one or more host ends. Therefore, the problem of low memory capacity can be solved and the effect of expanding memory capacity can be achieved.

[0104] In an exemplary embodiment, a switching device includes: a connector and a controller, wherein M upstream ports and N downstream ports are deployed on the connector; the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0105] In an exemplary embodiment, the switching device further includes: a target processor, wherein the controller includes: a structure management module and an in-band configuration port; the target processor is configured to send a target control signal to the structure management module through the in-band configuration port; the structure management module is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and the target uplink port and the target downlink port are bound according to the target mapping relationship.

[0106] In an exemplary embodiment, a universal asynchronous receiver / transmitter (UATS) interface is deployed on both the target processor and the controller, wherein the target processor is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0107] In an exemplary embodiment, the target upstream ports include m upstream ports, and the target downstream ports include n downstream ports, where m is less than or equal to M, and n is less than or equal to N.

[0108] In an exemplary embodiment, M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0109] In an exemplary embodiment, N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit.

[0110] In an exemplary embodiment, Figure 10 is a schematic diagram of the extended memory of a memory expansion module according to an embodiment of the present application. As shown in Figure 10, an uplink port USP is deployed on the switching device, which is connected to the host end through a CXL x16 CDFP (Compact Digital Format Pluggable) cable. The host end includes multiple CPUs. The downlink port DSP is also deployed on the switching device, which is connected to the memory end through a CXL x16 CDFP cable. The memory end includes multiple DIMM memory modules.

[0111] The memory expansion module also includes a power connector, a flash memory device and a debugging interface. The power connector can support P12V and P3V3_AUX power inputs, and the debugging interface facilitates debugging of the memory expansion module.

[0112] This embodiment also provides a memory expansion system for implementing the above-described embodiments and alternative implementations. Details already described will not be repeated. As used below, the term "unit" may refer to a combination of software and / or hardware that implements a predetermined function. Although the memory expansion system described in the following embodiments is preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0113] FIG11 is a schematic diagram of a memory expansion system according to an embodiment of the present application. As shown in FIG11 , the memory expansion system is characterized by comprising: a host end 1102, a switching device 1104, and a memory end 1106, wherein the switching device 1104 is deployed with M uplink ports (1108-1 to 1108-M) and N downlink ports (1110-1 to 1110-N), the N downlink ports (1110-1 to 1110-N) being connected to the memory end 1106 via a computing fast connection protocol, and the M uplink ports (1108-1 to 1110-N) being connected to the memory end 1106 via a computing fast connection protocol. 08-M) is connected to the host side 1102 through a computing fast connection protocol, where M is an integer greater than or equal to 1, and N is an integer greater than 1; the switching device 1104 is configured to control the binding between M upstream ports (1108-1 to 1108-M) and N downstream ports (1110-1 to 1110-N), where each upstream port is allowed to be mapped to N downstream ports; the memory side 1106 is configured to provide extended memory for the host side 1102; the host side 1102 is configured to use the memory side 1106 as extended memory.

[0114] Through the above-mentioned memory expansion system, the M upstream ports deployed on the connector are connected to the host end through the computing fast connection protocol, and the N downstream ports deployed on the connector are connected to the memory end through the computing fast connection protocol. Since the controller realizes the control of binding between the M upstream ports and the N downstream ports, each host end connected to the upstream port can use the extended memory connected to the downstream port with which it has a mapping relationship, thereby expanding the memory for one or more host ends. Therefore, the problem of low memory capacity can be solved and the effect of expanding memory capacity can be achieved.

[0115] In an exemplary embodiment, a switching device includes: a connector and a controller, wherein M upstream ports and N downstream ports are deployed on the connector; the controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

[0116] In an exemplary embodiment, the switching device further includes: a target processor, wherein the controller includes: a structure management module and an in-band configuration port; the target processor is configured to send a target control signal to the structure management module through the in-band configuration port; the structure management module is configured to search for a target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and the target uplink port and the target downlink port are bound according to the target mapping relationship.

[0117] In an exemplary embodiment, a universal asynchronous receiver / transmitter (UATS) interface is deployed on both the target processor and the controller, wherein the target processor is configured to write corresponding control signals and mapping relationships into the controller during the initialization phase of the switching device.

[0118] In an exemplary embodiment, the target upstream ports include m upstream ports, and the target downstream ports include n downstream ports, where m is less than or equal to M, and n is less than or equal to N.

[0119] In an exemplary embodiment, M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein the first uplink port and the second uplink port are both connected to the first processor, and the third uplink port and the fourth uplink port are both connected to the second processor.

[0120] In an exemplary embodiment, N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein the first downstream port is connected to the memory expansion controller in the first memory unit, and the second downstream port is connected to the memory expansion controller in the second memory unit.

[0121] In an exemplary embodiment, Figure 12 is a schematic diagram of memory expansion in a memory expansion system according to an embodiment of the present application. As shown in Figure 12, the memory expansion system includes a host side, a switch side (switch device), and a memory side. CPU0 and CPU1 on the host side form a dual-socket server, interconnected via a CXL bus to the input interface (uplink port) of a CXL SW (switch device). The CXL SW supports multi-host connections. The CXL SW's output interface is interconnected with a memory resource pool (memory side). All CXL SW input interfaces (downlink ports) support connection to each output interface. In this way, each CXL bus of the CPU can expand more memory, significantly increasing system memory capacity and maximizing CXL port resource utilization.

[0122] In an exemplary embodiment, Figure 13 is a schematic diagram of the extended memory of a large memory expansion system according to an embodiment of the present application. As shown in Figure 13, the memory expansion system includes multiple hosts (taking the hosts including Host0 to Host7 as an example), each host can be connected to multiple switching devices (CXL SW), and the number of memory resource pools on the memory side can also increase accordingly, realizing ultra-large capacity expansion of multiple hosts, multiple switching devices, and multiple memory resource pools.

[0123] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0124] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0125] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A switching device, characterized in that: include: connector and controller, where The connector is provided with M upstream ports and N downstream ports, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; The M uplink ports are configured to connect to the host end through a computing fast connection protocol; The N downstream ports are configured to connect to a memory end through a computing fast connection protocol, wherein the memory end is an extended memory of the host end; The controller is configured to control the binding between the M upstream ports and the N downstream ports, wherein each of the upstream ports is allowed to be mapped to the N downstream ports.

2. The switching device according to claim 1, characterized in that: The controller is configured to: Obtaining a target mapping relationship between a target upstream port and a target downstream port; The target uplink port and the target downlink port are bound according to the target mapping relationship.

3. The switching device according to claim 2, characterized in that: The switching device further includes: a target processor, wherein: The controller includes: a structure management module and an in-band configuration port; The target processor is configured to send a target control signal to the fabric management module via the in-band configuration port; The structure management module is configured to search for the target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and bind the target uplink port and the target downlink port according to the target mapping relationship.

4. The switching device according to claim 3, characterized in that: The target processor and the controller are both equipped with a universal asynchronous receiver / transmitter transmission interface, wherein: The target processor is configured to write the control signals having corresponding relationships and the mapping relationships into the controller during the initialization phase of the switching device.

5. The switching device according to claim 1, characterized in that: Universal asynchronous receiver / transmitter interfaces are deployed on both the target processor and the controller. During the initialization phase of the switching device, the controller receives signals sent by the target processor through the universal asynchronous receiver / transmitter interface, thereby configuring the types of the uplink port and the downlink port of the switching device. The target processor writes the control signal and the mapping relationship with the corresponding relationship into the controller through the universal asynchronous receiver and transmitter transmission interface, and the controller receives and stores the corresponding relationship between the control signal and the mapping relationship, wherein the mapping relationship includes the corresponding relationship between the upstream port and the downstream port.

6. The switching device according to claim 2, characterized in that: The target uplink ports include m uplink ports, and the target downlink ports include n downlink ports, wherein m is less than or equal to M, and n is less than or equal to N.

7. The switching device according to claim 1, characterized in that: The M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein: The first upstream port and the second upstream port are both connected to the first processor, and the third upstream port and the fourth upstream port are both connected to the second processor.

8. The switching device according to claim 1, characterized in that: The N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein: The first downstream port is connected to a memory expansion controller in the first memory unit, and the second downstream port is connected to a memory expansion controller in the second memory unit.

9. The switching device according to claim 1, characterized in that: The uplink port of the switching device is connected to the host side through the computing fast connection protocol. The host side includes processor 0 and processor 1, and processor 0 and processor 1 are interconnected through the hyperpath interconnect bus, forming a two-way service The device acts as the host end. When one processor performs memory expansion, the other processor can obtain the extended memory through the hyperpath interconnect bus, and each processor can provide two sets of CXL x16 interfaces, which are respectively connected to the uplink port of the switching device; the downlink port of the switching device is connected to the memory expansion controller on the memory end through the computing fast connection protocol, and memory expansion is performed through the double-rate controller inside the memory expansion controller.

10. A memory expansion module, characterized in that: include: Swap devices and memory terminals, where The switching device is deployed with M uplink ports and N downlink ports, and the N downlink ports are connected to the memory end through a computing fast connection protocol, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; The M uplink ports are configured to connect to the host end through a computing fast connection protocol; The switching device is configured to control the binding between the M upstream ports and the N downstream ports, wherein each of the upstream ports is allowed to be mapped to the N downstream ports; The memory end is configured to provide extended memory for the host end.

11. The memory expansion module according to claim 10, characterized in that: The switching device comprises: a connector and a controller, wherein: The connector is provided with the M upstream ports and the N downstream ports; The controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

12. The memory expansion module according to claim 11, characterized in that: The switching device further includes: a target processor, wherein: The controller includes: a structure management module and an in-band configuration port; The target processor is configured to send a target control signal to the fabric management module via the in-band configuration port; The structure management module is configured to search for the target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and bind the target uplink port and the target downlink port according to the target mapping relationship.

13. The memory expansion module according to claim 12, characterized in that: The target processor and the controller are both equipped with a universal asynchronous receiver / transmitter transmission interface, wherein: The target processor is configured to write the control signals having corresponding relationships and the mapping relationships into the controller during the initialization phase of the switching device.

14. The memory expansion module according to claim 11, characterized in that: The target uplink ports include m uplink ports, and the target downlink ports include n downlink ports, wherein m is less than or equal to M, and n is less than or equal to N.

15. The memory expansion module according to claim 10, characterized in that: The M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein: The first upstream port and the second upstream port are both connected to the first processor, and the third upstream port and the fourth upstream port are both connected to the second processor.

16. The memory expansion module according to claim 10, characterized in that: The N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein: The first downstream port is connected to a memory expansion controller in the first memory unit, and the second downstream port is connected to a memory expansion controller in the second memory unit.

17. A memory expansion system, characterized in that: include: Host side, switch device and memory side, where: The switching device is deployed with M upstream ports and N downstream ports, the N downstream ports are connected to the memory end through a computing fast connection protocol, and the M upstream ports are connected to the host end through a computing fast connection protocol, wherein M is an integer greater than or equal to 1, and N is an integer greater than 1; The switching device is configured to control the binding between the M upstream ports and the N downstream ports, wherein each of the upstream ports is allowed to be mapped to the N downstream ports; The memory end is configured to provide extended memory for the host end; The host end is configured to use the memory end as an extended memory.

18. The memory expansion system according to claim 17, characterized in that: The switching device comprises: a connector and a controller, wherein: The connector is provided with the M upstream ports and the N downstream ports; The controller is configured to: obtain a target mapping relationship between a target upstream port and a target downstream port; and bind the target upstream port and the target downstream port according to the target mapping relationship.

19. The memory expansion system according to claim 18, characterized in that: The switching device further includes: a target processor, wherein: The controller includes: a structure management module and an in-band configuration port; The target processor is configured to send a target control signal to the fabric management module via the in-band configuration port; The structure management module is configured to search for the target mapping relationship corresponding to the target control signal from control signals and mapping relationships having corresponding relationships; and bind the target uplink port and the target downlink port according to the target mapping relationship.

20. The memory expansion system according to claim 19, characterized in that: The target processor and the controller are both equipped with a universal asynchronous receiver / transmitter transmission interface, wherein: The target processor is configured to write the control signals having corresponding relationships and the mapping relationships into the controller during the initialization phase of the switching device.

21. The memory expansion system according to claim 18, characterized in that: The target uplink ports include m uplink ports, and the target downlink ports include n downlink ports, wherein m is less than or equal to M, and n is less than or equal to N.

22. The memory expansion system according to claim 17, wherein: The M uplink ports include: a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, and the host end includes: a first processor and a second processor, wherein: The first upstream port and the second upstream port are both connected to the first processor, and the third upstream port and the fourth upstream port are both connected to the second processor.

23. The memory expansion system according to claim 17, characterized in that: The N downstream ports include: a first downstream port and a second downstream port, and the memory end includes: a first memory unit and a second memory unit, wherein: The first downstream port is connected to a memory expansion controller in the first memory unit, and the second downstream port is connected to a memory expansion controller in the second memory unit.

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