Data access apparatus, system and method for SRAM array, device, chip, and medium

Abstract

A data access apparatus, system and method for an SRAM array, a device, a chip, and a medium. The apparatus comprises: M arbitration modules, each arbitration module being coupled to one of M SRAM groups; and a parsing module coupled to the M arbitration modules, and used for receiving N data access requests in parallel, parsing out at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and sending the access command to an arbitration module coupled to an SRAM group to which the access command points, wherein each arbitration module is used for, when determining that a single access command pointing to a corresponding SRAM group is received, sending to the corresponding SRAM group the access command pointing to the corresponding SRAM group, so that the access command is executed by the corresponding SRAM group; M is a positive integer greater than or equal to 2, and N is a positive integer. A plurality of SRAM groups are accessed in parallel, thereby improving access efficiency and solving access conflict problems.

Description

Data access device, system, method, equipment, chip and medium for SRAM array

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 5, 2023, with application number 202311133321.4 and application name “Data access device, system, method, equipment, chip and medium for SRAM array”. The entire contents of the application are incorporated by reference into this application. Technical Field

[0002] The present invention belongs to the field of data storage, and in particular to a data access device, system, method, equipment, chip and medium for a static random access memory (SRAM) array. Background Art

[0003] SRAM is a commonly used storage device in chip design. Due to limitations in the SRAM manufacturing process, the capacity of a single SRAM block is typically limited. System-on-a-chip (SOC) designs require large amounts of SRAM space, often using SRAM arrays containing multiple SRAM blocks to achieve large storage capacities.

[0004] Currently, for an SRAM array including multiple SRAM groups, when one SRAM group in the SRAM array is accessed, the other SRAM groups are in an idle state and inaccessible (not readable or writable), resulting in low access efficiency.

[0005] Summary of the Invention

[0006] The embodiments of the present invention provide a data selection device for an SRAM array, a storage system, and a system-on-chip.

[0007] The technical solutions of the embodiments of the present invention are as follows:

[0008] A data access device for an SRAM array, wherein the SRAM array includes M SRAM groups, the device comprising:

[0009] M arbitration modules, each arbitration module coupled to one of the M SRAM banks;

[0010] a parsing module coupled to the M arbitration modules and configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and directed to an SRAM group, and send the access command to the arbitration module coupled to the directed SRAM group;

[0011] wherein each arbitration module is configured to, when determining that the received access command directed to the corresponding SRAM group is single, send the access command directed to the corresponding SRAM group to the corresponding SRAM group, so that the access command is executed by the corresponding SRAM group;

[0012] Wherein, M is a positive integer greater than or equal to 2, and N is a positive integer.

[0013] A data access system for an SRAM array, comprising:

[0014] An SRAM array, wherein the SRAM array includes a plurality of SRAM groups, and each SRAM group includes a plurality of SRAMs;

[0015] M arbitration modules, each arbitration module coupled to one of the M SRAM banks;

[0016] a parsing module coupled to the M arbitration modules and configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and directed to a corresponding SRAM group, and send the access command to the arbitration module coupled to the directed SRAM group;

[0017] wherein each arbitration module is configured to, when determining that a single access command is received, send the received access command to a corresponding SRAM group so that the corresponding SRAM group executes the received access command;

[0018] Wherein, M is a positive integer greater than or equal to 2, and N is a positive integer.

[0019] A system-on-chip comprises the data access device of the SRAM array as described in any one of the above items or the data access system of the SRAM array as described in any one of the above items.

[0020] A data access method for an SRAM array, wherein the SRAM array includes M SRAM groups, the method comprising:

[0021] Receive N data access requests;

[0022] Parsing at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group;

[0023] For the access command pointing to each SRAM group, arbitration processing is performed, including: when it is determined that the access command pointing to the corresponding SRAM group is single, the access command pointing to the corresponding SRAM group is sent to the corresponding SRAM group so that the access command is executed by the corresponding SRAM group; where M is a positive integer greater than or equal to 2, and N is a positive integer.

[0024] An electronic device, comprising:

[0025] Memory;

[0026] processor;

[0027] The memory stores an application program executable by the processor, which is used to enable the processor to execute the data access method of the SRAM array as described in any one of the above items.

[0028] A computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, cause the processor to execute any one of the above methods for accessing data in an SRAM array.

[0029] It can be seen from the above technical solution that in an embodiment of the present invention, multiple data access requests are received in parallel, and each data access request is parsed to send access commands to arbitration modules coupled to the SRAM groups they point to, thereby realizing parallel processing of multiple data access requests, and multiple SRAM groups can be accessed in parallel, thereby improving the access efficiency of the SRAM array. The conflict problem of read commands and write commands accessing the same SRAM group at the same time can also be resolved based on the arbitration module. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of accessing an SRAM array in the related art.

[0031] FIG. 2 is an exemplary structural diagram of a data access device for an SRAM array according to an embodiment of the present invention.

[0032] FIG3 is an exemplary structural diagram of input and output ports of an arbitration module according to an embodiment of the present invention.

[0033] FIG. 4 is an exemplary structural diagram of a data access method for an SRAM array according to an embodiment of the present invention.

[0034] FIG5 is a diagram showing an exemplary structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0036] For the sake of brevity and intuitiveness in description, the solution of the present invention is explained below by describing several representative implementations. A large number of details in the implementations are only used to help understand the solution of the present invention. However, it is obvious that the technical solution of the present invention may not be limited to these details when implemented. In order to avoid unnecessarily obscuring the solution of the present invention, some implementations are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0037] Figure 1 is a schematic diagram of accessing an SRAM array in the related art. An SRAM array typically includes multiple SRAM groups, each of which contains multiple SRAMs. The SRAM array shown in Figure 1 includes M SRAM groups, namely SRAM Group 1, SRAM Group 2, SRAM Group 3, and SRAM Group M. Each SRAM group contains p SRAMs. Therefore, the SRAM array contains a total of M*p SRAMs. Where M is a positive integer greater than or equal to 2, and p is a positive integer.

[0038] In some embodiments, an SRAM bank is the target of a data access request in technical practice. At a given moment, the SRAM array can only process one data access request (a data access request includes either a read command or a write command, but not both). Based on this data access request, only one SRAM bank in the SRAM array is accessed, and other SRAM banks cannot be accessed simultaneously.

[0039] For example, assume that a data access party (e.g., a host) needs to read data from SRAM bank 1 in an SRAM array. The data access party sends a read command to the SRAM array with SRAM bank 1 as the destination address. In response to the read command, the SRAM array returns the data in SRAM bank 1 to the data access party. However, when data access to at least two SRAM banks in the SRAM array needs to be performed simultaneously (i.e., in parallel) (e.g., a request to read data from SRAM bank 1 and write data to SRAM bank 2 in parallel), the related art cannot access multiple SRAM banks in parallel.

[0040] To address the aforementioned issues, the applicant considered sending a read command with SRAM bank 1 as the destination address and a write command with SRAM bank 2 as the destination address in parallel to the SRAM array. However, the applicant further discovered that, because the SRAM array lacks a mechanism for collaboratively processing multiple parallel data access requests, this simple solution of sending multiple data access requests in parallel to the SRAM array does not enable parallel access to multiple SRAM banks.

[0041] An embodiment of the present invention proposes a technical solution for data access to an SRAM array, receives multiple data access requests, parses each data access request and sends access commands to arbitration modules coupled to the SRAM groups to which they are directed, thereby realizing parallel processing of multiple data access requests and parallel access to multiple SRAM groups, thereby improving the access efficiency of the SRAM array.

[0042] FIG2 is an exemplary structural diagram of a data access device for an SRAM array according to an embodiment of the present invention. The SRAM array shown in FIG2 includes M SRAM groups, namely, SRAM group 1, SRAM group 2, SRAM group 3, and SRAM group M. Each SRAM group includes p SRAMs. Therefore, the SRAM array includes a total of M*p SRAMs. The data access device includes:

[0043] M arbitration modules corresponding to the M SRAM banks, wherein each arbitration module is coupled to one of the M SRAM banks;

[0044] A parsing module coupled to M arbitration modules is used to receive N data access requests in parallel, parse at least one access command from each data access request, each access command is a read command or a write command, and points to an SRAM group, and send the access command to the arbitration module coupled to the pointed SRAM group.

[0045] Each of the M arbitration modules is configured to, when determining that a received access command directed to the corresponding SRAM group is single, send the access command directed to the corresponding SRAM group to the corresponding SRAM group so that the access command is executed by the corresponding SRAM group; wherein M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1.

[0046] In one optional embodiment, the M arbitration modules may be integrated into an overall arbitration unit, which corresponds to the M SRAM groups and handles access arbitration for the M SRAM groups as a whole. In another optional embodiment, a portion of the M arbitration modules may be integrated into one or more arbitration units (the specific number may depend on the specific integration strategy), while the remaining arbitration modules remain functionally independent. In this case, the one or more integrated arbitration units handle access arbitration for the SRAM groups corresponding to the one or more arbitration units as a whole, while the remaining arbitration modules continue to independently handle access arbitration for the SRAM groups corresponding to the remaining arbitration modules.

[0047] It can be seen that parallel processing of multiple data access requests is achieved, multiple SRAM groups can be accessed in parallel, and the access efficiency of the SRAM array is improved.

[0048] In one embodiment, the parsing module can receive N data access requests in parallel from a full-duplex data transmission bus; wherein the full-duplex data transmission bus includes at least one of the following: AXI-Lite; AXI-Full; and AXI-Stream. AXI-Lite and AXI-Full both implement data transmission based on memory mapping (i.e., including an address bus), while AXI-Stream implements data transmission in the form of a data stream without an address bus. AXI-Lite is a simplified version of AXI-Full, suitable for small-batch data transmission and is often used for command transmission; AXI-Full is suitable for large-batch, high-performance data transmission.

[0049] The above exemplary descriptions are of a typical example of a full-duplex data transmission bus. Those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the embodiments of the present invention.

[0050] In one embodiment, each data access request may include at least one access command. For example, a data access request may include both a write command and a read command, wherein the destination SRAM group of the write command and the destination SRAM group of the read command may be the same or different.

[0051] Example 1: Data Access Request 1 in Figure 2 can include both a write command and a read command. The write command's destination SRAM bank is SRAM bank 1, meaning the write command is directed to SRAM bank 1. The read command's destination SRAM bank is SRAM bank 2, meaning the read command is directed to SRAM bank 2. In other words, Data Access Request 1 indicates a write operation for SRAM bank 1 and a read operation for SRAM bank 2.

[0052] Example 2: Data Access Request 1 in Figure 2 includes both a write command and a read command. The write command's destination SRAM bank is SRAM Bank 1, meaning the write command is directed to SRAM Bank 1. The read command's destination SRAM bank is SRAM Bank 1, meaning the read command is directed to SRAM Bank 1. In other words, Data Access Request 1 indicates a write operation is initiated for SRAM Bank 1, and a read operation is initiated for SRAM Bank 1. In this case, the presence of both a read and a write command for the same SRAM bank typically results in a conflict, which can be resolved by the arbitration mechanism of the arbitration module described in detail later.

[0053] In one embodiment, the data access request may include only one of a write command and a read command.

[0054] Example 1: Data access request 2 in FIG2 only includes a write command, where the destination SRAM group of the write command is SRAM group 1. That is, data access request 2 indicates that a write operation is initiated for SRAM group 1.

[0055] Example 2: Data access request 2 in FIG2 only includes a read command, wherein the destination SRAM group of the read command is SRAM group 2. That is, data access request 2 indicates that a read operation is initiated for SRAM group 2.

[0056] The parsing module parses at least one access command in each data access request from N data access requests, each access command being a read command or a write command, and then sends the access command to an arbitration module coupled to the SRAM group pointed to by the access command.

[0057] For example: Assume that the parsing module receives four data access requests, namely data access request 1, data access request 2, data access request 3, and data access request 4.

[0058] The data access request 1 includes: (1) a write command 1 with SRAM group 1 as the destination SRAM group; and (2) a read command 1 with SRAM group 2 as the destination SRAM group.

[0059] The data access request 2 includes: (1) a write command 2 to the SRAM group with the SRAM group 3 as the destination.

[0060] The data access request 3 includes: (1) a write command 3 with SRAM group 4 as the destination SRAM group; and (2) a read command 2 with SRAM group 5 as the destination SRAM group.

[0061] The data access request 4 includes: (1) a write command 4 with SRAM group 6 as the destination SRAM group; and (2) a read command 3 with SRAM group 7 as the destination SRAM group.

[0062] The parsing module sends the write command 1 (with SRAM group 1 as the destination SRAM group) to the arbitration module 1 corresponding to SRAM group 1; sends the read command 1 (with SRAM group 2 as the destination SRAM group) to the arbitration module 2 corresponding to SRAM group 2; sends the write command 2 (with SRAM group 3 as the destination SRAM group) to the arbitration module 3 corresponding to SRAM group 3; sends the write command 3 (with SRAM group 4 as the destination SRAM group) to the arbitration module 4 corresponding to SRAM group 4; sends the read command 2 (with SRAM group 5 as the destination SRAM group) to the arbitration module 5 corresponding to SRAM group 5; sends the write command 4 (with SRAM group 6 as the destination SRAM group) to the arbitration module 6 corresponding to SRAM group 6; and sends the read command 3 (with SRAM group 7 as the destination SRAM group) to the arbitration module 7 corresponding to SRAM group 7.

[0063] Each arbitration module from arbitration module 1 to arbitration module 7 determines that the received access command directed to the corresponding SRAM bank is a single one. For example, each module determines that there are no simultaneous write and read commands. Therefore, each arbitration module can send its own write or read command to its corresponding SRAM bank, allowing multiple SRAM banks to execute multiple commands in parallel. Specifically, SRAM bank 1 executes write command 1; SRAM bank 2 executes read command 1; SRAM bank 3 executes write command 2; SRAM bank 4 executes write command 3; SRAM bank 5 executes read command 2; SRAM bank 6 executes write command 4; and SRAM bank 7 executes read command 3, thereby enabling parallel access to the seven SRAM banks in the SRAM array.

[0064] The above describes an exemplary example in which the arbitration module does not receive both a read command and a write command from the parsing module. In practice, based on the specific configuration of the data access request, the arbitration module may also receive both a read command and a write command from the parsing module, resulting in a read-write conflict.

[0065] In one embodiment, each arbitration module is configured to, when it is determined that the received access commands directed to the corresponding SRAM group are at least two commands, determine an execution order for the at least two access commands received based on a predetermined arbitration strategy, and send the at least two access commands to the corresponding SRAM group in sequence according to the execution order, so that the at least two access commands are sequentially executed by the corresponding SRAM group. For example, when it is determined that there are both a read command with the corresponding SRAM group as the destination and a write command with the corresponding SRAM group as the destination, arbitration is performed on the read command with the corresponding SRAM group as the destination and the write command with the corresponding SRAM group as the destination based on the predetermined arbitration strategy to obtain an arbitration result indicating the execution order. Based on the arbitration result, an access command (e.g., a read command with the corresponding SRAM group as the destination or a write command with the corresponding SRAM group as the destination) is first sent to the corresponding SRAM group, so that the corresponding SRAM group executes the read command with the corresponding SRAM group as the destination or the write command with the corresponding SRAM group as the destination. Then, after one access command is executed, the arbitration module sends another access command to the corresponding SRAM group.

[0066] When the arbitration module receives two access commands simultaneously from the parsing module, for example, a read command and a write command, it can determine the execution order based on a predetermined arbitration strategy, for example, by selecting a specific command to be executed first. Thus, embodiments of the present invention can resolve conflicts caused by read and write commands accessing the same SRAM bank simultaneously by performing arbitration based on the arbitration module.

[0067] Typically, to ensure logical consistency, the arbitration strategies used in each arbitration module are the same. However, the arbitration strategies used in each arbitration module may also be different.

[0068] Preferably, the arbitration strategy includes:

[0069] (1) Polling execution strategy;

[0070] (2) Read command priority strategy;

[0071] (3) Write command priority strategy;

[0072] (4) Time-sharing strategy.

[0073] In a round-robin execution strategy, read and write commands are executed in a round-robin fashion, meaning they are executed alternately. For example, when a read command and a write command are received simultaneously for the first time, the execution order is: execute the write command first, then execute the read command; when a read command and a write command are received simultaneously for the second time, the execution order is: execute the read command first, then execute the write command; when a read command and a write command are received simultaneously for the third time, the execution order is: execute the write command first, then execute the read command; and when a read command and a write command are received simultaneously for the fourth time, the execution order is: execute the read command first, then execute the write command. For another example, when the arbitration module receives two access commands (a read command and a write command) simultaneously from the parsing module, if the corresponding SRAM group most recently executed a read command (i.e., the last time a read command was executed), the execution order for the two access commands received this time is: execute the write command first, then execute the read command. If the corresponding SRAM group most recently executed a write command (i.e., the last time a write command was executed), the execution order for the two access commands received this time is: execute the read command first, then execute the write command. In a read-command priority strategy, read commands are prioritized. In a write-command priority strategy, write commands are prioritized. In a time-sharing strategy, commands are processed based on time periods. For example, the first time period processes only read commands, while the next time period processes write commands; or, the first time period processes only write commands, while the next time period processes read commands, and so on.

[0074] The above exemplary descriptions are typical examples of arbitration strategies. Those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the scope of protection of the embodiments of the present invention.

[0075] For example: Assume that the parsing module receives four data access requests, namely data access request 1, data access request 2, data access request 3, and data access request 4.

[0076] The data access request 1 includes: (1) a write command 1 with SRAM group 1 as the destination SRAM group; and (2) a read command 1 with SRAM group 2 as the destination SRAM group.

[0077] The data access request 2 includes: (1) a read command 2 of the SRAM group with the SRAM group 1 as the destination.

[0078] The data access request 3 includes: (1) a write command 2 with SRAM group 4 as the destination SRAM group; and (2) a read command 3 with SRAM group 5 as the destination SRAM group.

[0079] The data access request 4 includes: (1) a write command 3 with SRAM group 6 as the destination SRAM group; and (2) a read command 4 with SRAM group 7 as the destination SRAM group.

[0080] The parsing module sends the write command 1 and the read command 2 (both with SRAM group 1 as the destination SRAM group) to the arbitration module 1 corresponding to SRAM group 1; sends the read command 1 (with SRAM group 2 as the destination SRAM group) to the arbitration module 2 corresponding to SRAM group 2; sends the write command 2 (with SRAM group 4 as the destination SRAM group) to the arbitration module 4 corresponding to SRAM group 4; sends the read command 3 (with SRAM group 5 as the destination SRAM group) to the arbitration module 5 corresponding to SRAM group 5; sends the write command 3 (with SRAM group 6 as the destination SRAM group) to the arbitration module 6 corresponding to SRAM group 6; and sends the read command 4 (with SRAM group 7 as the destination SRAM group) to the arbitration module 7 corresponding to SRAM group 7.

[0081] Arbitration module 2, arbitration module 4, arbitration module 5, arbitration module 6, and arbitration module 7 all determine that they do not receive write commands and read commands at the same time (i.e., they do not receive write commands and read commands at the same time, but only receive one access command). Therefore, they can execute their respective write commands or read commands, thereby each accessing the five corresponding SRAM groups in the SRAM array in parallel.

[0082] Arbitration module 1 determines that it has both a write command and a read command (write command 1 and read command 2). It performs arbitration based on a predetermined arbitration strategy (assuming a read command priority strategy). The arbitration result is: read command 2 is executed first to read data from SRAM group 1. After read command 2 is executed, write command 1 is executed to write data to SRAM group 1. Therefore, arbitration module 1 first sends read command 2 to SRAM group 1 to read data from SRAM group 1, and then arbitration module 1 sends write command 1 to SRAM group 1 to write data to SRAM group 1.

[0083] In one embodiment, the read command includes a first group of selection signals and a read control instruction. The first group of selection signals is used to select a corresponding SRAM group in a read operation, and the read control instruction is used to read data from the corresponding SRAM group. For example, the read control instruction may include: (1) an SRAM chip select enable signal in the SRAM group, used to select an SRAM from the SRAM group; (2) an SRAM read enable signal, used to enable a read operation of the SRAM; and (3) a read address in the SRAM.

[0084] In one embodiment, the write command includes a second group of selection signals and a write control instruction. The second group of selection signals is used to select the corresponding SRAM group in the write operation, and the write control instruction is used to write data in the corresponding SRAM group. For example, the write control instruction may include: (1) an SRAM chip select enable signal in the SRAM group, used to select the SRAM from the SRAM group; (2) an SRAM write enable signal, used to enable the write operation of the SRAM; and (3) a write address in the SRAM.

[0085] Based on the above specific command types, the embodiment of the present invention further proposes an input and output port structure of an arbitration module.

[0086] FIG3 is an exemplary structural diagram of input and output ports of an arbitration module according to an embodiment of the present invention.

[0087] As shown in FIG3 , the input and output ports of the arbitration module include: a read command group selection signal input terminal for receiving a first group selection signal; a read control instruction input terminal for receiving a read control instruction; an arbitration strategy input terminal for receiving an arbitration strategy selection signal; a write command group selection signal input terminal for receiving a second group selection signal; a write control instruction input terminal for receiving a write control instruction; a command output terminal for sending a read control instruction or a write control instruction to the corresponding SRAM group; a read status indication signal output terminal for outputting a read status indication signal to the corresponding SRAM group; and a write status indication signal output terminal for outputting a write status indication signal to the corresponding SRAM group. The read status indication signal is used to indicate whether the SRAM group is in a readable state. For example, when the read status indication signal is at a high level, it indicates that the SRAM group is in a readable state. The write status indication signal is used to indicate whether the SRAM group is in a writable state. For example, when the write status indication signal is at a high level, it indicates that the SRAM group is in a writable state.

[0088] The data access device and data access system of the SRAM array can be applied to a system-on-chip. The embodiment of the present invention further provides a system-on-chip, comprising the data access system or the data access device of the SRAM array as described above.

[0089] It should be noted that the embodiments of the present application can use hardware description language to implement the business logic performed by the data access device as a specific hardware circuit. For example, the embodiments of the present application can utilize the code of the business logic described by the register transfer level (RTL) to implement a data access chip (i.e., the hardware circuit structure of the data access device) in a field programmable gate array (FPGA). For another example, the embodiments of the present application can implement the code of the business logic described by the RTL as an application specific integrated circuit (ASIC) chip (i.e., the hardware circuit structure of the data access device). It can be seen from this that, based on the business logic of the data access device described in the embodiments of Figures 2 and 3, those skilled in the art can undoubtedly implement the specific circuit structure of the data access device through hardware description language. Therefore, the specific structure of the data access device of the embodiments of the present application can be implemented as an FPGA or ASIC chip. Accordingly, the arbitration module and the parsing module can be implemented as the corresponding circuit structure in the FPGA or ASIC. Figure 4 is an exemplary structural diagram of the data access method of the SRAM array according to the embodiment of the present invention. As shown in Figure 4, the method includes:

[0090] Step 401: Receive N data access requests.

[0091] Step 402: parse at least one access command from each data access request, where each access command is a read command or a write command and points to an SRAM group.

[0092] Step 403: Perform arbitration processing for the access command pointing to each SRAM group, including: when it is determined that the access command pointing to the corresponding SRAM group is single, send the access command pointing to the corresponding SRAM group to the corresponding SRAM group so that the access command is executed by the corresponding SRAM group; where M is a positive integer greater than or equal to 2, and N is a positive integer.

[0093] In one embodiment, the data access method of the present application can be executed in an FPGA, an ASIC, or an electronic device.

[0094] In one embodiment, performing the arbitration process includes:

[0095] When it is determined that the access commands directed to the corresponding SRAM group are at least two access commands, determining an execution order of the at least two access commands based on a predetermined arbitration strategy;

[0096] The at least two access commands are sent to corresponding SRAM groups in sequence according to the execution order, so that the corresponding SRAM groups execute the at least two access commands in sequence.

[0097] Figure 5 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. Electronic device 500 includes: a processor 501 and a memory 502. Processor 501 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 501 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). Processor 501 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, processor 501 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, processor 501 may also include an AI processor, which is used to handle computing operations related to machine learning. For example, the AI ​​processor can be implemented as a neural network processor.

[0098] The memory 502 may include one or more computer-readable storage media, which may be non-transitory, and may also include high-speed random access memory and non-volatile memory, such as one or more magnetic disk storage devices and flash memory storage devices.

[0099] In some embodiments, the non-transitory computer-readable storage medium in the memory 502 is used to store at least one instruction, and the at least one instruction is used to be executed by the processor 501 to implement the data access method of the SRAM array provided in various embodiments of the present disclosure.

[0100] The above are only preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data access device for an SRAM array, wherein the SRAM array comprises M SRAM groups, characterized in that: The device comprises: M arbitration modules, each arbitration module coupled to one of the M SRAM groups; a parsing module coupled to the M arbitration modules, configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and send the access command to the arbitration module coupled to the pointed SRAM group; Each arbitration module is used for sending the access command directed to the corresponding SRAM group to the corresponding SRAM group when determining that the received access command directed to the corresponding SRAM group is single, so that the access command is executed by the corresponding SRAM group; Wherein M is a positive integer greater than or equal to 2, and N is a positive integer.

2. The device according to claim 1, characterized in that Each arbitration module is also used to determine the execution order of the at least two received access commands based on a predetermined arbitration strategy when it is determined that the received access commands pointing to the corresponding SRAM group are at least two commands, and send the at least two access commands to the corresponding SRAM group in sequence according to the execution order, so that the corresponding SRAM group executes the at least two access commands in sequence.

3. The device according to claim 1, characterized in that The arbitration strategy includes at least one of the following: Polling execution strategy; Read command priority strategy; Write command priority strategy; Time-sharing strategy.

4. The device according to claim 1, characterized in that The parsing module is further configured to receive the N data access requests in parallel from a full-duplex data transmission bus; wherein the full-duplex data transmission bus includes at least one of the following: Advanced Extensible Interface Protocol-Simplified Edition; Advanced Extensible Interface Protocol-Full Edition; Advanced Extensible Interface Protocol-Data Stream Edition.

5. The device according to any one of claims 1 to 4, characterized in that The read command includes a first group of selection signals and a read control instruction, wherein the first group of selection signals is used to select a corresponding SRAM group in a read operation, and the read control instruction is used to read data in the corresponding SRAM group; The write command includes a second group of selection signals and a write control instruction, wherein the second group of selection signals is used to select a corresponding SRAM group in a write operation, and the write control instruction is used to write data in the corresponding SRAM group; The arbitration module comprises: A read command group selection signal input terminal, used for receiving the first group selection signal; A read control instruction input terminal, used for receiving the read control instruction; An arbitration strategy input terminal, used for receiving an arbitration strategy selection signal; A write command group selection signal input terminal, used for receiving the second group selection signal; A write control instruction input terminal, used for receiving the write control instruction; A command output terminal is used to send a read control instruction or a write control instruction to a corresponding SRAM group; A read status indication signal output terminal, used to output a read status indication signal to a corresponding SRAM group; The write status indication signal output terminal is used to output the write status indication signal to the corresponding SRAM group.

6. A data access system for an SRAM array, comprising: An SRAM array, wherein the SRAM array comprises a plurality of SRAM groups, and each SRAM group comprises a plurality of SRAMs; M arbitration modules, each arbitration module coupled to one of the M SRAM groups; a parsing module coupled to the M arbitration modules, configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and send the access command to the arbitration module coupled to the pointed SRAM group; Each arbitration module is used for sending the access command directed to the corresponding SRAM group to the corresponding SRAM group when determining that the received access command directed to the corresponding SRAM group is single, so that the access command is executed by the corresponding SRAM group; Wherein M is a positive integer greater than or equal to 2, and N is a positive integer.

7. The system according to claim 6, characterized in that Each arbitration module is also used to determine the execution order of the at least two received access commands based on a predetermined arbitration strategy when it is determined that the received access commands pointing to the corresponding SRAM group are at least two commands, and send the at least two access commands to the corresponding SRAM group in sequence according to the execution order, so that the corresponding SRAM group executes the at least two access commands in sequence.

8. A system-on-chip, characterized in that: A data access device for an SRAM array as claimed in any one of claims 1 to 5 or a data access system for an SRAM array as claimed in any one of claims 6 to 7.

9. A data access method of an SRAM array, wherein the SRAM array comprises M SRAM groups, characterized in that: The method comprises: Receive N data access requests; Parsing at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group; For the access command pointing to each SRAM group, arbitration processing is performed, including: when it is determined that the access command pointing to the corresponding SRAM group is single, the access command pointing to the corresponding SRAM group is sent to the corresponding SRAM group so that the access command is executed by the corresponding SRAM group; wherein M is a positive integer greater than or equal to 2, and N is a positive integer.

10. The method according to claim 9, characterized in that The execution arbitration process also includes: When it is determined that the access commands directed to the corresponding SRAM group are at least two access commands, determining an execution order of the at least two access commands based on a predetermined arbitration strategy; The at least two access commands are sent to the corresponding SRAM group in sequence according to the execution order, so that the corresponding SRAM group executes the at least two access commands in sequence.

11. An electronic device, characterized in that: include: Memory; processor; The memory stores an application program executable by the processor, which is used to enable the processor to execute the data access method of the SRAM array according to any one of claims 9 to 10.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the processor executes the data access method for the SRAM array according to any one of claims 9 to 10.

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