Memory expansion device, and data processing method and system

Abstract

Embodiments of the present application relate to the field of computer technology, and disclose a memory expansion device, and a data processing method and system, capable of improving the execution efficiency of computing tasks on a host side. The memory expansion device comprises: a protocol controller, used for communicating with a host side and receiving a target data request sent by the host side; an elastic compute manager, used for switching the processing mode of a processing core on the basis of the target data request; and the processing core, used for executing, by means of different data processing paths on the basis of different processing modes the processing core is in, data processing operations on target data associated with the target data request, and submitting the processed target data to a memory, or forwarding the processed target data to the host side by means of a protocol controller, wherein the different data processing paths at least comprise corresponding data processing paths for performing data processing operations on the target data in an online processing mode and / or an offline processing mode.

Description

Memory expansion device and data processing method and system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 5, 2023, with application number 202311133879.2, entitled “A memory expansion device and data processing method and system”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a memory expansion device and a data processing method and system. Background Art

[0004] As computer systems have an increasing demand for memory capacity, memory expansion technology is widely used in computer systems to meet their memory capacity requirements.

[0005] However, when the host side performs computing tasks, it needs to access the memory multiple times, but the access latency of the host side to the expanded memory device is usually high, resulting in reduced execution efficiency of the computing tasks on the host side after the memory is expanded.

[0006] Summary of the Invention

[0007] The purpose of the embodiments of the present application is to provide a memory expansion device and a data processing method and system, which can improve the execution efficiency of computing tasks on the host side after memory expansion.

[0008] To solve the above technical problems, in a first aspect, an embodiment of the present application provides a memory expansion device, which includes a processing core, a protocol controller, an elastic computing manager, and a memory. The protocol controller is used to connect to the host side, the processing core is connected to the protocol controller, the elastic computing manager, and the memory respectively, and the protocol controller is connected to the elastic computing manager, wherein:

[0009] The protocol controller is used to communicate with the host and receive target data requests from the host;

[0010] The elastic computing manager is used to switch the processing mode of the processing core according to the target data request;

[0011] The processing core is used to perform data processing operations on the target data associated with the target data request through different data processing paths according to the different processing modes in which it is located, and submit the processed target data to the memory or forward it to the host side through the protocol controller;

[0012] The different data processing paths include at least: data processing paths respectively corresponding to performing data processing operations on target data in an online processing manner and / or an offline processing manner.

[0013] In a second aspect, an embodiment of the present application further provides a data processing system, the system including a host side and a memory expansion device as in the first aspect, wherein the host side is connected to the memory expansion device.

[0014] In a third aspect, an embodiment of the present application further provides a data processing method, which is applied to the memory expansion device of the first aspect, and the method includes:

[0015] The protocol controller receives the target data request sent by the host;

[0016] The elastic computing manager switches the processing mode of the processing core according to the target data request;

[0017] The processing core performs data processing operations on the target data associated with the target data request through the data processing path corresponding to its own processing mode, and submits the processed target data to the memory or forwards it to the host through the protocol controller;

[0018] The data processing path includes at least: data processing paths corresponding to respective data processing operations performed on target data in an online processing manner and / or an offline processing manner.

[0019] It can be seen from the above technical solution that by setting a processing core between the protocol controller and the memory inside the memory expansion device, the elastic computing manager controls the processing core through different data processing paths to perform the data processing operations required for different computing tasks, thereby realizing a universal memory expansion device that supports programmable inline computing functions, which can meet the computing requirements of different computing tasks. As a result, part of the host-side calculations can be offloaded to the memory expansion device, and the memory access and data processing operations related to the computing tasks are performed inside the memory expansion device, so that a large number of high-latency memory accesses between the host and the memory expansion device involved in the host's execution of computing tasks are replaced by low-latency accesses inside the memory expansion device, thereby reducing the total latency of the host's execution of computing tasks and improving the host's execution efficiency of computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] FIG1 is a schematic structural diagram of a memory expansion device provided in an embodiment of the present application;

[0022] FIG2 is a schematic diagram of a data processing path provided in an embodiment of the present application;

[0023] FIG3 is a schematic diagram of another data processing path provided in an embodiment of the present application;

[0024] FIG4 is a schematic diagram of another data processing path provided in an embodiment of the present application;

[0025] FIG5 is a schematic diagram of another data processing path provided in an embodiment of the present application;

[0026] FIG6 is a schematic diagram of another data processing path provided in an embodiment of the present application;

[0027] FIG7 is a schematic diagram of the structure of a processing engine provided in an embodiment of the present application;

[0028] FIG8 is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0029] FIG9 is a schematic structural diagram of another memory expansion device provided in an embodiment of the present application;

[0030] FIG10 is a schematic diagram of the structure of a data processing system provided in an embodiment of the present application;

[0031] FIG11 is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0032] FIG12 is a schematic diagram of a computer non-volatile readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the accompanying drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0035] Currently, the following two methods are commonly used to expand the memory capacity of the host side that performs computing tasks in a computer system:

[0036] 1. Use large-capacity Dual-Inline-Memory-Modules (DIMMs) and use all DIMM slot channels on the host to increase memory capacity;

[0037] 2. Use high-speed interconnect interfaces on the host side to achieve memory expansion, such as the Compute Express Link (CXL) interface and the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface.

[0038] Understandably, memory expansion lengthens the host's memory access link, resulting in higher access latency for the expanded memory devices. This is especially true for memory devices extended via high-speed interconnect protocols like CXL. For example, since CXL introduces the concept of switching to support memory resource pooling, the host's access link to these devices becomes even longer, leading to higher access latency. For example, the host's access latency to CXL memory devices includes the protocol's fixed latency, the switch's hardware path latency, and software latency.

[0039] When the host side performs a computing task, a typical computing process includes four processes: loading instructions, loading data, arithmetic and logic unit (ALU) calculation, and writing data. That is, one computing process may require 3 to 4 memory accesses. Therefore, for a computing task that requires N iterations of the above computing process, the host side requires 3N memory accesses to complete all the computing processes involved in the computing task. Assuming that the latency of each memory access is L, the total latency of the memory access involved in the host side executing the computing task is 3NL. If the latency of the host side performing ALU calculations remains unchanged, if the host side performs memory expansion, L will increase, that is, the total latency of the memory access involved in the host side executing the computing task will increase, resulting in an increase in the total latency of the host side executing the computing task, which in turn leads to a decrease in the efficiency of the host side in executing the computing task after the memory expansion.

[0040] In response to the problems existing in the above-mentioned related technologies, the present application proposes a memory expansion device with programmable inline computing function, which can offload part of the host-side calculations to the memory expansion device to reduce the number of times the host accesses the memory expansion device, thereby reducing the total delay of the host-side in executing computing tasks and improving the host-side's execution efficiency of computing tasks after memory expansion.

[0041] The following describes in detail a memory expansion device provided in an embodiment of the present application through some embodiments and their application scenarios in conjunction with the accompanying drawings.

[0042] In the first aspect, referring to FIG1 , a memory expansion device is provided in an embodiment of the present application. The memory expansion device includes a processing core, a protocol controller, an elastic computing manager, and a memory. The protocol controller is used to connect to the host side. The processing core is respectively connected to the protocol controller, the elastic computing manager, and the memory. The protocol controller is connected to the elastic computing manager, wherein:

[0043] The protocol controller is used to communicate with the host and receive target data requests from the host;

[0044] The elastic computing manager is used to switch the processing mode of the processing core according to the target data request;

[0045] The processing core is used to perform data processing operations on the target data associated with the target data request through different data processing paths according to the different processing modes in which it is located, and submit the processed target data to the memory or forward it to the host side through the protocol controller;

[0046] The different data processing paths include at least: data processing paths corresponding to data processing operations performed on target data in an online processing mode and / or an offline processing mode; the target data request may include at least one of a read request and a write request associated with the computing task; the above-mentioned memory expansion device supports programmable inline computing functions. The user can pre-configure the corresponding computing flow for the processing core through the elastic computing manager based on the computing task to be performed by the host side, so that the processing core can perform some operations on the data on behalf of the host side. For example, the host side can configure the elastic computing manager through the instruction bus of the protocol controller. The configuration parameters include the computing parameters required for the processing core to perform data processing operations. During execution, the elastic computing manager controls the processing mode of the processing core to control the processing core's participation in the computing task (i.e., control the processing core to perform data processing operations associated with the computing task using different data processing paths). The protocol controller (such as the CXL protocol controller) includes a physical layer, a data link layer, and a transaction layer. The physical layer mainly implements the encoding and decoding of various data messages. The data link layer is an intermediate intermediary layer between the physical layer and the transaction layer, and is mainly responsible for providing a reliable mechanism for data exchange between the physical layer and the transaction layer. The transaction layer provides buses for three sub-protocols: Input / Output (IO), Memory (MEM), and Cache, and communicates directly with the processing core.

[0047] In this embodiment, the embodiment of the present application adds a programmable inline computing function to the memory expansion device by setting a processing core between the protocol controller and the memory and setting an elastic computing manager to control the processing core to perform elastic processing mode switching (i.e., the elastic computing manager can adaptively change the processing mode of the relevant functional modules for performing online processing or offline processing within the processing core according to the computing requirements of the computing task, so that the data passing through these relevant functional modules can enter different data processing paths as the processing mode changes. The data processing paths (paths 1, 2, and 3) shown by the dotted lines in Figure 1 can be regarded as the target data entering the processing core passing through the processing core along path 1 for online processing when only the online processing-related functional modules are in working mode, and then leaving the processing core and entering the host side or memory; when only the offline processing-related functional modules are in working mode, the target data entering the processing core can be regarded as passing through the processing core along path 2 for offline processing when leaving the processing core and entering the host side or memory; when both the online processing and offline processing-related functional modules are in working mode, the target data entering the processing core can be regarded as passing through the processing core along path 3 for online processing and offline processing when leaving the processing core and entering the host side or memory.

[0048] It can be understood that the elastic computing manager controls the processing core to perform encryption and decryption, encoding and decoding, key-value calculation and other data processing operations through different data processing paths (i.e., adaptively in online processing and / or offline processing), thereby meeting the needs of different computing tasks, thereby offloading part of the computing tasks performed by the host side to the memory expansion device, so as to reduce the number of times the host accesses the memory expansion device.

[0049] For example, when executing a computing task, since the host side (such as the Central Processing Unit (CPU)) usually uses a serial processing mode, and the traditional memory expansion device only stores data, the host side needs to perform a memory read, ALU calculation and memory write operation for each data involved in the computing task. In addition, if a certain data needs to participate in different data processing operations in the same computing task, the host side needs to repeatedly read the data from the memory. Therefore, when the access latency between the host side and the memory expansion device increases, the total latency of the host side in executing the computing task will also be greatly increased.

[0050] Compared to the above-mentioned traditional memory expansion device, the memory expansion device provided by the embodiment of the present application can be used by the host side to issue a read request, so that the processing core performs data processing operations on the read request data stream required to be read by the host side during the process of the host side performing memory reading. As a result, the host side can read the calculation result of the computing task from the memory expansion device at one time (i.e., the read request data stream processed by the memory expansion device), so that the host side can know the calculation result of the computing task. The host side can also issue a write request to write the data involved in the computing task (i.e., the write request data stream) to the memory expansion device at one time. During the process of writing the multiple data to the memory expansion device, the processing core performs data processing operations on the write request data stream and stores the obtained calculation result (i.e., the processed write request data stream) in the memory of the memory expansion device, thereby completing the memory writing of the calculation result. By performing data processing during the host side's memory reading and / or memory writing, the memory expansion device can avoid the host side from performing multiple data reading and writing or repeated data reading and writing when executing the computing task, thereby reducing the number of times the host side accesses the memory expansion device, and further reducing the total execution latency of the computing task.

[0051] It can be understood that the memory expansion device provided in the embodiment of the present application provides a programmable inline computing function, and the elastic computing manager controls the programmed processing core to perform calculations on data (such as write request data streams or read request data streams) in the process of memory access (such as memory writing or memory reading) on ​​the host side in an online processing manner and / or offline processing manner through different data processing paths. That is, the memory expansion device completes operations such as reading the data required for calculation, data calculation, and storing the calculation results within the specified memory address range, thereby reducing the number of times the host side accesses the memory expansion device, so that a large number of high-latency memory accesses between the host and the memory expansion device are replaced by low-latency accesses in the memory expansion device (such as low-latency accesses between the processing core and the memory inside the memory expansion device), thereby reducing the total latency when the host side executes computing tasks.

[0052] It can be seen from the above technical solution that by setting a processing core between the protocol controller and the memory inside the memory expansion device, the elastic computing manager controls the processing core through different data processing paths to perform the data processing operations required for different computing tasks, thereby realizing a universal memory expansion device that supports programmable inline computing functions, which can meet the computing requirements of different computing tasks. As a result, part of the host-side calculations can be offloaded to the memory expansion device, and the memory access and data processing operations related to the computing tasks are performed inside the memory expansion device, so that a large number of high-latency memory accesses between the host and the memory expansion device involved in the host's execution of computing tasks are replaced by low-latency accesses inside the memory expansion device, thereby reducing the total latency of the host's execution of computing tasks and improving the host's execution efficiency of computing tasks.

[0053] In some embodiments, in one embodiment, the processing core includes a processing engine and a processor, and the elastic computing manager is connected to the processing engine and the processor respectively, wherein:

[0054] The elastic computing manager is used to switch the processing mode of the processing engine and processor according to the target data request;

[0055] The processing engine is used to select, based on its own processing mode, to perform data processing operations on the data passing through the processing engine in an online processing manner, or to select not to perform data processing operations on the data passing through the processing engine;

[0056] The processor is configured to select, according to a processing mode in which the processor is located, to perform data processing operations on the data passing through the processor in an offline processing manner, or to select not to perform data processing operations on the data passing through the processor.

[0057] In this embodiment, the processing engine can be an intellectual property core (IP core) based on a field programmable gate array (FPGA). The user can pre-configure the calculation process of the processing engine through the register transfer level (RTL) circuit, and configure the mode of the processing engine after startup (such as pass-through mode and working mode) through the elastic computing manager. The processing engine supports calculation of the data stream currently received by itself with extremely low latency (that is, performing data processing operations on the data associated with the target data request in an online processing manner).

[0058] The processor can be a single-core processor or a multi-core processor, including but not limited to hard-core processors or soft-core processors. Users can pre-configure the computing process for the processor through programming methods such as C / C++, and configure the mode of the processing engine after startup (such as bypass mode and working mode) through the elastic computing manager. The processor supports the use of pipelines and other methods to calculate the data (i.e., data blocks) in its own cache (i.e., perform data processing operations on the data associated with the target data request in an offline processing manner).

[0059] It can be understood that compared to the processing engine that can only process the currently received data stream (that is, the data that the host side needs to read and write), the processor's processing object includes the entire memory area, so the processing method is more flexible. For example, the processor can cache the received data stream and the memory data required to process the data stream, and then process the cached data, rather than being limited to processing only the received data stream.

[0060] In some embodiments, the processing mode of the processing engine includes a pass-through mode and a working mode, and the processing mode of the processor includes a bypass mode and a working mode.

[0061] In this embodiment, when the target data request submitted by the host side is a write request, if the processing engine is in working mode, the processing engine then processes the write request data stream carried by the write request online according to the relevant computing process configured by itself, and submits the processed write request data stream to the processor. If the processing engine is in pass-through mode, the processor directly submits the write request data stream carried by the write request to the processor. In bypass mode, the processor directly submits the data submitted by the processing engine to the memory for storage, while in working mode, the data submitted by the processing engine will be processed offline before being submitted to the memory for storage. Storage; similarly, when the target data request is a read request, if the processor is in working mode, the read request data stream required to read the read request submitted by the memory will be processed offline and then submitted to the processing engine. If the processor is in bypass mode, the read request data stream submitted by the memory will be submitted directly to the processing engine. The processing engine then chooses to process the read request data stream submitted by the processor online according to its own processing mode and the relevant computing process configured for it, and forwards the processed read request data stream to the host side through the protocol controller, or chooses to forward the read request data stream submitted by the processor directly to the host side through the protocol controller.

[0062] Among them, in order to enable the data entering the processing engine or processor to continue to enter the corresponding data processing path, the user (i.e., the host side) can use the elastic computing manager to configure the processing engine or processor to working mode or non-working mode (such as pass-through mode, bypass mode) before starting the processing engine or processor, or can use the elastic computing manager to switch it to working mode or non-working mode after starting the processing engine or processor to turn on or off the processing function of the processing engine or processor on the data passing through itself.

[0063] As a possible implementation, the processing core is further configured to perform at least one of the following:

[0064] When the processing engine is in the working mode and the processor is in the bypass mode, performing data processing operations on the data passing through the processing core in an online processing manner through the first data processing path;

[0065] When the processing engine is in the pass-through mode and the processor is in the working mode, performing data processing operations on the data passing through the processing core in an offline processing manner through the second data processing path;

[0066] When the processing engine is in the working mode and the processor is in the working mode, performing data processing operations on the data passing through the processing core in an online processing mode and an offline processing mode through the third data processing path;

[0067] When the processing engine is in the pass-through mode and the processor is in the bypass mode, no data processing operations are performed on the data passing through the processing core via the fourth data processing path.

[0068] In this embodiment, as shown in Figure 2, the processing core can process the read request data stream and / or write request data stream (i.e., target data) associated with the computing task through the following four data processing paths individually or in combination, so that the memory expansion device provided in the embodiment of the present application can be applicable to a variety of computing tasks.

[0069] 1. Implement the first data processing path (i.e., path 1) that is processed only by the processing engine.

[0070] The processor in the first data processing path is in bypass mode. At this time, the path can be regarded as the target data directly entering the protocol controller or memory after being processed by the processing engine, and the processor is only used to forward the data it receives.

[0071] During specific implementation, the processor is configured or switched to bypass mode and does not process the data associated with the target data request received by itself. The processing engine is configured or switched to working mode and is used to perform online processing on the data associated with the target data request received by itself according to the calculation process pre-configured by the processing engine. That is, at this time, the processing core processes the target data entering the processing core through the first data processing path.

[0072] Among them, the protocol controller is connected to the elastic computing manager through the instruction bus and to the processing core through the data bus. According to the actual computing task requirements, the elastic computing manager can control the processor and processing engine to switch the processing mode through the control status register (CSR) and interrupt controller connected to its own instruction bus. The host side can also send a data stream carrying control parameters to the processor and processing engine through the protocol controller to control the processor and processing engine to switch the processing mode, thereby changing the data processing path of the processing core.

[0073] 2. Implement a second data processing path (i.e., path 2) that is processed only by the processor

[0074] The processing engine in the second data processing path is in pass-through mode and will not perform data processing operations to generate additional delays. At this time, the path can be regarded as the target data directly entering the protocol controller or memory after being processed by the processor, and the processing engine is only used to forward the data it receives.

[0075] In specific implementation, the processing engine is configured or switched to a pass-through mode and does not process the data associated with the target data request received by itself. The processor is configured or switched to a working mode and is used to perform offline processing on the data associated with the target data request received by itself according to the computing process pre-configured by the processor. That is, at this time, the processing core processes the target data entering the processing core through the second data processing path.

[0076] 3. Implementing the third data processing path for hybrid processing (i.e., path 3)

[0077] The processing engine and processor in the third data processing path are both in working mode. At this time, the path can be regarded as target data being processed by the processor and the processing engine respectively before entering the protocol controller or memory.

[0078] During specific implementation, the processing engine is configured or switched to a working mode for performing online processing of the data associated with the target data request received by itself according to the computing process pre-configured by the processing engine, and the processor is configured or switched to a working mode for performing offline processing of the data associated with the target data request received by itself according to the computing process pre-configured by the processor, that is, at this time the processing core processes the target data entering the processing core through the third data processing path.

[0079] 4. The fourth data processing path (i.e., path 4) in which no processing is performed

[0080] The processing engine and processor in the fourth data processing path are both in a non-working mode. At this time, the path can be regarded as a direct transmission of target data between the protocol controller and the memory.

[0081] In specific implementation, the processing engine and the controller are both configured or switched to non-working mode, and do not process the data associated with the target data request received by themselves, that is, at this time the protocol controller directly reads and writes data to the memory through the fourth data processing path.

[0082] As a possible implementation, the processing engine includes a write request data stream processing unit and a read request data stream processing unit, wherein:

[0083] The elastic computing manager is used to select, based on the target data request, to switch at least one of the write request data stream processing unit and the read request data stream processing unit to the working mode so that the processing engine is in the working mode, or to select to switch both the write request data stream processing unit and the read request data stream processing unit to the pass-through mode so that the processing engine is in the pass-through mode.

[0084] It can be understood that the processing core can flexibly select any one of paths 1-4 as the path for processing the write request data stream, the path for processing the read request data stream, or the path for processing the read request data stream and the write request data stream based on the mode switching of the write request data stream processing unit and the read request data stream processing unit. For example, for computing tasks that need to process read and write request streams, the processing core can flexibly select at least one of the above paths 1-4 to complete the processing of the read and write request data streams based on the mode switching of the write request data stream processing unit.

[0085] Specifically, the target data includes at least one of a write request data stream and a read request data stream, wherein:

[0086] a write request data stream processing unit, configured to perform data processing operations on the write request data stream in the first data processing path or the third data processing path in an online processing manner when the unit is in a working mode, and not perform data processing operations on the write request data stream in the second data processing path or the fourth data processing path when the unit is in a pass-through mode;

[0087] The read request data stream processing unit is used to perform data processing operations on the read request data stream in the first data processing path or the third data processing path in an online processing manner when the unit is in the working mode, and not to perform data processing operations on the read request data stream in the second data processing path or the fourth data processing path when the unit is in the pass-through mode.

[0088] As shown in Figure 3, when applied to the processing of write request data streams, the above-mentioned path 1 can be regarded as path 1.1, which is used to implement only processing engine processing of write request data streams. At this time, the processing engine is in working mode, which means that the write request data stream processing unit is at least in working mode. When applied to the processing of read request data streams, the above-mentioned path 1 can be regarded as path 1.2, which is used to implement only processing engine processing of read request data streams. At this time, the processing engine is in working mode, which means that the read request data stream processing unit is at least in working mode. When applied to the processing of read and write request data streams, the above-mentioned path 1 can be regarded as a combination of paths 1.1 and 1.2, which is used to implement only processing engine processing of read and write request data streams. At this time, the processing engine is in working mode, which means that both the read request data stream processing unit and the write request data stream processing unit are in working mode.

[0089] As shown in Figure 4, when applied to the processing of write request data streams, the above-mentioned path 2 can be regarded as path 2.1, which is used to implement processor-only processing of write request data streams. At this time, the processing engine is in pass-through mode, which means that the write request data stream processing unit is at least in pass-through mode. When applied to the processing of read request data streams, the above-mentioned path 2 can be regarded as path 2.2, which is used to implement processor-only processing of read request data streams. At this time, the processing engine is in pass-through mode, which means that the read request data stream processing unit is at least in pass-through mode. When applied to the processing of read and write request data streams, the above-mentioned path 2 can be regarded as a combination of paths 2.1 and 2.2, which is used to implement processor-only processing of read and write request data streams. At this time, the processing engine is in pass-through mode, which means that both the read request data stream processing unit and the write request data stream processing unit are in pass-through mode.

[0090] As shown in Figure 5, when applied to the processing of write request data streams, the above-mentioned path 3 can be regarded as path 3.1, which is used to realize mixed processing of write request data streams. At this time, the processing engine is in working mode, which means that the write request data stream processing unit is at least in working mode. When applied to the processing of read request data streams, the above-mentioned path 3 can be regarded as path 3.2, which is used to realize mixed processing of read request data streams. At this time, the processing engine is in working mode, which means that the read request data stream processing unit is at least in working mode. When applied to the processing of read and write request data streams, the above-mentioned path 3 can be regarded as a combination of paths 3.1 and 3.2, which is used to realize processor-only processing of read and write request data streams. At this time, the processing engine is in working mode, which means that both the read request data stream processing unit and the write request data stream processing unit are in working mode.

[0091] As shown in Figure 6, when applied to the processing of write request data streams, the above-mentioned path 4 can be regarded as path 4.1, that is, the processing core does not process the write request data stream. At this time, the processing engine is in pass-through mode, which means that the write request data stream processing unit is at least in pass-through mode. When applied to the processing of read request data streams, the above-mentioned path 4 can be regarded as path 4.2, that is, the processing core does not process the read request data stream. At this time, the processing engine is in pass-through mode, which means that the read request data stream processing unit is at least in pass-through mode. When applied to the processing of read and write request data streams, the above-mentioned path 4 can be regarded as a combination of paths 4.1 and 4.2, that is, the processing core does not process read and write request data streams. At this time, the processing engine is in pass-through mode, which means that both the read request data stream processing unit and the write request data stream processing unit are in pass-through mode.

[0092] It can be understood that separate processing units are set for write request data streams and read request data streams to perform data processing operations, so that the processing engine can process write request data streams and read request data streams in parallel; and it allows users to flexibly select write request data stream processing units and / or read request data stream processing units according to actual needs to build a processing engine, so that the constructed processing engine correspondingly supports the processing functions of write request data streams and / or read request data streams, thereby improving the flexibility of the processing engine; it also allows users to flexibly decompose the configuration of the calculation process into the configuration of the calculation process for the read request data stream (i.e., the configuration of the read request data stream processing unit) and / or the configuration of the calculation process for the write request data stream (i.e., the configuration of the write request data stream processing unit) when configuring the calculation process for the processing engine, thereby reducing development complexity and improving algorithm freedom.

[0093] It is understandable that when a user configures a computing process for a processing engine that includes a write request data stream processing unit and a read request data stream processing unit, the user can configure the processing engine to process only the write request data stream, or only the read request data stream, or both the read and write request data streams, based on the overall execution logic of the computing task or the execution logic of some operations that are selected to be offloaded to the memory expansion device.

[0094] For example, a user can configure a computing process only for the write request data stream processing unit or the read request data stream processing unit to perform data processing operations, while the processing unit that is not configured with a computing process (i.e., the write request data stream processing unit or the read request data stream processing unit) will only be used to forward the data received by itself. The user or the protocol controller can also choose to configure or switch the processing unit (i.e., the write request data stream processing unit or the read request data stream processing unit) to a working mode or a pass-through mode to turn on or off the corresponding processing unit (i.e., the write request data stream processing unit or the read request data stream processing unit) to process the data received by itself.

[0095] As a possible implementation, the processing engine is further configured to switch its own processing mode according to the first parameter in the target data received by itself.

[0096] In this embodiment, the host side or protocol controller can flexibly switch the processing engine to pass-through mode or working mode by embedding control state parameters (i.e., first parameters) in the data stream submitted to the processing engine to meet the actual needs of the computing task.

[0097] As a possible implementation, the processing engine is further configured to add a second parameter to the target data received by the processing engine and send the second parameter to the processor;

[0098] The processor is further configured to switch its own processing mode according to the second parameter in the target data received by itself.

[0099] In this embodiment, the host side, protocol controller or processing engine can flexibly switch the processor to pass-through mode or working mode by embedding control state parameters (i.e., second parameters) in the data stream submitted to the processor to meet the actual needs of the computing task.

[0100] In one embodiment, as shown in FIG2 , the memory includes a first area and a second area, the first area is used to store data that has not been processed by the processing core, and the second area is used to store data that has been processed by the processing core.

[0101] In this embodiment, the first area serves as a normal memory area, and any memory data will not be modified by the processing core, so as to be used as memory expansion. In some embodiments, the first memory can be directly connected to the protocol controller; the second area serves as a buffer of the processing core, which will store data processed by the processing engine (such as a write request data stream processing unit) and will also be modified when the multi-core processor executes the calculation process. The modified data can be processed by the read data stream processing unit or the processor and then returned to the host end.

[0102] As a possible implementation, the processor is connected to the first area and the second area respectively, wherein:

[0103] The processor is further used to perform data processing operations on the write request data stream submitted by the host side through the protocol controller in an offline processing manner, submit the processed write request data to the second area, and perform data processing operations on the read request data stream submitted by the first area and / or the second area in an offline processing manner, and forward the processed read request data stream to the host side through the protocol controller.

[0104] In this embodiment, when processing the data associated with the target request, the processor can quickly read the data required for processing the data from the first area or the second area according to a pre-configured computing process, and then perform data processing operations on the data associated with the target request based on the read data, thereby further improving the flexibility of data processing.

[0105] As a possible implementation, as shown in FIG7 , the processing engine includes a write request data stream processing unit, and the processing engine also includes a metadata interface. The write request data stream processing unit is connected to the metadata interface and the second area respectively, and the metadata interface is connected to the first area, wherein:

[0106] The write request data stream processing unit is also used to submit the write request data stream submitted by the host side through the protocol controller directly to the first area through the metadata interface, and to perform data processing operations on the write request data stream and submit the processed write request data stream to the second area.

[0107] In this embodiment, the write request data stream processing unit will divide the write request data stream submitted by the host into two paths for forwarding within the device. One path is that the write request data stream processing unit directly forwards the write request data stream it receives to the first area through the metadata interface. The first area is used to store the original data (i.e., metadata) written by the host, thereby providing a traditional memory expansion function. The other path is that the write request data stream processing unit processes the write request data stream submitted by the host and then forwards it to the second area. The second area is used to store the data processed by the processing core (i.e., dynamic data), thereby providing a buffer for processing cores such as processing engines and processors to perform data processing operations, and for the host to read the processed data.

[0108] In some embodiments, the write request data stream processing unit can be connected to the second area through a processor. The write request data stream processing unit can submit its processed or unprocessed write request data stream to the processor for processing, and then the processor submits the processed write request data stream to the second area for storage, thereby improving the flexibility of the processing core's processing of the write request data stream.

[0109] As a possible implementation, as shown in FIG7 , the processing engine includes a read request data stream processing unit, and the processing engine also includes a metadata interface. The read request data stream processing unit is connected to the metadata interface and the second area respectively, and the metadata interface is connected to the first area, wherein:

[0110] The elastic computing manager is further configured to, when the target data request issued by the host includes a first read request, control the read request data stream processing unit to perform a first read operation, receive the read request data stream submitted by the first region via the metadata interface, and directly forward the received read request data stream to the host via the protocol controller;

[0111] The elastic computing manager is also used to control the read request data stream processing unit to perform a second read operation when the target data request issued by the host side includes a second read request, perform a data processing operation on the read request data stream submitted by the first area or the second area, and forward the processed read request data stream to the host side through the protocol controller, or forward the read request data stream submitted by the second area to the host side through the protocol controller.

[0112] In this embodiment, the read request issued by the host may include a metadata read request (i.e., a first read request) and a processed data read (i.e., a second read request). When the host issues the first read request, the elastic computing manager controls the read request data stream processing unit to submit the corresponding read request data stream submitted by the first area through the metadata interface to the protocol controller for forwarding, so that the host can read the data that has not been processed by the processing core (such as the original data involved in the computing task written by the host). When the host issues the second read request, the elastic computing manager controls the read request data stream processing unit to receive the corresponding read request data stream submitted by the first area or the second area, processes the corresponding read request data stream, and submits it to the protocol controller for forwarding. Alternatively, according to the actual configuration of the user, the elastic computing manager can also control the read request data stream processing unit not to process the corresponding read request data stream submitted by the second area, and directly forward it, so that the host can read the data stored in the second area that has been processed by the processing core (i.e., the calculation result).

[0113] It should be noted that the data forwarding operation of the metadata interface can be executed in parallel with the operations executed by the read request data stream processing unit and the write request data stream processing unit in the processing engine.

[0114] In some embodiments, as shown in FIG7 , the processing engine further includes a control status register, which is connected to the read request data stream processing unit and the elastic computing manager, respectively, wherein:

[0115] The elastic computing manager is further configured to control the read request data stream processing unit to execute the first read operation or the second read operation through the control status register.

[0116] In this embodiment, the elastic computing manager can control the reading method of the read request data stream processing unit through CSR. The CSR is connected to the elastic computing manager through the instruction bus, and controls the read request data stream processing unit to perform the first read operation or the second read operation according to the first request or the second request issued by the host side.

[0117] Among them, the user can also pre-configure the read operations that the read request data stream processing unit needs to perform in the CSR, such as only performing the first read operation, or only performing the second read operation, or performing the first read operation and the second read operation. When the CSR receives the read request issued by the host, it will automatically control the read request data stream processing unit to perform memory reading and / or data processing with the pre-configured read operation.

[0118] In some embodiments, the processing engine further includes a write request data stream processing unit, and the control status register is connected to the write request data stream processing unit, wherein:

[0119] The control status register is also used to set or record the status or parameters of the write request data stream processing unit and the read request data stream processing unit.

[0120] In this embodiment, the control status register may include all control registers and status registers within the processing engine, thereby setting or recording the status or parameters of the write request data stream processing unit and the read request data stream processing unit, such as the queue status of the memory read / write request unit in the processing engine's buffer (the buffer is used to cache write request data or read request data to be processed or sent by the processing engine in the form of a unit), the status and parameters of the processing core in the write data stream processing unit, the status and parameters of the processing core in the read data stream processing unit, etc. It will be understood that the protocol controller can switch the processing engine to working mode or pass-through mode by controlling the CSR.

[0121] As a possible implementation, the write request data stream processing unit includes multiple downstream flow processing cores; the multiple downstream flow processing cores are used to perform data processing operations in parallel on the write request data stream in the data processing path where the write request data stream processing unit is located when the write request data stream processing unit is in working mode.

[0122] In this embodiment, the write request data stream processing unit may include one or more downstream processing cores, which can execute in parallel to improve processing efficiency. As shown in Figure 7, each downstream processing core is connected to the data bus via a buffer. The write request data stream submitted by the host through the protocol controller will enter the corresponding buffer via the data bus, and then enter the one or more downstream processing cores in a first-in, first-out order.

[0123] Specifically, the write request data stream is submitted to the buffer in the form of units (i.e., memory write request units). The downstream processing core will process each memory write request unit in the buffer in sequence according to the calculation process. After each memory write request unit is processed, it enters the buffer and is then submitted from the buffer to the memory for storage or to the processor for further processing via the data bus.

[0124] As a possible implementation method, the read request data stream processing unit includes multiple upstream processing cores; the multiple upstream processing cores are used to perform data processing operations in parallel on the read request data stream in the data processing path where the read request data stream processing unit is located when the read request data stream processing unit is in working mode.

[0125] In this embodiment, as shown in Figure 7, the read request data stream processing unit may include one or more upstream processing cores, which can execute in parallel to improve processing efficiency. The write request data stream submitted by the memory or processor will enter the buffer via the data bus and then enter the one or more upstream processing cores in sequence from the buffer.

[0126] Specifically, the read request data stream is submitted to the upstream processing core's buffer in the form of units (i.e., memory write request units). The upstream processing core then processes each memory write request unit in its buffer in sequence according to the computational flow. After each memory write request unit is processed, it enters the buffer and is then submitted from the buffer to the protocol manager via the data bus for forwarding.

[0127] It should be noted that the upstream processing core is connected to the data bus through the upstream port, and the downstream processing core is connected to the data bus through the downstream port. Both the upstream port and the downstream port include an IO transaction bus and a MEM transaction bus, and both buses can also support burst mode.

[0128] In one embodiment, as shown in FIG8 and FIG9 , the target data includes a write request data stream, and the processor includes an interrupt controller and a microprocessor. The interrupt controller is connected to the elastic computing manager and the microprocessor respectively, and the elastic computing manager is connected to the protocol controller, wherein:

[0129] The elastic computing manager is further configured to send a first interrupt signal to the interrupt controller when the processor receives the target data, and to trigger the protocol controller to send a data processing completion message to the host in response to receiving the second interrupt signal;

[0130] The interrupt controller is used to trigger the microprocessor to perform offline processing in response to receiving the first interrupt signal, and to send a second interrupt signal to the elastic computing manager when the microprocessor completes the data processing operation on the target data.

[0131] In this embodiment, the elastic computing manager is connected to the protocol controller through an instruction bus. When the data associated with the target data request enters (or all enters) the processor, the elastic computing manager can submit a trigger event to the processor (such as to the interrupt controller of the processor) to trigger the processor to process the data associated with the target data request.

[0132] Exemplarily, the microprocessor is connected to the IO transaction bus of the protocol controller through an interrupt controller, an interrupt interface and an elastic computing manager in sequence to submit an interrupt event to the host side through a message. The interrupt interface is used to receive an external interrupt signal (such as a first interrupt signal) and output an interrupt signal (such as a second interrupt signal) to the outside. After the data stream (such as all data streams that the host side needs to write) enters the processor through the data interface of the processor, the elastic computing manager sends a first interrupt signal to the interrupt controller. At this time, the microprocessor in the processor starts to execute a pre-configured calculation process for all the written data streams (i.e., perform offline calculations). When all the calculation processes are executed, the interrupt controller in the processor sends a second interrupt signal to the elastic computing manager, so that the elastic computing manager informs the host side through the protocol controller that the data processing is completed.

[0133] It is understandable that, in addition to controlling the processing core to switch modes, the above-mentioned elastic computing manager is also mainly responsible for processing the interrupt signal of the microprocessor and the conversion of the IO sub-protocol message in the transaction layer of the protocol controller. For example, when the host side sets the interrupt register of the processing core to a valid value through the IO sub-protocol, the elastic computing manager submits a trigger event through the interrupt controller to trigger the microprocessor to perform offline processing. When the microprocessor completes the calculation process, it modifies the corresponding register through the memory-mapped bus, and then the elastic computing manager generates a message signaled interrupt (MSI) or extended message signaled interrupt (MSI-X) message and submits it to the host side through the IO sub-protocol of the transaction layer of the protocol controller to inform the host side that it can read the processed data.

[0134] In one embodiment, as shown in FIG9 , the processing core includes a processor and a processing engine, the protocol controller is connected to the processing engine, the processing engine is connected to the processor, the elastic computing manager is connected to the processing engine and the processor respectively, and the processor is connected to the memory.

[0135] It can be understood that the embodiment of the present application utilizes a processor and a processing engine to construct a heterogeneous processing core, so that the processing core can adaptively support online processing and / or offline processing of data through mode switching of the processor and the processing engine, which can further enhance the flexibility and convenient development of the processing core.

[0136] The processing engine is located in the upstream link of the entire processing core, connected to the protocol controller and processor through the data bus, performing online calculations on the data stream it currently receives, and can switch the processor to bypass mode or working mode by embedding control state parameters in the data stream to be forwarded to the processor. The processor is located in the downstream link of the entire processing core, connected to the processing engine and memory respectively. Unlike the processing engine in the upstream link, the multi-core processor as a downstream engine has more flexible processing methods. This is mainly due to two reasons: one is that the processor's processing objects include the entire memory area, not just the data stream currently read or written by the host; the other is the flexibility of the programming method. The processor can use various excellent library functions in the operating system environment and the multi-threading mechanism of the multi-core processor to achieve offline computing.

[0137] As a possible implementation, as shown in FIG8 , the processor includes a microprocessor (the microprocessor may include one or more CPUs) and a cache coherency unit (CCU). The cache coherency unit is connected to the processing engine, the memory, and the microprocessor, respectively, wherein:

[0138] a microprocessor configured to perform offline processing on data associated with a target data request received by a cache coherence unit according to a preconfigured computational process of the microprocessor when the processor is in an operating mode, and not perform offline processing on data associated with the target data request received by the cache coherence unit when the processor is in a bypass mode;

[0139] The cache consistency unit is used to submit the data associated with the target data request received by itself to the microprocessor for offline processing when the processor is in working mode, and to submit the data associated with the target data request received by itself directly to the memory or processing engine when the processor is in bypass mode.

[0140] It is understood that the cache coherence unit can be used to forward received data streams, cache memory data required by the processor to perform data processing operations, and maintain cache coherence. Specifically, the cache of the microprocessor can be refreshed based on hardware or software to maintain cache coherence with memory.

[0141] In some embodiments, the microprocessor can be configured to enable the cache sniffing function of the CCU to refresh the cache of the microprocessor, thereby eliminating the need to refresh the cache through software, thereby improving processing efficiency.

[0142] In some embodiments, as shown in FIG8 , the processor further includes a memory controller, and the memory controller is connected to the cache coherence unit and the memory, respectively, wherein:

[0143] The memory controller is used to write received data (such as a write request data stream) to the memory, or read data from the memory based on a read request issued by the host (or a data read request issued by the microprocessor, used to obtain the data required by the microprocessor to process the received read and write request stream), and submit the read data to the cache coherence unit for forwarding or caching. In the process of submitting the above data read request to the memory controller, the CCU can refresh the microprocessor's cache accordingly, thereby maintaining cache coherence and allowing the microprocessor to perform data processing using the current and latest memory data.

[0144] As a possible implementation, the microprocessor is further configured to enable a cache sniffing function of a cache coherence unit when the processor is in a working mode, so that the cache coherence unit refreshes the cache of the processor;

[0145] The microprocessor is further configured to disable a cache sniffing function of a cache coherence unit when the processor is in a bypass mode, so that the cache coherence unit does not refresh the cache of the processor.

[0146] In this embodiment, considering that when the processor is in working mode, the microprocessor needs to perform data processing operations based on cached data, the microprocessor can control the CCU to turn on the cache sniffing function to refresh the cache in time when the CCU receives data to maintain cache consistency; when the processor is in bypass mode, since the microprocessor does not perform data processing operations, the microprocessor can control the CCU to turn off the cache sniffing function and not refresh the cache to reduce latency.

[0147] In a second aspect, an embodiment of the present application provides a data processing system, which includes a host end and a memory expansion device as in the first aspect, wherein the host end is connected to the memory expansion device.

[0148] In some embodiments, the system includes at least two memory expansion devices, and the system also includes a switch device, the host end is connected to the switch device, and the switch device is respectively connected to the at least two memory expansion devices.

[0149] In this embodiment, as shown in FIG10 , when the number of interfaces on the host side (such as CXL interfaces) is limited, a switch can be used to connect multiple memory expansion devices such as those in the embodiment of the present application. Each memory expansion device is connected to the CPU on the host side through the switch and the CXL interface in turn. This can reduce the total latency of the CPU accessing the memory expansion device through the switch by offloading part of the CPU's operations to the memory expansion device, thereby improving the efficiency of the CPU in executing computing tasks.

[0150] It can be seen from the above technical solution that by setting a processing core between the protocol controller and the memory inside the memory expansion device, the elastic computing manager controls the processing core through different data processing paths to perform the data processing operations required for different computing tasks, thereby realizing a universal memory expansion device that supports programmable inline computing functions, which can meet the computing requirements of different computing tasks. As a result, part of the host-side calculations can be offloaded to the memory expansion device, and the memory access and data processing operations related to the computing tasks are performed inside the memory expansion device, so that a large number of high-latency memory accesses between the host and the memory expansion device involved in the host's execution of computing tasks are replaced by low-latency accesses inside the memory expansion device, thereby reducing the total latency of the host's execution of computing tasks and improving the host's execution efficiency of computing tasks.

[0151] In a third aspect, an embodiment of the present application provides a data processing method, which is applied to the memory expansion device disclosed in the embodiment of the first aspect. The method may include the following steps:

[0152] Step S101: The protocol controller receives a target data request sent by the host;

[0153] Step S102: The elastic computing manager switches the processing mode of the processing core according to the target data request;

[0154] Step S103: The processing core performs data processing operations on the target data associated with the target data request through the data processing path corresponding to the processing mode in which the processing core is located, and submits the processed target data to the memory or forwards it to the host end through the protocol controller;

[0155] The data processing path includes at least: data processing paths corresponding to respective data processing operations performed on target data in an online processing manner and / or an offline processing manner.

[0156] It can be seen from the above technical solution that by setting a processing core between the protocol controller and the memory inside the memory expansion device, the elastic computing manager controls the processing core through different data processing paths to perform the data processing operations required for different computing tasks, thereby realizing a universal memory expansion device that supports programmable inline computing functions, which can meet the computing requirements of different computing tasks. As a result, part of the host-side calculations can be offloaded to the memory expansion device, and the memory access and data processing operations related to the computing tasks are performed inside the memory expansion device, so that a large number of high-latency memory accesses between the host and the memory expansion device involved in the host's execution of computing tasks are replaced by low-latency accesses inside the memory expansion device, thereby reducing the total latency of the host's execution of computing tasks and improving the host's execution efficiency of computing tasks.

[0157] As a possible implementation, the processing core includes a processing engine and a processor, and the elastic computing manager is connected to the processing engine and the processor respectively;

[0158] The elastic computing manager switches the processing mode of the processing core according to the target data request, including:

[0159] The elastic computing manager switches the processing mode of the processing engine and processor according to the target data request;

[0160] The method also includes:

[0161] The processing engine chooses to perform data processing operations on the data passing through the processing engine in an online processing manner, or chooses not to perform data processing operations on the data passing through the processing engine, according to the processing mode in which the processing engine is located;

[0162] The processor chooses to perform data processing operations on the data passing through the processor in an offline processing manner, or chooses not to perform data processing operations on the data passing through the processor, according to the processing mode in which the processor is located.

[0163] As a possible implementation, the processing core performs a data processing operation on the target data associated with the target data request through a data processing path corresponding to the processing mode in which the processing core is located, including:

[0164] When the processing engine is in the working mode and the processor is in the bypass mode, the processing core performs data processing operations on the data passing through the processing core in an online processing manner through the first data processing path;

[0165] When the processing engine is in the pass-through mode and the processor is in the working mode, the processing core performs data processing operations on the data passing through the processing core in an offline processing manner through the second data processing path;

[0166] When the processing engine is in the working mode and the processor is in the working mode, the processing core performs data processing operations on the data passing through the processing core in an online processing mode and an offline processing mode through the third data processing path;

[0167] When the processing engine is in the pass-through mode and the processor is in the bypass mode, the processing core does not perform data processing operations on the data passing through the processing core via the fourth data processing path.

[0168] As a possible implementation, the processing engine includes a write request data stream processing unit and a read request data stream processing unit;

[0169] The elastic computing manager switches the processing engine's processing mode based on the target data request, including:

[0170] The elastic computing manager selects, based on the target data request, to switch at least one of the write request data stream processing unit and the read request data stream processing unit to the working mode so that the processing engine is in the working mode, or selects to switch both the write request data stream processing unit and the read request data stream processing unit to the pass-through mode so that the processing engine is in the pass-through mode.

[0171] As a possible implementation, the target data includes at least one of a write request data stream and a read request data stream;

[0172] The processing engine, based on its own processing mode, chooses to perform data processing operations on the data passing through the processing engine in an online processing manner, or chooses not to perform data processing operations on the data passing through the processing engine, including:

[0173] The write request data stream processing unit performs data processing operations on the write request data stream in the first data processing path or the third data processing path in an online processing manner when the write request data stream processing unit is in the working mode, and does not perform data processing operations on the write request data stream in the second data processing path or the fourth data processing path when the write request data stream processing unit is in the pass-through mode;

[0174] When the read request data stream processing unit is in working mode, it performs data processing operations on the read request data stream in the first data processing path or the third data processing path in an online processing manner. When it is in pass-through mode, it does not perform data processing operations on the read request data stream in the second data processing path or the fourth data processing path.

[0175] As a possible implementation, the write request data stream processing unit includes multiple downstream processing cores, and the read request data stream processing unit includes multiple upstream processing cores. When the write request data stream processing unit is in working mode, the write request data stream processing unit performs data processing operations on the write request data stream in the first data processing path or the third data processing path in an online processing manner, including:

[0176] The plurality of downstream processing cores perform data processing operations on the write request data stream passing through the write request data stream processing unit in parallel when the write request data stream processing unit is in a working mode;

[0177] When the read request data stream processing unit is in working mode, the multiple upstream processing cores perform data processing operations on the read request data stream passing through the read request data stream processing unit in parallel.

[0178] As a possible implementation, the processor includes a microprocessor and a cache coherence unit, and the cache coherence unit is connected to the processing engine, the memory, and the microprocessor respectively;

[0179] The processor, based on its own processing mode, chooses to perform data processing operations on the data passing through the processor in an offline processing manner, or chooses not to perform data processing operations on the data passing through the processor, including:

[0180] The microprocessor performs offline processing on target data received by the cache coherence unit according to a preconfigured computational process of the microprocessor when the processor is in an operating mode, and does not perform offline processing on the target data received by the cache coherence unit when the processor is in a bypass mode;

[0181] The method also includes:

[0182] When the processor is in working mode, the cache coherence unit submits the target data it receives to the microprocessor for offline processing. When the processor is in bypass mode, the cache coherence unit submits the target data it receives directly to the memory or processing engine.

[0183] As a possible implementation, the method further includes:

[0184] The microprocessor enables a cache sniffing function of a cache coherence unit when the processor is in a working mode, so that the cache coherence unit refreshes the cache of the processor;

[0185] When the microprocessor is in the bypass mode, the microprocessor turns off the cache sniffing function of the cache coherence unit so that the cache coherence unit does not refresh the cache of the processor.

[0186] As a possible implementation, the target data includes a write request data stream, and the processor further includes an interrupt controller, which is connected to the elastic computing manager and the microprocessor respectively;

[0187] The method also includes:

[0188] The elastic computing manager sends a first interrupt signal to the interrupt controller when the processor receives the target data, and triggers the protocol controller to send a data processing completion message to the host in response to receiving the second interrupt signal;

[0189] The interrupt controller triggers the microprocessor to perform offline processing in response to receiving the first interrupt signal, and sends a second interrupt signal to the elastic computing manager when the microprocessor completes the data processing operation on the target data.

[0190] As a possible implementation, the method further includes:

[0191] The processing engine switches its own processing mode according to the first parameter in the target data received by itself.

[0192] As a possible implementation, the method further includes:

[0193] The processing engine adds a second parameter to the target data received by itself and sends it to the processor;

[0194] The processor switches its own processing mode according to the second parameter in the target data received by itself.

[0195] As a possible implementation, the processor is a multi-core processor, and the multi-core processor includes a hard-core processor or a soft-core processor.

[0196] As a possible implementation, the memory includes a first area and a second area, the first area is used to store data that has not been processed by the processing core, and the second area is used to store data that has been processed by the processing core.

[0197] As a possible implementation, the processing core includes a processing engine for performing data processing operations on target data in an online processing manner, the target data includes a write request data stream, the processing engine further includes a metadata interface, a write request data stream processing unit in the processing engine is connected to the metadata interface and the second area respectively, and the metadata interface is connected to the first area, and the method further includes:

[0198] The write request data stream processing unit directly submits the write request data stream submitted by the host side through the protocol controller to the first area through the metadata interface, performs data processing operations on the write request data stream, and submits the processed write request data stream to the second area.

[0199] As a possible implementation, the processing core includes a processing engine for performing data processing operations on target data in an online processing manner, the target data includes a read request data stream, the processing engine includes a read request data stream processing unit, the read request data stream processing unit in the processing engine is respectively connected to the metadata interface and the second area, and the metadata interface is connected to the first area, and the method further includes:

[0200] When the target data request sent by the host includes a first read request, the elastic computing manager controls the read request data stream processing unit to perform a first read operation, receives the read request data stream submitted by the first region through the metadata interface, and directly forwards the received read request data stream to the host through the protocol controller;

[0201] When the target data request issued by the host side includes a second read request, the elastic computing manager controls the read request data stream processing unit to perform a second read operation, performs a data processing operation on the read request data stream submitted by the first area or the second area, and forwards the processed read request data stream to the host side through the protocol controller, or forwards the read request data stream submitted by the second area to the host side through the protocol controller.

[0202] As a possible implementation, the processing engine further includes a control status register, which is connected to the read request data stream processing unit and the elastic computing manager respectively. The method further includes:

[0203] The elastic computing manager controls the read request data stream processing unit to perform the first read operation or the second read operation through the control status register.

[0204] As a possible implementation, the processor is connected to the first area and the second area respectively, and the method further includes:

[0205] The processor performs data processing operations on the write request data stream submitted by the host side through the protocol controller in an offline processing manner, submits the processed write request data to the second area, and performs data processing operations on the read request data stream submitted by the first area and / or the second area in an offline processing manner, and forwards the processed read request data stream to the host side through the protocol controller.

[0206] The data processing method provided in the embodiment of the present application can implement the various processes implemented by the embodiment of the processing core side in the memory expansion device of the first aspect and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0207] The present application also provides an electronic device, as shown in Figure 11, which is a schematic diagram of the electronic device provided in the present application. As shown in Figure 11, the electronic device 100 includes a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus. The memory 110 stores a computer program that can be executed on the processor 120 to implement the steps of the data processing method disclosed in the present application.

[0208] The present application also provides a non-volatile computer-readable storage medium. See Figure 12, which is a schematic diagram of the non-volatile computer-readable storage medium provided in the present application. As shown in Figure 12, the non-volatile computer-readable storage medium 200 stores a computer program / instructions 210. When executed by a processor, the computer program / instructions 210 implements the steps of the data processing method disclosed in the present application.

[0209] An embodiment of the present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps in the data processing method disclosed in the embodiment of the present application.

[0210] Among them, the processor includes the processing core and elastic computing manager in the memory expansion device of the above embodiment, and the non-volatile readable storage medium, including computer non-volatile readable storage medium, such as computer read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.

[0211] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0212] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course, by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal to execute the methods of each embodiment of the present application.

[0213] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A memory expansion device, characterized in that: The memory expansion device includes a processing core, a protocol controller, an elastic computing manager and a memory, wherein the protocol controller is configured to be connected to a host end, the processing core is respectively connected to the protocol controller, the elastic computing manager and the memory, and the protocol controller is connected to the elastic computing manager, wherein: The protocol controller is configured to communicate with the host end and receive a target data request sent by the host end; The elastic computing manager is configured to switch a processing mode of the processing core according to the target data request; The processing core is configured to perform data processing operations on the target data associated with the target data request through different data processing paths according to different processing modes of the processing core, and submit the processed target data to the memory or forward it to the host end through the protocol controller; The different data processing paths include at least: data processing paths respectively corresponding to data processing operations performed on the target data in an online processing manner and / or an offline processing manner.

2. The device according to claim 1, characterized in that The processing core includes a processing engine and a processor, and the elastic computing manager is connected to the processing engine and the processor respectively, wherein: The elastic computing manager is configured to switch the processing modes of the processing engine and the processor according to the target data request; The processing engine is configured to select, according to the processing mode in which the processing engine is located, to perform data processing operations on the data passing through the processing engine in an online processing manner, or to select not to perform data processing operations on the data passing through the processing engine; The processor is configured to select, according to the processing mode in which the processor is located, to perform data processing operations on the data passing through the processor in an offline processing manner, or to select not to perform data processing operations on the data passing through the processor.

3. The device according to claim 2, characterized in that The processing core is further configured to perform at least one of the following: When the processing engine is in working mode and the processor is in bypass mode, performing data processing operations on data passing through the processing core in an online processing manner through a first data processing path; When the processing engine is in a pass-through mode and the processor is in a working mode, performing data processing operations on the data passing through the processing core in an offline processing manner through a second data processing path; When the processing engine is in the working mode and the processor is in the working mode, performing data processing operations on the data passing through the processing core in an online processing mode and an offline processing mode through a third data processing path; When the processing engine is in the pass-through mode and the processor is in the bypass mode, no data processing operation is performed on the data passing through the processing core via the fourth data processing path.

4. The device according to claim 3, characterized in that The processing engine includes a write request data stream processing unit and a read request data stream processing unit, wherein: The elastic computing manager is configured to select, based on the target data request, to switch at least one of the write request data stream processing unit and the read request data stream processing unit to a working mode so that the processing engine is in a working mode, or to select to switch both the write request data stream processing unit and the read request data stream processing unit to a pass-through mode so that the processing engine is in a pass-through mode.

5. The device according to claim 4, characterized in that The target data includes at least one of a write request data stream and a read request data stream, wherein: The write request data stream processing unit is configured to perform data processing operations on the write request data stream in the first data processing path or the third data processing path in an online processing manner when the write request data stream processing unit is in a working mode, and not perform data processing operations on the write request data stream in the second data processing path or the fourth data processing path when the write request data stream processing unit is in a pass-through mode; The read request data stream processing unit is configured to perform data processing operations on the read request data stream in the first data processing path or the third data processing path in an online processing manner when the unit is in the working mode, and not perform data processing operations on the read request data stream in the second data processing path or the fourth data processing path when the unit is in the pass-through mode.

6. The device according to claim 5, characterized in that The write request data stream processing unit includes a plurality of downstream processing cores, and / or the read request data stream processing unit includes a plurality of upstream processing cores, wherein: The multiple downstream processing cores are configured to perform data processing operations on the write request data stream passing through the write request data stream processing unit in parallel when the write request data stream processing unit is in working mode; The plurality of upstream processing cores are configured to perform data processing operations on the read request data stream passing through the read request data stream processing unit in parallel when the read request data stream processing unit is in a working mode.

7. The device according to claim 3, characterized in that The processor includes a microprocessor and a cache consistency unit, and the cache consistency unit is connected to the processing engine, the memory and the microprocessor respectively, wherein: The microprocessor is configured to perform offline processing on the target data received by the cache coherence unit according to a preconfigured calculation process of the microprocessor when the processor is in an operating mode, and not perform offline processing on the target data received by the cache coherence unit when the processor is in a bypass mode; The cache consistency unit is configured to submit the target data received by itself to the microprocessor for offline processing when the processor is in working mode, and to submit the target data received by itself directly to the memory or the processing engine when the processor is in bypass mode.

8. The device according to claim 7, characterized in that The microprocessor is further configured to enable a cache sniffing function of the cache coherence unit when the processor is in a working mode, so that the cache coherence unit refreshes the cache of the processor; The microprocessor is further configured to disable a cache sniffing function of the cache coherence unit when the processor is in bypass mode, so that the cache coherence unit does not refresh the cache of the processor.

9. The device according to claim 7, characterized in that The target data includes a write request data stream, and the processor further includes an interrupt controller, which is connected to the elastic computing manager and the microprocessor respectively, wherein: The elastic computing manager is further configured to send a first interrupt signal to the interrupt controller when the processor receives the target data, and is configured to trigger the protocol controller to send data processing completion information to the host end in response to receiving a second interrupt signal; The interrupt controller is configured to trigger the microprocessor to perform offline processing in response to receiving the first interrupt signal, and is configured to send the second interrupt signal to the elastic computing manager when the microprocessor completes the data processing operation on the target data.

10. The device according to claim 2, characterized in that The processing engine is further configured to switch its own processing mode according to the first parameter in the target data received by itself.

11. The device according to claim 10, characterized in that The processing engine is further configured to add a second parameter to the target data received by the processing engine and send the second parameter to the processor; The processor is further configured to switch its own processing mode according to a second parameter in the target data received by the processor.

12. The device according to any one of claims 2 to 11, characterized in that: The processor is a multi-core processor, and the multi-core processor includes a hard-core processor or a soft-core processor.

13. The device according to any one of claims 1 to 11, characterized in that: The memory includes a first area and a second area, the first area is configured to store data that has not been processed by the processing core, and the second area is configured to store data that has been processed by the processing core.

14. The device according to claim 13, characterized in that The processing core includes a processing engine configured to perform data processing operations on the target data in an online processing manner, the target data includes a write request data stream, the processing engine also includes a metadata interface, a write request data stream processing unit in the processing engine is connected to the metadata interface and the second area respectively, and the metadata interface is connected to the first area, wherein: The write request data stream processing unit is also configured to submit the write request data stream submitted by the host end through the protocol controller directly to the first area through the metadata interface, and to perform data processing operations on the write request data stream and submit the processed write request data stream to the second area.

15. The device according to claim 13, characterized in that The processing core includes a processing engine configured to perform data processing operations on the target data in an online processing manner, the target data includes a read request data stream, the processing engine also includes a metadata interface, a read request data stream processing unit in the processing engine is connected to the metadata interface and the second area respectively, and the metadata interface is connected to the first area, wherein: The elastic computing manager is further configured to control the read request data stream processing unit to perform a first read operation, receive a read request data stream submitted by the first area through the metadata interface, and directly forward the received read request data stream to the host through the protocol controller when the target data request issued by the host includes a first read request; The elastic computing manager is also configured to control the read request data stream processing unit to perform a second read operation when the target data request issued by the host end includes a second read request, perform a data processing operation on the read request data stream submitted by the first area or the second area, and forward the processed read request data stream to the host end through the protocol controller, or forward the read request data stream submitted by the second area to the host end through the protocol controller.

16. The device according to claim 15, characterized in that The processing engine further includes a control status register, which is connected to the read request data stream processing unit and the elastic computing manager respectively, wherein: The elastic computing manager is further configured to control the read request data stream processing unit to execute the first read operation or the second read operation through the control status register.

17. The device according to claim 13, characterized in that The processors are connected to the first area and the second area respectively, wherein: The processor is also configured to perform data processing operations on the write request data stream submitted by the host end through the protocol controller in an offline processing manner, submit the processed write request data to the second area, and perform data processing operations on the read request data stream submitted by the first area and / or the second area in an offline processing manner, and forward the processed read request data stream to the host end through the protocol controller.

18. A data processing system, characterized in that: The system includes a host end and a memory expansion device as described in any one of claims 1-17, and the host end is connected to the memory expansion device.

19. The system according to claim 18, characterized in that The system includes at least two memory expansion devices, and the system also includes a switch device, the host end is connected to the switch device, and the switch device is respectively connected to the at least two memory expansion devices.

20. A data processing method, characterized in that: It should be configured as a memory expansion device as described in any one of claims 1 to 17, and the method includes: The protocol controller receives a target data request sent by the host; The elastic computing manager switches the processing mode of the processing core according to the target data request; The processing core performs a data processing operation on the target data associated with the target data request through a data processing path corresponding to the processing mode in which the processing core is located, and submits the processed target data to the memory or forwards it to the host end through the protocol controller; The data processing path includes at least: data processing paths corresponding to respective data processing operations performed on the target data in an online processing manner and / or an offline processing manner.

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