Encoding method, apparatus and system, and chip

Abstract

The present application relates to the technical field of communications. Disclosed are an encoding method, apparatus and system, and a chip. In the method, a block pair is sent by means of a serial channel, wherein the block pair comprises a first block and a second block, the first block and the second block are of the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to comprise content indicating the type of the second block, such that the second block can carry content other than the content indicating the type of the second block, and thus the second block has high levels of expandability. In addition, the first block and the second block are of the same length, such that the first block and the second block may comprise the same number of bits of the same signal, or the first block and the second block comprise bits of different signals, but the number of bits of the signal comprised in the first block is the same as the number of bits of the signal comprised in the second block. The block pair is transmitted by means of a serial channel, such that the serial channel can have fewer pins. The serial channel in the method can be implemented on the basis of an MII; thus, the method can be applied to an MII scenario.

Description

Coding method, device, system and chip

[0001] This application claims priority to Chinese patent application number 202311148553.7, filed on September 6, 2023, entitled “Coding method, device, system and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a coding method, device, system and chip. Background Art

[0003] In the field of communication technology, a signal transmitter may encode a signal to obtain an encoding result, and transmit the encoding result to a signal receiver, which then decodes the received encoding result to recover the signal.

[0004] Summary of the Invention

[0005] The present application proposes an encoding method, a decoding method, a device, a system and a chip for transmitting signals in the form of block pairs.

[0006] In a first aspect, an encoding method is provided, comprising: transmitting a block pair via a serial channel, the block pair comprising a first block and a second block, the first block and the second block being of the same length, and the first block indicating the type of the second block. In this method, since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, thereby enabling the second block to carry content other than that indicating its own type, resulting in high scalability of the second block. Furthermore, the first block and the second block are of the same length, so the first block and the second block may include the same number of bits of the same signal, or the first block and the second block may include bits of different signals and the number of bits of the signals included is the same. Transmitting the block pair via a serial channel can reduce the number of pins of the serial channel. Furthermore, the serial channel in this method can be implemented based on a media independent interface (MII), so this method can be applied to MII scenarios.

[0007] Exemplarily, sending the block pair through a serial channel includes sending the block pair from a media access control (MAC) layer to a physical layer (PHY) through the serial channel.

[0008] Exemplarily, sending the block pair through a serial channel includes: sending the block pair from the PHY to the MAC layer through the serial channel.

[0009] In a second aspect, a decoding method is provided, comprising: receiving a block pair via a serial channel, the block pair comprising a first block and a second block, the first block and the second block being of the same length, and the first block indicating the type of the second block. Because the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, thereby enabling the second block to carry content other than that indicating its own type, resulting in high scalability of the second block. Furthermore, the first block and the second block are of the same length, and thus the first block and the second block may include the same number of bits of the same signal, or the first block and the second block may include bits of different signals and the number of bits of the signals included is the same. Receiving the block pair via a serial channel can reduce the number of pins of the serial channel. Furthermore, the serial channel in this method can be implemented based on MII, and thus the method can be applied to MII scenarios.

[0010] Exemplarily, receiving the block pair through a serial channel includes: receiving, from the MAC layer, the block pair sent by the PHY through the serial channel.

[0011] Exemplarily, sending the block pair through a serial channel includes: receiving the block pair sent by the MAC layer through the serial channel from the PHY.

[0012] In a possible implementation of the first or second aspect, the first block indicates the type of the second block, including but not limited to at least one of the following: if the first block is a data block, indicating that the second block is a data block; if the first block is a control block with a value of X, indicating that the second block is a control block; if the first block is a control block with a value of Y, indicating that the second block is a management block; if the first block is a control block with a value of Z, indicating that the second block is a data block; if the first block is a control block with a value of W, indicating that the second block indicates collision detection (COL) and carrier sense (CRS) in a bitmap manner. X can be called the first value, Y can be called the second value, Z can be called the third value, and W can be called the fourth value.

[0013] By using one or more first blocks to indicate the type of the second block, the encoding method is more flexible and diverse.

[0014] In some possible implementations of the first or second aspect, the first block is a J code block and the second block is a K code block; or the first block is a T code block and the second block is an R code block. In some possible implementations of the first or second aspect, when the first block is a J code block and the second block is a K code block, the block pair can be used to indicate a start-of-stream delimiter. When the first block is a T code block and the second block is an R code block, the block pair can be used to indicate an end-of-stream delimiter.

[0015] In some possible implementations of the first aspect or the second aspect, the second block includes a management signal, and thus the management signal can be transmitted through the transmission block pair.

[0016] Exemplarily, the management signal occupies 1 bit.

[0017] Exemplarily, the length of each of the first block and the second block is 5 bits, and thus the first block and the second block can be obtained based on the bits of a transmit data signal (TXD) of one cycle, respectively.

[0018] In some possible implementations of the first or second aspect, the first block is encoded in 4B / 5B. In another possible implementation, the first block is encoded in 8B / 10B. Therefore, the encoding method of the first block is relatively flexible.

[0019] Exemplarily, the second block includes a management signal, which occupies 1 bit or 2 bits. Therefore, in the second block, the carrying mode of the management signal is relatively flexible.

[0020] For example, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal. Because the second block only includes a 1-bit management signal, fewer bits in the second block are used to transmit the management signal. When the management signal is transmitted, the efficiency of transmitting the data signal or data signals is higher.

[0021] In some possible implementations of the first or second aspect, the serial channel is implemented based on MII.

[0022] In a third aspect, a data structure is provided, which includes the first aspect or any block pair described in the first aspect.

[0023] In a fourth aspect, a coding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method; and a processing module for performing other operations other than the operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method.

[0024] In the fifth aspect, a decoding device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method; and a processing module for performing other operations other than the operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method.

[0025] In a sixth aspect, an encoding device is provided, which includes: an encoding module for sending a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

[0026] Exemplarily, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0027] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block having a value of a first value, indicating that the second block is a control block.

[0028] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a value of the second value, indicating that the second block is a management block.

[0029] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a value of a third value, indicating that the second block is a data block.

[0030] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a fourth value, indicating that the second block indicates COL and CRS in a bitmap manner.

[0031] Exemplarily, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0032] Exemplarily, a block pair including a J code block and a K code block is used to indicate SSD, and a block pair including a T code block and an R code block is used to indicate ESD.

[0033] Exemplarily, it is characterized in that the second block includes a management signal.

[0034] Exemplarily, the management signal occupies 1 bit.

[0035] Exemplarily, the length of the first block and the length of the second block are both 5 bits.

[0036] Exemplarily, the first block is encoded in 4B / 5B mode.

[0037] Exemplarily, the first block is encoded in 8B / 10B mode.

[0038] Exemplarily, the second block includes a management signal, which occupies 1 bit or 2 bits.

[0039] Exemplarily, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0040] Exemplarily, the serial channel is implemented based on MII.

[0041] Exemplarily, the encoding module is configured to send block pairs from the MAC layer to the PHY via a serial channel.

[0042] Exemplarily, the encoding module is configured to send block pairs from the PHY to the MAC layer via a serial channel.

[0043] In a seventh aspect, a decoding device is provided, which includes: a decoding module for receiving a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

[0044] Exemplarily, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0045] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block having a value of a first value, indicating that the second block is a control block.

[0046] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a value of the second value, indicating that the second block is a management block.

[0047] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a value of a third value, indicating that the second block is a data block.

[0048] Exemplarily, the first block indicates the type of the second block, including: when the first block is a control block with a fourth value, indicating that the second block indicates COL and CRS in a bitmap manner.

[0049] Exemplarily, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0050] Exemplarily, a block pair including a J code block and a K code block is used to indicate SSD, and a block pair including a T code block and an R code block is used to indicate ESD.

[0051] Illustratively, the second block includes management signals.

[0052] Exemplarily, the management signal occupies 1 bit.

[0053] Exemplarily, the length of the first block and the length of the second block are both 5 bits.

[0054] Exemplarily, the first block is encoded in 4B / 5B mode.

[0055] Exemplarily, the first block is encoded in 8B / 10B mode.

[0056] Exemplarily, the second block includes a management signal, which occupies 1 bit or 2 bits.

[0057] Exemplarily, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0058] Exemplarily, the serial channel is implemented based on MII.

[0059] Exemplarily, the decoding module is configured to receive, from the MAC layer, a block pair sent by the PHY through a serial channel.

[0060] Exemplarily, the decoding module is configured to receive a block pair sent by the MAC layer through a serial channel from the PHY.

[0061] In an eighth aspect, a communication device is provided, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0062] In a ninth aspect, another communication device is provided, which includes: a PHY circuit, the PHY circuit being used to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0063] Any encoding device, decoding device or communication device in the fourth to ninth aspects above may be a chip or a communication device.

[0064] In a tenth aspect, a communication system is provided, comprising a MAC layer circuit and a PHY circuit, wherein the MAC layer circuit is configured to perform any encoding method according to the first aspect, and the PHY circuit is configured to perform any decoding method according to the second aspect; alternatively, the PHY circuit is configured to perform any encoding method according to the first aspect, and the MAC layer circuit is configured to perform any decoding method according to the second aspect. This communication system can be implemented using a chip or a communication device.

[0065] In an eleventh aspect, a chip is provided, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0066] In a twelfth aspect, another chip is provided, which includes: a PHY circuit, and the PHY circuit is used to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0067] It should be understood that the beneficial effects achieved by the technical solutions of the third to twelfth aspects of this application and the corresponding possible implementation methods can be referred to the technical effects of the technical solutions of the first to second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] FIG1 is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0069] FIG2 is a flow chart of an encoding method provided in an embodiment of the present application;

[0070] FIG3 is a schematic diagram of a block pair provided in an embodiment of the present application;

[0071] FIG4 is a schematic diagram of an Ethernet frame transmission according to an embodiment of the present application;

[0072] FIG5 is a schematic diagram of a misidentification provided by an embodiment of the present application;

[0073] FIG6 is a schematic diagram of a process of transmitting block pairs provided in an embodiment of the present application;

[0074] FIG7 is a schematic diagram of another process of transmitting block pairs provided in an embodiment of the present application;

[0075] FIG8 is a schematic diagram of a process of another transmission block pair provided in an embodiment of the present application;

[0076] FIG9 is a schematic diagram of a process of another transmission block pair provided in an embodiment of the present application;

[0077] FIG10 is a schematic diagram of another block pair provided in an embodiment of the present application;

[0078] FIG11 is a schematic diagram of a process for transmitting an H.sig code block according to an embodiment of the present application;

[0079] FIG12 is a schematic diagram of another process of transmitting an H.sig code block provided in an embodiment of the present application;

[0080] FIG13 is a schematic diagram of another process of transmitting an H.sig code block provided in an embodiment of the present application;

[0081] FIG14 is a flowchart of a decoding method provided in an embodiment of the present application;

[0082] FIG15 is a schematic diagram of a process of inputting a block pair into an RS according to an embodiment of the present application;

[0083] FIG16 is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application;

[0084] FIG17 is a schematic diagram of a data channel synchronization process provided by an embodiment of the present application;

[0085] FIG18 is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0086] FIG19 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0087] FIG20 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0088] FIG21 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0089] In the field of communication technology, a signal transmitting end can encode a signal to be sent to obtain an encoding result, and send the encoding result to a signal receiving end. After receiving the encoding result, the signal receiving end restores the signal based on the encoding result. In addition, in the field of communication technology, signals can be transmitted between a media access control (MAC) chip and a physical layer (PHY) chip through a media independent interface (MII). For example, in scenarios such as industrial IoT, the IoT terminal includes a PHY chip and a microcontroller (MCU), and the MCU includes a MAC chip. Signals are transmitted between the PHY chip and the MAC chip through the MII. For another example, in a scenario where a switch is used, the switch includes a PHY chip and a MAC chip, and signals are transmitted between the PHY chip and the MAC chip through the MII.

[0090] In the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, MII is a parallel interface that includes 18 pins used to transmit data signals, control signals, and management signals. The specific method for transmitting signals through these 18 pins can be found in the relevant content of the IEEE 802.3 standard and will not be described in detail here. However, since the packaging cost of the chip increases with the number of pins on the chip, when the number of pins available on the chip is relatively limited, it is necessary to reduce the number of MII pins in the chip, so that the number of pins used to provide other functions in the chip is relatively large.

[0091] The present invention provides an encoding method and a decoding method for obtaining block pairs based on a signal and transmitting the signal in the form of a transmission block pair. This method can be applied to scenarios where the signal is transmitted via MII, that is, the signal is a signal transmitted via MII. This method can also be applied to scenarios other than MII.

[0092] Figure 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application, using an MII scenario as an example. The method can be applied to the implementation environment shown in Figure 1. The method can also be applied to other implementation environments. For example, if the implementation environment of the method includes chip 1 and chip 2, and chip 1 and chip 2 are connected, the method can be applied to either chip 1 or chip 2.

[0093] Referring to FIG1 , the implementation environment includes a first device 101 and a second device 102. The first device 101 includes a MAC function module 1011 and one or more PHY function modules 1012 ( FIG1 exemplifies the example of the first device 101 including multiple PHY function modules 1012). Signals are transmitted between the MAC function module 1011 and each PHY function module 1012 via the MII. The second device 102 includes a MAC function module 10211 and a PHY function module 1022. Signals are transmitted between the MAC function module 10211 and the PHY function module 1022 via the MII. Signals can be transmitted between the PHY function modules 1012 and 1022.

[0094] In some embodiments, the second device 102 includes an MCU 1021 and a PHY functional module 1022, and the MCU 1021 includes a MAC functional module 10211. In some embodiments, the MAC functional module 1011, the PHY functional module 1012, or one or more of the MAC functional module 10211 and the PHY functional module 1022 may be located in a separate chip, in a separate die, or in one or more cores of a multi-core chip.

[0095] The encoding method and decoding method provided in the embodiments of the present application can be applied to signal transmission between the MAC function module 1011 and the PHY function module 1012, and can also be applied to signal transmission between the MAC function module 10211 and the PHY function module 1022. The number of first devices 101, the number of MAC function modules 1011, the number of PHY function modules 1012, the number of second devices 102, the number of MCUs 1021, the number of MAC function modules 10211, and the number of PHY function modules 1022 shown in Figure 1 are only examples and are not limited in the embodiments of the present application. The above-mentioned first device 101 can be a switch or a device applied to an Internet of Things terminal, and the second device 102 can be an Internet of Things terminal or a device applied to an Internet of Things terminal. For example, the above-mentioned first device 101 and the second device 102 can be single pair Ethernet (SPE) devices or advanced physical layer (APL) devices.

[0096] The encoding method provided in the embodiment of the present application can be shown in Figure 2. Next, the method is described in conjunction with the implementation environment shown in Figure 1. The method can be applied to the MAC functional module or the PHY functional module shown in Figure 1. As shown in Figure 2, the method includes but is not limited to S201.

[0097] S201 , sending a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block having the same length, and the first block indicating the type of the second block.

[0098] In the embodiments of the present application, a block pair refers to a pair of blocks, and a transmission block pair refers to blocks transmitted in pairs. For example, the first block is a code block encoded according to the IEEE 802.3 standard, and the second block is a block of the same length as the first block. That is, the second block may include multiple consecutive bits, which are considered as a block, and the number of bits included in the second block is the same as the number of bits included in the first block.

[0099] The block pairs sent by the serial channel are obtained by encoding the signal to be transmitted. In one possible implementation, the signal to be transmitted includes at least one of a data signal and / or a first control signal, and the signal to be transmitted also includes a management signal. In this embodiment of the present application, the data signal may be a signal for transmitting data, the first control signal may be a signal for controlling the transmission of data, and the management signal may be a signal other than the data signal and the first control signal.

[0100] In one possible implementation, the signal to be transmitted is related to an Ethernet frame. For example, the signal to be transmitted includes a data signal and / or a first control signal generated based on the Ethernet frame to be transmitted. Exemplarily, when the method is applied to a MAC functional module, the MAC functional module converts the Ethernet frame to be transmitted into a parallel signal transmitted via the MII, and obtains the signal to be transmitted based on the parallel signal transmitted by the MII. The parallel signal transmitted via the MII refers to a signal transmitted via multiple pins of the MII in the IEEE802.3 standard. Exemplarily, the data signal includes part or all of the data signal transmitted by the MII, and the first control signal includes part or all of the control signal transmitted by the MII.

[0101] Alternatively, both the data signal and the first control signal can be generated based on an Ethernet frame. For example, when the method is applied to a MAC functional module, the MAC functional module obtains an Ethernet frame and generates the data signal based on the Ethernet frame. For another example, when the method is applied to a MAC functional module, the MAC functional module obtains an Ethernet frame and generates the first part of the first control signal based on the Ethernet frame. In some embodiments, the first control signal also includes a second part. The second part can be generated by the execution entity of the method. That is, if the method is applied to a MAC functional module, the MAC functional module can generate the second part; if the method is applied to a PHY functional module, the PHY functional module can generate the second part.

[0102] In an embodiment of the present application, the first part may be a signal obtained based on the content of the Ethernet frame, for example, the first part is a control signal for MII transmission obtained based on the Ethernet frame; the second part may be an error signal for transmitting error information. For example, when it is necessary to interrupt the transmission of the Ethernet frame, an error signal is generated. For another example, after the Ethernet frame transmission is completed, if it is necessary to continue to occupy the channel, an error signal is generated. The embodiment of the present application does not limit the format of the error signal. That is, if the signal to be transmitted includes a data signal, the data signal is obtained based on the Ethernet frame; if the signal to be transmitted includes a first control signal, the first control signal includes at least one of the first part obtained based on the Ethernet frame or the generated second part.

[0103] In one possible implementation, when the Ethernet frame carries data, the signal to be transmitted includes a data signal generated based on the carried data; when the Ethernet frame does not carry data, the signal to be transmitted does not include a data signal. Exemplarily, the first part of the first control signal is obtained based on other parts of the Ethernet frame except the Ethernet frame start, or based on other parts of the Ethernet frame except the Ethernet frame start and the Ethernet frame end. Exemplarily, the Ethernet frame is also used to obtain a second control signal, and the signal to be transmitted may include the second control signal. Alternatively, the Ethernet frame is also used to obtain a second control signal and a third control signal, and the signal to be transmitted may include the second control signal and the third control signal. The second control signal may be generated based on the Ethernet frame start of the Ethernet frame, and the third control signal may be generated based on the Ethernet frame end of the Ethernet frame.

[0104] In the case where the method is applied to the MII scenario, the signal to be transmitted may include a signal transmitted through the MII, for example, the management signal includes a management data input output (MDIO) signal. Exemplarily, the method is applied to a MAC functional module, and the MAC functional module includes a management entity (STA). In this case, the management signal includes an MDIO signal driven by the STA. For another example, the method is applied to a PHY functional module. In this case, the management signal includes an MDIO signal driven by the PHY functional module. The manner in which STA drives the MDIO signal can refer to the manner in which STA drives the MDIO signal in the IEEE 802.3 standard, and the manner in which the PHY functional module drives the MDIO signal can refer to the manner in which the PHY functional module drives the MDIO signal in the IEEE 802.3 standard, which will not be further described here.

[0105] Still taking the signal to be transmitted including the signal transmitted through MII as an example for explanation, when the method is applied to the MAC functional module, the data signal and the first control signal can be represented as a whole by the transmit enable signal (transmit enable, TX_EN), transmit data error prompt signal (transmit error, TX_ER) and transmit data signal (transmit data, TXD) of MII transmission in the IEEE 802.3 standard. For example, the validity and invalidity of TX_EN and the validity and invalidity of TX_ER indicate whether the signal transmitted by TXD is a data signal or a control signal. Among them, the data signal includes but is not limited to the data (data) included in the Ethernet frame, and the control signal includes but is not limited to the preamble (preamble), low power idle (low power idle, LPI) and end-of-frame delimiter (end-of-frame delimiter, EFD) during Ethernet frame transmission. When the method is applied to the PHY functional module, the data signal and the first control signal can be collectively represented by the receive data valid signal (RX_DV), the receive data error prompt signal (RX_ER), and the receive data signal (RXD) transmitted by the MII in the IEEE 802.3 standard. In other words, the validity and invalidity of RX_DV and the validity and invalidity of RX_ER indicate whether the signal transmitted by RXD is a data signal or a control signal.

[0106] After obtaining the signal to be transmitted, the signal to be transmitted can be encoded to obtain a block pair, and then the block pair is sent through the serial channel. In some embodiments, the first block indicates the type of the second block, including but not limited to at least one of the following situations:

[0107] Case 1: The first block is a data block, indicating that the second block is a data block. The value of the first block used to indicate that the second block is a data block can be set based on experience or actual needs.

[0108] Case 2, when the first block is a control block with a value of X, indicates that the second block is a control block.

[0109] Case 3, when the first block is a control block with a value of Y, indicates that the second block is a management block.

[0110] Case 4, when the first block is a control block with a value of Z, indicates that the second block is a data block.

[0111] In case 5, when the first block is a control block with a value of W, the second block is instructed to indicate COL and CRS in a bitmap manner. Indicating COL and CRS means indicating the positions of COL and CRS in the second block, rather than indicating the values ​​of COL and CRS.

[0112] The values ​​of COL and CRS can be set based on experience or actual needs. For example, a COL value of 0 indicates valid and a value of 1 indicates invalid, or a value of 0 indicates invalid and a value of 1 indicates valid. For another example, a CRS value of 0 indicates valid and a value of 1 indicates invalid, or a value of 0 indicates invalid and a value of 1 indicates valid.

[0113] In the above cases 2 to 5, the values ​​of X, Y, Z, and W can be set based on experience or actual needs, and the values ​​of X, Y, Z, and W are different. X can be represented as a first value, Y can be represented as a second value, Z can be represented as a third value, and W can be represented as a fourth value. In addition, the above-mentioned various cases can be for multiple block pairs, that is, the method provided in the embodiment of the present application can be to send multiple block pairs through a serial channel, each block pair includes a first block and a second block, and the method in which the first block in different block pairs indicates the type of the second block can be any of the above cases 1 to 5.

[0114] Exemplarily, the data block includes data signals, the control block includes control signals, and the management block includes management signals. The data block and the control block may also include other signals. For example, the data block may also include management signals, and the control block may also include data signals and management signals. That is, in some embodiments, regardless of the type of the second block, the second block includes management signals. Exemplarily, the first control signal, the second control signal, and the third control signal are collectively referred to as control signals, and the type of the control block corresponds to the type of the control signal.

[0115] In some embodiments, the management signal occupies 1 bit. The position of the 1 bit occupied by the management signal can be set based on experience or actual needs. In other embodiments, the management signal occupies 1 bit or 2 bits. The position of the 1 bit or 2 bits occupied by the management signal can be set based on experience or actual needs. In the case where the management signal occupies 2 bits, the positions occupied by the 2 bits can be adjacent or non-adjacent. The number and position of the bit positions occupied by the management signal are relatively flexible.

[0116] In one possible implementation, the length of the first block and the second block are both 5 bits. Therefore, the first block and the second block can be obtained based on the bits of TXD of one cycle respectively. The cycle in which the bits of the first block are obtained and the cycle in which the bits of the second block are obtained can be two consecutive cycles. In some embodiments, when the length of the first block and the second block are both 5 bits, the first block is a data block and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block and the second block includes a 4-bit control signal and a 1-bit management signal. In some embodiments, the first block can be encoded in 4B / 5B mode, where 4B / 5B means 4 bits / 5 bits. The content of 4B / 5B encoding can be found in the 4B / 5B encoding in the IEEE 802.3 standard and will not be repeated here.

[0117] In another possible implementation, the length of the first block and the second block are both 10 bits. Therefore, the first block and the second block can each be derived based on two cycles of TXD bits. The two cycles used to derive the bits of the first block are continuous with the two cycles used to derive the bits of the second block. In some embodiments, if the length of the first block and the second block are both 10 bits, the situation for the first block and the second block is similar to the situation where the length of the first block and the second block is both 5 bits. For example, the first block is a data block, and the second block includes a bit of data signal and b bit of management signal; or, the first block is a control block, and the second block includes a bit of data signal and b bit of management signal; or, the first block is a control block, and the second block includes a bit of control signal and b bit of management signal, where b is equal to 1 or 2, and a is equal to 10-b. For example, the first block can be encoded in 8B / 10B mode, where 8B / 10B means 8 bits / 10 bits. For details about 8B / 10B encoding, please refer to the IEEE 802.3 standard for details about 8B / 10B encoding and will not be repeated here.

[0118] In some embodiments, the second block may be encoded or may directly include the corresponding signal without encoding. In the case where the second block is obtained by encoding, the encoding method of the second block may be the same as or different from the encoding method of the first block.

[0119] Exemplarily, in a block pair, the first block is a J code block and the second block is a K code block; or the first block is a T code block and the second block is an R code block. The above-mentioned J code block, K code block, T code block and R code block can be the J code block, K code block, T code block and R code block defined in IEEE 802.3, respectively. For example, the J code block is 11000, the K code block is 10001, the T code block is 01101, and the R code block is 00111. In one possible implementation, the block pair including the J code block and the K code block is used to indicate the start of stream delimiter (SSD), and the block pair including the T code block and the R code block is used to indicate the end of stream delimiter (ESD).

[0120] In a possible implementation, if the second block includes multiple bits of the same signal, the multiple bits may be transformed bits or untransformed bits. The embodiment of the present application does not limit the transformation method, for example, the transformation method includes sequential transformation.

[0121] Next, the obtained block pair will be described by taking the case where the first block is encoded in 4B / 5B mode as an example.

[0122] The 4B / 5B encoding method specified in the IEEE 802.3 standard encodes bits based on half-byte width, and the encoded symbols obtained are used to represent data codes and control codes. The coding efficiency of 4B / 5B encoding is 4 / 5*100%=80%. Figure 3 is a schematic diagram of a block pair provided in an embodiment of the present application. Referring to Figure 3, the block pair includes a first block and a second block, the first block is encoded in a 4B / 5B manner, and the second block includes a 1-bit management signal and 4-bit other signals. The type of other signals included in the second block is indicated by the first block. As shown in Figure 3, the first block can be a data code or a control code.

[0123] In some embodiments, the bits used to obtain the first block can be indicated by TX_EN and TX_ER transmitted by the MII. For example, in FIG3 , TX_EN and TX_ER can indicate that the bits of the first half byte are bits of a data signal or bits of a control signal, and can also indicate that the bits of the second half byte are bits of a data signal or bits of a control signal. The bits of the first half byte are used to obtain the first block, and the bits of the second half byte are used to obtain the second block.

[0124] The management signal is used to obtain the second block. As shown in Figure 3, the second block includes a 1-bit management signal, which is marked as "O". As shown in Figure 3, the 1-bit management signal can be located at the highest bit of the second block. The 1-bit management signal can also be located at other positions of the second block, which is not limited in the embodiments of the present application. The second block also includes four bits of the second half byte, and these four bits can be a 4-bit data signal or a 4-bit control signal. In combination with the block pair shown in Figure 3, if the block pair is obtained based on an 8-bit data signal, or based on an 8-bit control signal, or based on a 4-bit data signal and a 4-bit control signal, the coding efficiency of the block pair is 8 / 10*100%=80%.

[0125] In an embodiment of the present application, consecutive J code blocks and K code blocks are used for stream synchronization and to represent SSD. When consecutive J code blocks and K code blocks are identified, it is determined that the Ethernet frame transmission starts. Consecutive T code blocks and R code blocks are used to represent ESD. Thus, when consecutive T code blocks and R code blocks are identified, it is determined that the Ethernet frame transmission ends. Figure 4 is a transmission schematic diagram of an Ethernet frame provided by an embodiment of the present application. As shown in Figure 4, the Ethernet frame is represented by TX_EN, TX_ER, and TXD transmitted by the MII. The Ethernet frame includes the Ethernet frame start, the Ethernet frame end, and the part of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end. The signal encoding of the Ethernet frame start of the Ethernet frame is obtained to obtain a block pair, the first block of the block pair is a J code block, and the second block is a K code block. In Figure 4, the block pair is represented as / J / K / code. The signal encoding of the Ethernet frame end of the Ethernet frame is obtained to obtain a block pair, the first block of the block pair is a T code block, and the second block is an R code block. In Figure 4, the block pair is represented as / T / R / code. A signal representing a portion of an Ethernet frame excluding an Ethernet frame start and an Ethernet frame end is encoded to obtain a plurality of block pairs. For example, if the number of bits included in the Ethernet frame is not an integer multiple of a byte, the first block of a last block pair among the plurality of block pairs is a control block, and as shown in FIG4 , the second block of the block pair is a data block.

[0126] In one possible implementation, by using consecutive J code blocks and K code blocks to represent SSD, it is possible to avoid a block pair that is not composed of a J code block and a K code block being identified as a block pair composed of a J code block and a K code block. Figure 5 is a schematic diagram of a misidentification provided by an embodiment of the present application. As shown in Figure 5, the first block is identified as a J code block, and the second block of the block pair is mistakenly identified as a K code block, or the first block is identified as a K code block, and the second block of the previous block pair of the block pair is mistakenly identified as a J code block. By using consecutive T code blocks and R code blocks to represent ESD, it is possible to avoid a block pair that is not composed of a T code block and an R code block being identified as a block pair composed of a T code block and an R code block. For example, as shown in Figure 5, the first block is identified as a T code block, and the second block of the block pair is mistakenly identified as an R code block. Continuous J code blocks and K code blocks can be represented as / J / K / code, and continuous T code blocks and R code blocks can be represented as / T / R / code. The three situations shown in Figure 5 will all lead to misidentification of block pairs, that is, the bits of the management signal are mistakenly identified as bits of the J code block, K code block, or R code block. Therefore, in the embodiment of the present application, the J code block and the K code block need to be used continuously, and the T code block and the R code block need to be used continuously to avoid misidentification of block pairs.

[0127] For example, when the first block is encoded in 4B / 5B mode, the block pair may include the content shown in Table 1 below. 1 O represents a 1-bit management signal, the value of the position represented by O can be 1, and the value of the position represented by x can be 0 or 1.

[0128] Table 1

[0129] Exemplarily, in combination with the above-mentioned Table 1, the R code block can be used alone, that is, the first block of the block pair can be an R code block, and the second block of the block pair can be Oxxxx. In an embodiment of the present application, a 5-bit block with a value of 00111 is called an R code block. If the value of the block as the first block of the block pair is 00111, the block pair can also be called an R code block. In some embodiments, if the second block of the R code block is any case other than Ox1xx in Oxxxx, the block pair represents a reset extension. If the second block of the H code block is O ERR 1 CRS COL, the second block indicates COL and CRS, the block pair represents a physical layer channel status indication, wherein ERR represents an error indication, and the block pair can also be called an H.sig code block. If the second block of the S code block is O1110, the block pair represents PHY-level collision avoidance (PLCA) BEACON (a signal type). If the second block of the S code block is O1101, the block pair represents PLCA COMMIT (a signal type). If the second block of the S-code block is any other block in Oxxxx except O1110 and O1101, the block pair indicates a set extension. In other cases where the block pair is not shown in Table 1, the first and second blocks of the block pair are both control blocks, and the block pair indicates a reserved block. Exemplarily, the reserved block pair is used to expand new Ethernet functions, which is not limited in the present embodiment.

[0130] After obtaining the block pair, the block pair is sent through a serial channel. In one possible implementation, the serial channel is used to connect the MAC layer and the PHY, and the serial channel can also be referred to as a serial channel implemented based on the MII. Exemplarily, the serial channel is implemented by a pin or a group of pins. Thus, if the serial channel is implemented by a pin, the pin is used to send the block pair. If the serial channel is implemented by multiple pins, the differential signal transmitted through the multiple pins can be first obtained based on the block pair, and then the differential signal can be transmitted through the multiple pins to implement the sending of the block pair through a serial channel. Thus, by using a serial channel to send the block pair, only fewer pins need to be set to implement the serial channel.

[0131] Figure 6 is a schematic diagram of a block pair transmission process provided by an embodiment of the present application. This method can be applied to a MAC functional module or a PHY functional module. If the method is applied to a MAC functional module, the method can transmit block pairs to the PHY functional module via a serial channel. This transmission process can correspond to the TX serial transmission shown in Figure 6. If the method is applied to a PHY functional module, the method can transmit block pairs to the MAC functional module via a serial channel. This transmission process can correspond to the RX serial transmission shown in Figure 6.

[0132] In an embodiment of the present application, when a block pair is transmitted via a serial channel, the obtained block pair can be directly transmitted, or the block pair can be processed first and then transmitted. The processing performed on the block pair includes at least one of encoding or scrambling, and the encoding includes non-return-to-zero-invert (NRZI) encoding or non-return-to-zero (NRZ) encoding.

[0133] FIG7 is a schematic diagram of another process of transmitting a block pair provided by an embodiment of the present application. As shown in FIG7 , the signal to be transmitted includes a management signal, a data signal, and a first control signal transmitted in parallel by the MII. The signal to be transmitted is encoded to obtain a block pair. The length of the first block and the second block of the block pair are both 5 bits. After obtaining the block pair, the bits of the block pair are transmitted serially via the MII. Furthermore, as shown in FIG7 , when transmitting the block pair, the bits of the block pair can be transmitted in order from high to low bit position. In some embodiments, the bits of the block pair can also be transmitted in order from low to high bit position.

[0134] Figure 8 is a process diagram of another transmission block pair provided by an embodiment of the present application. As shown in Figure 8, the bit positions corresponding to the block pairs are used as management channels and data and control channels, wherein the bit positions used as management channels carry management signals, and the bit positions used as data and control channels carry data signals or first control signals. As shown in Figure 8, the 1-bit management signal included in each block pair is used to form an MDIO signal. Figure 9 is a process diagram of another transmission block pair provided by an embodiment of the present application. As shown in Figure 9, when there is no need to transmit a data signal, that is, when the data channel is idle, the first block of the block pair is a control block, and the second block of the block pair is a management block, and the management block includes multiple bits of management signals. Referring to Figure 9, each second block includes a 4-bit management signal, and these 4 bits are represented by "0". In this case, the transmission efficiency of the management signal is higher than that of the second block including only a 1-bit management signal.

[0135] FIG10 is a schematic diagram of another block pair provided by an embodiment of the present application. For example, as shown in FIG10 , the first block of the block pair is a control block, and the second block of the block pair indicates COL and CRS. The block pair can be called an H.sig code block, wherein x shown in FIG10 can be 0 or 1. FIG11 is a schematic diagram of a process for transmitting an H.sig code block provided by an embodiment of the present application. As shown in FIG11 , when the method is applied to a PHY function module and a block pair is transmitted to a MAC function module, if the MAC function module is in a transmitting mode, that is, the MAC function module transmits a block pair to the PHY function module, the PHY function module can transmit the H.sig code block to the MAC function module through the receiving channel of the MAC function module. The transmitting channel of the MAC function module can be a channel established by the MAC function module based on the MII for transmitting block pairs to the PHY function module, and the receiving channel of the MAC function module can be a channel established by the MAC function module based on the MII for receiving block pairs transmitted by the PHY function module.

[0136] If this method is applied to the PHY functional module and the block pair is transmitted to the MAC functional module, if the MAC functional module is in the receiving mode, that is, the MAC functional module receives the block pair sent by the PHY functional module, the PHY functional module can transmit the H.sig code block to the MAC functional module through the receiving channel of the MAC functional module.

[0137] Figure 12 is a schematic diagram of another process of transmitting an H.sig code block provided by an embodiment of the present application. As shown in Figure 12, the MAC function module receives data through a receiving channel, and the data is obtained based on an Ethernet frame. For example, the data obtained based on the Ethernet frame includes / data / shown in Figure 12. As shown in Figure 12, the PHY function module also transmits a block pair for representing SSD to the MAC function module, and the block pair includes / J / K / code. The PHY function module also transmits a block pair for representing ESD to the MAC function module, and the block pair includes / T / R / code. When there is no abnormality in the data, the MAC function module can obtain COL and / or CRS based on the received Ethernet frame. The MAC function module can also receive the H.sig code block sent by the PHY function module through the receiving channel. The CRS indicated by the second block in the H.sig code block can be valid, so that the second block of the H.sig code block can indicate virtual CRS occupancy.

[0138] In the case where this method is applied to the PHY function module and a block pair is transmitted to the MAC function module, if the MAC function module is in receiving mode and the data sent by the PHY function module to the MAC function module is abnormal, the H.sig code block can be used to replace the abnormal data for transmission. Figure 13 is another schematic diagram of the process of transmitting the H.sig code block provided by an embodiment of the present application. As shown in Figure 13, the MAC function module receives data through a receiving channel, and the data is obtained based on an Ethernet frame. For example, the data obtained based on the Ethernet frame includes / data / shown in Figure 13. As shown in Figure 13, the PHY function module also transmits a block pair for representing SSD to the MAC function module, and the block pair includes / J / K / codes. The MAC function module also receives the H.sig code block through the receiving channel. The validity of the COL and CRS indicated by the second block in the H.sig code block can be set according to demand, and the H.sig code block is obtained by replacing the abnormal data. As shown in Figure 13, the PHY function module can also transmit a block pair indicating idleness to the MAC function module. Exemplarily, the processes of transmitting the H.sig code block by the PHY functional module in FIG. 11 to FIG. 13 are all implemented in a half-duplex scenario.

[0139] The above description is based on the example of encoding the first block in 4B / 5B mode. If the first block is encoded in 8B / 10B mode, the setting method of the values ​​of the first block and the second block can be the same as the setting method of the values ​​of the first block and the second block in the 4B / 5B mode, and the embodiment of the present application will not be further described.

[0140] The preceding text describes the encoding method provided in the embodiments of the present application. This embodiment also provides a decoding method, as shown in Figure 14 . This method can be applied to the MAC functional module or the PHY functional module shown in Figure 1 , and the MAC functional module and the PHY functional module can be located on the same or different chips. As shown in Figure 14 , this method includes but is not limited to S1401.

[0141] S1401 , receiving a block pair through a serial channel, the block pair including a first block and a second block, the first block and the second block having the same length, and the first block indicating a type of the second block.

[0142] In an embodiment of the present application, the serial channel for receiving the block pair is the same as the serial channel for sending the block pair in the encoding method. The content of the serial channel can be found in the relevant description of the encoding method, which will not be repeated here. For the situation of the block pair, please refer to the relevant description of the encoding method, which will not be repeated here. For example, the block pair is decoded according to the encoding method for obtaining the block pair to obtain the signal included in the block pair. Taking the process diagram of transmitting the block pair shown in Figure 7 above as an example, the bits of the block pair are transmitted serially through the MII. After the bits of the block pair are received serially through the MII, the block pair is decoded to obtain the signal to be transmitted, that is, the management signal, the data signal and the first control signal are obtained. Among them, the length of the first block and the second block of the block pair are both 5 bits.

[0143] In some embodiments, if the method is applied to a PHY functional module, the serially received block pairs are input to a reconciliation sublayer (RS), and the RS performs an operation of decoding the block pairs. By performing the operation of decoding the block pairs in the RS, the method can directly convert the signals included in the block pairs into signals that can be processed in the physical layer signaling sublayer (PLS) in the RS, without first converting the signals included in the block pairs into parallel signals transmitted by MII in the IEEE 802.3 standard and then converting the parallel signals into signals processed by the PLS. This increases the efficiency of obtaining the PLS-processed signals.

[0144] Figure 15 is a schematic diagram of a process of inputting block pairs into RS provided by an embodiment of the present application. As shown in Figure 15, the block pairs received through the serial channel enter the RS, and the RS performs an operation of decoding the block pairs. The RS also converts the signal to be transmitted into a signal processed by PLS. For example, the signal processed by PLS includes the PLS service primitives shown in Figure 15. Exemplarily, a block pair whose first block is a data block is called a data code block, and a block pair whose first block is a control block is called a control code block. The code block represented by C shown in Figure 15 can be a control code block, and the code block represented by D shown in Figure 15 can be a data code block.

[0145] As shown in Figure 15, the RS can separate the control code block and the data code block, and perform operations on the separated data code block and the control code block. The performed operations are shown in C1 and C2 in Figure 15. The embodiment of the present application does not limit the type of operation. PLS service primitives include but are not limited to PLS control request (PLS control request), PLS data request (PLS data request), PLS signal indication (PLS signal indication), PLS carrier indication (PLS carrier indication), PLS data indication (PLS data indication) and PLS control indication (PLS control indication) shown in Figure 15.

[0146] In one possible implementation, after receiving multiple block pairs, it is necessary to identify the boundaries of the multiple block pairs and synchronize them. Synchronizing the multiple block pairs includes, but is not limited to, synchronizing management channels and data channels. Synchronizing the management channels ensures the interaction of management signals, while synchronizing the data channels ensures the interaction of data signals and control signals.

[0147] Figure 16 is a schematic diagram of the process of synchronization of a management channel provided by an embodiment of the present application. Referring to Figure 16, the block pair is an I code block, which can be uniquely identified, wherein x can be 0 or 1. When the management signal does not include an MDIO signal, the value of the bit of the management signal is 1. When the management signal includes an MDIO signal and the MDIO signal starts to be transmitted, multiple bits of the management signal will have a "101" jump, which can indicate the start field. Thus, the synchronization of the management channel can be achieved by identifying the start field. For other contents of the management signal shown in Figure 16, please refer to the relevant description of the management frame corresponding to the management signal in the IEEE 802.3 standard, which will not be repeated here. In addition, a0 to a4 shown in Figure 16 are only used to illustrate the value of the physical layer address field of the management frame, and r0 to r4 are only used to illustrate the value of the register address field of the management frame, and are not used to limit the values ​​of these two fields.

[0148] In one possible implementation, the synchronization of the data channel is achieved by identifying the SSD of the Ethernet frame, that is, by identifying consecutive J code blocks and K code blocks, it can be determined that the Ethernet frame starts to be transmitted, thereby achieving synchronization of the data channel. Figure 17 is a schematic diagram of the process of synchronization of a data channel provided by an embodiment of the present application, wherein x in Figure 17 can be 1 or 0. As shown in Figure 17, the previous block pair is first identified as an I code block, and then the first block of the next block pair is identified as a J code block, and the second block is identified as a K code block. Thus, after identifying the next block pair, it can be determined that the Ethernet frame starts to be transmitted, thereby achieving synchronization of the data channel. In one possible implementation, when synchronization of the data channel has been achieved, since the bit position corresponding to the management channel is fixed in the block pair, in this case, the bit position corresponding to the management channel can be directly located, so that synchronization of the management channel can be achieved by identifying the start field of the management signal.

[0149] In the method provided in an embodiment of the present application, a block pair is transmitted through a serial channel, and the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the method provided in an embodiment of the present application, the first block and the second block have the same length, so that the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting the block pair through a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the method can be implemented based on MII, so the method can be applied to the MII scenario.

[0150] An embodiment of the present application also provides a data structure, which includes any block pair in the above method embodiments.

[0151] The present application also provides an encoding device. Figure 18 is a schematic diagram of the structure of an encoding device provided in an embodiment of the present application. The device is applied to a MAC functional module or a PHY functional module. Based on the multiple modules shown in Figure 18, the device can perform all or part of the operations in the encoding method shown in Figure 2. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown, and the present application is not limited to this. As shown in Figure 18, the device includes an encoding module 1801.

[0152] The encoding module 1801 is configured to send a block pair through a serial channel. The block pair includes a first block and a second block. The first block and the second block have the same length. The first block indicates the type of the second block.

[0153] In some embodiments, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0154] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of X, indicating that the second block is a control block.

[0155] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Y, indicating that the second block is a management block.

[0156] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Z, indicating that the second block is a data block.

[0157] In some embodiments, the first block indicates the type of the second block, including: when the first block is a control block with a value of W, indicating that the second block indicates COL and CRS in a bitmap manner. X can be represented as a first value, Y can be represented as a second value, Z can be represented as a third value, and W can be represented as a fourth value.

[0158] In some embodiments, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0159] In some embodiments, a block pair including a J code block and a K code block is used to indicate SSD, and a block pair including a T code block and an R code block is used to indicate ESD.

[0160] In some embodiments, the second block includes a management signal.

[0161] In some embodiments, the management signal occupies 1 bit.

[0162] In some embodiments, the length of the first block and the second block are both 5 bits.

[0163] In some embodiments, the first block is encoded in 4B / 5B mode.

[0164] In some embodiments, the first block is encoded in 8B / 10B mode.

[0165] In some embodiments, the second block includes a management signal, which occupies 1 bit or 2 bits.

[0166] In some embodiments, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0167] In some embodiments, the serial channel is implemented based on MII.

[0168] In some embodiments, the encoding module 1801 is configured to send block pairs from the MAC layer to the PHY via a serial channel.

[0169] In some embodiments, the encoding module 1801 is configured to send block pairs from the PHY to the MAC layer via a serial channel.

[0170] In the device provided in an embodiment of the present application, a block pair is sent through a serial channel, and the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the device, the first block and the second block have the same length, so that the first block and the second block can include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting the block pair through a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the device can be implemented based on MII, so the device can be applied to the MII scenario.

[0171] The present application also provides a decoding device. Figure 19 is a schematic diagram of the structure of a decoding device provided in an embodiment of the present application. This device is applied to a MAC functional module or a PHY functional module. Based on the multiple modules shown in Figure 19, the device can perform all or part of the operations in the decoding method shown in Figure 14. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown, and this embodiment of the present application is not limited to this. As shown in Figure 19, the device includes a decoding module 1901.

[0172] The decoding module 1901 is configured to receive a block pair through a serial channel, where the block pair includes a first block and a second block. The first block and the second block have the same length, and the first block indicates a type of the second block.

[0173] In some embodiments, the first block indicates the type of the second block, including: the first block is a data block, indicating that the second block is a data block.

[0174] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of X, indicating that the second block is a control block.

[0175] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Y, indicating that the second block is a management block.

[0176] In some embodiments, the first block indicates a type of the second block, including: if the first block is a control block with a value of Z, indicating that the second block is a data block.

[0177] In some embodiments, the first block indicates the type of the second block, including: when the first block is a control block with a value of W, indicating that the second block indicates COL and CRS in a bitmap manner. X can be represented as a first value, Y can be represented as a second value, Z can be represented as a third value, and W can be represented as a fourth value.

[0178] In some embodiments, the first block is a J code block and the second block is a K code block; or, the first block is a T code block and the second block is an R code block.

[0179] In some embodiments, a block pair including a J code block and a K code block is used to indicate SSD, and a block pair including a T code block and an R code block is used to indicate ESD.

[0180] In some embodiments, the second block includes a management signal.

[0181] In some embodiments, the management signal occupies 1 bit.

[0182] In some embodiments, the length of the first block and the second block are both 5 bits.

[0183] In some embodiments, the first block is encoded in 4B / 5B mode.

[0184] In some embodiments, the first block is encoded in 8B / 10B mode.

[0185] In some embodiments, the second block includes a management signal, which occupies 1 bit or 2 bits.

[0186] In some embodiments, the first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; or, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

[0187] In some embodiments, the serial channel is implemented based on MII.

[0188] In some embodiments, the decoding module 1901 is configured to receive a block pair sent by the PHY through a serial channel from the MAC layer.

[0189] In some embodiments, the decoding module 1901 is configured to receive a block pair sent by the MAC layer through a serial channel from the PHY.

[0190] In the device provided in an embodiment of the present application, a block pair is received via a serial channel, the block pair including a first block and a second block, the first block and the second block having the same length, and the first block indicating the type of the second block. Since the type of the second block is indicated by the first block, the second block does not need to include content indicating its own type, so that the second block can carry other content in addition to the content indicating its own type, and the scalability of the second block is high. In the device, the first block and the second block have the same length, so that the first block and the second block may include the same number of bits of the same signal, or the first block and the second block include bits of different signals and the number of bits of the included signals is the same. By transmitting the block pair via a serial channel, the number of pins of the serial channel can be less. Furthermore, the serial channel in the device can be implemented based on MII, so the device can be applied to MII scenarios.

[0191] It should be understood that the devices provided in Figures 18 and 19 above are merely examples of the division of the above functional modules when implementing their functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the devices and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0192] Referring to FIG. 20 , FIG. 20 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. For example, as shown in FIG. 20 , the computer system is a computer system 2000. Computer system 2000 may be a network device, a routing device, or a switching device. The computer system 2000 shown in FIG. 20 is used to execute the encoding method described in FIG. 2 or the decoding method shown in FIG. 14 . The computer system 2000 is, for example, a server, and may be implemented using a general bus architecture.

[0193] As shown in FIG. 20 , a computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0194] The processor 2001 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the method provided in the embodiments of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. The processor 2001 can be a combination of various logic blocks, modules and circuits that implement or execute the contents disclosed in conjunction with the embodiments of the present application, or it can be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0195] Optionally, computer system 2000 also includes a bus. The bus is used to transmit information between the components of computer system 2000. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be classified as address buses, data buses, control buses, and the like. For ease of illustration, FIG20 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0196] The memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0197] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks. The communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 2004 can include a wired communication interface or a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0198] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG20 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0199] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as processor 2001 and processor 2005 shown in FIG20 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0200] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0201] In some embodiments, the memory 2003 is used to store program code 2010, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Alternatively, the processor 2001 itself can also store program code or instructions.

[0202] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the MAC functional module and / or PHY functional module in the above-mentioned various method embodiments, and the MAC functional module and / or PHY functional module may be implemented by the processor 2001 in the computer system 2000.

[0203] The computer system 2000 may also correspond to the apparatus shown in FIG. 18 and FIG. 19 , and each functional module in the apparatus shown in FIG. 18 or FIG. 19 may be implemented by a circuit in the processor 2000 .

[0204] 2 and the decoding method shown in FIG14 are performed by hardware integrated logic circuits in the processor of the computer system 2000. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor.

[0205] FIG21 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application. The computer system is used to execute the encoding method shown in FIG2 and the decoding method shown in FIG14 . Exemplarily, the computer system is a server, and servers may vary significantly due to different configurations or performance. The computer system may include one or more processors 2101, and the one or more processors 2101 are used to implement the MAC functional module and / or PHY functional module in the method embodiment. As shown in FIG21 , the computer system may also include one or more memories 2102, wherein the one or more memories 2102 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 2101. Exemplarily, the processor 2101 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The computer system may also include other components for implementing device functions, which are not described in detail here.

[0206] An embodiment of the present application also provides a communication device, which includes: a transceiver module for performing operations related to reception and / or transmission in the encoding method shown in Figure 2; a processing module for performing other operations in the encoding method shown in Figure 2 except for operations related to reception and / or transmission. An embodiment of the present application also provides another communication device, which includes: a transceiver module for performing operations related to reception and / or transmission in the decoding method shown in Figure 14; a processing module for performing other operations in the decoding method shown in Figure 14 except for operations related to reception and / or transmission. An embodiment of the present application provides another communication device, which includes: a MAC layer circuit, the MAC layer circuit is used to perform the encoding method shown in Figure 2 and / or the decoding method shown in Figure 14. An embodiment of the present application provides another communication device, which includes: a PHY circuit, the PHY circuit is used to perform the encoding method shown in Figure 2 and / or the decoding method shown in Figure 14.

[0207] The various encoding devices, various decoding devices, and various communication devices mentioned above may all be chips or communication devices.

[0208] An embodiment of the present application provides a chip, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute the encoding method shown in FIG2 and / or the decoding method shown in FIG14. An embodiment of the present application also provides another chip, comprising: a PHY circuit, the PHY circuit being configured to execute the encoding method shown in FIG2 and / or the decoding method shown in FIG14.

[0209] An embodiment of the present application further provides a communication system, comprising a MAC layer circuit and a PHY circuit; the MAC layer circuit is configured to execute the encoding method shown in FIG2 , and the PHY circuit is configured to execute the decoding method shown in FIG14 ; alternatively, the PHY circuit is configured to execute the encoding method shown in FIG2 , and the MAC layer circuit is configured to execute the decoding method shown in FIG14 . This communication system may be implemented in a chip or a communication device.

[0210] It should be understood that the processor may be a CPU, or other general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the Advanced Reduced Instruction Set Machine (ARM) architecture.

[0211] Furthermore, in an optional embodiment, if one or more of the aforementioned computer system, communication device, chip, or communication system further includes memory, the memory may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0212] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0213] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program or computer program product. The computer program or computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0214] To clearly illustrate the interchangeability of hardware and software, the above description has generally described the steps and components of each embodiment according to their functions. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0215] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer or completely on a remote computer or server.

[0216] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0217] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0218] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0219] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0220] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0221] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first block can be referred to as a second block, and similarly, a second block can be referred to as a first block.

[0222] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0223] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, a plurality of range locks means two or more range locks. The terms "system" and "network" are often used interchangeably herein.

[0224] It should be understood that the terms used in the description of the various examples herein are for the purpose of describing specific examples only and are not intended to be limiting. As used in the description of the various examples and in the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" (also known as "includes," "including," "comprises," and / or "comprising") when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groupings thereof. It should also be understood that, depending on the context, the phrase "if it is determined that..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that..." or "in response to determining that..." or "upon detecting [a stated condition or event]," or "in response to detecting [a stated condition or event]."

[0225] It should be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "a possible implementation" mean that specific features, structures, or characteristics associated with an embodiment or implementation are included in at least one embodiment of this application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "a possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0226] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application should be included in the scope of protection of the present application.

Claims

1. A coding method, characterized in that: The method comprises: A block pair is sent through a serial channel, the block pair including a first block and a second block, the first block and the second block have the same length, and the first block indicates a type of the second block.

2. The method according to claim 1, characterized in that The first block indicates a type of the second block, including: The first block is a data block, indicating that the second block is a data block.

3. The method according to claim 1 or 2, characterized in that: The first block indicates a type of the second block, including: In a case where the first block is a control block having a first value, it is indicated that the second block is a control block.

4. The method according to any one of claims 1 to 3, characterized in that: The first block indicates a type of the second block, including: In case the first block is a control block having a second value, it is indicated that the second block is a management block.

5. The method according to any one of claims 1 to 4, characterized in that: The first block indicates a type of the second block, including: In case that the first block is a control block having a value of a third value, it is indicated that the second block is a data block.

6. The method according to any one of claims 1 to 5, characterized in that: The first block indicates a type of the second block, including: In the case where the first block is a control block whose value is a fourth value, it indicates that the second block indicates the conflict detection COL and the carrier detection CRS in a bitmap manner.

7. The method according to claim 1, characterized in that The first block is a J code block, and the second block is a K code block; Alternatively, the first block is a T code block, and the second block is an R code block.

8. The method according to claim 7, characterized in that The block pair including the J code block and the K code block is used to indicate a stream start delimiter SSD, and the block pair including the T code block and the R code block is used to indicate a stream end delimiter ESD.

9. The method according to any one of claims 1 to 8, characterized in that: The second block includes management signals.

10. The method according to claim 9, characterized in that The management signal occupies 1 bit.

11. The method according to any one of claims 1 to 10, characterized in that: The length of the first block and the length of the second block are both 5 bits.

12. The method according to any one of claims 1 to 11, characterized in that: The first block is encoded in 4B / 5B mode.

13. The method according to any one of claims 1 to 6, characterized in that: The first block is encoded in 8B / 10B mode.

14. The method according to claim 13, characterized in that The second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

15. The method according to claim 9, characterized in that The first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

16. The method according to any one of claims 1 to 15, characterized in that: The serial channel is implemented based on a medium independent interface MII.

17. The method according to any one of claims 1 to 16, characterized in that: The sending of the block pair through a serial channel comprises: The block pairs are sent from the media access control MAC layer to the physical layer PHY via a serial channel.

18. The method according to any one of claims 1 to 16, characterized in that: The sending of the block pair through a serial channel comprises: The block pairs are sent from the physical layer PHY to the media access control MAC layer via a serial channel.

19. A decoding method, characterized in that: The method comprises: A block pair is received via a serial channel, the block pair comprising a first block and a second block, the first block and the second block having the same length, and the first block indicating a type of the second block.

20. The method according to claim 19, characterized in that The first block indicates a type of the second block, including: The first block is a data block, indicating that the second block is a data block.

21. The method according to claim 19 or 20, characterized in that The first block indicates a type of the second block, including: In a case where the first block is a control block having a first value, it is indicated that the second block is a control block.

22. The method according to any one of claims 19 to 21, characterized in that: The first block indicates a type of the second block, including: In case the first block is a control block having a second value, it is indicated that the second block is a management block.

23. The method according to any one of claims 19 to 22, characterized in that: The first block indicates a type of the second block, including: In case that the first block is a control block having a value of a third value, it is indicated that the second block is a data block.

24. The method according to any one of claims 19 to 23, characterized in that: The first block indicates a type of the second block, including: In the case where the first block is a control block whose value is a fourth value, it indicates that the second block indicates the conflict detection COL and the carrier detection CRS in a bitmap manner.

25. The method according to claim 19, characterized in that The first block is a J code block, and the second block is a K code block; Alternatively, the first block is a T code block, and the second block is an R code block.

26. The method according to claim 25, characterized in that The block pair including the J code block and the K code block is used to indicate a stream start delimiter SSD, and the block pair including the T code block and the R code block is used to indicate a stream end delimiter ESD.

27. The method according to any one of claims 19 to 26, characterized in that: The second block includes management signals.

28. The method according to claim 27, characterized in that The management signal occupies 1 bit.

29. The method according to any one of claims 19 to 28, characterized in that: The length of the first block and the length of the second block are both 5 bits.

30. The method according to any one of claims 19 to 29, characterized in that: The first block is encoded in 4B / 5B mode.

31. The method according to any one of claims 19 to 24, characterized in that: The first block is encoded in 8B / 10B mode.

32. The method according to claim 31, characterized in that The second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

33. The method according to claim 27, characterized in that The first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

34. The method according to any one of claims 19 to 33, characterized in that: The serial channel is implemented based on a medium independent interface MII.

35. The method according to any one of claims 19 to 34, characterized in that: The receiving block pair through a serial channel includes: The block pairs sent by the physical layer PHY are received from the media access control MAC layer through a serial channel.

36. The method according to any one of claims 19 to 34, characterized in that: The sending of the block pair through a serial channel comprises: The block pairs sent by the medium access control MAC layer are received from the physical layer PHY through a serial channel.

37. A coding device, characterized in that: The device comprises: The encoding module is used to send a block pair through a serial channel, wherein the block pair includes a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

38. The device according to claim 37, characterized in that The first block indicates a type of the second block, including: The first block is a data block, indicating that the second block is a data block.

39. The device according to claim 37 or 38, characterized in that The first block indicates a type of the second block, including: In a case where the first block is a control block having a first value, it is indicated that the second block is a control block.

40. The device according to any one of claims 37 to 39, characterized in that The first block indicates a type of the second block, including: In case the first block is a control block having a second value, it is indicated that the second block is a management block.

41. The device according to any one of claims 37 to 40, characterized in that The first block indicates a type of the second block, including: In case that the first block is a control block having a value of a third value, it is indicated that the second block is a data block.

42. The device according to any one of claims 37 to 41, characterized in that The first block indicates a type of the second block, including: In the case where the first block is a control block whose value is a fourth value, it indicates that the second block indicates the conflict detection COL and the carrier detection CRS in a bitmap manner.

43. The device according to claim 37, characterized in that The first block is a J code block, and the second block is a K code block; Alternatively, the first block is a T code block, and the second block is an R code block.

44. The device according to claim 43, characterized in that The block pair including the J code block and the K code block is used to indicate a stream start delimiter SSD, and the block pair including the T code block and the R code block is used to indicate a stream end delimiter ESD.

45. The device according to any one of claims 37 to 44, characterized in that The second block includes management signals.

46. ​​The device according to claim 45, characterized in that The management signal occupies 1 bit.

47. The device according to any one of claims 37 to 46, characterized in that The length of the first block and the length of the second block are both 5 bits.

48. The device according to any one of claims 37 to 47, characterized in that The first block is encoded in 4B / 5B mode.

49. The device according to any one of claims 37 to 42, characterized in that The first block is encoded in 8B / 10B mode.

50. The device according to claim 49, characterized in that The second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

51. The device according to claim 45, characterized in that The first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

52. The device according to any one of claims 37 to 51, characterized in that The serial channel is implemented based on a medium independent interface MII.

53. The device according to any one of claims 37 to 52, characterized in that The encoding module is used to send a block pair from a media access control MAC layer to a physical layer PHY through a serial channel.

54. The device according to any one of claims 37 to 52, characterized in that The encoding module is used to send a block pair from a physical layer PHY to a media access control MAC layer through a serial channel.

55. A decoding device, characterized in that: The device comprises: The decoding module is used for receiving a block pair through a serial channel, wherein the block pair comprises a first block and a second block, the first block and the second block have the same length, and the first block indicates the type of the second block.

56. The device according to claim 55, characterized in that The first block indicates a type of the second block, including: The first block is a data block, indicating that the second block is a data block.

57. The device according to claim 55 or 56, characterized in that The first block indicates a type of the second block, including: In a case where the first block is a control block having a first value, it is indicated that the second block is a control block.

58. The device according to any one of claims 55 to 57, characterized in that The first block indicates a type of the second block, including: In case the first block is a control block having a second value, it is indicated that the second block is a management block.

59. The device according to any one of claims 55 to 58, characterized in that The first block indicates a type of the second block, including: In case that the first block is a control block having a value of a third value, it is indicated that the second block is a data block.

60. The device according to any one of claims 55 to 59, characterized in that The first block indicates a type of the second block, including: In the case where the first block is a control block whose value is a fourth value, it indicates that the second block indicates the conflict detection COL and the carrier detection CRS in a bitmap manner.

61. The device according to claim 55, characterized in that The first block is a J code block, and the second block is a K code block; Alternatively, the first block is a T code block, and the second block is an R code block.

62. The device according to claim 61, characterized in that The block pair including the J code block and the K code block is used to indicate a stream start delimiter SSD, and the block pair including the T code block and the R code block is used to indicate a stream end delimiter ESD.

63. The device according to any one of claims 55 to 62, characterized in that The second block includes management signals.

64. The device according to claim 63, characterized in that The management signal occupies 1 bit.

65. The device according to any one of claims 55 to 64, characterized in that The length of the first block and the length of the second block are both 5 bits.

66. The device according to any one of claims 55 to 65, characterized in that The first block is encoded in 4B / 5B mode.

67. The device according to any one of claims 55 to 60, characterized in that The first block is encoded in 8B / 10B mode.

68. The device according to claim 67, characterized in that The second block includes a management signal, and the management signal occupies 1 bit or 2 bits.

69. The device according to claim 63, characterized in that The first block is a data block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit data signal and a 1-bit management signal; Alternatively, the first block is a control block, and the second block includes a 4-bit control signal and a 1-bit management signal.

70. The device according to any one of claims 55 to 69, characterized in that The serial channel is implemented based on a medium independent interface MII.

71. The device according to any one of claims 55 to 70, characterized in that The decoding module is used to receive a block pair sent by a physical layer PHY through a serial channel from a media access control MAC layer.

72. The device according to any one of claims 55 to 70, characterized in that The decoding module is used to receive a block pair sent by a media access control MAC layer through a serial channel from a physical layer PHY.

73. A communication device, characterized in that: The device comprises: a media access control MAC layer circuit, wherein the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-17, or the decoding method as described in any one of claims 19-35.

74. A communication device, characterized in that: The device includes: a physical layer PHY circuit, and the PHY circuit is used to execute the encoding method as described in any one of claims 1-16 and 18, or the decoding method as described in any one of claims 19-34 and 36.

75. A chip, characterized in that: The chip comprises: a media access control MAC layer circuit, and the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-17, or the decoding method as described in any one of claims 19-35.

76. A chip, characterized in that: The chip comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the encoding method as described in any one of claims 1-16 and 18, or the decoding method as described in any one of claims 19-34 and 36.

77. A communication system, characterized in that: The communication system includes a media access control MAC layer circuit and a physical layer PHY circuit; the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-17, and the PHY circuit is used to execute the decoding method as described in any one of claims 19-34 and 36; or, the PHY circuit is used to execute the encoding method as described in any one of claims 1-16 and 18, and the MAC layer circuit is used to execute the decoding method as described in any one of claims 19-35.

Images