Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component that can handle a larger current.　A multilayer ceramic electronic component 100 according to the present invention comprises: a multilayer ceramic capacitor provided with a laminate and at least four or more external electrodes 30, the laminate having a first main surface 12a and a second main surface 12b opposing each other in a lamination direction, a first surface 12c and a second surface 12d opposing each other in a first direction orthogonal to the lamination direction, and a third surface 12e and a fourth surface 12f opposing each other in a second direction orthogonal to the lamination direction and the first direction, and the at least four or more external electrodes 30 being disposed on any of the first surface 12c, the second surface 12d, the third surface 12e, and the fourth surface 12f; and a junction electrode 40 disposed on the first main surface 12a or the second main surface 12b and electrically connecting at least two or more external electrodes of the same potential among the external electrodes 30. The present invention is characterized by satisfying, when the DC resistance of the multilayer ceramic capacitor 10 is denoted by Rdc1 and the DC resistance of the junction electrode 40 is denoted by Rdc3, Rdc1 ≤ Rdc3.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] For example, feedthrough three-terminal capacitors are known as decoupling capacitors used to stabilize power supply voltages supplied to integrated circuit components (ICs) operating at high speeds and as noise suppression components for power lines supplied to integrated circuit components (ICs). A feedthrough three-terminal capacitor generally includes a laminate having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other. A plurality of first internal electrode layers and second internal electrode layers are alternately arranged in the stacking direction within the laminate. Each of the first internal electrode layers has both ends extending to the first end surface and the second end surface, and each of the second internal electrode layers has both ends extending to the first side surface and the second side surface. The first internal electrode layer is connected to a first external electrode and a second external electrode, and the second internal electrode layer is connected to a third external electrode and a fourth external electrode.

[0003] When a typical feedthrough three-terminal capacitor is used as a noise filter, a direct current flows through the signal internal electrodes (first internal electrode layers). However, when the capacitance is low, the number of signal internal electrodes (first internal electrode layers) decreases, which increases the direct current resistance and causes the problem of increased heat generation from the capacitor.

[0004] Therefore, as a structure of a low-capacitance feedthrough three-terminal capacitor that can suppress an increase in capacitance while suppressing an increase in DC resistance, a structure such as that described in Patent Document 1 is provided. By increasing the number of signal internal electrodes (first internal electrode layers) and arranging the signal internal electrodes (first internal electrode layers) opposite each other, both the capacitance and the DC resistance are suppressed.

[0005] Japanese Patent Application Publication No. 9-55335

[0006] However, the structure disclosed in Patent Document 1 has the following problems: There is a limit to how many signal internal electrodes (first internal electrode layers) can be increased within a given size constraint, making it difficult to accommodate even larger currents.

[0007] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic electronic component that can handle a larger current.

[0008] A multilayer ceramic electronic component according to the present invention comprises: a laminate having first and second main surfaces that face each other in a stacking direction, first and second surfaces that face each other in a first direction orthogonal to the stacking direction, and third and fourth surfaces that face each other in a second direction orthogonal to the stacking direction and the first direction; and at least four external electrodes arranged on any of the first, second, third, or fourth surfaces, wherein joining electrodes that electrically join at least two or more of the external electrodes at the same potential are arranged on either the first or second main surface, and wherein, when the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the joining electrode is Rdc3, the multilayer ceramic electronic component satisfies the relationship Rdc1≦Rdc3.

[0009] In the multilayer ceramic electronic component according to the present invention, joining electrodes that electrically join at least two or more of the external electrodes having the same potential are arranged on either the first main surface or the second main surface, and when the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the joining electrodes is Rdc3, Rdc1≦Rdc3 is satisfied. Therefore, the combined resistance of the multilayer ceramic capacitor and the joining electrodes is smaller than the resistance of the multilayer ceramic capacitor alone, and a multilayer ceramic electronic component that can handle larger currents can be provided.

[0010] According to the present invention, a multilayer ceramic electronic component capable of handling a larger current is provided.

[0011] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 11 is a perspective view showing an external appearance of a multilayer ceramic electronic component according to a first embodiment of the present invention. 12 is a front view of the multilayer ceramic electronic component according to the first embodiment of the present invention. 13 is a plan view of the multilayer ceramic electronic component according to the first embodiment of the present invention. 14 is a cross-sectional view taken along line IV-IV in FIG. 1. 15 is a cross-sectional view taken along line V-V in FIG. 1. 16 is a cross-sectional view taken along line VI-VI in FIG. 4. 17 is a cross-sectional view taken along line VII-VII in FIG. 4. 18 is an external perspective view of a multilayer ceramic electronic component according to a modified example of the first embodiment of the present invention. 19 is a cross-sectional view in the lamination direction showing a mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention. 20 is a cross-sectional view in a second direction showing a mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention. 21 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, corresponding to the cross-sectional view of FIG. 22. 22 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, corresponding to the cross-sectional view of FIG. 23. 23 is a cross-sectional view taken along line XIII-XIII in FIG. 24. 24 is a cross-sectional view taken along line XIV-XIV in FIG. 25. 17 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of FIG. 4. FIG. 17 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of FIG. 5. FIG. 18 is an external perspective view showing a multilayer ceramic electronic component according to a second embodiment of the present invention. FIG. 19 is a front view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 20 is a side view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 21 is a plan view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 22 is a cross-sectional view taken along line XXI-XXI of FIG. 17. FIG. 23 is a cross-sectional view taken along line XXII-XXII of FIG. 17. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV of FIG. 17. FIG. 25 is a cross-sectional view taken along line XXV-XXV of FIG. 17. FIG. 26 is an exploded perspective view of the laminate shown in FIG. 17.

[0013] A. First Embodiment 1. Multilayer Ceramic Electronic Component A multilayer ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0014] Fig. 1 is an external perspective view showing a multilayer ceramic electronic component according to a first embodiment of the present invention. Fig. 2 is a front view of the multilayer ceramic electronic component according to the first embodiment of the present invention. Fig. 3 is a plan view of the multilayer ceramic electronic component according to the first embodiment of the present invention. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 1. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4.

[0015] As shown in FIGS. 1 to 3, a multilayer ceramic electronic component 100 according to an embodiment of the present invention includes a multilayer ceramic capacitor 10 and a bonding electrode 40 .

[0016] (a) Multilayer Ceramic Capacitor The following describes the multilayer ceramic capacitor 10 according to the present invention. The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30.

[0017] The laminate 12 has a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first surface 12c and a second surface 12d facing in a first direction y perpendicular to the stacking direction x, and a third surface 12e and a fourth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first main surface 12a and the second main surface 12b of the laminate 12 is the stacking direction x.

[0018] The laminate 12 has a rectangular parallelepiped shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first and second main faces 12a and 12b, the first and second faces 12c and 12d, and the third and fourth faces 12e and 12f.

[0019] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 have an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0020] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first main surface 12a side, and a second outer layer portion 20b located on the second main surface 12b side.

[0021] The first outer layer portion 20a is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first main surface 12a and the internal electrode 16 closest to the first main surface 12a.

[0022] The second outer layer portion 20b is located on the second main surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second main surface 12b and the internal electrode 16 closest to the second main surface 12b.

[0023] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0024] The inner layer portion 18 has a first inner electrode 16a having one end exposed on the first surface 12c and the other end exposed on the second surface 12d, a second inner electrode 16b having one end exposed on the third surface 12e and the other end exposed on the fourth surface 12f, and an inner layer dielectric layer 14a.

[0025] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed primarily of BaTiO3, CaTiO3, SrTiO3, and CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer portion 18 and the outer layer portions 20a and 20b. At least one of Si, Mg, Ba, and Mn may also be added as an additive. The additive is present between the ceramic particles.

[0026] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited to this, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 14a be made of a material with a high dielectric constant, such as BaTiO3.

[0027] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0028] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0029] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 5 to 1000, including the first outer layer portion 20 a and the second outer layer portion 20 b. The thickness of the dielectric layer 14 is preferably, for example, 0.3 μm to 6.0 μm.

[0030] (Internal Electrode) The internal electrode 16 includes a first internal electrode 16a and a second internal electrode 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the inner dielectric layer 14a interposed therebetween.

[0031] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first principal surface 12a and the second principal surface 12b and has a first opposing electrode portion 22a facing the second internal electrode 16b, a first extraction electrode portion 24a connected to the first opposing electrode portion 22a and extending to the first surface 12c, and a second extraction electrode portion 24b extending to the second surface 12d.

[0032] The shape of the first opposing electrode portion 22a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 22a may be tapered in plan view, with a slope increasing in either direction.

[0033] The shapes of the first lead electrode portion 24a and the second lead electrode portion 24b of the first internal electrode 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either end.

[0034] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b has a second opposing electrode portion 22b facing the first internal electrode 16a, a third extraction electrode portion 24c connected to the second opposing electrode portion 22b and extending to the third surface 12e, and a fourth extraction electrode portion 24d extended to the fourth surface 12f.

[0035] The shape of the second opposing electrode portion 22b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 22b may be tapered in plan view, with a slope increasing in either direction.

[0036] The shapes of the third lead electrode portion 24c and the fourth lead electrode portion 24d of the second internal electrode 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either end.

[0037] The laminate 12 has a side portion (W gap) 26a of the laminate 12 located between one end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the third surface 12e, and a side portion (W gap) 26b of the laminate 12 located between one end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the fourth surface 12f.

[0038] The laminate 12 also has an end (L gap) 27a of the laminate 12 located between one end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the first surface 12c, and an end (L gap) 27b of the laminate 12 located between one end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the second surface 12d.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, the height of the potential barrier at the interface between the internal electrode 16 and the dielectric layer 14 is increased, and electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b.

[0041] The total number of the first internal electrodes 16 a and the second internal electrodes 16 b is preferably 2 to 1000. The thickness of the first internal electrodes 16 a and the second internal electrodes 16 b is not particularly limited, but is preferably 0.3 μm to 6.0 μm, for example.

[0042] (External Electrodes) The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrode 16 a and the second internal electrode 16 b. The external electrodes 30 include a first external electrode 30 a, a second external electrode 30 b, a third external electrode 30 c, and a fourth external electrode 30 d.

[0043] The first external electrode 30a is disposed on the first surface 12c and connected to the first internal electrode 16a. The first external electrode 30a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f.

[0044] The second external electrode 30b is disposed on the second surface 12d and connected to the first internal electrode 16a. The second external electrode 30b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the third surface 12e, and a portion of the fourth surface 12f.

[0045] The third external electrode 30c is disposed on the third surface 12e and connected to the second internal electrode 16b. The third external electrode 30c may also be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0046] The fourth external electrode 30d is disposed on the fourth surface 12f and connected to the second internal electrode 16b. The fourth external electrode 30d may also be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0047] Although not shown, the first external electrode 30 a to the fourth external electrode 30 d are disposed on the first principal surface 12 a or the second principal surface 12 b, but they do not have to be formed on either principal surface. In this case, the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be reduced, and the multilayer ceramic capacitor 10 can be made thinner.

[0048] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected, and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0049] Each of the first external electrode 30 a, the second external electrode 30 b, the third external electrode 30 c, and the fourth external electrode 30 d preferably has a base electrode layer 32 and a plating layer. The plating layer preferably has a lower plating layer 34 and an upper plating layer 36.

[0050] In other words, the first external electrode 30a preferably has a first base electrode layer 32a, a first lower plating layer 34a, and a first upper plating layer 36a. The second external electrode 30b preferably has a second base electrode layer 32b, a second lower plating layer 34b, and a second upper plating layer 36b. The third external electrode 30c preferably has a third base electrode layer 32c, a third lower plating layer 34c, and a third upper plating layer 36c. The fourth external electrode 30d preferably has a fourth base electrode layer 32d, a fourth lower plating layer 34d, and a fourth upper plating layer 36d.

[0051] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0052] First, a description will be given of the case where the base electrode layer 32 is formed by a baking layer. The baking layer contains a metal component and a glass component. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. Furthermore, the baking layer may be a multi-layer structure.

[0053] Furthermore, when the base electrode layer 32 is formed by a baked layer, it may be configured to contain a metal and the same type of component as the dielectric layer 14. In this case, if the dielectric layer 14 is made of a CaZrO system, the same type of component would be Ca or Zr.

[0054] The baked layer is formed by applying and baking a conductive paste containing a glass component and a metal component to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 to obtain the laminate 12 and then applying and baking the conductive paste. When simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip, it is preferable to add a dielectric component instead of the glass component, or to add both components to form the baked layer.

[0055] At the center of the stacking direction x connecting the first main surface 12a and the second main surface 12b of the first baking layer and the second baking layer located on the first surface 12c and the second surface 12d, the thickness in the first direction y connecting the first surface 12c and the second surface 12d of the first baking layer and the second baking layer (end surface center thickness) is preferably, for example, 5 μm or more and 55 μm or less.

[0056] Furthermore, when a base electrode layer (baked layer) is also provided on a portion of the first principal surface 12a or a portion of the second principal surface 12b, the thickness in the stacking direction x connecting the first principal surface 12a and the second principal surface 12b of the first baked layer and the second baked layer at the center in the first direction y connecting the first surface 12c and the second surface 12d of the first baked layer and the second baked layer located on the first principal surface 12a or the second principal surface 12b is preferably, for example, 1 μm or more and 30 μm or less.

[0057] Next, a case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may also completely cover the baked layer, or may cover only a portion of the baked layer. Furthermore, the conductive resin layer may be a multi-layer structure.

[0058] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0059] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0060] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0061] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a current path is formed inside the conductive resin layer.

[0062] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0063] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0064] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0065] The thickness of the thickest part of the conductive resin layer is preferably, for example, 5 μm or more and 50 μm or less.

[0066] Next, a case where the base electrode layer 32 is formed as a thin film layer will be described. The thin film layer may be formed on the surface of the laminate 12. When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0067] Alternatively, the base electrode layer 32 may be formed of a plating layer. In this case, the plating preferably contains at least one metal selected from Cu, Ni, Sn, Pd, Au, Ag, Bi, Zn, etc., or an alloy containing such a metal. The plating layer preferably does not contain glass, and the metal content per unit area of ​​the plating layer is preferably 99% by volume or more.

[0068] (Underlayer plating layer) The underlayer plating layer 34 includes a first underlayer plating layer 34a arranged to cover the first underlayer electrode layer 32a, a second underlayer plating layer 34b arranged to cover the second underlayer electrode layer 32b, a third underlayer plating layer 34c arranged to cover the third underlayer electrode layer 32c, and a fourth underlayer plating layer 34d arranged to cover the fourth underlayer electrode layer 32d.

[0069] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0070] The lower plating layer 34 is preferably Ni plating. When the lower plating layer 34 is Ni plating, the base electrode layer 32 can be prevented from being eroded by solder when the multilayer ceramic capacitor 10 is mounted.

[0071] The thickness of the lower plating layer 34 is preferably, for example, 1 μm or more and 8 μm or less.

[0072] (Upper layer plating layer) The upper layer plating layer 36 includes a first upper layer plating layer 36a arranged to cover the first lower layer plating layer 34a, a second upper layer plating layer 36b arranged to cover the second lower layer plating layer 34b, a third upper layer plating layer 36c arranged to cover the third lower layer plating layer 34c, and a fourth upper layer plating layer 36d arranged to cover the fourth lower layer plating layer 34d.

[0073] The upper plating layer 36 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0074] Furthermore, the upper plating layer 36 is preferably Sn plated. When the upper plating layer 36 is Sn plated, the wettability of the solder when mounting the multilayer ceramic capacitor 10 is improved, making it easier to mount.

[0075] The thickness of the upper plating layer 36 is preferably, for example, 1 μm or more and 8 μm or less.

[0076] The plating layer has a two-layer structure consisting of a lower plating layer 34 and an upper plating layer 36, but is not limited to this and may have a three-layer structure. When the plating layer has a three-layer structure, it is preferable that the layers are Sn-plated, Ni-plated, and Sn-plated from the laminate 12 side.

[0077] The dimension in the first direction y of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension L. The dimension L is preferably 0.51 mm or more and 3.2 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension W. The dimension W is preferably 0.21 mm or more and 2.5 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension T. The dimension T is preferably 0.05 mm or more and 2.5 mm or less.

[0078] Next, the joining electrode 40 will be described. A joining electrode 40 is arranged on either the first main surface 12 a or the second main surface 12 b of the laminate 12, and electrically joins at least two or more of the external electrodes 30 that have the same potential.

[0079] In the multilayer ceramic electronic component 100 of the first embodiment, the joining electrode 40 electrically joins the first external electrode 30 a and the second external electrode 30 b of the multilayer ceramic capacitor 10 on the first main surface 12 a of the laminate 12 .

[0080] The bonding electrode 40 includes a bonding base electrode 42, a bonding underlayer plating layer 44 covering the bonding base electrode 42, and a bonding upper layer plating layer 46 covering the bonding underlayer plating layer 44. The bonding electrode 40 may be configured only by the bonding base electrode 42. In this case, the bonding base electrode 42 is formed by, for example, a sputtering electrode.

[0081] When the DC resistance of the multilayer ceramic capacitor 10 is Rdc1 and the DC resistance of the bonding electrode 40 is Rdc3, it is preferable that Rdc1≦Rdc3. If Rdc1>Rdc3, the current containing noise components is less likely to flow through the capacitor due to the voltage division effect, and the noise removal effect is reduced.

[0082] Rdc3 is preferably 1.0 to 5.0 times Rdc1. Basically, lowering the combined resistance makes it easier for current to flow. However, if Rdc3 is more than 5.0 times Rdc1, the effect of making it easier for current to flow is reduced.

[0083] The thickness t1 of the bonding electrode 40 in the stacking direction x is preferably smaller than the thickness t2 of the external electrode 30 arranged on the same plane as the bonding electrode 40 in the stacking direction x.

[0084] The thicker the joining electrode 40 is in the stacking direction x, the smaller the Rdc3 can be. However, if the joining electrode 40 is larger than the dimension in the stacking direction x of the external electrode 30 arranged on the main surface, the dimension in the stacking direction x of the entire multilayer ceramic capacitor 10 becomes large. Therefore, by making the thickness in the stacking direction x of the joining electrode 40 smaller than the thickness in the stacking direction x of the external electrode 30 arranged on the same plane as the joining electrode 40, it is possible to increase Rdc3 and allow a large current to flow through the multilayer ceramic capacitor 10 without the dimension in the stacking direction x of the multilayer ceramic capacitor 10 becoming too large.

[0085] The Rdc of each of the bonding electrode 40 and the multilayer ceramic capacitor 10 is measured as follows. That is, first, the external electrode 30 of the multilayer ceramic capacitor 10 connected to the bonding electrode 40 is removed from the surface of the laminate 12, for example, by laser, polishing, or solvent treatment. At this time, it is sufficient to remove either one of the external electrodes 30 connected to the bonding electrode 40 from the surface of the laminate 12. Thereafter, the bonding electrode 40 and the multilayer ceramic capacitor 10 are each measured using a four-terminal method.

[0086] The main component of the bonding electrode 40 is preferably a metal such as Cu, NiCr, or NiCu, but is not limited to this.

[0087] The porosity of the bonding base electrode 42 of the bonding electrode 40 is preferably greater than the porosity of the base electrode layer 32 of the external electrode 30. By making the porosity of the bonding base electrode 42 greater than the porosity of the base electrode layer 32, Rdc3 can be increased. When the bonding under-layer plating layer 44 and the bonding upper-layer plating layer 46 are disposed, the porosity is defined as the area obtained by binarizing the voids and other areas when viewed in the stacking direction x of the bonding base electrode 42 and the base electrode layer 32 after the bonding under-layer plating layer 44 and the bonding upper-layer plating layer 46 are peeled off.

[0088] If the T dimension is 100 μm or less, for example, 50 μm or less, the flexural strength will be low. Therefore, by arranging the bonding electrode 40 on either the first main surface 12 a or the second main surface 12 b of the laminate 12, the flexural strength of the multilayer ceramic capacitor 10 can be improved.

[0089] 1 is rectangular, the shape is not limited thereto, and the width of the central region in the first direction y may be smaller or larger than the width of the end portions. Also, the bonding electrode 40 may have a tapered shape in which the dimension in the second direction z becomes smaller from one end side to the other end side or from the other end side to the one end side, or may be formed in a tapered, stepped shape.

[0090] 1, a joining electrode 40 that electrically joins the first external electrode 30a and the second external electrode 30b is disposed on the first main surface 12a. When the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the joining electrode 40 is Rdc3, Rdc1≦Rdc3. Therefore, the combined resistance of the multilayer ceramic capacitor 10 and the joining electrode 40 is smaller than the resistance of the multilayer ceramic capacitor 10 alone, and therefore a multilayer ceramic capacitor 10 that can handle larger currents can be provided.

[0091] Next, an example of a multilayer ceramic electronic component 100A according to a first modification of the first embodiment of the present invention will be described. Fig. 8 is a perspective view of the appearance of the multilayer ceramic electronic component according to the modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 7, and detailed descriptions thereof will be omitted.

[0092] As shown in FIG. 8, a multilayer ceramic electronic component 100A according to the modified example includes a multilayer ceramic capacitor 10 and a bonding electrode 40A.

[0093] In the first embodiment, in the multilayer ceramic electronic component 100A, the joining electrode 40A electrically joins the third external electrode 30c and the fourth external electrode 30d of the multilayer ceramic capacitor 10 on the first main surface 12a of the laminate 12.

[0094] When the DC resistance of the multilayer ceramic capacitor 10 is Rdc1 and the DC resistance of the bonding electrode 40A is Rdc3, it is preferable that Rdc1≦Rdc3.

[0095] 2. Mounting Structure of Multilayer Ceramic Electronic Component Next, a mounting structure 300 for the multilayer ceramic electronic component 100 according to the embodiment of the present invention will be described.

[0096] 9 and 10 are cross-sectional views in a lamination direction showing the mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention, respectively.

[0097] 9 and 10 , a mounting structure 300 for a multilayer ceramic electronic component according to this embodiment includes a multilayer ceramic electronic component 100 according to this embodiment and a mounting substrate 60. The mounting substrate 60 includes a substrate core material 62 and connecting conductors (conductor lands) 64.

[0098] The core material 62 of the substrate is, for example, a substrate made of a material in which a base material made of a mixture of glass cloth and nonwoven glass cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The core material 62 of the substrate may be a single-layer substrate or a substrate made of multiple laminated layers. The thickness of the core material 62 of the substrate is not particularly limited, but is preferably, for example, 200 μm to 800 μm.

[0099] One main surface of the core material 62 of the substrate is provided with conductor lands 64 and constitutes a substrate-side mounting surface 62 a on which the multilayer ceramic electronic component 100 is mounted.

[0100] The conductor lands 64 include a first conductor land 64a, a second conductor land 64b, a third conductor land 64c, and a fourth conductor land 64d.

[0101] The first conductor land 64a is a portion that is electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 66. The second conductor land 64b is a portion that is electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 66. The third conductor land 64c is a portion that is electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 66. The fourth conductor land 64d is a portion that is electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 66.

[0102] The conductor land 64 may be provided on the main surface of the core material 62 of the substrate opposite to the substrate-side mounting surface 62a.

[0103] The material of the conductor lands 64 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. The thickness of the conductor lands 64, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material 66 can be, for example, a high-heat-resistant epoxy adhesive or solder.

[0104] In the above description, the mounting substrate 60 corresponds to the mounting substrate of the present invention. The core material 62 of the substrate corresponds to the core material of the substrate of the present invention. The substrate-side mounting surface 62a corresponds to the mounting surface of the present invention. The multiple conductor lands 64 correspond to the multiple connecting conductors of the present invention. However, the connecting conductors of the present invention are not limited to so-called lands or other conductors that are provided between the multilayer ceramic capacitor 10 and the mounting substrate 60 and can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0105] Furthermore, in the mounting structure 300 for a multilayer ceramic electronic component, the first external electrode 30 a and the second external electrode 30 b are connected to the anode, which shortens the current distance and prevents an increase in insulation resistance while ensuring moisture resistance reliability.

[0106] In the mounting structure 300 of the multilayer ceramic electronic component shown in FIGS. 9 and 10 , the multilayer ceramic electronic component 100 is preferably mounted so that the bonding electrodes 40 of the multilayer ceramic electronic component 100 are disposed facing away from the mounting substrate 60. That is, the bonding electrodes 40 of the multilayer ceramic electronic component 100 are preferably disposed on the first main surface (non-mounting surface) of the multilayer ceramic capacitor 10, and the multilayer ceramic capacitor 10 of the multilayer ceramic electronic component 100 is preferably mounted on the mounting substrate 60 side. Mounting in this manner eliminates the need to increase the distance between the multilayer ceramic capacitor 10 and the mounting substrate 60, making it easier to achieve a low ESL effect. Furthermore, mounting can be performed without affecting the mounting of the multilayer ceramic electronic component 100 to the mounting substrate.

[0107] 3. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor 10 according to the present invention will now be described.

[0108] (a) Manufacturing Method of Multilayer Ceramic Capacitor First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0109] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are laminated together to form a portion that becomes the inner layer portion 18.

[0110] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first main surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second main surface 12b. In this way, a laminated sheet is produced.

[0111] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0112] The laminated block is then cut to a predetermined size to obtain laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0113] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0114] Next, a bonding electrode 40 is formed on the surface of the first main surface 12a of the laminate 12. To form the bonding electrode 40, a bonding base electrode 42 is formed using a method of applying a conductive paste by extruding it through a slit or a screen printing method.

[0115] Then, a first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first surface 12c and the second surface 12d of the laminate 12 on which the bonding electrode 40 is formed. Furthermore, a third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the third surface 12e and the fourth surface 12f of the laminate 12 obtained by firing.

[0116] When a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the base electrode layer 32.

[0117] More specifically, first, the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d are formed on the third surface 12e and the fourth surface 12f of the laminate 12 obtained by firing.

[0118] Here, various methods can be used to form the third and fourth base electrode layers 32c and 32d. For example, a method of applying a conductive paste by extruding it through a slit can be used. In this method, by increasing the amount of conductive paste extruded, the third and fourth base electrode layers 32c and 32d can be formed not only on the third surface 12e and the fourth surface 12f, but also on a portion of the first principal surface 12a and a portion of the second principal surface 12b.

[0119] Alternatively, the electrodes may be formed by a roller transfer method. In the case of the roller transfer method, when the third base electrode layer 32c and the fourth base electrode layer 32d are formed not only on the third surface 12e and the fourth surface 12f but also on a part of the first main surface 12a and a part of the second main surface 12b, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0120] Next, the first underlying electrode layer 32a of the first external electrode 30a and the second underlying electrode layer 32b of the second external electrode 30b are formed on the first surface 12c and the second surface 12d of the laminate 12 obtained by firing.

[0121] Here, various methods can be used to form the first and second base electrode layers 32 a and 32 b. For example, by using a method such as dipping, the first and second base electrode layers 32 a and 32 b can be formed so as to extend not only to the first surface 12 c and the second surface 12 d but also to parts of the first and second main surfaces 12 a and 12 b, parts of the third and fourth surfaces 12 e and 12 f.

[0122] In this embodiment, the first and second underlying electrode layers 32a and 32b, and the third and fourth underlying electrode layers 32c and 32d may be fired simultaneously.

[0123] When forming a conductive resin layer as the base electrode layer 32, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed alone directly on the laminate without forming a baked layer.

[0124] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal onto the baking layer or the laminate, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0125] The conductive resin paste can be applied by, for example, a method of applying the conductive paste by extruding it through a slit or a roller transfer method, similar to the method of forming the base electrode layer 32 as a baked layer.

[0126] Thereafter, a lower layer plating layer 34 is formed on the base electrode layer 32 and the surface of the laminate 12, and an upper layer plating layer 36 is formed to cover the lower layer plating layer 34. Simultaneously, a bonding lower layer plating layer 44 is formed on the surface of the bonding base electrode 42, and a bonding upper layer plating layer 46 is formed to cover the bonding lower layer plating layer 44. More specifically, a Ni plating layer is formed as the lower layer plating layer 34 on the base electrode layer 32. Then, a Sn plating layer is formed as the upper layer plating layer 36 on the surface of the lower layer plating layer 34. Similarly, a Ni plating layer is formed as the bonding lower layer plating layer 44 on the bonding base electrode 42, and a Sn plating layer is formed as the bonding upper layer plating layer 46 on the surface of the bonding lower layer plating layer 44. Either electrolytic plating or electroless plating may be used for plating. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0127] In this manner, the multilayer ceramic electronic component 100 shown in FIG. 1 can be manufactured.

[0128] Alternatively, the fired laminate 12 may be manufactured, and the external electrodes 30 may be formed on the laminate 12, after which the bonding electrodes 40 may be formed.

[0129] That is, after the external electrodes 30 are formed and the multilayer ceramic capacitor 10 is obtained, the bonding electrodes 40 are formed on the first main surface 12a of the laminate 12 of the multilayer ceramic capacitor 10 by screen printing or sputtering.

[0130] In this way, the multilayer ceramic electronic component 100 shown in FIG. 1 can be manufactured.

[0131] 4. Modifications of the Multilayer Ceramic Capacitor According to the First Embodiment Hereinafter, modifications (first modification and second modification) of the multilayer ceramic capacitor in the multilayer ceramic electronic component according to the first embodiment will be described. In addition, in each of these modifications, components corresponding to those in the above embodiment will be given the same reference numerals, and detailed description thereof will be omitted.

[0132] (1) First Modification A multilayer ceramic capacitor 10A according to a first modification of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12A of the multilayer ceramic capacitor 10A. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0133] Fig. 11 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 4. Fig. 12 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 5. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 11. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 11.

[0134] The multilayer ceramic capacitor 10A includes a laminate 12A and external electrodes 30.

[0135] The laminate 12A includes a first main surface 12a and a second main surface 12b that face the stacking direction x, a first surface 12c and a second surface 12d that face the first direction y that is perpendicular to the stacking direction x, and a third surface 12e and a fourth surface 12f that face the second direction z that is perpendicular to the stacking direction x and the first direction y.

[0136] The laminate 12A has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0137] At the ends (L gap) 27a, 27b of the laminate 12A, a first dummy electrode 25a is arranged so as to be exposed on the first surface 12c, and a second dummy electrode 25b is arranged so as to be exposed on the second surface 12d.

[0138] The first dummy electrode 25a and the second dummy electrode 25b are preferably arranged on the same plane as the second internal electrode 16b and have the same thickness as the second internal electrode 16b.

[0139] The current path can be shortened by reducing the coverage of the first dummy electrode 25a and the second dummy electrode 25b.

[0140] The first dummy electrode 25 a and the second dummy electrode 25 b may be disposed on the first outer layer portion 20 a and the second outer layer portion 20 b. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the ends (L gaps) 27 a and 27 b of the laminate 12 in the stacking direction x. By disposing them in this manner, when a plating layer is provided without providing a base electrode layer 32, it becomes easier to form the plating layer.

[0141] In addition, when the first dummy electrode 25a and the second dummy electrode 25b are arranged on the same plane as the second internal electrode 16b, the first dummy electrode 25a and the second dummy electrode 25b can be arranged on the same plane as the second internal electrode 16b by printing the first dummy electrode 25a and the second dummy electrode 25b together with the second internal electrode 16b when printing the second internal electrode 16b.

[0142] In addition, a third dummy electrode 25c may be arranged on the sides (W gap) 26a, 26b of the laminate 12A so as to be exposed on the third surface 12e, and a fourth dummy electrode 25d may be arranged so as to be exposed on the fourth surface 12f.

[0143] The third dummy electrode 25c and the fourth dummy electrode 25d are preferably arranged on the same plane as the first internal electrode 16a and have the same thickness as the first internal electrode 16a.

[0144] The current path can be shortened by reducing the coverage of the third dummy electrode 25c and the fourth dummy electrode 25d.

[0145] The third dummy electrode 25c and the fourth dummy electrode 25d may be disposed on the first outer layer portion 20a and the second outer layer portion 20b. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the side portions (W gaps) 26a and 26b of the laminate 12A in the stacking direction x. By disposing them in this manner, when a plating layer is provided without providing a base electrode layer 32, it is easier to form the plating layer.

[0146] In addition, when the third dummy electrode 25c and the fourth dummy electrode 25d are arranged on the same plane as the first internal electrode 16a, the third dummy electrode 25c and the fourth dummy electrode 25d can be arranged on the same plane as the first internal electrode 16a by printing the third dummy electrode 25c and the fourth dummy electrode 25d together with the second internal electrode 16b when printing the first internal electrode 16a.

[0147] In the multilayer ceramic capacitor 10A shown in FIGS. 11 to 14, the first dummy electrode 25a, the second dummy electrode 25b, the third dummy electrode 25c, and the fourth dummy electrode 25d are arranged on the side portions (W gaps) 26a, 26b of the laminate 12A and the end portions (L gaps) 27a, 27b of the laminate 12A, and therefore distortion during pressing can be prevented.

[0148] 11 to 14, the first dummy electrode 25a, the second dummy electrode 25b, the third dummy electrode 25c, and the fourth dummy electrode 25d are arranged on the side portions (W gaps) 26a, 26b of the laminate 12A and the end portions (L gaps) 27a, 27b of the laminate 12A, but this is not limitative. That is, the first dummy electrode 25a and the second dummy electrode 25b may be arranged on the end portions (L gaps) 27a, 27b of the laminate 12A, and the third dummy electrode 25c and the fourth dummy electrode 25d may not be arranged on the side portions (W gaps) 26a, 26b of the laminate 12A. On the other hand, the third dummy electrode 25c and the fourth dummy electrode 25d may be arranged on the side portions (W gaps) 26a and 26b of the laminate 12A, and the first dummy electrode 25a and the second dummy electrode 25b may not be arranged on the end portions (L gaps) 27a and 27b of the laminate 12A.

[0149] (2) Second Modification A multilayer ceramic capacitor 10B according to a second modification of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12B of the multilayer ceramic capacitor 10B. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0150] Fig. 15 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 4. Fig. 16 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the first embodiment of the present invention, and corresponds to the cross-sectional view of Fig. 5.

[0151] The laminate 12B includes a first main surface 12a and a second main surface 12b that face the stacking direction x, a first surface 12c and a second surface 12d that face the first direction y that is perpendicular to the stacking direction x, and a third surface 12e and a fourth surface 12f that face the second direction z that is perpendicular to the stacking direction x and the first direction y.

[0152] The laminate 12B has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0153] The laminate 12B has an inner layer portion 18, and a first outer layer portion 20a and a second outer layer portion 20b arranged to sandwich the inner layer portion 18 in the stacking direction x.

[0154] The inner dielectric layer 14a of the inner layer portion 18 may be disposed so as to be sandwiched between the first inner electrodes 16a. In this case, the first inner electrodes 16a are disposed continuously with the inner dielectric layer 14a of the inner layer portion 18 interposed therebetween.

[0155] Furthermore, the inner dielectric layer 14a of the inner layer portion 18 may be disposed so as to be sandwiched between the second inner electrodes 16b. In this case, the second inner electrodes 16b are disposed continuously via the dielectric layer 14 of the inner layer portion 18. The inner dielectric layer 14a of the inner layer portion 18 is composed of dielectric ceramic particles having a perovskite structure, with a perovskite-type compound containing, for example, Ba and Ti as the main component. At least one of Si, Mg, Ba, and Mn may be added as an additive to these main components. The additive is present between the ceramic particles.

[0156] The inner layer portion 18 of the laminate 12B has a capacitance forming portion 28 where the first inner electrode 16a and the second inner electrode 16b face each other with the dielectric layer 14 interposed therebetween to form a capacitance, and an inner electrode laminate portion 29 where two or more first inner electrodes 16a are continuously laminated. The capacitance forming portion 28 is what allows the multilayer ceramic capacitor 10B to exhibit its capacitor characteristics.

[0157] Moreover, the internal electrode laminate portion 29 is arranged so as to be divided by the second internal electrodes 16b into a plurality of internal electrode laminate portions 29. This disperses the aggregate of the first internal electrodes 16a, thereby improving the heat dissipation effect and achieving the effect of suppressing temperature rise.

[0158] As shown in Figures 15 and 16, in the multilayer ceramic capacitor 10B, the internal electrode laminate portion 29 is divided by two second internal electrodes 16b, and the internal electrode laminate portion 29 is divided into a first internal electrode laminate portion 29a, a second internal electrode laminate portion 29b, and a third internal electrode laminate portion 29c.

[0159] The second internal electrode 16b arranged so as to divide the internal electrode laminated portion 29, which is a region where two or more first internal electrodes 16a are continuously laminated, may be arranged singly. This makes it possible to laminate more first internal electrodes 16a, thereby obtaining the effect of reducing DC resistance.

[0160] Furthermore, the second internal electrodes 16b arranged so as to divide the internal electrode laminated portion 29, which is a region where two or more first internal electrodes 16a are continuously laminated, may be arranged by continuously laminating two or more second internal electrodes 16b. This makes it possible to ensure more sufficient connectivity between the second internal electrodes 16b and the external electrode 30 even if the number of second internal electrodes 16b is reduced.

[0161] The second internal electrode 16b may be disposed in an internal electrode laminate portion 29, which is a region where two or more first internal electrodes 16a located on the first main surface 12a side of the laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 29a and the first main surface 12a, and in an internal electrode laminate portion 29, which is a region where two or more first internal electrodes 16a located on the second main surface 12b side of the laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 29c and the second main surface 12b. This allows the capacitance forming portion 28 to be formed also in the vicinity of the first outer layer portion 20a and the second outer layer portion 20b, thereby obtaining part of the capacitance, shortening the current path to the mounting board and achieving the effect of low ESL.

[0162] Furthermore, the second internal electrode 16b does not have to be disposed in the internal electrode laminate portion 29, which is a region where two or more first internal electrodes 16a located on the first main surface 12a side of the laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 29a and the first main surface 12a, or in the internal electrode laminate portion 29, which is a region where two or more first internal electrodes 16a located on the second main surface 12b side of the laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 29c and the second main surface 12b. This increases the distance from the surface of the laminate 12B to the capacitance forming portion 28 where capacitance is formed, and provides the effect of making it less likely for insulation resistance degradation to occur even if a crack occurs from the surface of the laminate 12B due to an external load.

[0163] The thickness of the inner dielectric layer 14a adjacent to the second inner electrode 16b is preferably greater than the thickness of the inner dielectric layer 14a sandwiched between the first inner electrodes 16a, which makes it possible to stack more first inner electrodes 16a and further increase the effect of reducing DC resistance.

[0164] It is also preferable that the thickness of the second internal electrode 16b be greater than the thickness of the first internal electrode 16a, so that even when the capacitance is further reduced, connectivity between the third lead electrode portion 24c of the second internal electrode 16b and the third external electrode 30c disposed on the first surface 12c can be ensured, and connectivity between the fourth lead electrode portion 24d of the second internal electrode 16b and the fourth external electrode 30d disposed on the second surface 12d can be ensured.

[0165] B. Second Embodiment 1. Multilayer Ceramic Electronic Component Next, an example of a multilayer ceramic electronic component 500 according to a second embodiment of the present invention will be described.

[0166] FIG. 17 is an external perspective view showing a multilayer ceramic electronic component according to a second embodiment of the present invention. FIG. 18 is a front view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 19 is a side view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 20 is a plan view of the multilayer ceramic electronic component according to the second embodiment of the present invention. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 17. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 17. FIG. 23 is a cross-sectional view taken along line XXI-XXI in FIG. 17. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 17. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 17. FIG. 26 is an exploded perspective view of the laminate shown in FIG. 17.

[0167] The multilayer ceramic electronic component 500 includes a multilayer ceramic capacitor 510 and a bonding electrode 540 .

[0168] The multilayer ceramic capacitor 510 includes a laminate 512 and a plurality of external electrodes 530 .

[0169] The laminate 512 has a first main surface 512a and a second main surface 512b facing in a stacking direction x, a first surface 512c and a second surface 512d facing in a first direction y perpendicular to the stacking direction x, and a third surface 512e and a fourth surface 512f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first main surface 512a and the second main surface 512b of the laminate 512 is the stacking direction x.

[0170] Furthermore, it is preferable that the corners and ridges of the laminate 512 are rounded. Note that the corners refer to the portions where three adjacent surfaces of the laminate 512 intersect, and the ridges refer to the portions where two adjacent surfaces of the laminate 512 intersect. Furthermore, unevenness may be formed on part or all of the first main surface 512a and the second main surface 512b, the first surface 512c and the second surface 512d, and the third surface 512e and the fourth surface 512f.

[0171] The laminate 512 includes a plurality of dielectric layers 514 and a plurality of internal electrodes 516. The dielectric layers 514 include an inner dielectric layer 514a and an outer dielectric layer 514b. The internal electrodes 516 include a first internal electrode 516a and a second internal electrode 516b.

[0172] The laminate 512 also has an inner layer portion 518, a first outer layer portion 520a located on the first main surface 512a side, and a second outer layer portion 520b located on the second main surface 512b side.

[0173] The first outer layer portion 520a is located on the first main surface 512a side of the laminate 512 and is an aggregate of multiple outer layer dielectric layers 514b located between the first main surface 512a and the internal electrode 516 closest to the first main surface 512a.

[0174] The second outer layer portion 520b is located on the second main surface 512b side of the laminate 512 and is an aggregate of multiple outer layer dielectric layers 514b located between the second main surface 512b and the internal electrode 516 closest to the second main surface 512b.

[0175] The region sandwiched between the first outer layer portion 520 a and the second outer layer portion 520 b is the inner layer portion 518 .

[0176] The inner layer portion 518 has a first internal electrode 516a having one end exposed to the first surface 512c and the third surface 512e and the other end exposed to the second surface 512d and the fourth surface 512f, a second internal electrode 516b having one end exposed to the first surface 512c and the third surface 512e and the other end exposed to the second surface 512d and the third surface 512e, and an inner layer dielectric layer 514a.

[0177] The dielectric layer 514 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 514a and the outer dielectric layer 514b may be made of the same dielectric material or different dielectric materials.

[0178] For example, if the inner dielectric layer 514a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 516a and the second inner electrode 516b. Furthermore, without being limited to this, the inner dielectric layer 514a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 514a be made of a material with a high dielectric constant, such as BaTiO3.

[0179] The dielectric layer 514 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0180] The thinner the dielectric layer 514, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0181] The number of laminated dielectric layers 514 is not particularly limited, but is preferably 5 to 1000, including the first outer layer portion 520 a and the second outer layer portion 520 b. The thickness of the dielectric layer 514 is preferably, for example, 0.3 μm to 6.0 μm.

[0182] (Internal Electrode) The internal electrode 516 includes a plurality of first internal electrodes 516a and a plurality of second internal electrodes 516b. The first internal electrodes 516a and the second internal electrodes 516b are alternately stacked with the dielectric layer 514 interposed therebetween.

[0183] The first internal electrode 516a is disposed on the surface of the inner dielectric layer 514a. The first internal electrode 516a faces the first main surface 512a and the second main surface 512b, has a first opposing electrode portion 522a facing the second internal electrode 516b, and is laminated in the direction connecting the first main surface 512a and the second main surface 512b.

[0184] The first internal electrode 516a is extended by a first extension electrode portion 524a to the first surface 512c and the third surface 512e of the laminate 512, and is extended by a second extension electrode portion 524b to the second surface 512d and the fourth surface 512f of the laminate 512. The width of the first extension electrode portion 524a extended to the first surface 512c may be approximately equal to the width of the first extension electrode portion 524a extended to the third surface 512e, and the width of the second extension electrode portion 524b extended to the second surface 512d may be approximately equal to the width of the second extension electrode portion 524b extended to the fourth surface 512f.

[0185] Furthermore, the first internal electrode 516a is continuously extended to the first surface 512c and the third surface 512e of the laminate 512 by the first extension electrode portion 524a, and continuously extended to the second surface 512d and the fourth surface 512f of the laminate 512 by the second extension electrode portion 524b, but this is not limitative and the first internal electrode 516a may be extended discontinuously. Furthermore, the first internal electrode 516a may be arranged so that only one of the first surface 512c to the fourth surface 512f is exposed.

[0186] The second internal electrode 516b is disposed on a surface of the inner dielectric layer 514a different from the surface of the inner dielectric layer 514a on which the first internal electrode 516a is disposed. The second internal electrode 516b faces the first principal surface 512a and the second principal surface 512b, has a second opposing electrode portion 522b facing the first internal electrode 516a, and is laminated in a direction connecting the first principal surface 512a and the second principal surface 512b.

[0187] The second internal electrode 516b is extended by a third extension electrode portion 524c to the first surface 512c and the fourth surface 512f of the laminate 512, and is extended by a fourth extension electrode portion 524d to the second surface 512d and the third surface 512e of the laminate 512. The width of the third extension electrode portion 524c extended to the first surface 512c may be approximately equal to the width of the third extension electrode portion 524c extended to the fourth surface 512f, and the width of the fourth extension electrode portion 524d extended to the second surface 512d may be approximately equal to the width of the fourth extension electrode portion 524d extended to the third surface 512e.

[0188] The second internal electrode 516b is continuously extended to the first surface 512c and the fourth surface 512f of the laminate 512 by the third extension electrode portion 524c, and is continuously extended to the second surface 512d and the third surface 512e of the laminate 512 by the fourth extension electrode portion 524d, but this is not limitative and the second internal electrode 516b may be extended discontinuously. The second internal electrode 516b may be arranged so that only one of the first surface 512c to the fourth surface 512f is exposed.

[0189] Furthermore, when the multilayer ceramic capacitor 510 is viewed from the stacking direction, it is preferable that a straight line connecting the first extraction electrode portion 524a and the second extraction electrode portion 524b of the first internal electrode 516a intersects with a straight line connecting the third extraction electrode portion 524c and the fourth extraction electrode portion 524d of the second internal electrode 516b.

[0190] As shown in FIG. 23 , the laminate 512 also includes a side portion (W gap) 526a of the laminate 512 located between one end in the first direction y of the second opposing electrode portion 522b of the second internal electrode 516b and the first surface 512c, and a side portion (W gap) 526b of the laminate 512 located between the other end in the first direction y of the first opposing electrode portion 522a of the first internal electrode 516a and the second surface 512d.

[0191] Furthermore, as shown in FIG. 24 , the laminate 512 includes an end portion (L gap) 527a of the laminate 512 located between one end in the second direction z of the second opposing electrode portion 522b of the second internal electrode 516b and the third surface 512e, and a side portion (L gap) 527b of the laminate 512 located between the other end in the second direction z of the first opposing electrode portion 522a of the first internal electrode 516a and the fourth surface 512f.

[0192] The first internal electrode 516a and the second internal electrode 516b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited to these. Furthermore, the first internal electrode 516a and the second internal electrode 516b may be made of the same conductive material or different conductive materials.

[0193] Furthermore, by including Sn in the first internal electrode 516a and the second internal electrode 516b, the height of the potential barrier at the interface between the internal electrode 516 and the dielectric layer 514 is increased, and electric field concentration at the interface between the internal electrode 516 and the dielectric layer 514 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrodes 516, either the first internal electrode 516a or the second internal electrode 516b.

[0194] The total number of the first internal electrodes 516a and the second internal electrodes 516b is preferably 2 or more and 1000 or less. The thickness of the first internal electrodes 516a and the second internal electrodes 516b is not particularly limited, but is preferably, for example, 0.3 μm or more and 6.0 μm or less.

[0195] In this embodiment, the first opposing electrode portion 522a of the first internal electrode 516a and the second opposing electrode portion 522b of the second internal electrode 516b face each other via the inner dielectric layer 514a, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0196] (External Electrodes) The external electrodes 530 include a plurality of external electrodes 530 connected to the first internal electrode 516 a and the second internal electrode 516 b. The external electrodes 530 include a first external electrode 530 a, a second external electrode 530 b, a third external electrode 530 c, and a fourth external electrode 530 d.

[0197] The first external electrode 530a is disposed so as to cover the first lead electrode portion 524a on the first surface 512c and the third surface 512e, and so as to cover parts of the first principal surface 512a and the second principal surface 512b. The first external electrode 530a is electrically connected to the first lead electrode portion 524a of the first internal electrode 516a.

[0198] The second external electrode 530b is disposed so as to cover the second lead electrode portion 524b on the second surface 512d and the fourth surface 512f, and so as to cover parts of the first principal surface 512a and the second principal surface 512b. The second external electrode 530b is electrically connected to the second lead electrode portion 524b of the first internal electrode 516a.

[0199] The third external electrode 530c is disposed on the first surface 512c and the fourth surface 512f so as to cover the third lead electrode portion 524c, and is disposed so as to cover parts of the first principal surface 512a and the second principal surface 512b. The third external electrode 530c is electrically connected to the third lead electrode portion 524c of the second internal electrode 516b.

[0200] The fourth external electrode 530d is disposed on the second surface 512d and the third surface 512e so as to cover the fourth lead electrode portion 524d, and is disposed so as to cover parts of the first principal surface 512a and the second principal surface 512b. The fourth external electrode 530d is electrically connected to the fourth lead electrode portion 524d of the second internal electrode 516b.

[0201] Although not shown, the first external electrode 530a to the fourth external electrode 530d are disposed on the first principal surface 512a or the second principal surface 512b, but they do not have to be formed on either principal surface. In this case, the dimension of the multilayer ceramic capacitor 510 in the stacking direction x can be reduced, and the multilayer ceramic capacitor 510 can be made thinner.

[0202] In the laminate 512, a capacitance is formed by the first opposing electrode portion 522a of the first internal electrode 516a and the second opposing electrode portion 522b of the second internal electrode 516b facing each other via the dielectric layer 514. Therefore, a capacitance can be obtained between the first external electrode 530a and the second external electrode 530b to which the first internal electrode 516a is connected and the third external electrode 530c and the fourth external electrode 530d to which the second internal electrode 516b is connected, thereby exhibiting the characteristics of a capacitor.

[0203] The external electrode 530 preferably has a base electrode layer 532 and a plating layer formed to cover the base electrode layer 532. The plating layer includes a lower plating layer 534 and an upper plating layer 536 covering the lower plating layer 534.

[0204] The base electrode layer 532 includes a first base electrode layer 532 a, a second base electrode layer 532 b, a third base electrode layer 532 c, and a fourth base electrode layer 532 d. These first base electrode layer 532 a, second base electrode layer 532 b, third base electrode layer 532 c, and fourth base electrode layer 532 d are formed of thin film layers made up of a plurality of thin film electrodes to further improve performance.

[0205] The first base electrode layer 532a is formed to cover parts of the first and second principal surfaces 512a and 512b, as well as parts of the first surface 512c and third surface 512e. The second base electrode layer 532b is formed to cover parts of the first and second principal surfaces 512a and 512b, as well as parts of the second surface 512d and fourth surface 512f. The third base electrode layer 532c is formed to cover parts of the first and second principal surfaces 512a and 512b, as well as parts of the first surface 512c and fourth surface 512f. The fourth base electrode layer 532d is formed to cover parts of the first and second principal surfaces 512a and 512b, as well as parts of the second surface 512d and third surface 512e.

[0206] First, a description will be given of the case where the base electrode layer 532 is formed by a baking layer. The baking layer contains a metal component and a glass component. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Furthermore, the baking layer may be a multi-layer structure.

[0207] Furthermore, when the base electrode layer 532 is formed by a baked layer, it may be configured to contain a metal and the same type of component as the dielectric layer 514. In this case, if the dielectric layer 514 is made of a CaZrO system, the same type of component would be Ca or Zr.

[0208] The baking layer is formed by applying and baking a conductive paste containing a glass component and a metal component to the laminate 512. The baking layer may be formed by simultaneously firing a laminated chip having the internal electrodes 516 and the dielectric layer 514 and the conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having the internal electrodes 516 and the dielectric layer 514 to obtain the laminate 512 and then applying and baking the conductive paste. When simultaneously firing a laminated chip having the internal electrodes 516 and the dielectric layer 514 and the conductive paste applied to the laminated chip, it is preferable to add a dielectric component instead of the glass component, or to add both components to form the baking layer.

[0209] (Underlayer plating layer) The underlayer plating layer 534 includes a first underlayer plating layer 534a arranged to cover the first underlayer electrode layer 532a, a second underlayer plating layer 534b arranged to cover the second underlayer electrode layer 532b, a third underlayer plating layer 534c arranged to cover the third underlayer electrode layer 532c, and a fourth underlayer plating layer 534d arranged to cover the fourth underlayer electrode layer 532d.

[0210] The lower plating layer 534 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0211] Furthermore, the lower plating layer 534 is preferably Ni plating. When the lower plating layer 534 is Ni plating, it is possible to prevent the base electrode layer 532 from being eroded by solder when the multilayer ceramic capacitor 510 is mounted.

[0212] The thickness of the lower plating layer 534 is preferably, for example, 1 μm or more and 8 μm or less.

[0213] (Upper layer plating layer) The upper layer plating layer 536 includes a first upper layer plating layer 536a arranged to cover the first lower layer plating layer 534a, a second upper layer plating layer 536b arranged to cover the second lower layer plating layer 534b, a third upper layer plating layer 536c arranged to cover the third lower layer plating layer 534c, and a fourth upper layer plating layer 536d arranged to cover the fourth lower layer plating layer 534d.

[0214] The upper plating layer 536 includes at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0215] Furthermore, the upper plating layer 536 is preferably Sn plated. When the upper plating layer 536 is Sn plated, the wettability of the solder when mounting the multilayer ceramic capacitor 10 is improved, facilitating mounting.

[0216] The thickness of the upper plating layer 536 is preferably, for example, not less than 1 μm and not more than 8 μm.

[0217] The dimension of the multilayer ceramic capacitor 510 including the laminate 512 and the external electrodes 530 in the first direction y is defined as dimension L. The dimension L is preferably 0.1 mm or more and 6.0 mm or less. The dimension of the multilayer ceramic capacitor 510 including the laminate 512 and the external electrodes 530 in the second direction z is defined as dimension W. The dimension W is preferably 0.1 mm or more and 6.0 mm or less. The dimension of the multilayer ceramic capacitor 510 including the laminate 512 and the external electrodes 530 in the stacking direction x is defined as dimension T. The dimension T is preferably 0.03 mm or more and 1.8 mm or less. The dimensions of the multilayer ceramic capacitor 510 preferably satisfy the relationship 7 / 10≦L / W≦10 / 7. This allows the laminate 512 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0218] In the multilayer ceramic electronic component 500 of the second preferred embodiment, the joining electrode 540 electrically joins the first external electrode 530a and the second external electrode 530b of the multilayer ceramic capacitor 510 on the first main surface 512a of the laminate 512. Note that the joining electrode 540 may electrically join the third external electrode 530c and the fourth external electrode 530d of the multilayer ceramic capacitor 510, instead of electrically joining the first external electrode 530a and the second external electrode 530b of the multilayer ceramic capacitor 510.

[0219] The bonding electrode 540 includes a bonding base electrode 542, a bonding lower plating layer 544 covering the bonding base electrode 542, and a bonding upper plating layer 546 covering the bonding lower plating layer 544. Note that the bonding electrode 540 may be configured with only the bonding base electrode 542.

[0220] When the DC resistance of the multilayer ceramic capacitor 510 is Rdc1 and the DC resistance of the bonding electrode 540 is Rdc3, it is preferable that Rdc1≦Rdc3.

[0221] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0222] <1> A multilayer ceramic electronic component comprising: a laminate having first and second main surfaces opposing each other in a stacking direction, first and second surfaces opposing each other in a first direction perpendicular to the stacking direction, and third and fourth surfaces opposing each other in a second direction perpendicular to the stacking direction and the first direction; and at least four external electrodes arranged on any of the first, second, third, or fourth surfaces; and a joining electrode arranged on either the first or second main surface, electrically joining at least two of the external electrodes at the same potential, wherein Rdc1 is a DC resistance of the multilayer ceramic capacitor and Rdc3 is a DC resistance of the joining electrode, and wherein Rdc1≦Rdc3.

[0223] <2> The multilayer ceramic electronic component according to <1>, wherein Rdc3 is 1.0 to 5.0 times Rdc1.

[0224] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the thickness of the joining electrode in the stacking direction is smaller than the thickness of an external electrode disposed on the same plane as the joining electrode in the stacking direction.

[0225] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the external electrodes include a base electrode and a plating layer, the joining electrodes include a joining base electrode and a joining plating layer, the porosity of the joining base electrode is higher than the porosity of the base electrode disposed on the same plane as the joining base electrode, and the plating layer and the joining plating layer are the same type of plating.

[0226] <5> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the external electrodes include a base electrode and a plating layer, the joining electrode is a sputtered electrode, and the porosity of the joining electrode is lower than the porosity of the base electrode disposed on the same plane as the joining electrode.

[0227] 100, 100A, 500 Multilayer ceramic electronic component 10, 10A, 10B, 510 Multilayer ceramic capacitor 12, 512 Laminate 12a, 512a First surface 12b, 512b Second surface 12c, 512c Third surface 12d, 512d Fourth surface 12e, 512e Fifth surface 12f, 512f Sixth surface 14, 514 Dielectric layer 14a, 514a Inner dielectric layer 14b, 514b Outer dielectric layer 16, 516 Internal electrode 16a, 516a First internal electrode 16b, 516b Second internal electrode 18, 518 Internal layer portion 20a, 520a First outer side layer portion 20b, 520b Second outer side layer portion 22a, 522a First opposing electrode portion 22b, 522b Second opposing electrode portion 24a, 524a First lead electrode portion 24b, 524b Second lead electrode portion 24c, 524c Third lead electrode portion 24d, 524d Fourth lead electrode portion 26a, 26b, 526a, 526b Side portion of laminate (W gap) 27a, 27b, 527a, 527b End portion of laminate (L gap) 30, 530 External electrode 30a, 530a First external electrode 30b, 530b Second external electrode 30c, 530c Third external electrode 30d, 530d Fourth external electrode 32, 532 Base electrode layer 32a, 532a First base electrode layer 32b, 532b Second base electrode layer 32c, 532c Third base electrode layer 32d, 532d Fourth base electrode layer 34, 534 Underlayer plating layer 34a, 534a First underlayer plating layer 34b, 534b Second underlayer plating layer 34c, 534c Third underlayer plating layer 34d, 534d Fourth underlayer plating layer 36, 536 Upper layer plating layer 36a, 536a First upper layer plating layer 36b, 536b Second upper layer plating layer 36c, 536c Third upper layer plating layer 36d, 536d Fourth upper layer plating layer 40, 540 Bonding electrode 42, 542 Base bonding electrode 44, 544 Bonding underlayer plating layer 46, 546 Bonding upper layer plating layer 25a First dummy electrode 25b Second dummy electrode 25c Third dummy electrode 25d Fourth dummy electrode 28 Capacitance forming portion 29 Internal electrode laminate portion29a First internal electrode laminate portion 29b Second internal electrode laminate portion 29c Third internal electrode laminate portion x Lamination direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in the first direction W Dimension of multilayer ceramic capacitor in the second direction T Dimension of multilayer ceramic capacitor in the lamination direction

Claims

1. A multilayer ceramic electronic component comprising: a laminate having first and second main surfaces opposed to each other in a stacking direction, first and second surfaces opposed to each other in a first direction perpendicular to the stacking direction, and third and fourth surfaces opposed to each other in a second direction perpendicular to the stacking direction and the first direction; and at least four external electrodes arranged on any of the first, second, third or fourth surfaces; and a joining electrode arranged on any one of the first or second main surfaces, electrically joining at least two or more of the external electrodes having the same potential, wherein Rdc1 is a DC resistance of the multilayer ceramic capacitor and Rdc3 is a DC resistance of the joining electrode, where Rdc1≦Rdc3.

2. The multilayer ceramic electronic component according to claim 1, wherein Rdc3 is not less than 1.0 times and not more than 5.0 times Rdc1.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the thickness of said joining electrodes in said lamination direction is thinner than the thickness in said lamination direction of external electrodes arranged on the same plane as said joining electrodes.

4. A multilayer ceramic electronic component as described in any one of claims 1 to 3, wherein the external electrode comprises a base electrode and a plating layer, the joining electrode comprises a joining base electrode and a joining plating layer, the porosity of the joining base electrode is higher than the porosity of the base electrode arranged on the same plane as the joining base electrode, and the plating layer and the joining plating layer are the same type of plating.

5. A multilayer ceramic electronic component as claimed in any one of claims 1 to 3, wherein the external electrode comprises a base electrode and a plating layer, the joining electrode is a sputtering electrode, and the porosity of the joining electrode is lower than the porosity of the base electrode disposed on the same plane as the joining electrode.

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