Signal processing device and method for manufacturing semiconductor device

Abstract

The present technology relates to a signal processing device that enables weights used in inference processing to be suitably updated, and a method for manufacturing a semiconductor device. A signal processing device according to the present technology comprises: a plurality of memories that hold written information for a predetermined period of time, and that weight an input signal using a weight based on the information and output the weighted input signal; an output circuit that outputs an output signal in accordance with the input signal weighted by each of the plurality of memories; and a feedback circuit that writes information based on a time difference between the input signal and the output signal into the memories. The present technology can be applied to product-sum operation circuits that perform inference processing using AI, for example.

Description

Signal processing device and semiconductor device manufacturing method

[0001] The present technology relates to a signal processing device and a method for manufacturing a semiconductor device, and more particularly to a signal processing device and a method for manufacturing a semiconductor device that are capable of suitably updating weights used in inference processing.

[0002] In recent years, Domain Specific Architectures including circuits and chips that realize inference processing using AI (artificial intelligence) have been developed (see, for example, Patent Document 1). The most common circuits for realizing inference processing are multiply-accumulate circuits that include multiple SRAMs (Static Random Access Memories).

[0003] In the inference process, for example, information (weights) held in the SRAMs is multiplied by the input signals, and the calculation results obtained by adding the weighted input signals in each SRAM are output as inference data.

[0004] AI learning is realized, for example, by a program executed using a memory separate from the product-sum operation circuit. For example, learning is performed by backpropagation, such as a stochastic descent learning method based on the difference between inference data and training data, calculating the amount of change in weights to be updated and updating the weights so that the difference between inference data and training data becomes smaller.

[0005] Japanese Patent Application Laid-Open No. 2021-82130

[0006] However, after the inference, it is necessary to calculate the amount of change in the weight and update the weight using a memory prepared separately from the product-sum calculation circuit, which is time-consuming and consumes a lot of power.

[0007] The present technology has been made in consideration of such circumstances, and makes it possible to suitably update weights used in inference processing.

[0008] A signal processing device according to a first aspect of the present technology includes a plurality of memories that hold written information for a predetermined period of time and weight an input signal using a weight based on the information and output the weighted input signal, an output circuit that outputs an output signal in accordance with the input signal weighted by each of the plurality of memories, and a feedback circuit that writes the information based on a time difference between the input signal and the output signal into the memory.

[0009] A second aspect of the present technology relates to a method for manufacturing a semiconductor device that includes a plurality of memories that retain written information for a predetermined period of time and weight and output an input signal using a weight based on the information, an output circuit that outputs an output signal in response to the input signal weighted by each of the plurality of memories, and a feedback circuit that writes the information based on the time difference between the input signal and the output signal into the memory, wherein at least a portion of the feedback circuit is formed on a substrate, and the memory is formed in a wiring layer stacked on the substrate.

[0010] In a first aspect of the present technology, a plurality of memories hold written information for a predetermined period of time, an input signal is weighted using a weight based on the information and output, an output circuit outputs an output signal according to the input signal weighted by each of the plurality of memories, and a feedback circuit writes the information based on the time difference between the input signal and the output signal to the memory.

[0011] In a second aspect of the present technology, a semiconductor device including a plurality of memories that retain written information for a predetermined period of time and weight and output an input signal using a weight based on the information, an output circuit that outputs an output signal in accordance with the input signal weighted by each of the plurality of memories, and a feedback circuit that writes the information based on the time difference between the input signal and the output signal to the memory is manufactured by forming at least a portion of the feedback circuit on a substrate and forming the memory in a wiring layer stacked on the substrate.

[0012] 1 is a diagram illustrating an example of the configuration of a product-sum operation circuit including an SRAM. FIG. 2 is a diagram illustrating the flow of inference processing and learning using the product-sum operation circuit of FIG. 1. FIG. 3 is a diagram illustrating an example of the configuration of a product-sum operation circuit of the present technology. FIG. 4 is a diagram illustrating a learning method in the brain of an organism. FIG. 5 is a diagram illustrating an example of the configuration of a perceptron of the present technology. FIG. 6 is a diagram illustrating an example of control of gate voltage based on the time difference between an input signal and an output signal. FIG. 7 is a diagram illustrating updating of weights by gate voltage. FIG. 8 is a diagram illustrating an example of the configuration of a feedback circuit and an output circuit. FIG. 9 is a diagram illustrating transitions in the resistance value of a diffusion memristor. FIG. 10 is a diagram illustrating an example of a three-terminal nonvolatile memory. FIG. 11 is a diagram illustrating an example of the configuration of an output circuit when a pulse wave input signal is input. FIG. 12 is a diagram illustrating the flow of an AND circuit outputting a pulse signal. FIG. 13 is a diagram illustrating an example of the configuration of an output circuit when a square wave input signal is input. FIG. 14 is a diagram illustrating an example of the configuration of a feedback circuit when a pulse wave input signal is input. FIG. 15 is a diagram illustrating examples of gate voltage values ​​according to the positive / negative and degree of the time difference between the input signal and the output signal. FIG. 16 is a diagram illustrating the flow of a negative pulse generation circuit generating a negative pulse signal. FIG. 17 is a diagram illustrating an example of the configuration of a feedback circuit when a square wave input signal is input. FIG. 18 is a diagram illustrating another example of the configuration of a feedback circuit when a square wave input signal is input. FIG. 19 is a diagram illustrating an example of gate voltage. FIG. 1 is a diagram illustrating an example configuration of a feedback circuit that performs a reset operation; FIG. 2 is a diagram illustrating examples of gate voltages and weights when a reset operation is performed; FIG. 3 is a diagram illustrating another example configuration of a product-sum operation circuit; FIG. 4 is a diagram illustrating example configurations of a conventional memory cell and a memory cell of the present technology; FIG. 5 is a diagram illustrating an example configuration of a feedback circuit; FIG. 6 is a diagram illustrating a first modified example of the configuration of a perceptron; FIG. 7 is a diagram illustrating a second modified example of the configuration of a perceptron; FIG. 8 is a cross-sectional view schematically illustrating the configuration of a product-sum operation circuit of the present technology; and FIG. 9 is a diagram illustrating the operation of a CMOS circuit as a diffusion memristor.

[0013] Hereinafter, embodiments of the present technology will be described in the following order: 1. Overview of the product-sum calculation circuit 2. Details of each configuration 3. Modification

[0014] <1. Overview of product-sum circuits> In recent years, there has been development of domain-specific architectures that include circuits and chips that realize AI-based inference processing. The mainstream circuits for realizing inference processing are product-sum circuits that include SRAM.

[0015] FIG. 1 is a diagram showing an example of the configuration of a product-sum operation circuit including an SRAM.

[0016] The sum-of-products circuit in Fig. 1 is a circuit that realizes AI-based inference processing in hardware. The sum-of-products circuit in Fig. 1 is composed of multiple SRAMs 11 arranged in an array (matrix), an input circuit 12, and an output circuit 13. The input circuit 12 and the output circuit 13 are connected to, for example, a peripheral circuit 14 provided separately from the sum-of-products circuit.

[0017] 1, 3x3 SRAMs 11 are arranged in a plane as memory cells. Each SRAM 11 is composed of, for example, eight transistors. The SRAM 11 is connected to an input circuit 12 via one word line 21 and two bit lines 22 and 23, and is connected to an output circuit 13 via one word line 24 and two bit lines 25 and 26.

[0018] When an input signal is input from the input circuit 12 to the SRAM 11 via the word line 21, the information held in the SRAM 11 is read out by the output circuit 13 via the bit lines 25 and 26. When a drive signal is input from the output circuit 13 to the SRAM 11 via the word line 24, the input circuit 12 controls the voltages of the bit lines 22 and 23, and the information is written to the SRAM 11.

[0019] The peripheral circuit 14 supplies the input circuit 12 with an input signal indicating data to be input to the AI, and obtains from the output circuit 13 inference data indicating the inference results of the AI.

[0020] FIG. 2 is a diagram for explaining the flow of inference processing and learning using the product-sum calculation circuit of FIG.

[0021] In the inference process, the information held in the SRAM is multiplied by the input signal as a weight, and the weighted input signals are added together in each SRAM to produce an arithmetic result that is output as inference data. On the left side of Figure 2, the word lines 21 in the first to third rows, the SRAM 11 in the second column, and the bit lines 25 and 26 in the second column are shown in gray, indicating that the input signal is input to the SRAM 11 in the second column via the word lines 21 in the first to third rows, and the information read from each SRAM 11 in the second column is added together by the bit lines 25 and 26 in the second column and input to the output circuit 13. In other words, the SRAMs 11, bit lines 25 and 26, and output circuit 13 arranged in the same column form a single perceptron (product-sum operation circuit).

[0022] AI learning is realized by a program executed using, for example, the peripheral circuit 14. To perform AI learning, the peripheral circuit 14 first supplies an input signal indicating student data to the input circuit 12 as shown on the left side of Figure 2, and obtains inference data from the output circuit 13.

[0023] Next, the peripheral circuit 14 calculates the amount of change in the weights to be updated, for example, by backpropagation, such as a stochastic descent learning method based on the difference between the training data that serves as the training teacher and the inference data, as shown by the white arrow #1 in Fig. 2. Next, as shown on the right side of Fig. 2, the peripheral circuit 14 controls the input circuit 12 and the output circuit 13 to write information to the SRAM 11 to be updated, thereby updating the weights.

[0024] As shown by the white arrow #2 in Figure 2, AI learning is completed by repeating the inference process, calculation of the amount of change in the weights to be updated, and updating the weights so that the difference between the inference data and the training data becomes smaller.

[0025] However, after the inference process, the peripheral circuit 14 needs to calculate the weight change amount and update the weight, which is time-consuming and consumes a lot of power. Therefore, there is a demand for development of Computing in Memory (CiM), Spiked Neural Network (SNN), Neuromorphic Computing, etc.

[0026] The present technology was conceived with the above points in mind, and enables the weights used in the inference process (product-sum operation) to be updated in an optimal manner, such as by updating the weights almost simultaneously with the inference process or by updating the weights all at once.

[0027] FIG. 3 is a diagram illustrating a configuration example of a product-sum calculation circuit according to the present technology.

[0028] The sum-of-products circuit in Fig. 3 is a circuit that realizes AI-based inference processing in hardware. The sum-of-products circuit in Fig. 3 is composed of a plurality of three-terminal nonvolatile memories 51 arranged in an array, a feedback circuit 52 provided for each three-terminal nonvolatile memory 51, an input circuit 53, and an output circuit 54. The input circuit 53 and the output circuit 54 are connected to, for example, a peripheral circuit 55 provided separately from the sum-of-products circuit.

[0029] 3, 3×3 memory cells each consisting of a three-terminal nonvolatile memory 51 and a feedback circuit 52 are arranged in a plane. That is, the feedback circuit 52 is provided within the memory cell array. Note that the arrangement and number of memory cells are merely examples and are not limited to these, and it is also possible to arrange memory cells in 8×8, 16×16, 64×64, or other arrangements.

[0030] The three-terminal nonvolatile memory 51 has at least three terminals: a gate, a source, and a drain. The resistance between the source and the drain changes nonvolatilely in response to the gate voltage. Because it has three terminals, the resistance between the source and the drain can be changed even when a current is flowing between the source and the drain. The three-terminal nonvolatile memory 51 functions as a memory that retains information for a predetermined period of time by changing the resistance between the source and the drain in response to the gate voltage. The three-terminal nonvolatile memory 51 is connected to an input circuit 53 via a horizontal signal line 61 and to an output circuit 54 via a vertical signal line 62. A feedback circuit 52 is connected to the gate of the three-terminal nonvolatile memory 51.

[0031] The feedback circuit 52 is connected to the input circuit 53 in parallel with the three-terminal nonvolatile memory 51 via a horizontal signal line 61, and is connected to the output circuit 54 via a vertical signal line 63. The feedback circuit 52 controls the gate voltage of the three-terminal nonvolatile memory 51 based on the input from the input circuit 53 and the output from the output circuit 54.

[0032] When an input signal is input from the input circuit 53 to the three-terminal nonvolatile memory 51 via the horizontal signal line 61, the information held in the three-terminal nonvolatile memory 51 is read out by the output circuit 54 via the vertical signal line 62. In the inference process, the information held in the three-terminal nonvolatile memory 51 is multiplied by the input signal as a weight, and the calculation result obtained by adding the weighted input signals in each three-terminal nonvolatile memory 51 is output as inference data.

[0033] 3, the horizontal signal lines 61 in the first to third rows, the three-terminal nonvolatile memories 51 in the second column, and the vertical signal line 62 in the second column are shown in gray, which indicates that an input signal is input to the three-terminal nonvolatile memory 51 in the second column via the horizontal signal lines 61 in the first to third rows, and information read out from each three-terminal nonvolatile memory 51 in the second column is added by the vertical signal line 62 in the second column and input to the output circuit 54. In other words, the three-terminal nonvolatile memories 51, vertical signal lines 62, and output circuits 54 arranged in the same column configure one perceptron.

[0034] Furthermore, when the output from the output circuit 54 is input to the feedback circuit 52 via the vertical signal line 63, the gate voltage is controlled by the feedback circuit 52, and information is written to the three-terminal nonvolatile memory 51. Therefore, even if the peripheral circuit 55 does not perform calculations of the amount of change in the weight, the weight used in the inference process is updated according to the output from the output circuit 54.

[0035] In Figure 3, the feedback circuit 52 in the second column and the vertical signal line 63 in the second column are shown with dashed lines, which indicates that the output from the output circuit 54 is input to the feedback circuit 52 in the second column via the vertical signal line 63 in the second column, and the weights held in each three-terminal non-volatile memory 51 in the second column are updated collectively by each feedback circuit 52 in the second column.

[0036] The peripheral circuit 55 supplies an input signal to the input circuit 53 and acquires inference data from the output circuit 54. For example, the peripheral circuit 55 repeatedly performs AI learning by inputting an input signal indicating student data to the AI ​​(input circuit 53) until the difference between the inference data and the teacher data becomes equal to or less than a predetermined threshold.

[0037] Here, the feedback circuit 52 updates the weights used in the inference process by imitating the learning process in the brain of a living organism.

[0038] FIG. 4 is a diagram illustrating the learning method in the brain of an organism.

[0039] As shown in Figure 4A, in the brain of an organism, the axon of neuron A and the dendrite of neuron B are connected via a synapse. Neuron A fires in response to some kind of stimulus, and an action potential is transmitted to neuron B via the axon. Neuron B fires in response to the firing of neuron A or other neurons connected via synapses, causing the conduction of an action potential.

[0040] As shown in Figure 4B, when neuron B fires later than neuron A (Δt > 0), the connection between neuron A and neuron B becomes stronger, and when neuron B fires earlier than neuron A (Δt < 0), the connection between neuron A and neuron B becomes weaker. This phenomenon is called STDP (Spike Timing Dependent Plasticity).

[0041] Here, when the firing time of neuron B is later than the firing time of neuron A, the smaller the time difference between the firing times of neuron A and neuron B, the stronger the connection between neuron A and neuron B. Also, when the firing time of neuron B is earlier than the firing time of neuron A, the smaller the absolute value of the time difference between the firing times of neuron A and neuron B, the weaker the connection between neuron A and neuron B. In this way, STDP (Spike Timing Dependent Plasticity) is time-dependent.

[0042] FIG. 5 is a diagram illustrating an example of the configuration of a perceptron according to the present technology.

[0043] 5 , in the perceptron of the present technology, when an input signal X of a predetermined voltage is input to the drain of a three-terminal nonvolatile memory 51, a signal of a current value corresponding to the resistance value between the source and drain of the three-terminal nonvolatile memory 51 is output to an output circuit 54. The signal of the current value corresponding to the resistance value between the source and drain of the three-terminal nonvolatile memory 51 corresponds to the input signal X weighted by the three-terminal nonvolatile memory 51. The output circuit 54 outputs an output signal Y obtained by inputting the input signal X weighted by the three-terminal nonvolatile memory 51 to an activation function.

[0044] In this technology, the gate voltage Vg of the three-terminal nonvolatile memory 51, which is related to the resistance value between the source and drain, is controlled based on the time difference Δt between the input signal X and the output signal Y. If the time when the input signal X rises is T(X) and the time when the output signal Y rises is T(Y), then the time difference Δt is expressed as T(Y) - T(X), for example.

[0045] 6 is a diagram illustrating an example of control of the gate voltage Vg based on the time difference between the input signal X and the output signal Y. In FIG. 6, the horizontal axis represents time, and the vertical axis represents voltage.

[0046] 6, when time T(Y) is later than time T(X) (Δt>0), the gate voltage Vg rises after time T(Y), in other words, a positive gate voltage Vg is applied to the gate of the three-terminal nonvolatile memory 51. Also, when time T(Y) is earlier than time T(X) (Δt<0), the gate voltage Vg falls after time T(Y), in other words, a negative gate voltage Vg is applied to the gate of the three-terminal nonvolatile memory 51, in other words, a negative gate voltage Vg is applied to the gate of the three-terminal nonvolatile memory 51.

[0047] FIG. 7 is a diagram illustrating the updating of the weights according to the gate voltage Vg.

[0048] When time T(Y) is later than time T(X), as shown in the balloon in Figure 7, a positive gate voltage Vg is applied to the gate of the three-terminal nonvolatile memory, and the resistance between the source and drain of the three-terminal nonvolatile memory 51 becomes smaller. Therefore, the weight is strengthened. Strengthening the weight when time T(Y) is later than time T(X) corresponds to strengthening the connection between neuron A and neuron B when the firing time of neuron B is later than the firing time of neuron A.

[0049] Furthermore, when time T(Y) is earlier than time T(X), as shown in the balloon in Figure 7, a negative gate voltage Vg is applied to the gate of the three-terminal nonvolatile memory 51, and the resistance between the source and drain of the three-terminal nonvolatile memory 51 increases. Therefore, the weight is weakened. The weakening of the weight when time T(Y) is earlier than time T(X) corresponds to the weakening of the connection between neuron A and neuron B when the firing time of neuron B is earlier than the firing time of neuron A.

[0050] As described above, in the brain of an organism, the connections between neurons are strengthened or weakened depending on the time difference between the firing times of the neurons. In this way, the feedback circuit 52 updates the weights used in the inference process by writing information based on the time difference between the input signal X and the output signal Y into the three-terminal nonvolatile memory 51.

[0051] This allows the feedback circuit 52 to update the weights almost simultaneously with the inference process. Furthermore, the product-sum calculation circuit of the present technology can simultaneously update the resistance values ​​(weights) of the multiple three-terminal nonvolatile memories 51 that make up one perceptron. This eliminates the need to calculate or update the amount of change in the weights using a memory separate from the product-sum calculation circuit, reducing the effort and power consumption.

[0052] FIG. 8 is a diagram showing an example of the configuration of the feedback circuit 52 and the output circuit 54.

[0053] As shown in FIG. 8A, the feedback circuit 52 is composed of a negative pulse generating circuit 81 and diffusion memristors 82 and 83.

[0054] An input signal X is input to the negative pulse generating circuit 81 , and when the input signal X rises, the negative pulse generating circuit 81 outputs a negative pulse signal to the drain of the diffusion memristor 83 .

[0055] The diffusion memristors 82 and 83 are elements having three terminals and volatilely storing resistance values. In the diffusion memristors, a filament is formed when an electric field is applied, and the filament is decomposed when the electric field is no longer applied. An input signal X is input to the gate of the diffusion memristor 82, and an output signal Y is input to the drain. Furthermore, an output signal Y is input to the gate of the diffusion memristor 83.

[0056] The diffusion memristors 82 and 83 output from their sources a signal input to their drains in response to a signal input to their gates. The signal output from the sources of the diffusion memristors 82 and 83 is input to the gate of the three-terminal nonvolatile memory 51 as a signal of gate voltage Vg.

[0057] FIG. 9 is a diagram illustrating the transition of the resistance value of a diffusion memristor.

[0058] As shown in Figure 9A, when no pulse is input to the gate of the diffusion memristor (when no electric field is applied), no filament is formed, so the conductance is low and the diffusion memristor does not transmit much of the pulse.

[0059] As shown in FIG. 9B, when a pulse is input to the gate of the diffusion memristor (when an electric field is applied), a filament is formed, which increases the conductance and allows the diffusion memristor to pass the pulse.

[0060] As shown in Figure 9C, if a certain period of time passes after a pulse is input to the gate of the diffusion memristor (when no electric field is applied), the filament decomposes, resulting in a low conductance and a low transmission of the pulse through the diffusion memristor.

[0061] As shown in FIG. 8B, the output circuit 54 outputs a voltage value Σw i X i and the reference voltage value Ref is input. i denotes the weight stored in the three-terminal nonvolatile memory 51(i), and X i indicates the voltage value of the input signal input to the three-terminal nonvolatile memory 51(i). The output circuit 54 outputs the voltage value Σw i X i is equal to or greater than the reference voltage value Ref, the output signal Y is output as a pulse, for example.

[0062] 2. Details of Each Component Three-Terminal Nonvolatile Memory FIG. 10 is a diagram showing an example of a three-terminal nonvolatile memory 51. As shown in FIG.

[0063] As shown in FIG. 10, the three-terminal nonvolatile memory 51 may be one resistive element, one nonvolatile memory element, a combination of two elements including a resistive element, or a combination of two elements including a nonvolatile memory element.

[0064] For example, the three-terminal nonvolatile memory 51 is realized by a single resistive element such as a three-terminal ECRAM (Electro Chemical Random-Access Memory), a three-terminal domain wall motion element, or a three-terminal memristor. A memristor is a device whose impedance changes depending on the frequency of use and time.

[0065] For example, the three-terminal nonvolatile memory 51 is realized by one nonvolatile memory element such as a Ferroelectric Field Effect Transistor (FeFET), a Metal Oxide Nitride Oxide Silicon (MONOS), or a floating gate.

[0066] For example, the three-terminal nonvolatile memory 51 can be realized by combining two elements, a transistor as a switch (selector) and a memristor, or by combining two elements, such as a transistor and a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a phase-change RAM (PCM).

[0067] In this way, when the three-terminal nonvolatile memory 51 is realized by one element, the element whose resistance changes has a gate. When the three-terminal nonvolatile memory 51 is realized by two elements, a selector is connected to, for example, the drain of the element whose resistance changes.

[0068] Regarding the Output Circuit, for example, a pulse wave signal or a square wave signal is used as the input signal X and the output signal Y. First, a case where pulse wave signals are used as the input signal X and the output signal Y will be described.

[0069] FIG. 11 is a diagram showing an example of the configuration of the output circuit 54 when a pulse wave input signal is input.

[0070] As shown in FIG. 11, the output circuit 54 is composed of a capacitor 101 , a resistor 102 , an inverter 103 , a delay circuit 104 , and an AND circuit 105 .

[0071] A charge ΣQ as an input signal X, each weighted by a plurality of three-terminal nonvolatile memories 51, is stored at the other end of a capacitor 101, one end of which is grounded, and a signal with a voltage value of ΣQ / C is input to an inverter 103 and an AND circuit 105.

[0072] The resistor 102 is connected in parallel with the capacitor 101 and gradually releases the charge stored in the capacitor 101 to the ground.

[0073] The inverter 103 inverts the input signal and outputs it to the delay circuit 104 .

[0074] The delay circuit 104 delays the signal input from the inverter 103 and outputs the delayed signal to the AND circuit 105. The delay circuit 104 is configured by resistors, capacitors, multi-stage inverters, and the like.

[0075] The AND circuit 105 outputs a pulse signal as the output signal Y when the level of the signal input from the capacitor 101 and the level of the signal input from the delay circuit 104 are both 1 (High).

[0076] FIG. 12 is a diagram for explaining the flow of the AND circuit 105 outputting a pulse signal.

[0077] As shown in the upper part of A in FIG. 12, when the level of the input signal X is 0 (Low), the level of the signal output from the inverter 103 becomes 1 (High) and the level of the output signal Y becomes 0.

[0078] As indicated by the tip of the hollow arrow #21, when the level of the input signal X becomes 1, the signal output from the inverter 103 is delayed and input to the AND circuit 105, and the level of the output signal Y becomes 1.

[0079] As indicated by the tip of the hollow arrow #22, after the level of the input signal X becomes 1, the level of the signal output from the inverter 103 becomes 0, and this signal is delayed and input to the AND circuit 105. Therefore, the level of the output signal Y becomes 0.

[0080] As shown in B of Figure 12, the output signal Y is a pulse signal that has a level of 0 at timing t1 (upper side of A in Figure 12), a level of 1 at timing t2 (end of white arrow #21), and a level of 0 at timing t3 (end of white arrow #22).

[0081] FIG. 13 is a diagram showing an example of the configuration of the output circuit 54 when a rectangular wave input signal is input.

[0082] As shown in FIG. 13A, the output circuit 54 is composed of a resistor 121 and a delay circuit 122.

[0083] When a current ΣI is input as an input signal X weighted by a plurality of three-terminal nonvolatile memories 51, the voltage value of the grounded resistor 121 becomes R×ΣI, and a signal of that voltage value is input to the delay circuit 122.

[0084] The delay circuit 122 delays the signal with a voltage value of R×ΣI and outputs it as an output signal Y. The delay circuit 104 is composed of resistors, capacitors, multi-stage inverters, etc. As shown in B of Fig. 13 , the output signal Y is a rectangular wave that rises at a predetermined timing.

[0085] 14 is a diagram showing an example of the configuration of the feedback circuit 52 when a pulse wave input signal is input. As described above, the feedback circuit 52 in FIG. 14 is composed of a negative pulse generating circuit 81, a diffusion memristor 82, and a diffusion memristor 83.

[0086] As shown in FIG. 14, the negative pulse generating circuit 81 of the feedback circuit 52 includes an inverter 151 , a capacitor 152 , diodes 153 and 154 , and a resistor 155 .

[0087] The inverter 151 inverts the input signal X and outputs the inverted signal !X to the capacitor 152.

[0088] One end of the capacitor 152 is connected to the inverter 151, and the other end is connected to the anode side of a diode 153, the cathode side of which is grounded, and the cathode side of a diode 154. The anode side of the diode 154 is connected to a resistor 155 and the drain of the diffusion memristor 83. A signal X2 is output from the output side of the negative pulse generating circuit 81 to the drain of the diffusion memristor 83.

[0089] When the level of the input signal X input to the gate of the diffusion memristor 82 becomes high, the output signal Y input to the drain of the diffusion memristor 82 passes through for a predetermined period of time. After the predetermined period has elapsed, the output signal Y becomes less likely to pass through.

[0090] On the other hand, when the level of the output signal Y input to the gate of the diffusion memristor 83 becomes high, the signal X2 input to the drain of the diffusion memristor 83 passes through for a predetermined period. After the predetermined period has elapsed, the signal X2 becomes less likely to pass through.

[0091] 15, when T(X)<T(Y) (Δt>0), the pulse of output signal Y can pass through diffusion memristor 82, so a positive gate voltage Vg is output, and the weight held in three-terminal nonvolatile memory 51 is strengthened. Note that, because the pulse of signal X2 (the pulse of inverted signal !X) ends before time T(Y), the pulse of signal X2 cannot pass through diffusion memristor 83, and a negative gate voltage Vg is not output.

[0092] Here, when the time difference between time T(X) and time T(Y) is small, the decrease in conductance of the diffusion memristor 82 is also small, and therefore the voltage value of the output signal Y (gate voltage Vg) passing through the diffusion memristor 82 is large. On the other hand, when the time difference between time T(X) and time T(Y) is large, the decrease in conductance of the diffusion memristor 82 is also large, and therefore the voltage value of the output signal Y (gate voltage Vg) passing through the diffusion memristor 82 is small. In other words, the smaller the time difference between time T(X) and time T(Y), the larger the voltage value of the gate voltage Vg, and the stronger the weight held in the three-terminal nonvolatile memory 51.

[0093] 15, when T(X)>T(Y) (Δt>0), the pulse of signal X2 can pass through the diffusion memristor 83, so a negative gate voltage Vg is output, and the weight held in the three-terminal nonvolatile memory 51 is weakened. Note that, because the pulse of output signal Y ends before time T(X), the pulse of output signal Y cannot pass through the diffusion memristor 82, and a positive gate voltage Vg is not output.

[0094] Here, when the time difference between time T(X) and time T(Y) is small, the decrease in conductance of the diffusion memristor 83 is also small, and therefore the absolute value of the voltage value of the output signal Y (gate voltage Vg) passing through the diffusion memristor 83 becomes large. On the other hand, when the time difference between time T(X) and time T(Y) is large, the decrease in conductance of the diffusion memristor 82 is also large, and therefore the absolute value of the voltage value of the output signal Y (gate voltage Vg) passing through the diffusion memristor 83 becomes small. In other words, the smaller the time difference between time T(X) and time T(Y), the smaller the voltage value of the gate voltage Vg, and the weaker the weight held in the three-terminal nonvolatile memory 51.

[0095] In this way, the feedback circuit 52 writes information corresponding to the positive / negative or magnitude of the time difference Δt between the input signal X and the output signal Y into the three-terminal nonvolatile memory 51. This enables the feedback circuit 52 to mimic the time dependency of STDP in the brain of a living organism.

[0096] FIG. 16 is a diagram for explaining the flow of the negative pulse generating circuit 81 generating a negative pulse signal.

[0097] As shown in the upper part of A in Figure 16, the voltage on the input side of the negative pulse generating circuit 81 (capacitor 152) is Vin, the voltage on the output side of the capacitor 152 is V2, and the voltage on the output side of the negative pulse generating circuit 81 (the anode side of the diode 154) is Vout.

[0098] As indicated by the tip of hollow arrow #41, when Vin > 0, capacitor 152 is charged, and V2 = 0 V and Vout = 0 V. As indicated by hollow arrow #42, when Vin = 0 V, capacitor 152 is discharged, and V2 < 0 and Vout < 0. The negative charge accumulated in capacitor 152 is gradually released to ground via resistor 155.

[0099] As shown in FIG. 16B, at timing t11 (the tip of arrow #41 in FIG. 16A) when Vin > 0, V2 = 0 V and Vout = 0 V. However, at timing t12 when Vin falls, V2, which is capacitively coupled to capacitor 152, and Vout, which is connected by a diode in the forward direction, fall. Thereafter, the negative charge accumulated in capacitor 152 is released to ground via resistor 155, so that at timing t13 (the tip of arrow #42 in FIG. 16A), V2 and Vout gradually increase. At timing t134 when Vin rises, capacitor 152 is charged, and V2 and Vout rise.

[0100] At timing t14, V2>0, but negative charges are accumulated in the capacitor 152 via the diode 153, and V2 gradually decreases to 0V.

[0101] In this way, the signal X2 output from the negative pulse generating circuit 81 becomes a negative pulse signal that falls at timing t12 and rises at timing t14.

[0102] FIG. 17 is a diagram showing an example of the configuration of the feedback circuit 52 when a rectangular wave input signal is input.

[0103] As shown in FIG. 17, the feedback circuit 52 is composed of MOSFETs 201, 203, 205, 207, and 209, resistors 202 and 206, and capacitors 204 and 208.

[0104] When the level of the inverted signal !X of the input signal is high, the gate of MOSFET 201 is turned on. A predetermined positive voltage Vsig is applied to the drain of MOSFET 201, and the source is connected to a resistor 202 with one end grounded and to the drain of MOSFET 203. In the following, the voltage on the source side of MOSFET 201 is referred to as VgPpre.

[0105] When the levels of the input signal X and the inverted signal !Y of the output signal Y are both high, the gate of MOSFET 203 is turned on. The source of MOSFET 203 is connected to a capacitor 204, one end of which is grounded, and to the drain of MOSFET 209. In the following, the voltage on the source side of MOSFET 203 is referred to as VgP.

[0106] When the level of the inverted signal Y of the input signal is high, the gate of MOSFET 205 is turned on. A predetermined negative voltage −Vsig is applied to the drain of MOSFET 205, and the source is connected to a resistor 206, one end of which is grounded, and the drain of MOSFET 207.

[0107] When the inverted signal !X of the input signal X and the output signal Y are both at high levels, the gate of the MOSFET 207 is turned on. The source of the MOSFET 203 is connected to a capacitor 208, one end of which is grounded, and to the drain of a MOSFET 209.

[0108] When the levels of the input signal X and the output signal Y are both high, the gate of the MOSFET 209 is turned on. The source of the MOSFET 209 is the output terminal of the feedback circuit 52, and the voltage on the source side of the MOSFET 209 becomes the gate voltage Vg.

[0109] 14 has been described as an example in which the feedback circuit 52 is configured with a diffusion memristor or the like when a pulse wave input signal is input, but it may be configured with a MOSFET or the like as described with reference to Fig. 17. Also, in Fig. 17, has been described as an example in which the feedback circuit 52 is configured with a MOSFET or the like when a square wave input signal is input, but it may be configured with a diffusion memristor or the like as described with reference to Fig. 14.

[0110] FIG. 18 is a diagram showing an example of the gate voltage Vg.

[0111] A of Fig. 18 shows the relationship between the time difference Δt between the input signal X and the output signal Y and the gate voltage Vg in the feedback circuit 52 of Fig. 17. As shown in A of Fig. 18, the feedback circuit 52 of Fig. 17 outputs a gate voltage Vg that is inversely proportional to the time difference Δt, for example. This enables the feedback circuit 52 to mimic the time dependency of STDP in the brain of an organism.

[0112] 18B shows the relationship between time and the voltage values ​​of the input signal X, the output signal Y, VgPpre, VgP, and the gate voltage Vg. In FIG. 18B, only the case where the rising time of the output signal Y is earlier than the rising time of the input signal X will be described.

[0113] 18B, when the time difference Δt is large, VgP rises at timing t21 when input signal X rises, but VgPpre and VgP gradually decrease because the gate of MOSFET 201 is turned off and the charge is gradually released via resistor 202. At timing t22 when output signal Y rises, the gate of MOSFET 203 is turned off and the gate of MOSFET 209 is turned on, so VgP, which has decreased in accordance with the time difference Δt, is output as gate voltage Vg.

[0114] 18B, at timing t21' when the input signal X rises, the period during which VgPpre and VgP gradually decrease after VgP rises is short. Therefore, at timing t22 when the output signal Y rises, VgP, which remains high, is output as the gate voltage Vg.

[0115] FIG. 19 is a diagram showing another example of the configuration of the feedback circuit 52 when a rectangular wave input signal is input.

[0116] The feedback circuit 52 in FIG. 19 is composed of MOSFETs 251, 253, and 255 and capacitors 252 and 254.

[0117] When the levels of the input signal X and the inverted signal !Y are both high, the gate of MOSFET 251 is turned on. A predetermined positive voltage Vsig is applied to the drain of MOSFET 251, and the source is connected to a capacitor 252, one end of which is grounded, and to the drain of MOSFET 255. In the following, the voltage on the source side of MOSFET 251 is referred to as VgP.

[0118] When the levels of the inverted signal !X and the output signal Y are both high, the gate of MOSFET 253 is turned on. A predetermined negative voltage −Vsig is applied to the drain of MOSFET 253, and the source is connected to a capacitor 254, one end of which is grounded, and to the drain of MOSFET 255. In the following, the voltage on the source side of MOSFET 253 is referred to as VgN.

[0119] When the levels of the input signal X and the output signal Y are both high, the gate of the MOSFET 255 is turned on. The source of the MOSFET 255 is the output terminal of the feedback circuit 52, and the voltage on the source side of the MOSFET 203 becomes the gate voltage Vg.

[0120] FIG. 20 is a diagram showing an example of the gate voltage Vg.

[0121] A in Fig. 20 shows the relationship between the time difference Δt between time T(X) and time T(Y) and the gate voltage Vg in the feedback circuit 52 in Fig. 19. As shown in A in Fig. 20, the feedback circuit 52 in Fig. 19 outputs a gate voltage Vg that is positive when Δt > 0 and negative when Δt < 0, for example. This enables the feedback circuit 52 to mimic STDP in the brain of an organism.

[0122] FIG. 20B shows the relationship between the voltage values ​​of the input signal X, the output signal Y, VgP, VgN, and the gate voltage Vg and time.

[0123] 20B, at timing t31 when the input signal X rises, the gate of MOSFET 251 is turned on and VgP rises, as shown by the solid line in B of Fig. 20. At timing t32 when the output signal Y rises, the gate of MOSFET 251 is turned off and the gate of MOSFET 255 is turned on, so VgP is output as the gate voltage Vg.

[0124] On the other hand, if the time at which the output signal Y rises is later than the time at which the input signal X rises, the gate of MOSFET 253 is turned on and VgN falls at timing t32 when the output signal Y rises, as shown by the dashed line in B of Fig. 20. At timing t31' when the input signal X rises, the gate of MOSFET 253 is turned off and the gate of MOSFET 255 is turned on, so VgN is output as the gate voltage Vg.

[0125] 21 is a diagram showing an example of the configuration of a feedback circuit 52 that performs a reset operation. In Fig. 21, the same components as those in Fig. 14 are denoted by the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0126] The feedback circuit 52 in FIG. 21 differs from the feedback circuit 52 in FIG. 14 in that MOSFETs 301 and 302 are provided in the negative pulse generating circuit 81.

[0127] When the level of the control signal Ctrl for controlling the reset operation is High, the gate of the MOSFET 301 is turned on. The input signal X is input to the drain of the MOSFET 301, and the source is connected to the input side of the inverter 151.

[0128] When the inverted signal !Ctrl of the control signal Ctrl is at a high level, the gate of the MOSFET 302 is turned on. The input signal X is input to the drain of the MOSFET 302, and the source is connected to the drain of the diffusion memristor 83. When the gate of the MOSFET 302 is turned on, the input signal X is bypassed to the drain of the diffusion memristor 83, and the feedback circuit 52 is regarded as a circuit in which the negative pulse generating circuit 81 is omitted, as shown in speech bubble #51 in FIG.

[0129] 22, whether Δt > 0 or Δt < 0, a positive gate voltage Vg is applied to the gate of three-terminal nonvolatile memory 51, thereby strengthening the weights held in three-terminal nonvolatile memory 51. Therefore, by inputting an inverted signal !Ctrl of the control signal Ctrl to all feedback circuits 52, the weights held in all three-terminal nonvolatile memories 51 are aligned to predetermined values, and AI is reset.

[0130] An example in which a three-terminal nonvolatile memory is replaced with an SRAM. Figure 23 is a diagram showing another example of the configuration of a product-sum operation circuit. In Figure 23, the same components as those in Figure 3 are assigned the same reference numerals. Duplicate explanations will be omitted as appropriate.

[0131] The product-sum operation circuit of FIG. 23 differs from the product-sum operation circuit of FIG. 3 in that an SRAM 351 and a feedback circuit 352 are provided instead of the three-terminal nonvolatile memory 51 and the feedback circuit 52 .

[0132] 23, 3×3 memory cells each consisting of an SRAM 351 and a feedback circuit 352 are arranged in a plane. The SRAM 351 is a volatile memory, and stores written information for, for example, the period while power is being supplied.

[0133] FIG. 24 is a diagram showing configuration examples of a conventional memory cell and a memory cell according to the present technology.

[0134] As shown in A of Figure 24, a conventional memory cell is an SRAM consisting of, for example, eight transistors, and is connected to three horizontal wirings including one word line and two bit lines, and to a vertical wiring including one word line and two bit lines.

[0135] 24B, the memory cell of the present technology is configured by connecting a feedback circuit 352 to a latch unit of an SRAM 351 configured with, for example, six transistors. The SRAM 351 is connected to an input circuit 53 via one word line as horizontal wiring, and to an output circuit 54 via two bit lines as vertical wiring.

[0136] The feedback circuit 352 is connected to the input circuit 53 via word lines serving as horizontal wiring to which the SRAM 351 is connected, and is connected to the output circuit 54 via vertical signal lines 361. The feedback circuit 352 writes information based on the input from the input circuit 53 and the output from the output circuit 54 to the SRAM 351.

[0137] In this way, while a conventional memory cell requires six wires, the memory cell of the present technology can achieve inference processing and learning using only four wires.

[0138] FIG. 25 is a diagram showing an example of the configuration of the feedback circuit 352.

[0139] As shown in FIG. 25, the feedback circuit 352 is composed of diffusion memristors 381 and 382 .

[0140] The diffusion memristors 381 and 382 are elements having three terminals and volatilely storing resistance values. An input signal X is input to the gate of the diffusion memristor 381, and an output signal Y is input to the drain. The diffusion memristor 83 receives the output signal Y as an input to its gate and the input signal X as an input to its drain.

[0141] The diffusion memristors 381 and 382 output a signal input to the drain from the source in response to a signal input to the gate.

[0142] If the rising time of the output signal Y is later than the rising time of the input signal X, first, when the input signal X rises, the gate of the diffusion memristor 381 is turned on, and the output signal Y passes through the diffusion memristor 381 and is input to the left latch unit of the SRAM 351. When the output signal Y is input to the left latch unit of the SRAM 351, the left latch unit of the SRAM 351 holds information "1" and the right latch unit holds information "0".

[0143] On the other hand, if the rising time of the output signal Y is earlier than the rising time of the input signal X, first, when the output signal Y rises, the gate of the diffusion memristor 382 is turned on, and the input signal X passes through the diffusion memristor 382 and is input to the right latch unit of the SRAM 351. When the input signal X is input to the right latch unit of the SRAM 351, the left latch unit of the SRAM 351 holds information "0" and the right latch unit holds information "1".

[0144] 23, when an input signal is input from the input circuit 53 to the SRAM 351 via a word line, the information held in the SRAM 351 is read out via a bit line by the output circuit 54. In the inference process, the information held in the SRAM 351 is multiplied by the input signal as a weight, and the calculation result obtained by adding the weighted input signals in each SRAM 351 is output as inference data.

[0145] 23, the word lines in the first to third rows, the SRAM in the second column, and the bit line in the second column are shown in gray, which indicates that an input signal is input to the SRAM 351 in the second column via the word lines in the first to third rows, and information read from the SRAM 351 in the second column is added by the bit line in the second column and input to the output circuit 54. In other words, one perceptron is configured by the SRAM 351, bit line, and output circuit 54 arranged in the same column.

[0146] Furthermore, when the output from the output circuit 54 is input to the feedback circuit 352 via the vertical signal line 361, information based on the input of the input circuit 53 and the output of the output circuit 54 is written to the SRAM 351. Therefore, even if the peripheral circuit 55 does not perform calculations such as calculations of the amount of change in the weights, the weights used in the inference process are updated according to the output from the output circuit 54.

[0147] In Figure 23, the feedback circuit 352 in the second column and the vertical signal line 361 in the second column are shown with dashed lines, which indicates that the output from the output circuit 54 is input to the feedback circuit 352 in the second column via the vertical signal line 361 in the second column, and the weights held in each SRAM 351 in the second column are updated collectively by each feedback circuit 352 in the second column.

[0148] 26 is a diagram showing a first modified example of the configuration of a perceptron. In the example of FIG. 26, an input signal X is input to the drain of the three-terminal nonvolatile memory 51 of the memory cell on the left side. i-1 is input, and the input signal X i is input, and the input signal X i+1 is entered.

[0149] Although the above describes an example in which the feedback circuit 52 is connected to the horizontal signal line 61 (the drain of the three-terminal nonvolatile memory 51), the feedback circuit 52 may also be connected to the vertical signal line 62 (the source of the three-terminal nonvolatile memory 51) as shown in Fig. 26. In other words, the feedback circuit 52 may be connected to the previous stage of the three-terminal nonvolatile memory 51, or may be connected to the subsequent stage of the three-terminal nonvolatile memory 51.

[0150] When connected to the front stage of the three-terminal nonvolatile memory 51, for example, the feedback circuit 52 of the central memory cell iThe gate voltage of the three-terminal nonvolatile memory 51 is controlled in accordance with the time difference between the output signal Y and the output signal Y. That is, the gate voltage of the three-terminal nonvolatile memory 51 is controlled for each memory cell.

[0151] On the other hand, when connected to the rear stage of the three-terminal nonvolatile memory 51, for example, the feedback circuit 52 of the central memory cell receives the weighted input signal X i-1 , X i , X i+1 The gate voltage of the three-terminal nonvolatile memory 51 is controlled in accordance with the time difference between the input signal to which the values ​​are added and the output signal Y. That is, the gate voltage of the three-terminal nonvolatile memory 51 is controlled for each perceptron.

[0152] FIG. 27 is a diagram showing a second modified example of the configuration of the perceptron.

[0153] 27 , a feedback circuit 401 provided for each perceptron is connected to a vertical signal line 62 and a vertical signal line 63. In other words, one feedback circuit 401 is provided for a plurality of three-terminal nonvolatile memories 51, and the feedback circuit 401 is connected to the subsequent stage of the three-terminal nonvolatile memory 51 (the previous stage of the output circuit 54) and the subsequent stage of the output circuit 54.

[0154] The feedback circuit 401 receives the input signal X i-1 , input signal X i , and the input signal X i+1 The gate voltages of all three-terminal nonvolatile memories 51 that make up the perceptron are collectively controlled according to the input signal to which the sum of the signals is added and the output signal Y. Since there is no need to provide a feedback circuit in each memory cell, it is possible to reduce the circuit area of ​​the product-sum operation circuit.

[0155] - About CMOS The product-sum circuit of this technology can be realized using CMOS (Complementary Metal-Oxide-Semiconductor).

[0156] FIG. 28 is a cross-sectional view schematically illustrating the configuration of a product-sum calculation circuit according to the present technology.

[0157] 28 , in the product-sum calculation circuit of the present technology, wiring layers 502 to 506 are stacked on the upper side of a substrate 501 made of Si or the like. Etch stop films 511 to 515 made of SiN, BN, SiON, SiC, or the like are formed on the upper side of the wiring layers 502 to 506, respectively.

[0158] A transistor 531 is formed on a substrate 501, and the source / drain regions of the transistor 531 are connected to a metal layer 533 formed on a wiring layer 502 by an electrode 532. In Fig. 28, the metal layer and the through electrode are made of, for example, Cu, and a barrier metal film is formed between the metal layer and the interlayer film of the wiring layer.

[0159] An ECRAM 534 is formed in the wiring layer 505 as a three-terminal nonvolatile memory 51. The ECRAM 534 is composed of a gate electrode 601, a drain electrode 602, a source electrode 603, a channel region (first electrochemical cell) 604, an insulating film 605 acting as a solid electrolyte, and a second electrochemical cell 606. The gate electrode 601, the drain electrode 602, and the source electrode 603 are made of Ti, TiN, TaN, Au, Pt, Pd, Cu, ITO, or the like, and the channel region 604 is made of WO3, TiO2, LiCoO2, or the like. The insulating film 605 is made of HfO2, YSZ (Yttria-Stabilized Zirconia), BZY (Yttria-doped Barium Zirconate), HZO (Hafnium-Zirconium Oxide), Nafion, LiPON, or the like, and the second electrochemical cell 606 is made of WO 3-x , TiO 2-x The second electrochemical cell 606 may not be provided.

[0160] In the ECRAM 534, the concentrations of chemical elements are different between the two electrochemical cells, so that oxygen intercalation ions are transferred between the two electrochemical cells, and the conductance of the channel of the first electrochemical cell changes due to a redox process.

[0161] An etch stop film 513 is formed between the ECRAM 534 and the interlayer film of the wiring layer 505 and between the ECRAM 534 and the interlayer film of the wiring layer 504 .

[0162] The gate electrode 601 is connected to a metal layer 535 formed on the wiring layer 505, and the drain electrode 602 is connected to a metal layer 536 formed on the wiring layer 504 and a metal layer 537 formed on the wiring layer 503. The source electrode 603 is connected to a metal layer 538 formed on the wiring layer 505.

[0163] A diffusion memristor 539 included in the feedback circuit 52 is formed in the wiring layer 506. The diffusion memristor 539 is composed of a gate electrode 621, a drain electrode 622, a source electrode 623, an insulating film 624, and a metal film 625. The gate electrode 621, the drain electrode 622, and the source electrode 623 are made of Ti, TiN, TaN, Au, Pt, Pd, Cu, ITO, or the like, and the insulating film 624 is made of SiO2, SiO x N y , Ta2O5, etc. The metal film 625 is made of Ag, Cu, etc.

[0164] A diffusion memristor is an element that stores resistance values ​​volatilically by utilizing the phenomenon that, when a voltage is applied between electrodes, an Ag filament is formed in the insulating film due to the electric field, reducing the resistance between the source and drain, but when the voltage is removed, the Ag granulates to minimize the interfacial energy, increasing the resistance between the source and drain. Diffusion memristor 539 is an element in which such a diffusion memristor has been converted into a three-terminal element. When a gate voltage is applied, a filament is formed, reducing the resistance between the source and drain, but when the gate voltage is removed, the filament disintegrates, increasing the resistance between the source and drain.

[0165] An etch stop film 514 is formed between the diffusion memristor 539 and the interlayer film of the wiring layer 506 and between the diffusion memristor 539 and the interlayer film of the wiring layer 505 .

[0166] The gate electrode 621 is connected to a metal layer 540 formed on the wiring layer 506, and the drain electrode 622 is connected to metal layers 541 to 544 formed on the wiring layers 505 to 502, respectively. The source electrode 623 is connected to a metal layer 545 formed on the wiring layer 506.

[0167] Next, the flow of forming the product-sum calculation circuit of FIG. 28 will be described.

[0168] First, a transistor such as a planar type or FinFET type is formed on a substrate 501 in a normal FEOL (Front-End-Of-Line) process. In the FEOL process, a feedback circuit 52 is formed. Next, a desired lower electrode is formed in a wiring layer, and then an ECRAM 534 is formed. A gate electrode 601 of the ECRAM 534 is connected to the output side of the feedback circuit 52. The ECRAM 534 may be a planar type, a FinFET type, or a vertical type (wherein the channel is formed like a contact between upper and lower wiring).

[0169] Next, the upper and lower wirings are connected to the ECRAM 534 by a wiring via process or the like. Next, a diffusion memristor 539 is formed in the wiring layer. Specifically, an insulating film 624 is formed between the drain electrode 622 and the source electrode 623, and a gate electrode 621 is formed so that Ag can be introduced and extracted from the insulating film 624.

[0170] In this manner, the product-sum calculation circuit shown in FIG. 28 is formed.

[0171] In the FEOL process, the diffusion memristor included in the feedback circuit 52 may be formed on the substrate 501 as a CMOS circuit.

[0172] Fig. 29 is a diagram illustrating the operation of a CMOS circuit as a diffusion memristor. In the example of Fig. 29, the diffusion memristor is configured as a CMOS circuit in which one end of a resistor is grounded and the other end of a capacitor is connected to the gate of a MOSFET.

[0173] As shown in FIG. 29A, when no pulse is input to the gate of the MOSFET, the conductance is low and the MOSFET does not pass much of the pulse.

[0174] As shown in Figure 29B, when a pulse is input to the gate of the MOSFET, charge is stored in the capacitor and the gate of the MOSFET is turned on, thus increasing the conductance and allowing the MOSFET to pass the pulse.

[0175] As shown in Figure 29C, when a certain period of time has passed since a pulse was input to the gate of the MOSFET, the charge stored in the capacitor is gradually released to ground via the resistor, gradually turning the gate of the MOSFET off. This reduces the conductance, and the MOSFET does not pass as many pulses through.

[0176] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0177] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0178] Example of configuration combinations The present technology can also be configured as follows.

[0179] (1) A signal processing device comprising: a plurality of memories that hold written information for a predetermined period and weight an input signal using a weight based on the information and output the weighted input signal; an output circuit that outputs an output signal in accordance with the input signal weighted by each of the plurality of memories; and a feedback circuit that writes the information based on the time difference between the input signal and the output signal to the memory. (2) The signal processing device described in (1), wherein the feedback circuit writes the information in accordance with the positive / negative or degree of the time difference between the input signal and the output signal to the memory. (3) The signal processing device described in (2), wherein the feedback circuit writes the information to the memory that strengthens the weight when the time difference between the input signal and the output signal is positive. (4) The signal processing device described in (3), wherein the feedback circuit writes the information to the memory that strengthens the weight as the degree of the time difference between the input signal and the output signal becomes smaller. (5) The signal processing device according to any one of (2) to (4), wherein the feedback circuit writes the information to the memory to weaken the weight when the time difference between the input signal and the output signal is negative. (6) The signal processing device according to (5), wherein the feedback circuit writes the information to the memory to weaken the weight as the time difference between the input signal and the output signal becomes smaller. (7) The signal processing device according to any one of (1) to (6), wherein the memory has at least three terminals, and the feedback circuit writes the information to the memory by controlling a gate voltage of the memory to change a resistance value between the source and drain of the memory. (8) The signal processing device according to (7), wherein the memory is configured by a resistive element having a gate or a nonvolatile memory element having a gate, or a combination of a transistor having a gate and a resistive element or a nonvolatile memory element. (9) The signal processing device according to any one of (1) to (8), wherein the input signal and the output signal are pulse wave or rectangular wave signals. (10) The signal processing device according to any one of (1) to (9), wherein the feedback circuit includes a diffusion memristor.(11) The signal processing device according to (10), wherein the feedback circuit is configured by the diffusion memristor, the gate of which receives the input signal and the drain of which receives the output signal, and the drain of the diffusion memristor, the gate of which receives the output signal and the drain of which receives a negative pulse wave signal based on the input signal. (12) The signal processing device according to any of (1) to (11), wherein the feedback circuit resets the information held in the memory when a control signal is input. (13) The signal processing device according to any of (1) to (11), wherein one feedback circuit is provided for one memory. (14) The signal processing device according to (13), wherein the feedback circuit receives the input signal to the memory or the input signals weighted by each of a plurality of memories. (15) The signal processing device according to any of (1) to (12), wherein one feedback circuit is provided for a plurality of the memories. (16) The signal processing device according to (1) to (6), wherein the memory is an SRAM. (17) The signal processing device according to (16), wherein the feedback circuit is configured by a diffusion memristor having a gate to which the input signal is input and a drain to which the output signal is input, and a diffusion memristor having a gate to which the output signal is input and a drain to which the input signal is input. (18) A method for manufacturing a semiconductor device comprising: a plurality of nonvolatile memories that hold written information for a predetermined period and weight an input signal using a weight based on the information and output the weighted input signal; an output circuit that outputs an output signal in accordance with the input signal weighted by each of the plurality of memories; and a feedback circuit that writes the information based on a time difference between the input signal and the output signal to the memories, wherein at least a part of the feedback circuit is formed on a substrate, and the memories are formed in a wiring layer stacked on the substrate.

[0180] 51 Three-terminal nonvolatile memory, 52 Feedback circuit, 53 Input circuit, 54 Output circuit, 55 Peripheral circuit, 81 Negative pulse generating circuit, 82, 83 Diffused memristor, 101 Capacitor, 102 Resistor, 103 Inverter, 104 Delay circuit, 105 AND circuit, 121 Resistor, 122 Delay circuit, 151 Inverter, 152 Capacitor, 153, 154 Diode, 155 Resistor, 201 MOSFET, 202 Resistor, 203 MOSFET, 204 Capacitor, 205 MOSFET, 206 Resistor, 207 MOSFET, 208 Capacitor, 209 MOSFET, 251 MOSFET, 252 Capacitor, 253 MOSFET, 254 Capacitor, 255 MOSFET, 301, 302 MOSFET, 351 SRAM, 352 Feedback circuit, 381, 382 Diffused memristor, 401 Feedback circuit

Claims

1. A signal processing device comprising: a plurality of memories which hold written information for a predetermined period of time and weight an input signal using a weight based on said information and output the weighted input signal; an output circuit which outputs an output signal in response to the input signal weighted by each of said plurality of memories; and a feedback circuit which writes the information based on the time difference between the input signal and the output signal into said memories.

2. The signal processing device according to claim 1, wherein said feedback circuit writes said information according to the positive / negative or degree of the time difference between said input signal and said output signal into said memory.

3. The signal processing device according to claim 2, wherein said feedback circuit writes said information for strengthening said weight to said memory when the time difference between said input signal and said output signal is positive.

4. The signal processing device according to claim 3, wherein said feedback circuit writes into said memory said information such that the smaller the time difference between said input signal and said output signal is, the stronger said weight is.

5. The signal processing device according to claim 2, wherein said feedback circuit writes said information to said memory so as to weaken said weight when the time difference between said input signal and said output signal is negative.

6. The signal processing device according to claim 5, wherein said feedback circuit writes into said memory said information that weakens said weight as the degree of the time difference between said input signal and said output signal becomes smaller.

7. The signal processing device according to claim 1, wherein the memory has at least three terminals, and the feedback circuit controls a gate voltage of the memory to change a resistance value between a source and a drain of the memory, thereby writing the information to the memory.

8. The signal processing device according to claim 7, wherein the memory is configured by a resistive element having a gate, a non-volatile memory element having a gate, or a combination of a transistor having a gate and a resistive element or a non-volatile memory element.

9. The signal processing device according to claim 1, wherein the input signal and the output signal are pulse wave or rectangular wave signals.

10. The signal processing device according to claim 1, wherein the feedback circuit includes a diffusion memristor.

11. The signal processing device according to claim 10, wherein the feedback circuit is composed of the diffusion memristor, the gate of which receives the input signal and the drain of which receives the output signal, and the diffusion memristor, the gate of which receives the output signal and the drain of which receives a negative pulse wave signal based on the input signal.

12. The signal processing device according to claim 1, wherein the feedback circuit resets the information held in the memory when a control signal is input.

13. The signal processing device according to claim 1, wherein one of the feedback circuits is provided for one of the memories.

14. The signal processing device according to claim 13, wherein the input signal input to the memory or the input signals weighted by each of the plurality of memories are input to the feedback circuit.

15. The signal processing device according to claim 1, wherein one feedback circuit is provided for a plurality of memories.

16. The signal processing device according to claim 1, wherein the memory is an SRAM.

17. The signal processing device according to claim 16, wherein the feedback circuit is composed of a diffusion memristor having a gate to which the input signal is input and a drain to which the output signal is input, and a diffusion memristor having a gate to which the output signal is input and a drain to which the input signal is input.

18. A method for manufacturing a semiconductor device comprising: a plurality of memories that retain written information for a predetermined period of time and weight and output an input signal using a weight based on the information; an output circuit that outputs an output signal in response to the input signal weighted by each of the plurality of memories; and a feedback circuit that writes the information based on the time difference between the input signal and the output signal into the memory, wherein at least a portion of the feedback circuit is formed on a substrate, and the memory is formed in a wiring layer stacked on the substrate.

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