Three-dimensional stacked capacitor array string structure for physical unclonable function, and operating method thereof

Abstract

A three-dimensional stacked capacitor array string structure for a physical unclonable function (PUF), and an operating method thereof are disclosed. The three-dimensional stacked capacitor array string structure for a PUF, presented in the present invention, is an array composed of memory elements for a PUF, comprising: wordlines to which challenges are applied; bitlines from which responses according to the applied challenges are extracted; and strings, which use the three-dimensional stacked capacitor array structure in order to perform encryption for the PUF, so as to extract a plurality of challenge-response pairs according to the difference in selection method.

Description

A three-dimensional stacked capacitor array string structure for physically unclonable functions and its operating method

[0001] The present invention relates to a three-dimensional stacked capacitor array string structure for a physically non-replicable function and an operating method thereof.

[0002] The proliferation of mobile devices and the rapid growth of smart communication technologies are driving the demand for reliable encryption solutions for secure communications.

[0003] In the existing security and authentication fields, encryption has mostly been performed through software security methods. However, existing software-based encryption solutions have recently caused many security incidents, such as personal information leaks, and the need for more powerful security solutions is increasing.

[0004] As security incidents such as personal information leaks increase in modern society, higher security is required. To this end, research on PUFs, which utilize unpredictable characteristics such as hardware manufacturing process deviations and intrinsic characteristics for encryption, is actively being conducted.

[0005] Therefore, a large number of challenge-response pairs are essential for generating a security key, and the physically unclonable function, which basically performs encryption by utilizing the unique physical characteristics of the device, is suitable for high security because it is difficult to copy or hack because it utilizes physical characteristics.

[0006] The technical problem to be achieved by the present invention is to propose a physically unclonable function (PUF) technology, which is a hardware-based security technology that can be utilized in two ways through a three-dimensional stacked capacitor array structure. The PUF can be utilized in two ways depending on the string selection method in the three-dimensional structure. If a string is selected randomly, it can be utilized in a challenge (input)-response (output) mode. If only one string is selected, it can be utilized in a mode where each two-dimensional array is used as an independent, individual physically unclonable function, allowing multiple PUF chip operations to be performed within a single array.

[0007] In one aspect, the three-dimensional stacked capacitor array structure for a physically unclonable function proposed in the present invention includes a wordline to which a challenge is applied in an array composed of memory elements for a physical unclonable function (PUF), a bitline from which a response according to the applied challenge is extracted, and a string for extracting a plurality of challenge-response pairs according to a difference in a selection method using the three-dimensional stacked capacitor array structure to perform encryption for the PUF.

[0008] In the three-dimensional stacked capacitor array structure according to an embodiment of the present invention, since the capacitor elements are connected in parallel, parallel operation is possible, and a plane of the three-dimensional stacked capacitor array structure for operation in a challenge-response mode or a multi-chip mode is selected depending on the selection method of the word line, the bit line, and the string.

[0009] According to an embodiment of the present invention, in order to maximize the number of security keys using PUF by utilizing all xyz planes of a three-dimensional stacked capacitor array structure according to the selection method of the word line, the bit line, and the string, the operation principle of the challenge-response mode is shown by randomly setting all word lines and string selections.

[0010] According to an embodiment of the present invention, the xz plane of the three-dimensional stacked capacitor array structure is utilized as one PUF chip according to the selection method of the word line, the bit line, and the string, thereby demonstrating the operating principle of a multi-chip mode through the independent use of individual PUF chips in the z direction.

[0011] In another aspect, the operating method of the three-dimensional stacked capacitor array structure for a physically unclonable function proposed in the present invention includes a step of applying a challenge to a wordline in an array composed of memory elements for a physically unclonable function (PUF), a step of extracting a response according to the applied challenge from a bitline, and a step of extracting a plurality of challenge-response pairs according to a difference in a selection method using a string of the three-dimensional stacked capacitor array structure to perform encryption for the PUF.

[0012] According to embodiments of the present invention, a three-dimensional stacked capacitor array string structure for a physically unclonable function (PUF) and an operating method thereof are provided, so that the PUF can be utilized in two ways depending on a string selection method in a three-dimensional structure, and can be utilized in a challenge (input)-response (output) mode when a string is randomly selected. Since the three-dimensional structure is utilized, the number of challenge-response pairs increases exponentially, so that it can be utilized as a very strong physically unclonable function. In addition, if only one string is selected, a mode in which each two-dimensional array is utilized as an independent, individual physically unclonable function can be performed, so that multiple PUF chip operations can be performed within a single array.

[0013] FIG. 1 is a drawing showing a three-dimensional stacked capacitor array string structure for a physically non-replicable function according to one embodiment of the present invention.

[0014] FIG. 2 is a diagram for explaining a challenge-response mode according to one embodiment of the present invention.

[0015] FIG. 3 is a drawing for explaining a multi-chip mode according to one embodiment of the present invention.

[0016] FIG. 4 is a flowchart illustrating an operation method of a three-dimensional stacked capacitor array for a physically non-replicable function according to one embodiment of the present invention.

[0017] FIG. 5 is a drawing showing a cross-sectional TEM image of a MOS capacitor having a TANOS stack according to one embodiment of the present invention.

[0018] FIG. 6 is a diagram showing charging currents for different threshold voltages of a MOS capacitor according to one embodiment of the present invention.

[0019] FIG. 7 is a diagram showing a Hamming weight distribution, an inter-Hamming distance distribution, and an intra-Hamming distance distribution for a multi-chip mode in a CRP mode according to one embodiment of the present invention.

[0020] The present invention proposes a Physical Unclonable Function (PUF) technology, a hardware-based security technology that can be utilized in two ways using a three-dimensional stacked capacitor array structure. The PUF can be utilized in two ways depending on the string selection method in the three-dimensional structure. When a string is selected randomly, it can be utilized in a challenge (input)-response (output) mode. This can be utilized as a very strong physically unclonable function because the number of challenge-response pairs increases exponentially due to the use of the three-dimensional structure. Additionally, when only one string is selected, each two-dimensional array can be utilized as an independent, individual physically unclonable function, allowing multiple PUF chip operations to be performed within a single array. Unlike software-based methods, the present invention proposes a hardware physical unclonability function that is unpredictable due to the three-dimensional structure of memory semiconductors. By utilizing a three-dimensional stacked array structure of capacitor elements with memory functions, it is possible to operate as a very strong physically unclonable function in which each challenge-response pair can increase exponentially by changing the string selection method, and as a more random physically unclonable function with added dispersion between each chip. The hardware security technology can be applied in processes such as encryption key generation or security authentication, and can be utilized in various IoT devices. Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0021]

[0022] FIG. 1 is a drawing showing a three-dimensional stacked capacitor array string structure for a physically non-replicable function according to one embodiment of the present invention.

[0023] In arrays composed of memory elements, PUFs are typically implemented for security and authentication by extracting responses from bitlines (BL) when a challenge is applied along a wordline (WL). Various challenge application and response extraction methods are utilized, and responses are typically extracted through random current comparisons resulting from matrix multiplication operations performed upon voltage application.

[0024] At this time, PUF functionality is implemented by exploiting manufacturing process variations, device-to-device variations, and variations due to program erase operations. Therefore, obtaining a random source for a random PUF chip is crucial. Furthermore, since challenge-response pairs used for security and authentication cannot be reused, obtaining as many challenge-response pairs as possible becomes a crucial factor.

[0025] The present invention proposes a PUF technology that can be utilized in two modes by exploiting differences in string selection methods through the structural characteristics of a three-dimensional stacked capacitor array. This ensures that the PUF can be utilized in a very robust PUF mode with exponentially increasing challenge-response, and in a more random PUF mode by utilizing the deviation between two-dimensional PUFs as an additional random source.

[0026] The structure of a three-dimensional stacked capacitor array (i WLs, j strings, k BLs) and a plane selection method for utilizing each mode according to one embodiment of the present invention are shown. In the array structure, capacitor elements are connected in parallel, so parallel operation is possible, and through this, by differentiating the string selection method, two modes of operation are possible.

[0027] A three-dimensional stacked capacitor array string structure for a physically unclonable function according to an embodiment of the present invention includes a wordline (110) to which a challenge is applied in an array composed of memory elements for a physically unclonable function (PUF), a bitline (120) from which a response according to the applied challenge is extracted, and a string (130) for extracting a plurality of challenge-response pairs according to a difference in a selection method using the three-dimensional stacked capacitor array structure to perform encryption for the PUF.

[0028] According to an embodiment of the present invention, since the capacitor elements in the three-dimensional stacked capacitor array structure are connected in parallel, parallel operation is possible, and through this, two modes of operation are possible by differentiating the method of string selection.

[0029] According to an embodiment of the present invention, a plane of a three-dimensional stacked capacitor array structure for operation in a challenge-response mode (141) or a multi-chip mode (142) can be selected depending on the selection method of the word line (110), the bit line (120), and the string (130).

[0030] By utilizing a three-dimensional memory array, the number of challenge-response pairs in a PUF chip can be exponentially increased, enabling it to operate as a very strong PUF, thereby enhancing security. Furthermore, since multiple independent two-dimensional PUF chips can be utilized by selecting only one string at a time, it becomes possible to operate multiple PUF chips within a single memory chip. Since the random characteristics of the basic PUF chip can be additionally utilized to exploit the variation between PUF chips, even greater randomness can be guaranteed.

[0031] According to one embodiment of the present invention, in order to maximize the number of security keys using PUF by utilizing all xyz planes of a three-dimensional stacked capacitor array structure according to the selection method of the word line (110), the bit line (120), and the string (130), the operation principle of the challenge-response mode (141) can be expressed by randomly setting all word lines and string selections.

[0032] According to another embodiment of the present invention, the xz plane of the three-dimensional stacked capacitor array structure can be utilized as one PUF chip depending on the selection method of the word line (110), the bit line (120), and the string (130), thereby demonstrating the operating principle of the multi-chip mode (141) through the independent use of individual PUF chips in the z direction.

[0033]

[0034] FIG. 2 is a diagram for explaining a challenge-response mode according to one embodiment of the present invention.

[0035] Figure 2 illustrates the operating principle of the challenge-response mode, which can maximize the number of security keys by utilizing the entire 3D xyz plane. Since the number of inputs that can be set can increase exponentially when all word lines and string selections are randomly set, the number of challenge-response pairs also increases exponentially, enabling operation as a highly robust PUF with a high level of security.

[0036] In one embodiment of the present invention, if a method of generating a response by randomly selecting two BLs and comparing them is selected, WL selection method 2 i Dog, How to Select String 2 j Dog, How to Choose BL k The total number of CRPs (Challenge-Response Pairs) multiplied by C2 (2) i x 2 j x kC2) can be secured. However, this is only one example, and in addition, various CRPs can be generated depending on the selection method of the word line, the bit line, and the string, thereby indicating an operation mode according to plane selection.

[0037]

[0038] FIG. 3 is a drawing for explaining a multi-chip mode according to one embodiment of the present invention.

[0039] Figure 3 illustrates the operating principle of the multi-chip mode by utilizing the xz plane as a single PUF chip in a three-dimensional structure and utilizing independent individual PUF chips in the z direction. When one string is selected, the two-dimensional array corresponding to each string can be independently utilized as a single PUF chip, and multi-chip mode operation that can utilize multiple PUF chips in a single memory chip is possible. Similarly, if a method of generating a response by randomly selecting two BLs and comparing them is selected, WL selection method 2 i Dog, How to Choose BL k Total number of CRPs multiplied by C2 (2) i x k C2) can be secured. This is only one example, and in addition, various CRPs can be generated depending on the selection method of the word line, bit line, and string, thereby indicating an operation mode according to plane selection.

[0040]

[0041] FIG. 4 is a flowchart illustrating an operation method of a three-dimensional stacked capacitor array for a physically non-replicable function according to one embodiment of the present invention.

[0042] An operating method of a three-dimensional stacked capacitor array for a physically unclonable function according to one embodiment of the present invention includes a step (410) of applying a challenge to a wordline in an array composed of memory elements for a physically unclonable function (PUF), a step (420) of extracting a response according to the applied challenge from a bitline, and a step (430) of extracting a plurality of challenge-response pairs according to a difference in a selection method using a string of a three-dimensional stacked capacitor array structure to perform encryption for the PUF.

[0043] In step (410), a challenge is applied to a wordline in an array composed of memory elements for a physically unclonable function (PUF).

[0044] In step (420), a response according to the above-mentioned challenge is extracted from the bitline.

[0045] In step (430), a string of a three-dimensional stacked capacitor array structure is used to extract multiple challenge-response pairs according to differences in selection methods to perform encryption for PUF.

[0046] According to an embodiment of the present invention, since the capacitor elements in the three-dimensional stacked capacitor array structure are connected in parallel, parallel operation is possible, and through this, two modes of operation are possible by differentiating the method of string selection.

[0047] In step (430), since the capacitor elements in the three-dimensional stacked capacitor array structure are connected in parallel, parallel operation is possible, and a plane of the three-dimensional stacked capacitor array structure for operation in challenge-response mode (431) or multi-chip mode (432) is selected depending on the selection method of the word line, the bit line, and the string.

[0048] In step (431), all word lines and strings may be randomly selected to operate in a challenge-response mode in order to maximize the number of security keys using PUF by utilizing all xyz planes of the three-dimensional stacked capacitor array structure according to the selection method of the word line, the bit line, and the string.

[0049] In step (432), depending on the selection method of the word line, the bit line, and the string, the xz plane of the three-dimensional stacked capacitor array structure can be utilized as one PUF chip to operate in a multi-chip mode through independent individual PUF chip utilization in the z direction.

[0050]

[0051] FIG. 5 is a drawing showing a cross-sectional TEM image of a MOS capacitor having a TANOS stack according to one embodiment of the present invention.

[0052] A specific embodiment of the present invention utilizes a MOS capacitor array having a TANOS (TiN / Al2O3 / Si3N4 / SiO2 / Si) stack. The structure can operate as a capacitor with memory function by changing the threshold voltage depending on the degree of charge stored in the charge trap layer. The present invention is not limited to the structure and can be applied to an array of capacitors (such as ferroelectric capacitors) with memory function.

[0053]

[0054] FIG. 6 is a diagram showing charging currents for different threshold voltages of a MOS capacitor according to one embodiment of the present invention.

[0055] The operating mechanism of reading a capacitor is as follows: first, a charging voltage (Vc) is applied to the gate electrode to charge the capacitor. Then, the gate bias is changed to a discharging voltage (Vd) to detect the charge accumulated across the capacitor in the BL direction. The threshold voltage (Vth) of the MOS capacitor can be adjusted by program and erase operations thanks to the charge trap layer, so that the accumulated charge can be modulated accordingly. During the transition period from Vc to Vd, the discharge current flows in the BL direction, and the amount of charge (Q) discharged during this period is determined by the Vth of the capacitor.

[0056]

[0057] FIG. 7 is a diagram showing a Hamming weight distribution, an inter-Hamming distance distribution, and an intra-Hamming distance distribution for a multi-chip mode in a CRP mode according to one embodiment of the present invention.

[0058] Based on the operating characteristics of the MOS capacitor according to one embodiment of the present invention, a three-dimensional stacked capacitor array was configured and the operating characteristics of the PUF were confirmed as shown in Fig. 7 when operated in each mode, and uniformity, diffusion, and uniqueness close to 50% can be secured in both modes.

[0059] Possible BL selection cases for two operating modes according to embodiments of the present invention ( 16The main PUF metrics are analyzed by grouping the number of C2 = 120-bit keys. The 1k challenge is tested with 1k random WL selection in multi-chip mode, while the 1M challenge is tested with an additional 1k random string selection in CRP mode. The extracted Hamming weight distributions are shown in Fig. 7(a), confirming that the extracted uniformity is ~50% in both modes. As shown in Fig. 7(b), the total Hamming distance is 0.01 for multi-chip mode and CRP mode, respectively. 1k C2= ~500k and 1M A diffusion of ~50% was verified using C2 = ~0.5T. The uniqueness of multiple PUF chips in a single 3D array structure is shown in Fig. 7(c) along the string (z) axis (total Hamming distance 1,000 × 16 It is evaluated at ~50% on 16 PUF instances along with C2= 120k.

[0060]

[0061] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

[0062] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0063] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0064] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0065] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A wordline to which a challenge is applied in an array composed of memory elements for a physically unclonable function (PUF); A bitline from which a response is extracted according to the above-mentioned challenge; and A string that extracts multiple challenge-response pairs according to the difference in selection method using a three-dimensional stacked capacitor array structure to perform encryption for PUF. A capacitor array structure including:

2. In paragraph 1, In the above three-dimensional stacked capacitor array structure, the capacitor elements are connected in parallel, so parallel operation is possible. Selecting a plane of a three-dimensional stacked capacitor array structure for operation in a challenge-response mode or a multi-chip mode according to the selection method of the word line, the bit line, and the string. Capacitor array structure.

3. In paragraph 2, In order to maximize the number of security keys using PUF by utilizing all xyz planes of the three-dimensional stacked capacitor array structure according to the selection method of the word line, the bit line and the string, all word lines and string selections are randomly set to represent the operating principle of the challenge-response mode. Capacitor array structure.

4. In paragraph 2, The operating principle of the multi-chip mode through the use of independent individual PUF chips in the z direction by utilizing the xz plane of the three-dimensional stacked capacitor array structure as one PUF chip according to the selection method of the word line, the bit line and the string is shown. Capacitor array structure.

5. A step in which a challenge is applied to a wordline in an array composed of memory elements for a physically unclonable function (PUF); A step in which a response according to the above-mentioned authorized challenge is extracted from a bitline; and A step of extracting multiple challenge-response pairs according to differences in selection methods using a string of a three-dimensional stacked capacitor array structure to perform encryption for PUF. A method of operating a capacitor array including:

6. In paragraph 5, The step of extracting multiple challenge-response pairs according to the difference in selection method using a string of a three-dimensional stacked capacitor array structure to perform encryption for the above PUF is as follows. In the above three-dimensional stacked capacitor array structure, the capacitor elements are connected in parallel, so parallel operation is possible. Selecting a plane of a three-dimensional stacked capacitor array structure for operation in a challenge-response mode or a multi-chip mode according to the selection method of the word line, the bit line, and the string. How a capacitor array works.

7. In paragraph 6, The step of extracting multiple challenge-response pairs according to the difference in selection method using a string of a three-dimensional stacked capacitor array structure to perform encryption for the above PUF is as follows. In order to maximize the number of security keys using PUF by utilizing all xyz planes of the three-dimensional stacked capacitor array structure according to the selection method of the word line, the bit line and the string, all word lines and string selections are randomly set to represent the operating principle of the challenge-response mode. How a capacitor array works.

8. In paragraph 6, The step of extracting multiple challenge-response pairs according to the difference in selection method using a string of a three-dimensional stacked capacitor array structure to perform encryption for the above PUF is as follows. The operating principle of the multi-chip mode through the use of independent individual PUF chips in the z direction by utilizing the xz plane of the three-dimensional stacked capacitor array structure as one PUF chip according to the selection method of the word line, the bit line and the string is shown. How a capacitor array works.

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