Capacitor

Abstract

A capacitor according to one embodiment of the present invention comprises: a base which includes a first surface and a second surface opposite to the first surface and which includes a plurality of structures protruding from the second surface in a first direction from the first surface toward the second surface; a first electrode layer disposed on the structure and the second surface between the plurality of structures; a first dielectric layer disposed on the first electrode layer; and a second electrode layer disposed on the first dielectric layer, wherein the second surface between the plurality of structures is more porous than the structure.

Description

capacitor

[0001] An embodiment of the present invention relates to a capacitor.

[0002] Semiconductor packages are used in a variety of fields, including automobiles, communications, and computers. They typically include printed circuit boards (PCBs), semiconductor chips positioned on the PCBs, and passive components positioned on the PCBs. Passive components may include, for example, resistors, inductors, and capacitors.

[0003] As semiconductor packaging becomes more sophisticated, the demand for high-performance, highly reliable, and ultra-small capacitors is increasing. To meet these demands, silicon-based capacitors and anodic aluminum oxide (AAO)-based capacitors have been proposed. Silicon-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on a silicon base, while AAO-based capacitors include electrode layers, dielectric layers, and electrode layers sequentially stacked on an AAO base.

[0004] As the need for reducing the signal path of semiconductor packages and the size of semiconductor packages increases, high-capacity capacitors that can be mounted inside or underneath semiconductor packages are required.

[0005] The technical problem to be achieved by the present invention is to provide an ultra-small and high-capacity capacitor.

[0006] A capacitor according to one embodiment of the present invention comprises a base including a first surface and a second surface opposite the first surface, and a plurality of structures protruding from the second surface along a first direction from the first surface toward the second surface, a first electrode layer disposed on the second surface between the plurality of structures and the structure, a first dielectric layer disposed on the first electrode layer, and a second electrode layer disposed on the first dielectric layer, wherein the second surface between the plurality of structures is more porous than the structures.

[0007] Further comprising a first metal layer disposed between the second surface and the first electrode layer between the plurality of structures, wherein the first metal layer includes at least one of titanium (Ti) and tungsten (W), and the first metal layer can be in direct contact with the first electrode layer.

[0008] The second metal layer may further be disposed between the second surface and the first metal layer between the plurality of structures, and the second metal layer may include at least one of gold (Au) and silver (Ag).

[0009] The second surface between the plurality of structures can be in direct contact with the first electrode layer.

[0010] The average width of the plurality of structures in a second direction perpendicular to the first direction in which the plurality of structures protrude may be 1.5 μm to 3.5 μm, and the average height of the plurality of structures based on the second surface of the base may be 3.5 μm or more and 175 μm or less.

[0011] The average width of the plurality of structures in the second direction may be 2 μm to 3 μm, and the average height of the plurality of structures based on the second surface of the base may be 30 μm or more and 120 μm or less.

[0012] The ratio of the average height of the plurality of structures based on the second surface of the base to the average width of the plurality of structures in a second direction perpendicular to the first direction in which the plurality of structures protrude may be 1 to 50.

[0013] The ratio of the average height of the plurality of structures to the average width of the plurality of structures may be 15 to 40.

[0014] The angle formed by the second surface of the base and the side surface of the structure may be 90 to 100 degrees.

[0015] The first electrode layer may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, and copper (Cu), and the second electrode layer may include aluminum (Al).

[0016] According to another embodiment of the present invention, a capacitor includes a base including a first surface and a second surface opposite to the first surface, and a structure protruding from the second surface in a direction from the first surface toward the second surface, a first metal layer disposed on the second surface and including a first through hole, a second metal layer disposed on the first metal layer and including a second through hole, a first electrode layer disposed on the second metal layer and the structure, a first dielectric layer disposed on the first electrode layer, and a second electrode layer disposed on the first dielectric layer, wherein the structure penetrates the first through hole and the second through hole, an etching rate of the first metal layer is higher than an etching rate of the second metal layer, and a silicon diffusion coefficient of the second metal layer is lower than a silicon diffusion coefficient of the first metal layer.

[0017] The first metal layer may include at least one of gold (Au) and silver (Ag), and the second metal layer may include at least one of titanium (Ti) and tungsten (W).

[0018] According to embodiments of the present invention, an ultra-small, high-capacity capacitor can be provided. Furthermore, according to embodiments of the present invention, a capacitor having a simple manufacturing process, low cost, and high reliability can be provided.

[0019] FIG. 1 is a cross-sectional view of a capacitor according to one embodiment of the present invention.

[0020] Figure 2 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0021] Figure 3 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0022] Figure 4 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0023] Figure 5 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0024] Figure 6 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0025] Figures 7 to 9 illustrate a method for manufacturing a capacitor according to an embodiment of the present invention.

[0026] FIG. 10 is a drawing for explaining an etching mechanism during a manufacturing process of a plurality of structures in a capacitor according to an embodiment of the present invention.

[0027] Figure 11 is an SEM image of a structure manufactured according to an embodiment of the present invention.

[0028] Figures 12 and 13 are cross-sectional views of a capacitor according to another embodiment of the present invention.

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0032] Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

[0033] In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C”, it may include one or more of all combinations that can be combined with A, B, C.

[0034] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0035] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0036] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0037] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it can include the meaning of a downward direction as well as an upward direction based on one component.

[0038] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0039] FIG. 1 is a cross-sectional view of a capacitor according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of a capacitor according to another embodiment of the present invention, FIG. 3 is a cross-sectional view of a capacitor according to another embodiment of the present invention, FIG. 4 is a cross-sectional view of a capacitor according to another embodiment of the present invention, FIG. 5 is a cross-sectional view of a capacitor according to another embodiment of the present invention, and FIG. 6 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0040] Referring to FIGS. 1 to 3, the capacitor (100) includes a base (110), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140).

[0041] The base (110) includes a first surface (111), a second surface (112) opposite the first surface (111), and a third surface (113) disposed between the first surface (111) and the second surface (112). The first surface (111), the second surface (112), and the third surface (113) may be referred to as an upper surface, a lower surface, and a side surface, respectively.

[0042] The base (110) may include a semiconductor material or an insulator material. For example, the base (110) may be a silicon (Si) substrate. For example, the base (110) may be a doped silicon substrate. For example, the base (110) may be an n-type doped silicon substrate or a p-type doped silicon substrate.

[0043] According to an embodiment of the present invention, the base (110) includes a structure (115) protruding from the second surface (112) in a first direction from the first surface (111) toward the second surface (112). The base (110) includes a plurality of structures (115), and the plurality of structures (115) are arranged to be spaced apart from each other. At this time, the plurality of structures (115) include silicon and may be formed integrally with the base (110). That is, the plurality of structures (115) may extend from the second surface (112) of the base (110). The plurality of structures (115) may be formed by a method of etching a silicon substrate. In order to form the plurality of structures (115), the silicon substrate may be etched in a negative or positive manner. The plurality of structures (115) may have the same shape or a regular shape, and the spacing between the plurality of structures (115) may be the same, or may have a pattern of regularly increasing or regularly decreasing.

[0044] According to an embodiment of the present invention, at least some of the plurality of structures (115) may have a cone shape. For example, at least some of the plurality of structures (115) may have a polygonal pyramid shape or a cone shape. For example, at least some of the plurality of structures (115) may have a triangular pyramid shape. Alternatively, at least some of the plurality of structures (115) may have a column shape. For example, at least some of the plurality of structures (115) may have a polygonal column shape or a cylinder shape. For example, at least some of the plurality of structures (115) may have a triangular prism shape. In the present specification, when the ratio of the area of ​​the top surface to the area of ​​the bottom surface of each structure (115) is 1 or less, it may be referred to as a cone shape. That is, when the angle (θ) formed by the bottom surface and the side surface of each structure (115) is less than 90 degrees, it may be referred to as a cone shape. In this specification, when the ratio of the area of ​​the top surface to the area of ​​the bottom surface of each structure (115) is 1, it can be referred to as a columnar shape. That is, when the angle (θ) formed by the bottom surface and the side surface of each structure (115) is 90 degrees, it can be referred to as a columnar shape. Here, the bottom surface of each structure (115) is a surface extending horizontally from the second surface (112) between the plurality of structures (115) to each structure (115), and the top surface of each structure (115) can be an opposite surface in the first direction with respect to the bottom surface of each structure (115).

[0045] At this time, the angle (θ) formed by the bottom and side surfaces of each structure (115) may be 80 to 90 degrees, preferably 85 to 90 degrees. That is, the angle (180-θ) formed by the second surface (112) of the base (110) in the spaced area between the plurality of structures (115), that is, the second surface (112) between the plurality of structures (115), and the side surfaces of each structure (115) may be 90 to 100 degrees, preferably 90 to 95 degrees. When the angle (θ) exceeds 90 degrees, it may be difficult to manufacture the plurality of structures (115), and when the angle (θ) is less than 80 degrees, it may be difficult to have a sufficient specific surface area for implementing a capacitor. When the angle (θ) formed by the bottom and side surfaces of each structure (115) satisfies this numerical range, the number of structures (115) arranged per unit area can be maximized, and the surface area of ​​the structures (115) per unit volume can also be maximized.

[0046] At this time, at least some of the plurality of structures (115) may be parallel to each other. For example, an imaginary extension line from the center of the bottom surface of one of the plurality of structures (115) to the center of the top surface may be parallel to an imaginary extension line from the center of the bottom surface of another of the plurality of structures (115) to the center of the top surface. Accordingly, since the first electrode layer (120) can be deposited with a uniform thickness on the surfaces of the plurality of structures (115), a highly reliable capacitor can be obtained.

[0047] According to an embodiment of the present invention, the average width (D) of the bottom surfaces of the plurality of structures (115) in the second direction perpendicular to the first direction may be 1.5 μm to 3.5 μm, preferably 2 μm to 3 μm. Accordingly, while having a sufficient specific surface area for implementing a capacitor, the possibility of damage to the structure can be minimized and durability can be increased.

[0048] At this time, the average height (H) of the plurality of structures (115) based on the second surface (112) of the base (110) may be 3.5 µm or more and 175 µm or less, preferably 30 µm or more and 120 µm or less, and more preferably 40 µm or more and 60 µm or less. Here, the height (H) of each structure (115) may be the height from the second surface (112) of the base (110). Accordingly, the structure may be easily manufactured while having a sufficient specific surface area for implementing a capacitor.

[0049] Accordingly, the ratio (H / D) of the average height (H) of the plurality of structures (115) based on the second surface (112) of the base (110) to the average width (D) of the plurality of structures (115) in the second direction perpendicular to the first direction in which the plurality of structures (115) protrude may be 1 to 50, preferably 15 to 40, and more preferably 20 to 30. Accordingly, the structure may be easily manufactured while having a sufficient specific surface area for implementing a capacitor.

[0050] According to an embodiment of the present invention, a first electrode layer (120) is disposed on a base (110), a first dielectric layer (130) is disposed on the first electrode layer (120), a second electrode layer (140) is disposed on the first dielectric layer (130), a first electrode pad (150) is connected to the first electrode layer (120), and a second electrode pad (160) is connected to the second electrode layer (140).

[0051] The capacitance of a capacitor can be calculated according to the following mathematical formula 1.

[0052]

[0053] Here, C is the capacitance, ε is the permittivity, S is the area of ​​the electrode layer, and d is the distance between the electrode layers. According to this, it can be seen that the larger the area of ​​the electrode layer, the greater the capacitance.

[0054] According to an embodiment of the present invention, a porous layer (117) is arranged to contact the second surface (112) of the base (110) in a spaced area between a plurality of structures (115). That is, at least a portion of the surface of the second surface (112) of the base (110) in the spaced area between the plurality of structures (115) may be porous. That is, the second surface (112) of the base (110) may be more porous than the structures (115). Alternatively, the second surface (112) of the base (110) may be more porous than the first surface (111) of the base (110). Here, porosity means a form having a large number of small pores. That the second surface (112) of the base (110) may be more porous than the structure (115) may mean that the porosity of the second surface (112) of the base (110) is greater than the porosity of the structure (115). Similarly, that the second surface (112) of the base (110) is more porous than the first surface (111) of the base (110) may mean that the porosity of the second surface (112) of the base (110) is greater than the porosity of the first surface (111) of the base (110).

[0055] According to an embodiment of the present invention, the porous layer (117) may have the same material as the base (110), but may be porous. For example, the porous layer (117) may be a porous silicon layer. That is, the porous layer (117) may be a silicon layer having a large number of fine pores. Accordingly, the specific surface area of ​​the second surface (112) of the base (110) may be increased in the spaced area between the plurality of structures (115).

[0056] Referring to FIG. 1, the second surface (112) of the base (110) between the plurality of structures (115) is in direct contact with the first electrode layer (120). At this time, if the second surface (112) of the base (110) between the plurality of structures (115) is porous, the bonding force between the porous layer (117) and the first electrode layer (120) increases, and the first electrode layer (120) can be evenly arranged in the boundary area between the second surface (112) of the base (110) and the side surface of the structure (115).

[0057] Referring to FIGS. 2 and 3, a first metal layer (1191) is disposed on a porous layer (117) in a spaced area between a plurality of structures (115). When the first metal layer (1191) is disposed on the porous layer (117), the bonding force between the porous layer (117) and the first electrode layer (120) is further increased through the first metal layer (1191), and the upper surface of the first metal layer (1191) can be flattened.

[0058] According to an embodiment of the present invention, the first metal layer (1191) is disposed on the second surface (112) of the base (110) and includes a through hole, and the structure (115) is positioned inside the through hole of the first metal layer (1191). According to an embodiment of the present invention, the structure (115) and the first metal layer (1191) each have a plurality of through holes, and each structure (115) can be disposed in each through hole.

[0059] According to an embodiment of the present invention, a first electrode layer (120) is disposed on a first metal layer (1191) and a structure (115). Accordingly, the first metal layer (1191) can be in contact with the second surface (112) of the base (110), the side surface of the structure (115), and the lower surface of the first electrode layer (120). At this time, the first metal layer (119) and the first electrode layer (120) can be made of the same material or different materials.

[0060] Referring to FIG. 2, the first metal layer (1191) may include at least one of titanium (Ti) and tungsten (W). For example, the first metal layer (1191) may include at least one of titanium (Ti), titanium nitride (TiN), tungsten (W), and titanium tungsten (TiW).

[0061] Compared to the case where the first electrode layer (120) is directly deposited on the second surface (112) of the base (110) made of silicon, when the first electrode layer (120) is deposited on the first metal layer (1191), the thickness of the first electrode layer (120) can be uniformly deposited, and the bonding strength of the first electrode layer (120) can be improved. In particular, when the upper surface of the first metal layer (1191) is flattened by the porous layer (117), the deposition of the first electrode layer (120) is easier.

[0062] Alternatively, referring to FIG. 3, a second metal layer (1192) may be further disposed between the second surface (112) of the base (110) and the first metal layer (1191). At this time, the second metal layer (1192) may include a metal having a higher etching rate and a lower silicon diffusion coefficient than the first metal layer (1191). For example, when the first metal layer (1191) includes at least one of titanium (Ti) and tungsten (W), the second metal layer (1192) may include at least one of gold (Au) and silver (Ag). Accordingly, the second metal layer (1192) can form a plurality of structures (115) by etching the base (110) at a high speed, and the first metal layer (1191) can prevent the diffusion of the second metal layer (1192) to reduce the effect of the diffused gold (Au) or silver (Ag) on ​​the capacitance. To this end, the first metal layer (1191) can be arranged to cover the entire upper surface of the second metal layer (1192). That is, the second metal layer (1192) can be arranged so as not to be in direct contact with the first electrode layer (120).

[0063] According to an embodiment of the present invention, the first electrode layer (120) is disposed on a plurality of structures (115) and a metal layer.

[0064] At this time, the first electrode layer (120) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin. For example, the first electrode layer (120) may include TiN, TiO2, MoO x, WO x , may include at least one of ITO and ITGO, wherein x is a positive integer.

[0065] Next, the first dielectric layer (130) is placed on the second surface (112) of the base (110) and the first electrode layer (120) on the plurality of structures (115).

[0066] At this time, the first dielectric layer (130) is SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z and may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the first dielectric layer (130) satisfies these conditions, it is easy to deposit the first dielectric layer (130) on the first electrode layer (120) with a uniform thickness.

[0067] Next, the second electrode layer (140) is placed on the second surface (112) of the base (110) and the first dielectric layer (130) on the plurality of structures (115).

[0068] At this time, the second electrode layer (140) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the second electrode layer (140) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0069] The material of the second electrode layer (140) may be the same as the material of the first electrode layer (120), but is not limited thereto. That is, the material of the second electrode layer (140) may be different from the material of the first electrode layer (120). For example, the first electrode layer (120) may be deposited using at least one of titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the second electrode layer (140) may be plated using Al.

[0070] As illustrated in FIG. 4, the space between the second electrode layers (140) among the plurality of structures (115) may be filled with a filler (400). Here, the filler (400) may be a material having insulating performance and a lower thermal expansion coefficient than the second electrode layer (140). For example, the filler (400) may include Al2O3. Accordingly, even if the temperature of the capacitor (100) increases, the space between the plurality of structures (115) does not undergo thermal expansion, so that a capacitor (100) having high reliability can be obtained. Alternatively, the filler (400) may include SiO2. Accordingly, the filler (400) may play a role of passivation. FIG. 4 illustrates an example in which a filler (400) is further arranged in the structure according to the embodiment of FIG. 3 among the embodiments of FIGS. 1 to 3, but is not limited thereto. A filler (400) may be further arranged in the structure according to the embodiments of FIGS. 1 and 2.

[0071] Unlike the embodiments of FIGS. 1 to 4 in which the second electrode layer (140) is deposited according to the shape of the first dielectric layer (130), referring to FIG. 5, the second electrode layer (140) may be arranged to fill between the plurality of structures (115). Accordingly, the overall resistance of the capacitor (100) can be reduced, thereby obtaining a capacitor with a fast response speed. FIG. 5 illustrates, as an example, that the second electrode layer (140) fills between the plurality of structures (115) in the structure according to the embodiment of FIG. 3 among the embodiments of FIGS. 1 to 3, but is not limited thereto. The second electrode layer (140) may also fill between the plurality of structures (115) in the structure according to the embodiments of FIGS. 1 to 2.

[0072] Meanwhile, the above description focuses on an example in which a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140) are sequentially laminated on a base (110), but is not limited thereto. According to an embodiment of the present invention, a dielectric layer and an electrode layer may be further alternately arranged on the second electrode layer (140).

[0073] Referring to FIG. 6, the second dielectric layer (180) is placed on the second electrode layer (140).

[0074] At this time, the second dielectric layer (180) is SiO2, Si3N3, SiN4, ZAZ, HfO2, ZrO2, Hf x Zr y O z and may include at least one of Al2O3, wherein x, y, and z are positive integers. When the material of the second dielectric layer (180) satisfies these conditions, it is easy to deposit the second dielectric layer (140) on the second electrode layer (140) with a uniform thickness.

[0075] Next, the third electrode layer (190) is placed on the second dielectric layer (180).

[0076] At this time, the third electrode layer (190) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the third electrode layer (190) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0077] The material of the third electrode layer (190) may be the same as the materials of the first electrode layer (120) and the second electrode layer (140), but is not limited thereto. That is, the material of the third electrode layer (190) may be different from the materials of the first electrode layer (120) and the second electrode layer (140). For example, the first electrode layer (120) and the second electrode layer (140) may include titanium (Ti), molybdenum (Mo), tungsten (W), and indium-tin, and the third electrode layer (190) may include Al. Unlike the embodiment of FIG. 6 in which the third electrode layer (190) is deposited according to the shape of the second dielectric layer (180), the third electrode layer (190) may be arranged to fill between the plurality of structures (115). Accordingly, the overall resistance of the capacitor (100) can be reduced, so that a capacitor with a fast response speed can be obtained. FIG. 6 illustrates an example in which a second dielectric layer (180) and a third electrode layer (190) are further arranged in the structure according to the embodiment of FIG. 3 among the embodiments of FIGS. 1 to 3, but is not limited thereto. In the structure according to the embodiments of FIGS. 1 to 2, a second dielectric layer (180) and a third electrode layer (190) may also be further arranged.

[0078] FIGS. 7 to 9 illustrate a method for manufacturing a capacitor according to an embodiment of the present invention, and FIG. 10 is a drawing for explaining an etching mechanism during a manufacturing process of a plurality of structures in a capacitor according to an embodiment of the present invention.

[0079] Referring to Fig. 7(a), the upper surface of a silicon substrate is patterned into the shape of a structure using a photoresist (PR). Here, the silicon substrate may contain silicon at 90% or more, preferably 99% or more, and more preferably 99.999% or more.

[0080] Referring to Fig. 7(b), a second metal layer (1192) is deposited on the upper surface of the silicon substrate. Here, the second metal layer (1192) may include at least one of gold (Au) and silver (Ag). At this time, the second metal layer (1192) may be deposited by an evaporator. Accordingly, the metal layer is deposited only on the upper portion of the photoresist and the exposed area between the photoresist, and the metal layer is not deposited in the area covered by the photoresist, so that the photoresist can perform a mask function.

[0081] Referring to Fig. 7(c), only the second metal layer (1192) deposited in the exposed area between the photoresists on the silicon substrate is left through the lift off process.

[0082] Referring to Fig. 7(d), a silicon substrate is etched to form a plurality of structures (115). Etching can be performed by a chemical reaction of silicon. For example, when a second metal layer (1192) such as gold (Au) or silver (Ag) is deposited on the upper surface of the silicon substrate and wet etching is performed in an HF and H2O2 environment, etching is performed by an electrochemical reaction of the second metal layer (1192), silicon, HF, and H2O2. For example, etching can be performed by the following chemical reaction.

[0083] [Reaction Formula 1]

[0084] 3H2O2+6H + → 6H2O+6h +

[0085] [Reaction Formula 2]

[0086] 6h + +2Si+12HF→2H2SiF6+6H + +H2

[0087] That is, 6h generated by reaction formula 1 in the second metal layer (1192) + can oxidize Si.

[0088] The overall reaction equation can be expressed as shown in the following reaction equation 3.

[0089] [Reaction Formula 3]

[0090] 2Si+12HF+3H2O2→2H2SiF6+6H2O+H2

[0091] Referring to Figure 10, the hole (h) according to Reaction Scheme 1 + ) can oxidize and etch Si under the second metal layer (1192). Accordingly, a porous silicon layer (117) can be formed under the metal layer (1192).

[0092] Referring to Fig. 7(e), the second metal layer (1192) is removed. As described above, when the second metal layer (1192) includes gold (Au) or silver (Ag) having a high silicon diffusion coefficient, the gold (Au) or silver (Ag) may diffuse during the process of depositing the first electrode layer, dielectric layer, and second electrode layer in a high-temperature environment, thereby contaminating the chamber and causing capacitor failure. Removing the second metal layer (1192) as shown in Fig. 7(e) can prevent the diffusion of gold (Au) or silver (Ag).

[0093] Alternatively, referring to Fig. 8(a), the upper surface of a silicon substrate is patterned into the shape of a structure using a photoresist. Here, the silicon substrate may contain silicon at 90% or more, preferably 99% or more, and more preferably 99.999% or more.

[0094] Referring to Fig. 8(b), a first metal layer (1191) is deposited on the upper surface of the silicon substrate. Here, the first metal layer (1191) may include at least one of titanium (Ti) and tungsten (W). At this time, the first metal layer (1191) may be deposited by an evaporator. Accordingly, the first metal layer (1191) is deposited only on the upper portion of the photoresist and the exposed area between the photoresist, and the first metal layer (1191) is not deposited in the area covered by the photoresist, so that the photoresist can perform a mask function.

[0095] Referring to Fig. 8(c), only the first metal layer (1191) deposited in the exposed area between the photoresists on the silicon substrate is left through the lift off process.

[0096] Referring to Fig. 8(d), a silicon substrate is etched to form a plurality of structures (115). Etching can be performed by a chemical reaction of silicon. For example, when a first metal layer (1191) such as Ti or W is deposited on the upper surface of a silicon substrate and wet etching is performed in an HF and H2O2 environment, etching is performed by an electrochemical reaction of the first metal layer (1191), silicon, HF, and H2O2. The chemical reaction for etching can refer to the above-described reaction formulas 1 to 3.

[0097] Accordingly, a porous silicon layer (117) can be formed under the first metal layer (1191). When the first metal layer (1191) includes Ti or W instead of Au or Ag as shown in FIGS. 8(a) to 8(d), since Ti or W has a lower silicon diffusion coefficient than Au or Ag, the process for removing the first metal layer (1191) as shown in FIG. 7(e) can be omitted.

[0098] Alternatively, referring to Fig. 9(a), the upper surface of a silicon substrate is patterned into the shape of a structure using a photoresist. Here, the silicon substrate may contain silicon at 90% or more, preferably 99% or more, and more preferably 99.999% or more.

[0099] Referring to Fig. 9(b), a double metal layer is deposited on the upper surface of a silicon substrate. Here, the double metal layer may include a first metal layer (1191) including at least one of titanium (Ti) and tungsten (W) and a second metal layer (1192) including at least one of gold (Au) and silver (Ag). At this time, the first metal layer (1191) and the second metal layer (1192) may be deposited by an evaporator. The first metal layer (1191) may be deposited on the second metal layer (1192). Accordingly, the metal layer is deposited only in the exposed area between the upper portion of the photoresist and the photoresist, and the double metal layer is not deposited in the area covered by the photoresist, so that the photoresist can perform a mask function.

[0100] Referring to Fig. 9(c), only the double metal layer deposited in the exposed area between the photoresists on the silicon substrate is left through the lift off process.

[0101] Referring to Fig. 9(d), a silicon substrate is etched to form a plurality of structures (115). Etching can be performed by a chemical reaction of silicon. For example, when wet etching is performed in an HF and H2O2 environment while a double metal layer is deposited on the upper surface of a silicon substrate, etching is performed by an electrochemical reaction of the metal layer, silicon, HF, and H2O2. The chemical reaction for etching can refer to the above-described reaction formulas 1 to 3.

[0102] Accordingly, a porous silicon layer (117) can be formed under the double metal layer. When the first metal layer (1191) including Ti or W is disposed on the second metal layer (1192) including Au or Ag as shown in FIGS. 9(a) to 9(d), a high etching speed can be obtained due to the etching rate of Au or Ag, and the process for removing the metal layer can be omitted due to the low silicon diffusion coefficient of Ti or W.

[0103] As illustrated in FIGS. 7 to 9, after forming a plurality of structures (115) on the base (110), deposition of a first electrode layer (120), a dielectric layer (130), and a second electrode layer (130) may be sequentially performed. The first electrode layer (120) may be deposited using an ALD (atomic layer deposition) process. Using the ALD process, the material of the first electrode layer (120) may be conformally deposited on the surface of the base (110) and the plurality of structures (115) in atomic units. Accordingly, the first electrode layer (120) may be uniformly deposited on the second surface (112) of the base (110) and the side surfaces and upper surfaces of the plurality of structures (115).

[0104] The first dielectric layer (130) can be deposited using an ALD process. According to this, the material of the first dielectric layer (130) can be uniformly and conformally deposited on an atomic level on the surface of the first electrode layer (120).

[0105] The second electrode layer (140) may be deposited using an ALD process. According to this, the material of the second electrode layer (140) may be conformally deposited on the surface of the first dielectric layer (130) at an atomic level. Alternatively, the second electrode layer (140) may be formed on the first dielectric layer (130) by an electrolytic plating process. At this time, the second electrode layer (140) may include Al. When the second electrode layer (140) includes Al, contamination within the chamber can be prevented due to the low silicon diffusion coefficient of Al.

[0106] Next, a first electrode pad (150) is connected on the first electrode layer (120), and a second electrode pad (160) is connected on the second electrode layer (140). In order to connect the first electrode pad (150) to the first electrode layer (120), the second electrode layer (140) and the first dielectric layer (130) may be etched. In addition, the first electrode pad (150) and the second electrode pad (160) may be deposited by sputtering.

[0107] Fig. 11 is a SEM image of a structure manufactured according to an embodiment of the present invention. Fig. 11(a) is an image of a plurality of structures formed by etching a silicon substrate, Fig. 11(b) is an enlarged image of the upper part of the structure, Fig. 11(c) is an image of the middle part of the structure, and Fig. 11(d) is an image of the lower part of the structure. Referring to Figs. 11(a) to 11(d), it can be seen that according to an embodiment of the present invention, a structure having a width of 2.52 μm, a height of 52 μm, and an aspect ratio of 20.6 can be obtained.

[0108] Figures 12 and 13 are cross-sectional views of a capacitor according to another embodiment of the present invention. Duplicate descriptions of the same content as described with reference to Figures 1 to 11 are omitted.

[0109] Referring to FIG. 12, the capacitor (100) includes a base (110), a plurality of structures (115), a porous layer (117), a first metal layer (1191), a second metal layer (1192), a first electrode layer (120), a first dielectric layer (130), a second electrode layer (140), a first electrode pad (150) connected to the first electrode layer (120), and a second electrode pad (160) connected to the second electrode layer (140).

[0110] In order to place the first electrode pad (150) and the second electrode pad (160), according to an embodiment of the present invention, an insulating layer (200) is further placed on the second electrode layer (140). As illustrated, the insulating layer (200) may extend between the second electrode layers (140) on the sides of the plurality of structures (115) and may serve as a filler.

[0111] On the second electrode layer (140) of the upper surface of the plurality of structures (115), the insulating layer (200) includes a first opening (200C1) and a second opening (200C2). A first electrode pad (150) may be arranged in the first opening (200C1), and a second electrode pad (160) may be arranged in the second opening (200C2). Accordingly, the second electrode pad (160) arranged in the second opening (200C2) may be connected to the second electrode layer (140). In order to connect the first electrode pad (150) arranged in the first opening (200C1) with the first electrode layer (120), the insulating layer (200) may extend along the edge of the first opening (200C1) to the first dielectric layer (130), and the first dielectric layer (130) may include a first hole (130C1) corresponding to the first opening (200C1). Accordingly, the first electrode pad (150) may be connected to the first electrode layer (120). At this time, the first dielectric layer (130) may protrude toward the center of the first hole (130C1) more than the extension portion (202) of the insulating layer (200) around the first hole (130C1). Accordingly, since the electrode layer can be evenly filled in the first opening (200C1) and the first hole (130C1), the reliability of the capacitor can be increased.

[0112] When the first electrode pad (150) and the second electrode pad (160) are arranged in this structure, the upper surfaces of the first electrode pad (150) and the second electrode pad (160) can be arranged to have the same height. Accordingly, when the capacitor (100) according to the embodiment of the present invention is mounted on a printed circuit board, there is no need to separately adjust the heights of the first electrode pad (150) and the second electrode pad (160), so the assembly process can be improved, and the bonding strength between the first electrode pad (150) and the second electrode pad (160) and the printed circuit board can be improved.

[0113] Referring to FIG. 13, the capacitor (100) includes a base (110), a plurality of structures (115), a porous layer (117), a first metal layer (1191), a second metal layer (1192), a first electrode layer (120), a first dielectric layer (130), a second electrode layer (140), a second dielectric layer (180), a third electrode layer (190), a first electrode pad (150) connected to the first electrode layer (120), a second electrode pad (160) connected to the second electrode layer (140), and a third electrode pad (165) connected to the third electrode layer (190).

[0114] In order to arrange the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165), according to an embodiment of the present invention, an insulating layer (200) is further arranged on the third electrode layer (190). As illustrated, the insulating layer (200) may extend between the third electrode layers (190) on the sides of the plurality of structures (115) and may serve as a filler.

[0115] On the third electrode layer (190) of the upper surface of the plurality of structures (115), the insulating layer (200) includes a first opening (200C1), a second opening (200C2), and a third opening (200C3). A first electrode pad (150) may be arranged in the first opening (200C1), a second electrode pad (160) may be arranged in the second opening (200C2), and a third electrode pad (165) may be arranged in the third opening (200C3). Accordingly, the third electrode pad (165) arranged in the third opening (200C3) may be connected to the third electrode layer (190).

[0116] In order to connect the first electrode pad (150) arranged in the first opening (200C1) with the first electrode layer (120), the insulating layer (200) may extend along the edge of the first opening (200C1) to the second dielectric layer (180), and the second dielectric layer (180) may include a first hole (180C1) corresponding to the first opening (200C1). In addition, the second dielectric layer (180) may extend around the first hole (180C1) to the first dielectric layer (130), and the first dielectric layer (130) may include a second hole (130C1) corresponding to the first hole (180C1). Accordingly, the first electrode pad (150) may be connected to the first electrode layer (120). At this time, the second dielectric layer (180) around the first hole (180C1) may protrude toward the center of the first hole (180C1) more than the extension (202) of the insulating layer (200). Accordingly, the electrode layer may be evenly filled in the first opening (200C1) and the first hole (180C1), thereby increasing the reliability of the capacitor.

[0117] Additionally, at least one dielectric segment (130S) may be further arranged within the second hole (130C1) so as to be spaced apart from the second hole (130C1). Accordingly, since the electrode layer can be evenly filled in the first opening (200C1), the first hole (180C1), and the second hole (130C1), the reliability of the capacitor can be increased.

[0118] Although not shown, a portion of the upper surface of the electrode layer within the first opening (200C1) may be concave. Accordingly, when the first electrode pad (150) is bonded, the excess electrode layer does not protrude to the side of the first electrode pad (150), thereby increasing the reliability of the capacitor (100).

[0119] In order to connect the second electrode pad (160) arranged in the second opening (200C2) with the second electrode layer (140), the insulating layer (200) may extend along the edge of the second opening (200C2) to the second dielectric layer (180), and the second dielectric layer (180) may include a third hole (180C2) corresponding to the second opening (200C2). Accordingly, the second electrode pad (160) may be connected to the second electrode layer (140). At this time, the second dielectric layer (180) may protrude toward the center of the third hole (180C2) more than the extension portion (202) of the insulating layer (200) around the third hole (180C2). Accordingly, since the electrode layer can be evenly filled in the second opening (200C2) and the third hole (180C2), the reliability of the capacitor can be increased.

[0120] Although not shown, a portion of the upper surface of the electrode layer within the second opening (200C2) may be concave. Accordingly, when bonding the second electrode pad (160), the excess electrode layer does not protrude to the side of the second electrode pad (160), thereby increasing the reliability of the capacitor (100).

[0121] When the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) are arranged in this structure, the upper surfaces of the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) can be arranged to have the same height. Accordingly, when the capacitor (100) according to the embodiment of the present invention is mounted on a printed circuit board, there is no need to separately adjust the heights of the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165), so that the assembly process can be improved, and the bonding strength between the first electrode pad (150), the second electrode pad (160), and the third electrode pad (165) and the printed circuit board can be improved.

[0122] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A base including a first surface and a second surface opposite to the first surface, and including a plurality of structures protruding from the second surface along a first direction from the first surface toward the second surface; The second surface between the plurality of structures and the first electrode layer disposed on the structure, A first dielectric layer disposed on the first electrode layer, and A second electrode layer is disposed on the first dielectric layer, A capacitor wherein the second surface between the plurality of structures is more porous than the structures.

2. In paragraph 1, Further comprising a first metal layer disposed between the second surface and the first electrode layer between the plurality of structures, The first metal layer comprises at least one of titanium (Ti) and tungsten (W), A capacitor in which the first metal layer is in direct contact with the first electrode layer.

3. In paragraph 2, Further comprising a second metal layer disposed between the second surface and the first metal layer between the plurality of structures, A capacitor wherein the second metal layer comprises at least one of gold (Au) and silver (Ag).

4. In paragraph 1, A capacitor in which the second surface between the plurality of structures is in direct contact with the first electrode layer.

5. In paragraph 1, A capacitor wherein the average width of the plurality of structures in a second direction perpendicular to the first direction in which the plurality of structures protrude is 1.5 µm to 3.5 µm, and the average height of the plurality of structures based on the second surface of the base is 3.5 µm or more and 175 µm or less.

6. In paragraph 1, A capacitor wherein a ratio of the average height of the plurality of structures based on the second surface of the base to the average width of the plurality of structures in a second direction perpendicular to the first direction in which the plurality of structures protrude is 1 to 50.

7. In paragraph 1, A capacitor in which the angle formed by the second surface of the base and the side surface of the structure is 90 to 100 degrees.

8. In paragraph 1, A capacitor wherein the first electrode layer comprises at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, and copper (Cu), and the second electrode layer comprises aluminum (Al).

9. A base including a first surface and a second surface opposite to the first surface, and including a structure protruding from the second surface along a direction from the first surface toward the second surface; A first metal layer disposed on the second surface and including a first through hole, A second metal layer disposed on the first metal layer and including a second through hole, A first electrode layer disposed on the second metal layer and the structure, A first dielectric layer disposed on the first electrode layer, and A second electrode layer is disposed on the first dielectric layer, The above structure penetrates the first through hole and the second through hole, The etching rate of the first metal layer is higher than the etching rate of the second metal layer, A capacitor in which the silicon diffusion coefficient of the second metal layer is lower than the silicon diffusion coefficient of the first metal layer.

10. In paragraph 9, The first metal layer comprises at least one of gold (Au) and silver (Ag), A capacitor wherein the second metal layer comprises at least one of titanium (Ti) and tungsten (W).

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