High power factor ac / DC converters with reduced storage capacitance

Abstract

An electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising: an input stage comprising primary-side circuitry comprising a PFC boost converter and a first switch converter circuitry comprising a plurality of first switching devices in a stacked configuration; an output stage comprising secondary-side circuitry comprising a second switch converter circuitry comprising a plurality of second switching devices in a stacked configuration; a resonant circuit coupled to the first switch converter circuitry and the second switch converter circuitry; and a pulse width controller (PWM)-based controller comprising an input current control loop circuitry, an output voltage regulation loop circuitry, a voltage ripple reduction loop circuitry, and pulse width modulator circuitry.

Description

HIGH POWER FACTOR AC / DC CONVERTERS WITH REDUCED STORAGE CAPACITANCEFIELD

[0001] This disclosure relates to methods and systems for power conversion.BACKGROUND

[0002] The development of a grid-connected Electric Vehicle (EV) transportation system has been considered as one of the essential solutions to help to significantly reduce fossil fuel consumption [1], [2], As a result, the global EV sales are predicted to grow rapidly in the coming years, reaching 14 million by 2025 [3], DC fast and ultra-fast charging infrastructure are being developed to match the driving range of internal combustion engine-based vehicles, and plugging to the power grid facilitates reactive power support, load balance, and integration of renewable energy resources. Moreover, High-Voltage (HV) battery systems are emerging as an attractive power solution for EVs due to their ability to provide ultra-fast charging, and recent commercial EVs such as the Porsche Taycan and Aston Martin Rapide Type E have revealed their 800 IV battery technology. As illustrated in Figure 1, the Onboard Battery Charger (OBC) in the power interface typically consists of two stages: the AC-DC Power Factor Correction (PFC) converter and the isolated DC-DC converter stage, and it needs to be capable of providing HV gain to boost a wide range of input AC voltages [4], However, the adoption of EV technology still faces technical, economical, and policy barriers, including high battery costs, short battery lifetime, reliability issues, lower driving range, long charging time, and complex charging infrastructure [5], To overcome these challenges, the design of suitable power converter topology and implementation of advanced control methods to provide reliable operation with high efficiency are essential.

[0003] Power conversion approach in single-phase OBCs can be classified as two- stage [6]-

[0010] or single-stage conversion

[0011]

[0016] _ Regardless of the selected approach,following standards such as IEEE std 1547-2018

[0017] or SAE J2894-1

[0018] , having a high-quality sinusoidal input current with a very high-power factor and minimum input current harmonics is a crucial necessity in EV OBC technologies. To that end, boostbased PFC converters are commonly used in EV technologies since they can achieve a high-power factor correction with relatively simple circuitry. There are various boostbased PFC converter topologies documented in the literature that can be used as the frontend stage in EV chargers, including single-stage and two-stage topologies

[0019] -

[0021] .

[0004] The traditional PFC front-end converter based on a diode bridge rectifier with a boost converter is the most lossy component due to its high semiconductor count that contribute to 30%-50% of the total loss at low-input conditions [4], Moreover, since these converters operate in Continuous Conduction Mode (CCM), Phase-Locked Loop (PLL) is necessary for converter control

[0019] ,

[0020] , To address this, bridgeless topologies have been proposed to eliminate diode bridge rectifiers for improved efficiency and reduced losses. Therefore, a feasible front-end AC-DC converter should have the capability to eliminate diode bridge rectifiers while maintaining efficiency and reliability.

[0005] For isolated DC-DC stage in EV OBC circuits, resonant DC-DC converters are typically used. LLC and CLLC resonant circuits are the most promising topologies due to their high efficiency and soft-switching capabilities

[0022] -

[0024] . However, due to its better voltage regulation capability and reduced output voltage ripple (because of the additional series inductor with the load), CLLC resonant circuit is commonly preferred. Various single-stage OBC topologies have been proposed in the literature to reduce the number of components and improve the overall efficiency of the converter. For instance,

[0012] introduced a single-stage converter configuration comprising a full-bridge diode rectifier with an active clamp circuit and interleaved series resonant circuits. A single-stage PFC OBC without an intermediate DC-link was presented in

[0014] providing soft-switching operation without any external snubber circuits throughout the AC line voltage range. In

[0015] , a Cuk-type bridgeless AC-DC converter was reported, which featured a seriescurrent ripple compensator utilizing only two switches throughout the topology. However, it is worth noting that this topology does not offer soft-switching operation. Additionally,

[0016] presented a single-stage resonant OBC converter that inherently incorporates PFC. Most of these designs have been proposed for 300-4007* battery systems, but when developing an AC-DC OBC converter for high voltage (approximately 8007*) battery systems, the required HV gain of the OBC circuit as well as the potential HV across each switch must be taken into account.

[0006] Typically, to provide an output DC voltage with minimal amount of voltage ripple, both the DC-link and the output capacitors require very large capacitance to filter out the low frequency voltage ripple (see Figure 2a). The low voltage ripple requirement is especially very stringent in HV battery charging system. For example, the allowed output voltage ripple should be below 5% in an EV battery system according to SAE J2894-1

[0018] , As shown in Figure 2b to reduce the amount capacitance required in both capacitors, a separate output voltage ripple reduction circuit (VRRC) has been proposed in the literature

[0025] -

[0027] . The VRRC typically requires at least one inductor, one high voltage capacitor and some additional semiconductor switches. The VRRC absorbs the low frequency oscillating energy, and hence, the required total capacitance can be reduced. However, the additional circuit components used in the VRRC can result in conduction power loss. Therefore, the necessity of the design of a ripple reduction control system without adding a VRRC to reduce the bulky DC-link and filter capacitances for higher reliability becomes highly crucial. Multiple researches have been conducted on the development of AC-DC converters for EV application; however, they are plagued with numerous drawbacks, such as: high voltage stress on the semiconductor devices; utilization of PFC front-end converter based on diode bridge rectifier with high power loss, 3) hard-switching operation of the semiconductor devices; utilization of bulky DC-link and filter capacitors with low reliability and lifetime; low-voltage design of the battery chargers (~300-400F*); and low input current quality of the converter.SUMMARY

[0007] In one example, an electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising: an input stage comprising primary-side circuitry comprising a PFC boost converter and a first switch converter circuitry comprising a plurality of first switching devices in a stacked configuration; an output stage comprising secondary-side circuitry comprising a second switch converter circuitry comprising a plurality of second switching devices in a stacked configuration; a resonant circuit coupled to the first switch converter circuitry and the second switch converter circuitry; and a pulse width controller (PWM)-based controller comprising an input current control loop circuitry, an output voltage regulation loop circuitry, a voltage ripple reduction loop circuitry, and pulse width modulator circuitry.

[0008] The electrical power conversion system comprises a bridgeless single-stage AC-DC CLLC resonant converter with a fully soft-switching operation and minimum low-frequency voltage ripple featuring reduced storage capacitances. In addition, the bridgeless single-stage AC-DC CLLC resonant converter comprises a closed-loop duty ratio control system based on the input current and DC-link voltage that provides high- quality and sinusoidal input current. Furthermore, a feedback control loop minimizes the low-frequency output voltage oscillation, eliminating the need for bulky DC-link and output storage electrolytic-type capacitors which have short life-span and reduces the overall reliability of the system. The stacked switches-based configuration of the converter reduces the voltage stress of the switches to half of the DC-link voltage, making the converter suitable for HV battery systems. Also, soft-switching operation is facilitated for all the semiconductor devices as the converter operates above resonance throughoutthe operation of the converter. Additionally, output voltage regulation is achieved through a variable frequency (VF) control algorithm to have a consistent power supply.

[0009] Advantageously, the electrical power conversion system does not require any large size DC-link and output capacitors, but includes an integrated active voltage ripple reduction control scheme that allows much lower output capacitance to be used. In one example, the converter provides power factor correction in AC / DC rectifier mode (i.e., the converter is capable of a power factor greater than 0.98) and an output voltage ripple of about 1.4%, with an efficiency greater than 96%, in one power conversion stage. The converter also provides galvanic isolation, which is a safety feature for emerging high power on-board EV chargers and other energy storage applications. In addition, the semiconductor switches of the power converter are capable of loss-less switching behaviour, or soft-switching operation, to maximize the overall power efficiency.

[0010] Furthermore, the converter provides power factor correction (PFC), and achieves low DC output voltage ripple in one conversion stage. With soft-switching operation, high frequency power conversion at frequencies in the hundreds of kilo hertz is possible, and galvanic isolation can be provided in the converter by using a small size high frequency transformer.

[0011] In one aspect, a fully soft-switched bridgeless AC-DC resonant converter is presented to address the mentioned challenges. Apart from guaranteeing soft-switching operation for all semi-conductor devices, the fully soft-switched bridgeless AC-DC resonant converter features three closed-loop controllers enabling: high-quality sinusoidal input current; usage of small DC-link and output filter capacitors that result in higher reliability for the converter with reduced cost and size; lower DC-link and output voltage low frequency ripples; and regulated output voltage for wide range of input voltage using VF modulation technique.

[0012] In another example, an electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising:a first circuitry comprising a resonant circuit network cascaded with a high frequency switching element pairs on an AC side of the system; an integrated active voltage ripple reduction circuitry magnetically coupled to the resonant circuit network, wherein the integrated active voltage ripple reduction circuitry suppress low frequency voltage ripples in an output voltage of the electrical power conversion system; wherein the high frequency switching element pairs exhibit loss-less switching characteristics, thereby maximizing the overall power efficiency of the electrical power conversion system.

[0013] In another example, a voltage ripple controller (VRC) circuitry comprising: a directional circuitry; a first energy storage capacitor integrated with a electrical power conversion system, wherein a first voltage across the first energy storage capacitor comprises first voltage ripples, and a second energy storage capacitor, wherein a second voltage across the second energy storage capacitor comprises second voltage ripples, and wherein the first voltage ripples and the second voltage ripples have a 180° phase difference such that an output voltage of the electrical power conversion system is substantially free of ripples; and wherein the VRC is integrated with the electrical power conversion system.

[0014] Advantageously, the electrical power conversion system does not require any large size DC-link and output capacitors, but includes an integrated active voltage ripple reduction control scheme that allows much lower output capacitance to be used. In one example, the converter provides power factor correction in AC / DC rectifier mode (i.e. the converter is capable of a power factor greater than 0.98) and an output voltage ripple of about 1.4%, with an efficiency greater than 96%, in one power conversion stage. The converter also provides galvanic isolation, which is a safety feature for emerging high power on-board EV charger and other energy storageapplications. In addition, the semiconductor switches of the power converter are capable of loss-less switching behaviour, or soft-switching operation, to maximize the overall power efficiency.

[0015] Furthermore, the converter provides power factor correction (PFC), and achieves low DC output voltage ripple in one conversion stage. With soft-switching operation, high frequency power conversion at frequencies in the hundreds of kilo hertz is possible, and galvanic isolation can be provided in the proposed converter by using a small size high frequency transformer.

[0016] In another example, an electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising: a first circuitry comprising a resonant circuit network cascaded with high frequency switching element pairs on an AC side of the system; a DC side rectifier; an integrated active voltage ripple reduction circuitry magnetically coupled to the resonant circuit network, wherein the integrated active voltage ripple reduction circuitry suppress low frequency voltage ripples in an output voltage of the DC side rectifier; wherein the high frequency switching element pairs exhibit loss-less switching characteristics, thereby maximizing the overall power efficiency of the electrical power conversion system.

[0017] In yet another example, a voltage ripple controller (VRC) circuitry comprising: a directional circuitry; a first energy storage capacitor integrated with a electrical power conversion system, wherein a first voltage across the first energy storage capacitor comprises first voltage ripples, and a second energy storage capacitor, wherein a second voltage across the second energy storage capacitor comprises second voltage ripples, and wherein thefirst voltage ripples and the second voltage ripples have a 180° phase difference such that an output voltage of the electrical power conversion system is substantially free of ripples; and wherein the VRC is integrated with the electrical power conversion system.BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 shows power connections and on-board charging system for high- voltage (HV) battery system in an electric vehicle (EV);

[0019] Figure 2a shows an AC-DC converter configuration with large storage capacitance for voltage ripple reduction;

[0020] Figure 2b shows an AC-DC converter configuration with an integrated voltage ripple reduction circuit (VRRC);

[0021] Figure 3a shows a bridgeless AC-DC EV on-board charger OBC with reduced storage capacitors;

[0022] Figure 3b shows a controller for the bridgeless AC-DC EV OBC with reduced storage capacitors;

[0023] Figure 4 shows example operating waveforms of the AC-DC converter;

[0024] Figures 5a-i show operational stages of the bridgeless AC-DC converter within a switching period in the positive half cycle;

[0025] Figure 6 shows conditions for DCM and CCM operation of the front-end PFC boost rectifier;

[0026] Figure 7 shows an equivalent circuit of a CLLC resonant circuit in the AC- DC converter;

[0027] Figure 8 shows an overall voltage gain plot of the converter for Ds= 0 for m = 10 and k = 0.8;

[0028] Figure 9 shows an overall voltage gain plot of the converter for Ds> 0;

[0029] Figure 10 shows a block diagram of an input current controller for the converter;

[0030] Figure 11 shows a block diagram of a VFM-based output voltage regulation controller for the converter;

[0031] Figure 12 shows a block diagram of a VFM-based output voltage regulation controller for the converter;

[0032] Figure 13 shows a bode diagram of a ripple reduction controller for the converter;

[0033] Figure 14 shows ripple reduction control key waveforms;

[0034] Figure 15 shows a bode diagram of the developed VFM-based output voltage regulation controller for the converter;

[0035] Figure 16 shows an image of a proof-of-concept prototype of the AC-DC converter;

[0036] Figure 17 shows input and output waveforms of the converter at rated power;

[0037]

[0038] Figure 18 shows input voltage, input current, and boost inductor current waveforms;

[0039] Figure 19 shows voltage over and current flowing through Switch 1 at line frequency;

[0040] Figure 20 shows voltage over and current flowing through Switch 1 at switching frequency;

[0041] Figure 21 shows voltage over and current flowing through Switch 2 at line frequency;

[0042] Figure 22 shows voltage over and current flowing through Switch 2 at switching frequency;

[0043] Figure 23 shows voltage over and current flowing through Switch 6 at line frequency;

[0044] Figure 24 shows voltage over and current flowing through Switch 6 at switching frequency;

[0045] Figure 25 shows dynamic performance of the AC / DC converter against output voltage reference change;

[0046] Figure 26 shows dynamic performance of the AC / DC converter against input voltage variation.;

[0047] Figure 27 shows dynamic performance of the AC / DC converter without and with the closed-loop control systems;

[0048] Figure 28 shows efficiency curve of the converter for different input voltages;

[0049] Figure 29 shows a power factor curve of the converter for different input voltages;

[0050] Figure 30 shows a block diagram of an integrated VRC in an AC / DC power block for a variety of power applications;

[0051] Figure 31 shows a direct AC / DC converter topology with an integratedVRC;

[0052] Figure 32 shows a non-isolated AC / DC converter with an integrated VRC;

[0053] Figure 33 shows a non-isolated AC / DC converter topology with an integrated VRC and active auxiliary circuit on the AC side;

[0054] Figure 34 shows exemplary topology of an active auxiliary circuit used in a direct AC / DC converter topology with an integrated VRC;

[0055] Figure 35 shows an exemplary topology of an isolated version of the AC / DC converter with integrated VRC;

[0056] Figure 36 shows an isolated version of the proposed AC / DC converter with integrated VRC and an auxiliary circuit therein;

[0057] Figure 37 shows a non-isolated AC / DC converter topology with an integrated VRC and active auxiliary circuit on the DC side;

[0058] Figures 38a and 38b show a modulation scheme based on the circuit of Figure 6;

[0059] Figure 39 shows low -frequency operating waveforms of the converter;

[0060] Figure 40 shows high-frequency operating waveforms of the converter;

[0061] Figures 41a-c show operating stages of the converter;

[0062] Figure 42 shows the output voltage and the input AC current when the load changes;

[0063] Figure 43a shows primary side switch current and voltage waveforms for top switch (SI);

[0064] Figure 43b shows primary side switch current and voltage waveforms for bottom switch (S2);

[0065] Figure 44 shows the output voltage and the input AC current when there is a step change in the input AC voltage;

[0066] Figures 45a and 45b show the output voltage and the input AC current in an isolated converter when the load changes;

[0067] Figure 46a shows primary side switch current and voltage waveforms for top switch (isi);

[0068] Figure 46b shows primary side switch current and voltage waveforms for bottom switch (iS2);

[0069] Figure 47 shows a three-phase AC / DC topology (parallel configuration) based on the VRC scheme; and

[0070] Figure 48 shows a three-phase AC / DC topology based on the soft-switched VRC scheme.DETAILED DESCRIPTION

[0071] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the following description to refer to the same or similar elements. While embodiments of the disclosure may be described, modifications, adaptations, and other implementations are possible. For example, substitutions, additions, or modifications may be made to theelements illustrated in the drawings, and the methods described herein may be modified by substituting, reordering, or adding stages to the disclosed methods. Accordingly, the following detailed description does not limit the disclosure. Instead, the proper scope of the disclosure is defined by the appended claims.

[0072] Referring to Figure 3a, there is shown an example circuit diagram of a bridgeless AC-DC electrical vehicle (EV) on-board charger (OBC) with reduced storage capacitors, generally designated by the numeral 10. A controller 11 for the OBC 10 is shown in Figure 3b. In one example, the AC-DC converter 10 and the designed control system 20 developed for HV OBCs in EV systems. The converter 10 comprises a bridgeless PFC boost rectifier 12 connected to an isolated CLLC resonant circuit module 14 through a first set of stacked switches S 16, S2 18, S320, S422 configuration marked as leg A 24. Moreover, the output of the isolated CLLC resonant circuit 14 is connected to a second set of stacked switches S5 30, V 32 configuration acting as a high-frequency (HF) half-wave rectifier, marked as leg B 34, whose output is coupled to a battery 36. The switches Si - Se are semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In leg A 24 of the converter 10, two middle switches S2 18 and S3 20 operate together with the same duty ratio DP, while switches Si 16 and S4 22 operate with a duty ratio of 1 - Dp. Moreover, two middle switches S5 30 and Sc 32 in leg B 34 operate together with the same duty ratio Dsgenerated from the closed-loop oscillation control system. Due to the stacked switches configuration of the switches in both leg A 24 and leg B 34, the voltage stress across each switch in leg A 24 is half of the DC-link voltage and the voltage stress across each switch in leg B 34 is half of the output voltage, making the converter 10 suitable for HV EV application. Furthermore, the CLLC resonant circuit module 14 consists of a resonant inductor Lr40, a high frequency (HF) transformer 42 with magnetizing inductance Lm44, and two resonant capacitors Cp46 and Cs48.

[0073] In leg A 24 of the converter 10, each switch Si 16, & 18, & 20, S422 is shared between the resonant converter stage 14 and the input PFC boost stage 12. Therefore, each switch Si 16, S2 18, & 20, S422 current consists of the resonant current ires and the PFC current io. As the result of the presence of the resonant circuit 14, all the switches Si 16, S2 18, S3 20, S4 22, & 30 and So 32 in the converter 10 are able to achieve soft- switching operation. Example operating waveforms of the AC-DC converter 10 are illustrated in Figure 4. Since the converter 10 operates symmetrically during both positive and negative half-cycles, only the positive half-cycle is addressed in this analysis. Moreover, the switching frequency of leg A 24 and leg B 34 of the converter 10 is identical to the switching frequency fsw, as will be described below. For steady-state analysis of the converter 10, the switching period Tsw is divided into nine operating modes. The operational stages of the AC-DC converter 10 within the switching period Tsw is illustrated in Figures 5a-i.

[0074] A. Interval to < t < ti (Figure 5a)

[0075] During this interval, the gate signals are applied to the switches Si 16 and S4 22 in leg A 24, and the boost current is discharging through Di 50. As the result, the currents im + ires and ires force the antiparallel diode of Si 16 and S422 to conduct, respectively. Accordingly, S422 current reaches zero sooner than Si 16 current. During this interval, the voltage stress across switches S2 18 and & 20 is half of the DC-link voltage VDC-iinkI . Moreover, the lagging resonant current ires forces the antiparallel diodes of switches & 30 and So 32 in leg B 34 to conduct. The current flowing through the switches Si 16, S422, 330 and So 32 in this interval are shown below:

[0076]

[0077] B. Interval: tl < t < t2 (Figure 5b)

[0078] During this interval, the gate signals are still applied to the switches Si 16 and S422 in leg A 24. At this point, the switch S422 changes its polarity as the boost current stops flowing through S4 22 and turns ON with Zero Voltage Switching (ZVS). Moreover, the gate signals are applied to the switches & 30 and 6 32 in leg B 34 and since the lagging resonant current is now positive, Ss 30 and Ss 32 turn ON under ZVS to reduce the ripple by changing the gain of the converter 10 using variable duty ratio Ds.

[0079] C. Interval: t2 < t < ts (Figure 5c)

[0080] In this interval, the gate signals are still applied to the switches Si 16 and S2 18 in leg A 24. At t = t2, the boost current becomes zero and the switch Si 16 changes its polarity and turns ON under ZVS. At this point, the boost current stops flowing through the switch Si 16 and the Si 16 current is the resonant current. Moreover, depending on the duty ratio Ds, the switches & 30 and & 32 remain on for a while and then turn OFF.

[0081] 1). Interval: ts< t < t4 (Figure 5d)

[0082] The switches Si 16 and S4 22 are still conducting, while the gate signal of the switches Ss 30 and Ss 32 are removed. At the same time, the snubber capacitors Css 70 and Css 72 start to charge. As the result, the voltages across the switches & 30 and Ss 32 charge gradually, which results in near Zero Current Switching (ZCS) turn OFF for V 30and & 32. Moreover, the resonant current flows through the diodes D336 and D437 and charges the output capacitors Coi 38 and C0239.

[0083]

[0084] E. Interval: t4 < t < ts (Figure 5e)

[0085] During this interval, the gate signals of the switches Si 16 and S4 22 are removed and the snubber capacitors Csi 60 and Cs466 start to charge. As the result, the voltages across the switches Si 16 and &22 charge gradually, which results in near ZCS turn OFF for Ss 30 and Se 32.

[0086] F. Interval: ts < t < t6 (Figure 5f)

[0087] During this interval, the gate signals are applied to the switches S2 18 and S3 20, and the boost current begins to charge which will result in ZCS turn ON for Di 50. At the same time, the currents IDI + ires and ires forces the antiparallel diode of S2 18 and S3 20 to conduct, respectively. Since ires> IDI + ires, the current going through the antiparallel diode of S320 is higher than S2 18. Accordingly S320 current will reach zero sooner than S2 18 current. During this interval, the voltage stress across switches Si 16 and S4 22 is half of the DC-link voltage VDC-imk / 2. The current flowing through the antiparallel diodes of the switches S218 and S320 are as shown below:

[0088]

[0089] G: Interval: t6 < t < t7 (Figure 5g)

[0090] At t = t6, the gate signals are still applied to the switches & 18 and & 20, and the current that were flowing through the antiparallel diode of & becomes zero, resulting in ZVS turn ON for S2. However, since ires is still positive and ires < im, the antiparallel diode of S320 is still ON.

[0091] H:Interval: / / < t < ts (Figure 5h)

[0092] At t = t7, the gate signals are still applied to the switches S218 and S3 20, and the current that were flowing through the antiparallel diode of S3 20 becomes zero too, resulting in ZVS turn ON for S3 20. Moreover, the negative resonant current ires start flowing through the antiparallel diodes of the switches Ss 30 and S632 in leg B 34.

[0093] I:Interval: ts < t < t9 (Figure 5i)

[0094] At t = Is, the gate signals of the switches S2 18 and S3 20 are removed and the snubber capacitors Cs2 62 and Css 64 start to charge. As the result, the voltages across the switches S218 and & 20 start to rise slowly, which allows a near ZCS turn OFF for S2 18 and & 20.

[0095] CONVERTER ANALYSIS

[0096] A. PFC Boost Converter

[0097] With the bridgeless AC-DC rectifier 10 operating in DCM operational mode, the input voltage v and input current im are in-phase with near unity power factor, as a result. The input voltage and current of the converter 10 can be given as below, where Re is the emulated resistance and togis the grid angular frequency.

[0098] ■ c-Vin’lin — p2 Levin= VMsin(gt)

[0099] Since the PFC boost converter 12 operates in DCM operational mode, the average boost inductor current should be less than the current ripple. Therefore, the condition for DCM operation of the front-end PCF boost converter 12 is as below:

[0100]

[0101] where {ib(t)}Tswis the average current flowing through the PFC boost inductor (Lb) 52 and (ib(t))Tswis its current ripple which are given below:

[0102] (8)(9)

[0103] This is during the CCM operation of the converter 10, where the average inductor current is higher than its current ripple, the duty ratio should vary as below:

[0104]

[0105] substituting (8)-( 10) into (7) leads to the condition for the DCM operation of the PFC inductor Lb 52 as below:

[0106]

[0107] Based on the steady-state equivalent model of the boost converter

[0028] , the voltage gain of the boost converter 12 during DCM operation is as below:

[0108]

[0109] Considering i inform = (4Lbfsw / VDC-Hnk)iin(t), the normalized gain of the boost converter 12 during DCM operation can be shown as below:

[0110]

[0111] Figure 6 shows a 3-D diagram that illustrates the relationship between the normalized gain (GB, ™), duty ratio (Dp), and normalized input current of the PFC boost inductor (inform). The white separating surface in Fig 6 shows the Boundary Conduction Mode (BCM) of the front-end PFC boost converter 12. In BCM, the DCM gain of the converter in (13) is equal to CCM gain of the converter which is 1 / (1 - Dp(t)). Therefore, the condition for BCM operation of the front-end PFC boost converter 12 is as below:

[0112]

[0113] From Figure 6, it can be seen that using the duty ratio of DP= 0.5, the converter 10 remains in DCM operational mode with the widest range of input current.

[0114] B. Maximum and RMS Switch Currents

[0115] During the positive half-cycle of the input voltage v , switches Si 16 and & 18 are responsible for carrying both the boost inductor current and the resonant current, while & 20 and Si 22 only carry the resonant current. This operational characteristic can be observed in Figures 5a-i. Specifically, the antiparallel diode of Si 16 in the interval [to < t < tS\ and the switch S2 18 in the interval [Z5 < t < Zs] handle both the boost inductor current and the resonant current. A similar situation occurs for the antiparallel diode of Si 22 and S3 20 during the negative cycle of the input voltage. This means that the peak currents of the antiparallel diodes of Si 16 and &22, and the peak currents of S218 and S320 must be considered during the design of the bridgeless boost converter 10. Because of the converter’s symmetrical operation, is2,max = isi, max an . is 1, min lS4,min. As shown in Figures 5a-i, the maximum current going through S2 18 is the sum of ires, max and ib. ax.

[0116] To perform steady-state analysis of the topology of the converter 10, the following assumptions are made: (1) all components, including semiconductor switches and diodes, are ideal, (2) the delay between the switches gating signals is neglected, and (3) the effect of snubber capacitors is ignored. The Fourier series representation of the input voltage to the resonant circuit vresis given by (15). Due to the DC blocking function of CP, only the AC components of vre. are applied to the resonant circuit, where Voc-imk is the DC -link voltage.

[0117]

[0118] in (15) and (16), harmonic order is shown by h. Moreover, the relative angular frequency (cor) is given by (17), where cu™, mo, and Q represent angular switching frequency, angular resonant frequency, and quality factor, respectively.

[0119]

[0120] The resonant current ires can be calculated from vresin (15) as below:

[0121]

[0122] where Zt,h can be calculated as below:

[0123]

[0124] where k = Lr / Lmis defined as the ratio between the secondary side and the magnetizing inductance, and m = Cs / Cpis defined as the ratio between the secondary-side and the primary-side capacitances. Moreover, Racis the equivalent resistance seen by the resonant circuit and considering Ds= 0, where leg B 34 act like a half-wave rectifier, Raccan be defined as (23) where RL is the load.

[0125]

[0126] However, since the two middle switches .S'j 30 and Se 32 in leg B 34 are switching at the same frequency of the switches in leg A 24 (fsw), the equivalent resistance (Rac) varies based on the secondary side duty ratio (Ds) which can later help to control the gain of the converter 10. The equivalent resistance (Rac) in this case can be approximated as below:

[0127]

[0128] As a result, the peak currents of the switches S2 18 and Si 16 based on first harmonic approximation (h = 1) can be calculated as shown in (25).

[0129] Moreover, the peak currents of the switches S5 30 and .87 32 based on first harmonic approximation (h = 1) can be calculated as shown in (26).

[0130]

[0131] C. Voltage Gain

[0132] The overall voltage gain of the bridgeless single stage AC-DC converter 10 is the multiplication of the gains of the front-end PFC boost converter 12, stacked switch converter 24, CLLC resonant circuit 14, and HF half-wave rectifier 34. Since the switching frequency of the converter is much higher than the input voltage frequency, the input voltage (v,«) can be considered constant during each switching period Tsw. Therefore, the gain of the PFC boost converter 12 operating in DCM can be calculated as (27).

[0133]

[0134] Based on (15), the RMS value of the input voltage to the resonant circuit (vres) can be calculated as (28).

[0135]

[0136] Based on the designed control system described below, the duty ratio of the stacked switches in leg A 24 will be slightly changing around Dp= 0.5, following theinput voltage frequency (fg= 60Hz). Therefore, considering the average value of Dp= 0.5 to further simplify the voltage gain equation, the RMS value give in (28) can be simplified as shown in (29).

[0137]

[0138] The equivalent circuit of the CLLC resonant circuit is given in Figure 7. By ignoring the higher order harmonics, the voltage gain of the CLLC resonant circuit can be calculated as (30).

[0139]

[0140] As the result, total voltage gain of the converter 10 considering an average value of 0.5 for the duty ratio of the switches in leg A 24 (Dp) is given in (31).

[0141]

[0142] The overall voltage gain of converter 10 in the absence of the HF switches in leg B 34 (i.e. Ds= 0) is illustrated in Figure 8 for k = 10 and m = 0.8 and different quality factors (Q). On the other hand, in the bridgeless rectifier where the two switches Ss 30and 6 32 in leg B 34 are switching with the same frequency as the switches in leg A 24 (fsw) and with D, > 0; Rac(see (24)), and therefore, quality factors changes below:

[0143]

[0144] As the result, the overall gain of the converter 10 becomes dependant to the duty ratio of the switches in leg B 34 (A) as presented in (33).

[0145]

[0146] Figure 9 demonstrates the overall gain plot of the converter 10 when Ds> 0. It can be seen that in this way, the overall gain of the converter 10 can be controlled using Dsand independent of leg A 24, which later will be used in the controller 11 to help the converter 10 to achieve a reduced output voltage ripple. Details of the controller 11 are described below.

[0147] CONTROL SYSTEM DESIGN

[0148] As mentioned above, achieving high quality sinusoidal input current, having a reduced output voltage ripple while critically reducing the converter’s storage capacitances, and ensuring voltage regulation are desirable for efficient and reliable operation of EV systems. These factors greatly influence the performance, longevity, and overall functionality of EV systems. This section presents the designed control system that will help the converter 10 achieve the aforementioned objectives. Looking at Figure 3b, the controller (PWM)-based controller 11 comprises an input current control loopcircuitry 80, an output voltage regulation loop circuitry 82, and voltage ripple reduction loop circuitry 84, and pulse width modulator circuitry 86.

[0149] A. Input Current Control

[0150] Looking at input control loop circuitry 80, as previously stated above, the PFC boost stage 12 in the bridgeless AC-DC converter 10 operates in DCM operational mode. In this mode, the AC line voltage and current are in phase and have a near unity power factor. From (12), the average input current of the PFC boost converter 12 can be calculated as below:

[0151]

[0152] The input current shown in (34) indicates that the average input current of the converter will not be purely sinusoidal. However, as it is clear in (34), it is possible to achieve a high quality sinusoidal input current (zw) by properly controlling the primaryside duty ratio Dpso that the destructive term VDC- link / vzn - sin(cogt) in the denominator of (34) is eliminated. To that end, the primary-side duty ratio (Dp) is chosen as (35).

[0153]

[0154] In this way, by implementing a closed-loop control system as shown in Figure 10, the denominator term in (34) will be canceled-out and the input current will become purely sinusoidal.

[0155] However, in the converter 10 the bulky DC-link capacitors are replaced with smaller ones, the DC-link voltage has more fluctuation which results in higher voltage ripple in the output of the converter 10. Moreover, since the converter 10 is designed to operate in DCM, CCM operation of the converter 10 at the peak of the input current canresult in current spikes, harmonic distortion, and hardswitching operation of the switches in leg A 24. Therefore, as the duty ratio of the primary-side switches (Dp) is set to vary based on (35), it should be also controlled to prevent the converter 10 from going to CCM operation considering the conditions described below under the discussion pertaining to the converter analysis. As the result, for a better duty ratio control and to further weaken voltage fluctuation and maintain the DCM operation of the converter 10, the duty ratio of the primary-side switches has been considered to be as (36).

[0156]

[0157] The parameter Kcin (36) is tuned properly to lower the DC-link voltage ripple and maintain the DCM operation of the converter 10 to guarantee soft-switching by forcing Dpto change in a pre-defined interval. Using the (Dp) defined in (36) the input current of the converter 10 (zA) can be re-defined as presented in (37), which is purely sinusoidal as the result of using the closed-loop control system.

[0158]

[0159] B. Output Voltage Regulation

[0160] As shown in Figure 11, to provide output voltage regulation for the AC-DC converter 10 during its operation, Variable Frequency Modulation (VFM) technique is utilized. Moreover, the designed VFM-based controller is developed to be solely responsible for output voltage regulation to avoid a never-ending frequency variation (which can cause stability issues) due to the high output voltage ripple of the converter 10 as a result of using small DC-link and output filter capacitors. To that end, the output voltage of the converter 10 is first fed to a low -pass filter (LPF) to remove the low-frequency ripples and then the filtered voltage is compared with a reference value (Vo,ref = 8001A) to generate the error signal (see Figure 11).

[0161] Then the generated error signal is fed to a PI controller to generate the required control signal which is in this case, is the switching frequencyMoreover, the PI controller gains (Ktoand Kpo) shown in (38) are calculated based on the fundamental harmonic approximation (FHA) and using Control System Analysis Toolbox in MATLAB.

[0162] There exist two subsystems in the overall close-loop system that have different operating frequencies: the bridgeless AC-DC converter 10 that is working with a very high frequency ( / ™ ~ 100kHz) and the VFM-based PI controller which is working with low frequency. In control systems theory, when there exist subsystems interacting with each other and are working with different operating frequencies, using the complete model of the subsystem that is working with high operating frequency only complicates the overall model of the closed-loop system and using an average model of the system is sufficient for designing the low frequency (PI) controller.

[0029] -

[0031] , Therefore, using the FHA model is sufficient to design the PI controllers for output voltage regulation of the converter 10.

[0163] To that end, a PI controller in the form of (38) is developed for output voltage regulation. First, to cancel-out the destructive effect of the Pi’s pole at zero, Pi’s zero should be considered close to the origin. Therefore, Kio / Kpo= 125 x 10-6 has been considered. Moreover, considering the output range of the VFM controller (fsw~ 1 )kHz). the proportional gain of the PI controller is considered as Kpo= 800. As the result, KiO= 0. 1 can be calculated. The bode diagram of the closed-loop system is illustrated in Figure 12, where phase margin and gain margin are 31° and 2.8dB, respectively.

[0164]

[0165] C. Output Voltage Ripple Reduction

[0166] As shown in Figure 13, to reduce the high output voltage ripple of the converter 10 which occurs as a result of using low storage capacitances, a closed-loop controller based on Pulse Width Modulation (PWM) technique is presented. The PWM- based controller 11 is developed to be solely responsible for output voltage ripple reduction using the switches .S'? 30 and .N 32 in leg B 34 of the topology. To design the output voltage ripple reduction controller independent of the VFM controller, it is desirable to make an error signal solely as a result of output voltage ripple.

[0167] To that end, the actual output of the converter 10 is compared with the LPF fed output of the converter 10 as illustrated in Figures 13 and 14. Then, the calculated error signal is fed to a PI controller to generate the required control signal which in this case, is the duty ratio (A) of the switches Sj 30 and N 32 in leg B 34 of the converter 10. Moreover, the PI controller gains (Kir and Kpr) shown in (39) are calculated based on the fundamental harmonic approximation (FHA) and using Control System Analysis Toolbox in MATLAB.

[0168]

[0169] Considering the fact that the error signal in this case is the output voltage ripple (E = Ripple), the control signal (Ds) generated by (39) can be defined in (40).

[0170]

[0171] Now combining the time-varing Dsand equivalent resistance (Rac) defined in (24) results in (41).

[0172]

[0173] As a result, by properly choosing the PI controller gains (Kprand Kir), the equivalent resistance (Rac), and therefore, the overall gain of the converter 10 can be controlled to minimize the output voltage ripple enabling the converter 10 to utilized low storage capacitances.

[0174] Similar to the VFM controller as described above, there exist two subsystems in the overall close-loop system with different operating frequencies: 1) the bridgeless AC-DC converter 10 that is working with a very high frequency (fsw~ 100kHz), 2) the designed PWM-based PI controller which is working with low frequency. Similar to the discussion pertaining to the VFM controller design, using an average model of the system is sufficient for designing the low frequency (PI) controller used for output voltage ripple reduction

[0029] -

[0031] . Therefore, using FHA model is sufficient to design the PI controllers.

[0175] To that end, a PI controller in the form of (38) is developed for output voltage regulation. First, to cancel-out the destructive effect of the Pi’s pole at zero, Pi’s zero should be considered close to the origin. Therefore, Kto / Kpo = I O ' has been considered. Moreover, considering the output range of the PWM-based controller 11, the proportional gain of the PI controller is considered as Kpr= 0.01. As a result, r = 0.00001 can be calculated. The bode diagram of the closed-loop system is illustrated in Figure 15, where phase margin and gain margin are 39° and 7.4dB, respectively.

[0176] EXPERIMENTAL VALIDATION

[0177] To verify the performance of the bridge less AC-DC converter 10 and the effectiveness of the designed control system, a proof-of-concept hardware prototype has been developed and tested in the laboratory using a 1. IkW, 120Frow / 800 fc, 100 - \1QkHz SiC-based design. Moreover, PLECS RT Box 1 is used as the controller unit. Figure 16shows a picture of the hardware prototype, while Table I shows the system specification and system parameters.

[0178] Parameters ValuesRated Power (Po) 1.1k WOutput Voltage (Vo) SOOL^cInput AC Voltage (uin) 90 — 135VaC,rm£Switching Frequency ) > lOOkff;Input Filter Inductance (£;„ ) 550p,HInput Filter Capacitance (Cn) 0.8fiFBoost Inductance (Lb) 20 .HDC-link Capacitances < C ', i . C, ) 25 / / FPrimary Resonant Capacitance (Cp) (J.068 / 1 FSecondary Resonant Capacitance (Cs) 0.68 / rFResonant Inductance (Lr) 2&) ,HMagnetizing Inductance (Lm) 27f){J.HOutput Filter Capacitances ( „i , C',,2 ) 25 / / ,FSwitches (Si - IMW65R030M 1HXKSA1Diodes (D - S4) GP3D005A170B

[0179] A. Design Procedure

[0180] Since the drain-source breakdown voltage of the IMW65R030M1HXKSA1 switches is 650V and the stress of voltage across switches is half of the DC-link voltage, The maximum switch voltage is designed to be 500V, making DC-link voltage VDC-imk = 1000. According to Figure 9, the bottom limit forthe switching frequency happens around a>r = 1.45. Therefore, to design the converter 10 to operate with the switching frequency fsw> 100kHz, the base frequency of the resonant circuit is set to fo = IQkHz. The specification and parameters of the prototype are given in Table I based on the following:

[0181]

[0182]

[0183]

[0184]

[0185]

[0186] Ls= kLm260 / 12? (47)

[0187]

[0188] Cs= mCp0.68 / iff (49)

[0189] fsw- 1.45 x f0~ lOOfeHz (50)

[0190] B. Steady-State Experimental Results

[0191] The steady-state experimental waveforms obtained from the prototype are shown in Figures 17-24. Figure 17 illustrates input voltage (v™), input current ( / ;„), output voltage (Fo), and output current (Io) waveforms at 120Eac,rms input and 800 fc output voltage. As can be seen in Figure 17, the input power factor is PF = 0.993 and the converter 10 achieved an efficiency of 95.3 at around l.lkW power which was measured by “power analysis tool” of the KEYSIGHT MSOX6004A oscilloscope.

[0192] Moreover, Figure 18 illustrates the boost inductors current ib) of the frontend PFC circuit along with input voltage vm) and input current (i ). It can be seen that using the calculated boost inductance at the chosen switching frequency and power level, the PFC circuit operates in DCM as desired.

[0193] The switches Si 16, S2 18, and Se 32 voltage and current waveforms at line and switching frequency are shown in Figures 19-24. Each switch current in the bridgeless converter 10 has a low -frequency envelope and therefore, the soft-switching operation of each switch needs to be verified in both positive and negative line cycles. Due to the similar operation of the switches Si 16 and S4 22, S2 18 and S3 20, and S5 30 and So 32, showing the switching waveforms for Si 16, S2 18, and Se 32 would be sufficient to confirm the soft-switching performance of the converter 10. The voltage and current waveforms of switch Si 16 at line frequency are shown in Figure 19. Moreover, the soft-switching operation of the switch Si 16 in both positive and negative line cycles are shown in Figure 19. To further verify the soft-switching operation of switch Si 16, voltage and current waveforms of switch Si 16 at switching frequency are illustrated in Figure 20. Since the resonant current is lagging behind the resonant voltage due to the presence of CLLC resonant converter 14, switch Si 16 current first flows through its antiparallel diode. Accordingly, as shown in Figure 20, Si 16 current is negative at the moment that it turns ON, resulting in ZVS Turn ON for switch Si 16. Moreover, due tothe presence of snubber capacitors, voltage across .S' / 16 slowly rises from zero proving ZCS turn OFF for this switch S 16 as shown in Figure 20.

[0194] Similarly, the voltage and current waveforms of switch S2 18 at line frequency are shown in Figure 21. Moreover, the soft-switching operation of the switch S2 18 in both positive and negative line cycles are shown in Figure 21. To further verify the soft- switching operation of switch S2 18, voltage and current waveforms of S2 18 at switching frequency are illustrated in Figure 22. Similar to the switch Si 16, switch S2 18 current first flows through its antiparallel diode resulting in ZVS Turn ON for switch S2 18 as illustrated in Figure 22. Moreover, due to the presence of snubber capacitors, voltage across S2 18 slowly rises from zero proving ZCS turn OFF for this switch S2 18 as shown in Figure 22.

[0195] Similar to the switches Sy 16 and S2 18, to show the soft-switching operation of the switch Se 32, its voltage and current waveforms at line frequency are shown in Figure 23. Moreover, the soft-switching operation of the switch Se 32 in both positive and negative line cycles are shown in Figure 23. To further verify the soft-switching operation of switch Se 32, voltage and current waveforms of .N 32 at switching frequency are illustrated in Figure 24. Similar to the switches Si 16 and S2 18, switch V 32 current first flows through its antiparallel diode resulting in ZVS Turn ON as illustrated in Figure 24. Moreover, due to the presence of snubber capacitors, voltage across V 32 slowly rises from zero proving ZCS turn OFF for this switch Se 32 as shown in Figure 24.

[0196] C. Dynamic Response Experimental Results

[0197] To further validate the performance of the developed closed-loop control systems, several dynamic responses are captured in case of reference tracking, input voltage variation and transition between open loop and closed loop control system. The dynamic responses of the converter 10 are shown in Figures 25-27.

[0198] To validate the performance of the developed VFM-based controller regarding reference voltage tracking, reference voltage of the converter 10 is changedfrom the nominal 800E / Cto 750 Enduring the normal operation ofthe converter 10. Figure 25 illustrates the dynamic performance of the converter 10 to this reference variation. Input voltage (v™), input current (fin), DC-link voltage (Voc-iink), and output voltage (Fo) of the converter 10 are shown in Figure 25. It can be seen in Figure 25 that the closed- loop control system was able to track the new reference voltage with zero steady-state error and fast transient response.

[0199] To further validate that the control system is able to regulate the output voltage of the converter ( o) for different input voltages (V;„), the input voltage of the converter 10 is changed from 120Fr™ to 135 Er™ and the dynamic response the converter 10 is illustrated in Figure 26. As can be seen in Figure 25, the closed-loop control system was able to maintain the 800 Vdc output of the system despite the change in the input voltage of the converter 10 with zero steady state error and fast transient response.

[0200] Finally, to show the effectiveness of the closed-loop controllers in terms of ripple reduction, the ripple reduction and VFM-based controller are turned off and the converter 10 is operated with open-loop controller with a fixed switching frequency. Then, using a C block in PLECS RT Boxl, both feedback loops are manually activated to see the effect of the closed-loop controllers in terms of reducing the output voltage ripple and regulating the voltage at 800 Vdc. The dynamic response of the converter 10 is presented in Figure 27. As can be seen in Figure 27, the closed-loop control system successfully reduced the voltage ripple and regulated the output voltage to 800 / cwith zero steady-state error and fast transient response.

[0201] D. Comparison

[0202] To show the superiority of the topology and the closed-loop controller 11, the converter 10 was compared with several other state-of-the art EV OBC topologies with reduced storage units. The result of this comparison is summarized in Table II.

[0203] TABLE IICOMPARISON WITH THE SATE-OF-T HE-ART EV OBCs

[0204] With similar switching frequency range and comparable efficiency, the converter 10 was able to reduce the voltage ripple while utilizing the lowest storage capacitances with reduced number of semi-conductor devices. Figure 28 illustrates the measured efficiency for a range of an input voltages. It can be observed that the maximum efficiency of 95.3% was achieved at Vm = 120rms. Moreover, Figure 29 shows the measured power factor of the converter 10 for a range of an input voltages. It can be observed that using the closed-loop duty ratio controller, the quality of the input current remains high for different input voltages.

[0205] In another implementation, referring to Figure 30, there is shown a circuit diagram of a single-stage AC / DC converter 110, comprising an integrated voltage ripple controller (VRC) circuitry that can be applied to a variety of AC / DC conversion power applications, such as energy storage in an AC grid, an electric vehicle charger and a power interface between AC and DC micro-grids. Depending on the power application, the AC / DC power conversion block may be configured as a direct AC / DC (uni -directional or bi-directional) conversion stage with the integrated VRC. Use of the integrated VRC concept gives rise to a multitude of different AC / DC converter topologies depending on the system and load requirements of the associated AC / DC power conversion.

[0206] Advantageously, such topologies minimize the use of passive components in the VRC stage. The integration process is accomplished by first identifying the voltageof a magnetic component that has the same polarity with the voltage across the magnetic component in the VRC. Once the current paths and all the voltage polarities of all the magnetic components are identified and investigated, the integration process can be developed and performed. By means of integration, either the magnetic or the capacitive component, or even both of them will be shared between the power circuit and the VRC.

[0207] Figure 31 shows a topology of a highly compact uni-directional AC / DC nonisolated converter 120 with an integrated VRC 122 comprising one input capacitor Cfi 124 with a simplified resonant circuit network comprising an inductance LCOu 126 and a capacitance Cr128. By integrating the VRC circuitry 122 into the converter 120 less components, such as an additional inductor and capacitor, are required, which enhances the power density [W / m3] of the overall circuit 120. In addition, the overall circuit 120 size can be further reduced. As such, in one example, the overall converter 120 only requires four switches Si 130, Si 132, Svrci 134, Svrc2 136, in total, which further simplifies the controller 122 and gate driver design. In one example, the converter 120 may be used for interfacing with the AC grid or single -phase AC generator for powering residential DC electronic loads or connecting to a DC micro-grid. In another implementation, the topology shown in Figure 31 may be easily modified from the unidirectional converter 120 configuration to a bi-directional converter 150 configuration, as shown in Figure 32, in which switches Di 138, Di 140, Di 141, Du 142 are replaced by active switches Smi 152, Smi 154, S3 156, S4 158.

[0208] In each of the aforementioned AC / DC converters 120, 150, an active auxiliary circuit may be included on the AC input side to assist the converter 120, 150’s switches to achieve extended zero switching-power loss, thereby achieving higher efficiency. In one example, active auxiliary circuit 160 is included in the topology of Figure 31, such as converter 170, depicted in Figure 33. Figure 34 shows another converter 180 topology comprising an active auxiliary circuit 182, where Qif 184 is a low frequency active switch and Laa186 is the auxiliary inductor for assisting loss-less switching operation. In AC / DCconversion where electrical isolation is required, an isolated version of the AC / DC topology 190 is shown in Figure 35, where the high frequency transformer 192 with magnetizing inductance Lmi194 is used to provide isolation, and Cri196 and Cri198 are the resonant capacitors.

[0209] The auxiliary circuit presented in Figure 34 can also be applied to the output stage of an AC / DC converter. For example, Figure 36 shows an AC / DC converter 200 in which the auxiliary circuit 182 is applied to the output stage of the isolated converter shown in Figure 35. In one implementation, the output load may be connected across all three capacitors (Cmi 202, CM 204, C;„3206) or across only capacitor CM 206. In Figure 36, the load 208 is connected across CM 206. Similarly, the same output auxiliary circuit 182 may also be applied to the non-isolated AC / DC converter 210 topology, as shown in Figure 37.

[0210] To illustrate the operation of the exemplary AC / DC converters, the converter 180 presented in Figure 34 is used as an example, as the voltage ripple controlling technique can be applied to other AC / DC topologies presented above. Figure 38a shows the AC / DC converter 220, with the modulation control scheme for the two switches (Svrci134, Svrc2 136) in the VRC 122, as shown in Figure 38b, in more detail.

[0211] The fundamental operation of the converter 220 will now be described. Figures 39 and 40 show the key operating waveforms of the converter 220 in linefrequency and high-frequency, respectively. From the low frequency waveforms, it can be observed that the input current (Cf) naturally follows the sinusoidal AC input voltage due to the discontinuous conduction mode (DCM) of the bridgeless boost converter. Hence, natural power factor correction for variable AC input can be achieved. By filtering the high frequency components in the input current (zly), a sinusoidal input current can be obtained, as shown by iavgin Figure 39. The integrated voltage ripple controller (VRC) is a boost-type decoupling cell, and comprises a bi-directional circuitry and an energy storage capacitor C / 2224 which is integrated with the original converter 122. The outputvoltage vo(t) of the converter 220 without the integrated voltage ripple controller consists of a ripple voltage. The fundamental frequency of the ripple voltage is twice that of the AC supply frequency (120Hz). Hence, vo(t) can be given as below:

[0212]

[0213] As shown in Figure 38b, with this modulation technique the output voltage ripples in the output capacitor voltages (Vcoiand VCO2 across Coi202 and CO2 204, respectively, have 180° phase difference, hence, the voltage ripples cancel each other, and the output does not include any voltage ripple.

[0214] Figure 40 shows high frequency waveforms of converter 220, in which the input PFC (power factor correction) stage is a bridgeless boost converter circuit. Switches Si 130 and S2 132 are controlled such that the duty ratio for switch Si 130 and switch S2 132 are 180° out of phase. The converter shown in Figure 34 (or Figure 38) then consists of a series LC resonant circuit (Cr128 andZcou 126), where the resonant inductor LCOu 126 is coupled and integrated with the VRC circuit 122. The presence of the resonant circuit, together with the auxiliary circuit (Caai230, Caaa2 232, and Laa234) assist primary side switches Si 130 and S2 132 to achieve soft-switching operation. For steady-state operation in the positive and negative half-cycles, the high frequency operation of the converter 220 within one switching period Ts can be divided into 3 operating stages, as shown in Figures 41a-c. Since the converter 220 operates symmetrically during both positive and negative half-cycles, only the positive half-cycle is addressed in the analysis that follows.

[0215] Looking at Figure 41a, in a first operating stage \to<t<ti\ at the beginning of this interval, at t=to, the boost inductor A / 234 begins to charge from zero. Hence, zero current tum-ON is obtained for diode / L 141 . During this stage, the current going through the couple inductor 126 is negative. The lagging resonant current ires) forces theantiparallel diodes D3 141 of Si 130, D2 140 of Svrci134 to conduct. When the gate signal is applied to Si 130, the current flowing through the antiparallel diodes D3 141, D2 140 is now conducted by the switches Si 130, Svrci134. Since antiparallel diodes l)s 141, D2 140 were conducting before turning ON the switches, soft-switching turn-on can be obtained for switch Sy 130.

[0216] Now looking at Figure 41b, in a second operating stage [ <t<C] the boost inductor Lf 249 current is discharging to the circuit through l)s 141. Also, the negative input current tojand the auxiliary inductor Laa234, forces the antiparallel diodes / ft 141. Di 138 of S2 130 to conduct. Since the boost converter 220 operates in discontinuous conduction mode (DCM), IDS becomes zero at t=t2.

[0217] Referring to Figure 41c, in a third operating stage [C<t<ty| at the beginning of this stage, the current flowing through the antiparallel diode D2 140 of switch S2 132 is now conducted by the switch SWc2 136. Since antiparallel diodes Ds 141, D2 140 were conducting before turning ON the switches S2 132, Svrc2 136 zero voltage switching can be obtained for switch S2 132.

[0218] OPERATION IN THE PEC STAGE

[0219] In the converter 220, due to the discontinuous conduction mode (DCM) operation mode of the boost converter, the AC line current and voltage are in phase with near unity power factor. Thus, the rectifier input current should be proportional to the applied input voltage:

[0220]

[0221] where vacis the AC input voltage given by (52), and R- is the emulated resistance and is represented by (53).

[0222]

[0223]

[0224] In general, the boost converter operates in continuous conduction mode (CCM) if the average inductor current is higher than its current ripple; and it operates in discontinuous conduction mode (DCM) if the average inductor current is less than its current ripple. Hence the conditions for CCM and DCM are:

[0225] for CCM (54)

[0226]

[0227] where <iif(t)>Ts is the average boost inductor Lf 249 current given by (56), and AiLf(t) is the inductor current ripple shown in (57).

[0228]

[0229]

[0230] If the boost converter operates in CCM, and if the inductor is small enough that its influence on the low-frequency components of the converter waveforms is negligible, then the duty ratio should follow the function given by (58).

[0231] . / w-i-M V (58) ' del

[0232] Substitution of (56), (57) and (58) into (54) leads to:

[0233]

[0234] SIMULATION VERIFICATION AND RESULTS

[0235] Single-Phase Non-Isolated AC / DC Converter (see Figure 34)

[0236] In order to confirm the operation and accuracy of the VRC technique inAC / DC converter 220 system, the non-isolated converter 220 with the auxiliary circuit 60 on the AC side shown in Figure 34 with a rated power of IkW and an output voltage of 300V is tested in PSIM (Powersim). The input tested voltage range is 90 - 135Vrms, 60Hz. TABLE I lists the system specifications and converter circuit parameters. Figure 42 shows the simulated output voltage, input AC voltage and input AC current when the output load current changes from the rated value of 3A to 1 ,5A. It can be observed that the output voltage achieves very low output voltage ripple (less than 1.7% for both conditions). In this case, the magnitude of the sinusoidal 120Hz PWM modulation signals that apply to the VRC switches is reduced by about 40%. The achieved input power factor at the rated power condition is 0.98 and the input power achieved at reduced load condition is greater than 0.975. Figure 43a shows the switch current and voltage waveforms of the primary side switch Si, and Figure 43b shows the switch current and voltage of the primary side switch S2. It can be observed that zero current switching and zero voltage switching condition is achieved for both switches Si, S2. The achieved full load efficiency is 96.4%. Figure 44 shows the simulated output voltage, input AC voltage and input AC current when the AC input voltage changes from 135Vrms to 115Vrms. It can be observed that the output voltage is stable and maintains with a very low output voltage ripple (-1.8% the whole operation).

[0237] TABLE I. DESIGN SPECIFICATIONS & CIRCUIT PARAMETERS

[0238] TABLE II lists the achieved percentage of voltage ripple in the output voltage for different load conditions.

[0239] TABLE II. PERCENTAGE OF OUTPUT VOLTAGE RIPPLE

[0240] Single-Phase Isolated AC / DC Converter (see Figure 35)

[0241] In order to confirm the operation of isolated version of the AC / DC converter with an integrated VRC, a 1.4kW system was tested in PSIM with the same input AC voltage range in TABLE I, and an output voltage of 360V. TABLE III lists the system specifications and converter circuit parameters. Figure 45 shows the simulated output voltage, input AC voltage and input AC current when the output load current changes from the rated value of 3.4A to 1.7A. It can be observed that a stable average output voltage of 360V with a high quality input line current is achieved. The achieved output voltage ripple is less than 1.8%, with an input power factor of at least 0.975 is achieved. Figure 46a shows the primary side switch Si current and voltage waveforms, and Figure 46b shows the primary side switch S2 current and voltage waveforms. It can be observed that zero current switching turn-on is achieved for the top switch Si and zero voltage switching turn-on is achieved for the bottom switch S2. The overall efficiency is 95.6% at the rated power.

[0242] TABLE III. DESIGN SPECIFICATIONS & CIRCUIT PARAMETERS

[0243] The proposed integrated VRC concept can also be applied to three-phase AC / DC converter configurations. Based on the topology presented in Figure 34, various three-phase AC / DC converter structures can be derived. Accordingly, Figure 47 shows a converter 250 with parallel output configuration comprising three converters 180 of Figure 34 in parallel, including a three-phase transformer 252. Figure 48 shows a three- phase topology 160 configuration with the integrated soft-switching VRC circuit.

[0244] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0245] Embodiments are described above with reference to block diagrams and / or operational illustrations of methods, systems. The operations / acts noted in the blocks may be skipped or occur out of the order as shown in any flow diagram. For example, two or more blocks shown in succession may be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon thefimctionality / acts involved. While the specification includes examples, the disclosure's scope is indicated by the following claims. Furthermore, while the specification has been described in language specific to structural features and / or methodological acts, the claims are not limited to the features or acts described above. Rather, the specific features and acts described above are disclosed as example for embodiments.

[0246] REFERENCES[1] B. Maclnnis and J. A. Krosnick. (Oct. 2020). Climate insights 2020: Electric vehicles. Resources for the Future (RFF). [Online]. Available: https: / / www.rff.org / publications / reports / climateinsights2020-electric-vehicles[2] United States Environmental Protection Agency. (Apr. 2021). Inventory of U.S. Greenhouse Gas Emissions and Sinks. [Online]. Available: https: / / www.epa.gov / ghgemissions / inventory-us-greenhouse-gasemissions-and- sinks[3] C. McKerracher et al., “Electric vehicle outlook 2021,” BloombergNEF, London, U.K., Tech. Rep., Aug. 2021. [Online]. Available: https: / / about.bnef.com / electric- vehicle -outlook / [4] M. Abbasi, K. Kanathipan, J. Lam “An Interleaved Bridgeless Single-Stage AC / DC Converter With Stacked Switches Configurations and Soft-Switching Operation for High-Voltage EV Battery Systems", IEEE Trans. Ind. App., vol. 58, no. 5, pp. 5533- 5545, Mar. 2022.[5] M. Safayatullah, M. T. Elrais, S. Ghosh, R. Rezaii and I. Batarseh “A Comprehensive Review of Power Converter Topologies and Control Methods for Electric Vehicle Fast Charging Applications", IEEE Access, vol. 10, pp. 40753-40793, Apr. 2022.[6] C. Shi, H.Wang, S. Dusmez, and A. Khaligh, “A SiC -based high-efficiency isolated onboard PEV charger with ultrawide DC-link voltage range,” IEEE Trans. Ind. Appl., vol. 53, no. 1, pp. 501-511, Jan. / Feb. 2017.[7] J. Lee and H. Chae, “6.6-kW onboard charger design using DCM PFC converter with harmonic modulation technique and two-stage DC / DC converter,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1243-1252, Mar. 2014.[8] B. Whitaker et al., “A high-density, high-efficiency, isolated on-board vehicle battery charger utilizing silicon carbide power devices,” IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2606-2617, May 2014.[9] R. Pandey and B. Singh, “A power factor corrected resonant EV charger using reduced sensor based bridgeless boost PFC converter,” IEEE Trans. Ind. Appl., vol. 57, no. 6, pp. 6465-6474, Nov. / Dec. 2021.

[0010] H. V. Nguyen, D.-C. Lee, and F. Blaabjerg, “A novel SiC-based multifunctional onboard battery charger for plug-in electric vehicles,” IEEE Trans. Power Electron., vol. 36, no. 5, pp. 5635-5646, May 2021.

[0011] C. Oh, D. Kim, D. Woo, W. Sung, Y. Kim, and B. Lee, “A high-efficient nonisolated single-stage on-board battery charger for electric vehicles,” IEEE Trans. Power Electron, vol. 28, no. 12, pp. 5746-5757, Dec. 2013.

[0012] S. Jeong, Y. Jeong, J. Kwon, and B. Kwon, “A soft-switching single-stage converter with high efficiency for a 3.3-kW on-board charger,” IEEE Trans. Ind. Electron., vol. 66, no. 9, pp. 6959-6967, Sep. 2019.

[0013] W. Liu, A. Yurek, B. Sheng, Y. Chen, Y.-F. Liu, and P. C. Sen, “A single stage 1.65kW AC -DC LLC converter with power factor correction (PFC) for on-board charger (OBC) application,” in Proc. IEEE Energy Convers. Congr. Expo., 2020, pp. 4594-4601.

[0014] D. Zinchenko, A. Blinov, A. Chub, D. Vinnikov, I. Verbytskyi and S. Bayhan, "High-Efficiency Single-Stage On-Board Charger for Electrical Vehicles," in IEEE Transactions on Vehicular Technology, vol. 70, no. 12, pp. 12581-12592, Dec. 2021.

[0015] D. Patil and V. Agarwal, “Compact onboard single-phase EV battery charger with novel low-frequency ripple compensator and optimum filter design,” IEEE Trans. Veh. Technol., vol. 65, no. 4, pp. 1948-1956, Apr. 2016.

[0016] S. Li, J. Deng, and C. C. Mi, “Single-stage resonant battery charger with inherent power factor correction for electric vehicles,” IEEE Trans. Veh. Technol., vol. 62, no. 9, pp. 4336-4344, Nov. 2013.

[0017] IEEE Standard for Interconnection and Interoperability of Distributed Energy Resources With Associated Electric Power Systems Interfaces, IEEE Standard 1547- 2018 (Revision of IEEE Std 1547-2003), 2018, pp. 1-138.

[0018] SAE J2894-1: Power Quality Requirements for Plug-In Electric Vehicle Chargers — Part 1: Requirements, SAE International Standard, 2019.

[0019] F. Musavi, W. Eberle and W. G. Dunford, “A High-Performance Single-Phase Bridgeless Interleaved PFC Converter for Plug-in Hybrid Electric Vehicle Battery Chargers," IEEE Trans. Ind. App. vol. 47, no. 4, pp. 1833-1843, July-Aug. 2011.

[0020] A. Dixit, K. Pande, S. Gangavarapu, and A. K. Rathore, “DCM-based bridgeless PFC converter for EV charging application,” IEEE J. Emerg. Sei. Top. Ind. Electron., vol. 1, no. 1, pp. 57-66, Jul. 2020.

[0021] M. Pahlevaninezhad, P. Das, J. Drobnik, P. K. Jain, and A. Bakhshai, “AZVS interleaved boost AC / DC converter used in Plug-in electric vehicles,” IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3513-3529, Aug. 2012.

[0022] J. Wu, S. Li, S.-C. Tan, and S. Y. R. Hui, “Capacitor-clamped LLC resonant converter operating in capacitive region for high-power-density EV charger,” IEEE Trans. Power Electron., vol. 36, no. 10, pp. 11 456-11 468, Oct. 2021.

[0023] C. Liu et al., “High-efficiency hybrid full-bridge-half-bridge converter with shared ZVS lagging leg and dual outputs in series,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 849-861, Feb. 2013.

[0024] S. Derakhshan and J. Lam, "A Single-Stage AC / DC Bridge-Less Converter with an Adaptive Control Scheme and Reduced DC-Link and Output Capacitances for High Voltage EV Systems," 2023 IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, USA, 2023, pp. 2037-2042.

[0025] N. Spode, M. A. Dalia Costa, G. Z. Abdelmessih, J. M. Alonso and R. R. Duarte, "Reducing Low-Frequency Ripple Using Alternative Output Capacitor Connection on Integrated Converters for LED Drivers," in IEEE Transactions on Industry Applications, doi: 10.1109 / HA.2023.3257825.

[0026] S. Bang, J. -s. Seo, L. Chang, D. Blaauw and D. Sylvester, "A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering," in IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 919-929, April 2016.

[0027] J. V. Missula, R. Adda and P. Tripathy, "Ripple Reduction in the DC-link Capacitor Voltages of Single-phase ANPC Inverter using External Chopper Circuit," IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society, Singapore, 2020, pp. 2436-2441.

[0028] R. W. Erickson and D. Maksimovic, Fundamental of Power Electronics, 2nd ed. Boston, MA, USA: Kluwer, 2001.

[0029] H. K. Khalil, Nonlinear Systems, 3rd Edition, Prentice Hall, Upper Saddle River, 2002.

[0030] A. Isidori, Nonlinear control systems: an introduction, Berlin, Heidelberg: Springer Heidelberg, 1985.

[0031] J. Schiffer, D. Efimov, R. Ortega, “Global synchronization analysis of droop- controlled microgrids-A multivariable cell structure approach," Automatica, Volume 109, 2019.

[0032] M. Kwon and S. Choi, “An electrolytic capacitorless bidirectional EV charger for V2G and V2H applications,” IEEE Trans. Power Electron., vol. 32, no. 9, pp. 6792- 6799, Sep. 2017.

[0033] L. Xue, Z. Shen, D. Boroyevich, P. Matavelli and D. Diaz, "Dual Active Bridge- Based Battery Charger for Plug-in Hybrid Electric Vehicle With Charging Current Containing Low Frequency Ripple," IEEE Trans. Power Electron., vol. 30, no. 12, pp. 7299-7307, Dec. 2015.

[0034] Y. Zhang, J. Fang, F. Gao, S. Gao, D. J. Rogers and X. Zhu, "Integrated High- and Low-Frequency Current Ripple Suppressions in a Single-Phase Onboard Charger for EVs," IEEE Trans. Power Electron., vol. 36, no. 2, pp. 1717-1729, Feb. 2021.

Claims

CLAIMS:

1. An electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising: an input stage comprising primary-side circuitry comprising a PFC boost converter and a first switch converter circuitry comprising a plurality of first switching devices in a stacked configuration; an output stage comprising secondary-side circuitry comprising a second switch converter circuitry comprising a plurality of second switching devices in a stacked configuration; a resonant circuit coupled to the first switch converter circuitry and the second switch converter circuitry; and a pulse width controller (PWM)-based controller comprising an input current control loop circuitry, an output voltage regulation loop circuitry, a voltage ripple reduction loop circuitry, and pulse width modulator circuitry.

2. The electrical power conversion system of claim 1, wherein the input current control loop circuitry controls a primary-side duty ratio (Dp) of the plurality of first switching devices in the first switch converter circuitry to generate a purely sinusoidal input current (im).

3. The electrical power conversion system of claim 2, wherein the primary-side duty ratio Dpis dependent on at least a tunable parameter (Kc) for minimizing a DC-link voltage ripple and maintaining DCM operation of the system with soft-switching of the plurality of first switching devices, whereby the primary-side duty ratio (Dp) is forced to change in a pre-defined interval.

4. The electrical power conversion system of claim 2, wherein the primary-side ratio (Dp) is defined as:wherein v is an input voltage, i is an input current, mgis a grid angular frequency and Foc / iniis the DC-link voltage.

5. The electrical power conversion system of claim 1, wherein the voltage ripple reduction loop circuitry comprises a PI controller for receiving a calculated error signal of an output voltage ripple to generate a duty ratio control signal (Ds) of the plurality of second switching devices.

6. The electrical power conversion system of claim 5, wherein the duty ratio control signal (Ds) is defined as:wherein Ripple (t) is the output voltage ripple, Kprand K,rare PI controller gains.

7. The electrical power conversion system of claim 6, wherein the PI controller gains (Kpr and Kr) are selectable to determine an equivalent resistance and control an overall gain of the system to minimize the output voltage ripple, thereby enabling the system to use low storage capacitances.

8. The electrical power conversion system of claim 1, wherein the output voltage regulation loop circuitry minimizes frequency variation due to the high output voltage ripple of the system as a result of an input stage and an output stage capacitance.

9. The electrical power conversion system of claim 8, wherein the output voltage of the system is first input into a low-pass filter (LPF) to remove the low -frequency ripples and then the filtered voltage is compared with a reference value to generate the error signal.

10. The electrical power conversion system of claim 9, wherein the generated error signal is fed to a PI controller to generate a switching frequency (fsw) control signal.

11. The electrical power conversion system of any one of claims 1 to 10, wherein the pulse width modulator circuitry receives the control signal from each of the input current control loop circuitry, the output voltage regulation loop circuitry, and the voltage ripple reduction loop circuitry and generates a plurality of regulated voltages.

12. The electrical power conversion system of claim 1, wherein the PFC boost converter circuitry operates a in discontinuous conduction mode (DCM).

13. The electrical power conversion system of claim 1, wherein the output voltage regulation circuitry comprises a variable frequency (VF) control algorithm for providing consistent power supply.

14. The electrical power conversion system of claim 1, wherein the electrical power conversion system operates above resonance thereby facilitating a soft-switching operation for the switching devices of the electrical power conversion system.

15. An electrical power conversion system configured to convert an AC power input to a DC power output, the system comprising:a first circuitry comprising a resonant circuit network cascaded with high frequency switching element pairs on an AC side of the system; a DC side rectifier; an integrated active voltage ripple reduction circuitry magnetically coupled to the resonant circuit network, wherein the integrated active voltage ripple reduction circuitry suppress low frequency voltage ripples in an output voltage of the DC side rectifier; wherein the high frequency switching element pairs exhibit loss-less switching characteristics, thereby maximizing the overall power efficiency of the electrical power conversion system.

16. The electrical power conversion system of claim 15, wherein the resonant network comprises a resonant capacitance and a resonant inductance integrated with the integrated active voltage ripple reduction circuitry.

17. The electrical power conversion system of claim 16, wherein the system is unidirectional.

18. The electrical power conversion system of claim 17, wherein the system is bidirectional.

19. The electrical power conversion system of claim 15, wherein the integrated active voltage ripple reduction circuitry comprises consists of a bi-directional circuitry and an energy storage capacitor.

20. The electrical power conversion system of any one of claims 15 to 18, wherein the system is isolated.

21. The electrical power conversion system of any one of claims 15 to 18, wherein the system is non-isolated.

22. The electrical power conversion system of any one of claims 15 to 18, further comprising an active auxiliary circuit comprising at least one low frequency active switch and at least one auxiliary inductor for enhancing loss-less switching operation of the system.

23. The electrical power conversion system of claim 15, comprising an input power factor of about 0.98, and an output voltage ripple of about 1.4%.

24. The electrical power conversion system of claim 15, wherein the first circuitry and the integrated active voltage ripple reduction circuitry of a first electrical power conversion system are coupled with another first circuitry and another integrated active voltage ripple reduction circuitry of a second electrical power conversion system and a third electrical power conversion system to form a three-phase AC / DC converter configuration.

25. The electrical power conversion system of claim 24, wherein first electrical power conversion system, the second electrical power conversion system and the third electrical power conversion system are coupled in parallel.

26. A voltage ripple controller (VRC) circuitry comprising: a directional circuitry; a first energy storage capacitor integrated with a electrical power conversion system, wherein a first voltage across the first energy storage capacitor comprises firstvoltage ripples, and a second energy storage capacitor, wherein a second voltage across the second energy storage capacitor comprises second voltage ripples, and wherein the first voltage ripples and the second voltage ripples have a 180° phase difference such that an output voltage of the electrical power conversion system is substantially free of ripples; and wherein the VRC is integrated with the electrical power conversion system.

27. The voltage ripple controller circuitry of claim 26, wherein the directional circuitry is uni -directional.

28. The voltage ripple controller circuitry of claim 26, wherein the directional circuitry is bi-directional.

29. The voltage ripple controller circuitry of claim 26, wherein three voltage ripple controller (VRC) circuitries are coupled together in a parallel configuration to implement a three-phase AC / DC electrical power conversion system.

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