Method and device for implementing CP testing, and CP testing system

Abstract

The present application discloses a method and a device for implementing CP testing, and a CP testing system. The method comprises: by means of IC design, ensuring that test points requiring CP testing in odd-numbered rows and even-numbered rows of a memory storage array included in an IC are arranged consistently; and using a probe card to perform CP testing on the test points in the odd-numbered rows and the even-numbered rows of the designed IC in an alternating manner.

Description

A method and device for implementing CP testing and a CP testing system Technical Field

[0001] The present application relates to, but is not limited to, integrated circuit technology, and in particular to a method and device for implementing CP testing and a CP testing system. Background Art

[0002] Chip Probing (CP) refers to wafer testing. CP testing occurs between wafer fabrication and packaging in the entire chip production process. Its purpose is to sort out defective products before packaging (wafer sorting), thereby improving the factory yield rate and reducing subsequent packaging and testing costs. For large, pin-rich Application-Specific Integrated Circuit (ASIC) chips, the numerous test points create a pressing technical challenge.

[0003] SUMMARY OF THE INVENTION

[0004] The present application provides a method and apparatus for implementing CP testing and a CP testing system.

[0005] The present invention provides a method for implementing CP testing, including:

[0006] The integrated circuit (IC) is designed so that the test points requiring CP testing in the odd and even rows of the memory storage array included in each IC in the wafer to be tested are arranged in the same manner;

[0007] A probe card is used to perform CP testing on the IC through test points with odd and even rows interleaved.

[0008] In an exemplary embodiment, the odd-even row interleaved CP test includes:

[0009] By translating the wafer to be tested, the odd rows of the memory storage array included in each IC are tested, and then by translating the wafer to be tested, the even rows of the memory storage array included in each IC are tested.

[0010] In an exemplary embodiment, each chip included in the wafer to be tested has a structure of an application specific integrated circuit ASIC + a dynamic random access memory DRAM, and one chip includes a 5×8 memory storage array.

[0011] In one exemplary embodiment, each row of the memory storage array includes the same DRAM.

[0012] In an exemplary embodiment, the testing of odd-numbered rows of a memory storage array included in each of the ICs by translating the wafer to be tested includes:

[0013] For the odd rows of the memory storage array, a first TD is performed on the chip at the initial position of the wafer to be tested; a second TD is performed after the wafer to be tested is laterally translated by one chip; and a third TD is performed after the wafer to be tested is laterally translated by one chip again, so as to implement CP testing of the odd rows;

[0014] The testing of even-numbered rows of the memory storage array included in each IC by translating the wafer to be tested includes:

[0015] For the even rows of the memory storage array, the fourth TD is performed on the chip at the initial position of the wafer to be tested or the chip corresponding to the position of one chip translated in the opposite direction based on the third TD; the fifth TD is performed after the wafer to be tested is translated horizontally by one chip, and the sixth TD is performed after the wafer to be tested is translated horizontally by one chip again, so as to realize the CP test of the even rows.

[0016] An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above methods for implementing CP testing.

[0017] An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: for executing the steps of any of the above-mentioned methods for implementing CP testing.

[0018] The embodiment of the present application further provides a device for implementing CP testing, comprising: a pre-processing unit and a testing unit; wherein,

[0019] A pre-processing unit is configured to make the arrangement of test points requiring CP testing in odd and even rows of a memory storage array included in each IC in the wafer to be tested consistent through IC design;

[0020] The test unit is configured to use a probe card to perform an odd-even row staggered CP test on the IC through the test points.

[0021] The embodiment of the present application also provides a CP test system, comprising: a wafer to be tested, a probe card, and a test machine; wherein,

[0022] The wafer to be tested is placed on a test machine; the wafer to be tested includes one or more exposed chips, and the test points requiring CP testing in the odd and even rows of the memory storage array included in the chip are arranged in the same manner;

[0023] The test machine, under the control of the moving mechanism, makes the wafer to be tested move according to the corresponding TD. The test machine is equipped with test drives corresponding to different TDs to achieve different TDs.

[0024] The probe card is set to correspond to different TD pins to connect the test points of the exposed chip to the test machine to complete different TDs and realize CP testing.

[0025] In an exemplary embodiment, each chip included in the wafer to be tested has a structure of an application specific integrated circuit ASIC + dynamic random access memory DRAM, and one chip includes 5×8 memory storage arrays;

[0026] The test machine is provided with test drives corresponding to different TDs for realizing different TDs; under the control of a moving mechanism, the test machine places the wafer to be tested at an initial position for a first TD; translates the wafer to be tested laterally by one chip position for a second TD; translates the wafer to be tested laterally by another chip position for a third TD; places the wafer to be tested at a position one chip in the direction of the third TD from the initial position for a fourth TD, or translates the wafer to be tested in a direction opposite to the third TD by one chip position; translates the wafer to be tested laterally by one chip position for a fifth TD; and translates the wafer to be tested laterally by another chip position for a sixth TD;

[0027] The probe card corresponds to the first TD needle output, so as to connect the test point of the chip corresponding to the initial position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the second TD needle output, so as to connect the test point of the chip shifted by one chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the third TD needle output, so as to connect the test point of the chip shifted by another chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the fourth TD needle output, so as to connect the test point of the chip corresponding to the position of one chip in the third TD direction of the preset initial position or the test point of the chip corresponding to the position shifted by one chip in the opposite direction of the third TD with the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the fifth TD needle output, so as to connect the test point of the chip shifted by one chip position with the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the sixth TD needle output, so as to connect the test point of the chip shifted by another chip position with the test machine to complete the even-numbered row test of the corresponding chip.

[0028] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0029] Summary of the Figures

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0031] FIG1 is a schematic diagram of the composition structure of a DRAM of a 3D IC chip according to an embodiment of the present application;

[0032] FIG2 is a schematic diagram of odd and even rows of a memory storage array included in an IC according to an embodiment of the present application;

[0033] FIG3 is a flow chart of a method for implementing CP testing in an embodiment of the present application;

[0034] FIG4 is a schematic diagram showing the position of the bumps penetrated by the probes after TD is executed on the even-numbered rows of the IC design in an embodiment of the present application;

[0035] FIG5 is a schematic diagram of a TD execution process of a wafer in an embodiment of the present application;

[0036] FIG6 is a schematic diagram of the composition structure of an apparatus for implementing CP testing in an embodiment of the present application.

[0037] Details

[0038] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0039] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0041] After the wafer is manufactured, thousands of bare dies (unpackaged chips) are regularly distributed throughout the wafer. Since the wafer has not yet been diced and packaged, the chip bumps are all exposed. These tiny bumps are used as test points and need to be connected to the tester through the probe card's output pins. This chip test is performed by connecting the exposed chips to the tester through the probe card (also referred to as CP card in this application) on the entire wafer that has not been diced and packaged, thus performing a CP test. The probe card includes probes and chip peripheral circuits.

[0042] Take a chip including 7420 bumps and a die size of 21.3mm x 32.08mm as an example, where the chip die area, i.e., die size, refers to the area of ​​the actual physical area on the integrated circuit chip used to place electronic components. A bump is a tiny solder joint used to connect the chip to the package or printed circuit board. For such a large chip, there are so many bumps. Due to the limited test resources of the probe card and the probe card's pinout restrictions, it is impossible to pierce all the bumps in a touch done test process. The test process is usually divided into multiple test steps, each of which tests a specific function or logic of the chip. After completing a test step, the test system records the test results and prepares for the next test step. Each time a test step is completed, it is called a touch done. It should be noted that touch done is a general expression, usually used by test engineers or test system operators during the test process. It may vary depending on different test systems or test processes and is not used to limit the scope of protection of this application.

[0043] To improve CP testing efficiency, an embodiment of the present application provides a method for implementing CP testing, as shown in FIG3 , which may include:

[0044] Step 300: Designing the ICs so that the test points requiring CP testing in the odd and even rows of the memory storage array included in each IC in the wafer to be tested are arranged in a consistent manner.

[0045] In an exemplary embodiment, the IC may include but is not limited to 2D IC, 3D IC, etc. As long as it is a large chip with a sufficient number of bumps, the method for implementing CP testing provided in the embodiments of the present application can be applied.

[0046] A three-dimensional integrated circuit (3D IC) chip is a specialized integrated circuit design featuring a three-dimensional stacked structure, typically consisting of multiple chip layers stacked using vertical connection technology. Each chip layer can have a different function, enabling the integration of multiple diverse functions into a single chip. In a 3D IC chip, the ASIC layer implements specific application functions, while memory, such as dynamic random access memory (DRAM), stores data. The memory layer provides additional storage capacity and data transmission capabilities.

[0047] In one embodiment, a 3D IC chip features a unique ASIC+DRAM structure. As shown in Figure 1, a chip includes four blocks 11, each containing ten memory cells 12. The DRAM is a relatively independent memory cell as shown in Figure 1, so it can be tested separately during CP testing. The ASIC, on the other hand, is a single unit. During CP testing, regardless of which DRAM cell is being tested, the entire ASIC must be powered on. As shown in Figure 1, a block includes two rows, for a total of eight rows. As shown in Figure 2, diagonal shading indicates odd-numbered rows, and diagonal square shading indicates even-numbered rows. Combining Figures 1 and 2, a row contains five DRAMs, and a row is a repeating unit. The bump distribution in each row is highly similar, and the bump density within each row is high. Due to resource limitations or other reasons, a test driver (TD) (i.e., a single test action) cannot fully test a 5×8 memory array in a single CP test. Therefore, CP testing can be performed in batches, testing a subset of memory cells each time. In one embodiment, the five DRAMs in each row are identical.

[0048] In an exemplary embodiment, taking the 3D IC shown in Figure 2 as an example, through step 300, the bump arrangements that require CP testing in the first and second rows can be made consistent, the bump arrangements that require CP testing in the third and fourth rows can be made consistent, the bump arrangements that require CP testing in the fifth and sixth rows can be made consistent, and the bump arrangements that require CP testing in the seventh and eighth rows can be made consistent.

[0049] In one embodiment, taking the 3D IC shown in FIG. 2 as an example, the chip has a one-die-two-shot structure and uses a 5×4 photo repeat. Therefore, the first, second, third, and fourth rows are consistent with the fifth, sixth, seventh, and eighth rows. Therefore, after aligning the bump arrangement for CP testing in the odd and even rows in step 300, the first through eighth rows of the chip are consistent. "One-die-two-shot" is a term used in semiconductor manufacturing to refer to placing two chips (dies) with different functions or designs on the same wafer and manufacturing them in the same process. In semiconductor manufacturing, "photo repeat" is a term related to the photolithography step. Photolithography is a key manufacturing step used to create chip patterns on a wafer. In the photolithography process, a photomask is used to project the chip pattern onto a silicon wafer, and ultraviolet light exposure and chemical etching are used to form the pattern. Photo repeat refers to the process of repeatedly using the same photolithography mask on a single silicon wafer. This practice of reusing photolithography masks can effectively improve manufacturing efficiency and reduce costs. Because the production of photolithography masks is an expensive and time-consuming process, reusing the same mask multiple times can save time and resources. 5×4 refers to the use of a single photolithography mask (photomask) to repeatedly project the chip pattern during the photolithography process. Each mask area is 5 chips wide by 4 chips high.

[0050] In the embodiment of the present application, the arrangement of the test points in odd rows and the test points in even rows are consistent, which means that by using one probe card, the tester can test the entire wafer on the same machine, thereby improving the wafer CP test efficiency and reducing the test cost.

[0051] Step 301: Use a probe card to perform an odd-even row interleaved CP test on the IC through the test points.

[0052] In an exemplary embodiment, a probe card is used to test the odd rows of the memory storage array included in each IC by translating the wafer to be tested, and then to test the even rows of the memory storage array included in each IC by translating the wafer to be tested.

[0053] Still taking Figure 2 as an example, the entire chip consists of 8 rows of storage arrays. When doing CP testing, it is necessary to take into account both test efficiency and test feasibility. Combined with the consistent distribution characteristics of the Bumps that need CP testing in the odd and even rows in the embodiment of the present application, a CP test method with odd and even rows interleaved can be selected. In the embodiment of the present application, the CP test method with odd and even rows interleaved is to divide the DRAM storage array into two parts, odd rows and even rows, and test these two parts separately. In the test, the odd rows (such as rows 1, 3, 5, and 7) are tested first, and then the even rows (such as rows 2, 4, 6, and 8) are tested. The test method with odd and even rows interleaved is an effective strategy for taking into account both CP test efficiency and CP test feasibility when testing the DRAM storage array. It makes full use of the Bump distribution characteristics, meets the probe card needle density limit at the same time, and can effectively improve the CP test efficiency. Figure 4 is a schematic diagram of the position of the Bump where the probe is pierced after the even rows execute TD in the embodiment of the present application.

[0054] In one embodiment, testing odd-numbered rows of a memory storage array included in each IC is achieved by translating the wafer to be tested, which may include:

[0055] For the odd rows of the memory storage array, the first TD is performed on the chip at the initial position of the wafer to be tested; the second TD is performed after the wafer to be tested is laterally shifted by one chip, and the third TD is performed after the wafer to be tested is laterally shifted by one chip again to achieve CP testing of the odd rows;

[0056] In one embodiment, testing the even-numbered rows of the memory storage array included in each IC by translating the wafer to be tested may include:

[0057] For the even rows of the memory storage array, the fourth TD is performed on the chip at the initial position of the wafer to be tested or the chip corresponding to the position of one chip shifted in the opposite direction based on the third TD; the fifth TD is performed after the wafer to be tested is shifted horizontally by one chip, and the sixth TD is performed after the wafer to be tested is shifted horizontally by one chip again to achieve CP testing of the even rows.

[0058] For general chips, a TD test is usually performed once with a probe card to complete the CP test. However, for the above-mentioned 3D IC chip, due to the large size of the chip, a TD test of a probe card at a time cannot meet the CP test of the entire chip. However, in the embodiment of the present application, since the test points that require CP testing in the odd and even rows, i.e., the Bump arrangement in this embodiment, are consistent, only one probe card is needed to complete the testing of odd and even rows during the odd and even row tests. That is to say, in the embodiment of the present application, during the CP test, on the first machine, the tester can test the entire wafer using a probe card.

[0059] In the embodiment of the present application, when the test points requiring CP testing in the odd and even rows of the memory storage array included in the IC are arranged uniformly, the CP testing method of staggered odd and even rows is used to solve the problem of too many bumps and difficulty in probe card needle extraction.

[0060] An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above methods for implementing CP testing.

[0061] An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: for executing the steps of any of the above-mentioned methods for implementing CP testing.

[0062] Figure 5 is a schematic diagram of the TD execution process of a wafer in an embodiment of the present application, and the TD execution process (TD map) shown in Figure 5, in Figure 5, y / x represents the coordinate value. In the embodiment shown in Figure 5, the TD map includes N dies, and the wafer is circular. According to the method for implementing CP testing provided in an embodiment of the present application, a die needs to be divided into one TD for odd rows and one TD for even rows. Combined with the maximum limit on the number of pins on the CP card, in one embodiment, after a wafer performs 6 TD tests, the CP test of a wafer can be achieved. As shown in Figure 5, the first TD is to test the odd rows of the die in the gray shaded part. Before the second TD, the wafer is first horizontally translated by one die and then TD is performed once. In this way, it is translated three times to perform TD three times, that is, the CP test of each die's odd rows is completed; then it is translated to the even rows and TD is performed three times in the same translation manner as above, thereby completing the CP test of each die's even rows. In this way, through the method for implementing CP testing provided in the embodiment of the present application, the same CP card can be used to complete the CP test of a wafer through 6 TDs, thereby improving the CP test efficiency and reducing the CP test cost.

[0063] FIG6 is a schematic diagram of the composition structure of the device for implementing CP testing in an embodiment of the present application. As shown in FIG6 , the device may include: a pre-processing unit and a testing unit; wherein,

[0064] A pre-processing unit is configured to make the arrangement of test points requiring CP testing in odd and even rows of a memory storage array included in each IC in the wafer to be tested consistent through IC design;

[0065] The test unit is configured to use a probe card to perform an odd-even row staggered CP test on the IC through the test points.

[0066] The embodiment of the present application also provides a CP test system, comprising: a wafer to be tested, a probe card, and a test machine; wherein,

[0067] The wafer to be tested is placed on a test machine; the wafer to be tested includes one or more exposed chips, and the test points requiring CP testing in the odd and even rows of the memory storage array included in the chip are arranged in the same manner;

[0068] The test machine, under the control of the moving mechanism, makes the wafer to be tested move according to the corresponding TD. The test machine is equipped with test drives corresponding to different TDs to achieve different TDs.

[0069] The probe card is set to correspond to different TD pins to connect the test points of the exposed chip to the test machine to complete different TDs and realize CP testing.

[0070] In an exemplary embodiment, each chip included in the wafer to be tested has a special structural feature of ASIC+DRAM, and one chip includes 5×8 memory cells;

[0071] A test machine is provided with test drives corresponding to different TDs for realizing different TDs; under the control of a moving mechanism, corresponding to the first TD, the wafer to be tested is placed at an initial position; corresponding to the second TD, the wafer to be tested is translated laterally (to the right or left) by one chip position; corresponding to the third TD, the wafer to be tested is further translated laterally by one chip position; corresponding to the fourth TD, the wafer to be tested can be placed at a position one chip away from the initial position in the direction of the third TD (to the right or left), or the wafer to be tested can be translated by one chip position in the opposite direction (to the left or right) of the third TD; corresponding to the fifth TD, the wafer to be tested is translated laterally by one chip position; corresponding to the sixth TD, the wafer to be tested is further translated laterally by one chip position;

[0072] The probe card corresponds to the first TD pinout, so as to connect the test points of the chip corresponding to the initial position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the second TD pinout, so as to connect the test points of the chip shifted by one chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the third TD pinout, so as to connect the test points of the chip shifted by another chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the fourth TD pinout, so as to connect the test points of the chip corresponding to the position of one chip in the third TD direction of the preset initial position or the test points of the chip corresponding to the position shifted by one chip in the opposite direction based on the third TD with the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the fifth TD pinout, so as to connect the test points of the chip shifted by one chip position with the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the sixth TD pinout, so as to connect the test points of the chip shifted by another chip position with the test machine to complete the even-numbered row test of the corresponding chip.

[0073] In the embodiment of the present application, the arrangement of the test points in odd rows and the test points in even rows are consistent, which means that by using one probe card, the tester can test the entire wafer on the same machine, thereby improving the wafer CP test efficiency and reducing the test cost.

[0074] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A method for implementing CP testing, comprising: The test points requiring CP test in the odd-numbered rows and even-numbered rows of the memory storage array included in each IC in the wafer to be tested are arranged in a consistent manner through integrated circuit IC design; A probe card is used to perform an odd-even row interleaved CP test on the IC through the test points.

2. The method according to claim 1, wherein: The CP test of odd-even row interleaving includes: By translating the wafer to be tested, the odd-numbered rows of the memory storage array included in each of the ICs are tested, and then by translating the wafer to be tested, the even-numbered rows of the memory storage array included in each of the ICs are tested.

3. The method according to claim 2, wherein: Each chip included in the wafer to be tested has a structure of an application specific integrated circuit ASIC+dynamic random access memory DRAM, and one chip includes a 5×8 memory storage array.

4. The method according to claim 3, wherein: The DRAMs included in each row of the memory storage array are identical.

5. The method according to claim 4, wherein: The testing of the odd-numbered rows of the memory storage array included in each IC is achieved by translating the wafer to be tested, including: For the odd rows of the memory storage array, a first TD is performed on the chip at the initial position of the wafer to be tested; a second TD is performed after the wafer to be tested is laterally translated by one chip, and a third TD is performed after the wafer to be tested is laterally translated by one chip again, so as to realize the CP test of the odd rows; The testing of even-numbered rows of a memory storage array included in each IC is achieved by translating the wafer to be tested, including: For the even-numbered rows of the memory storage array, the fourth TD is performed on the chip at the initial position of the wafer to be tested or the chip corresponding to the position of one chip translated in the opposite direction based on the third TD; the fifth TD is performed after the wafer to be tested is translated horizontally by one chip, and the sixth TD is performed after the wafer to be tested is translated horizontally by one chip again, so as to realize the CP test of the even-numbered rows.

6. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the method for implementing CP testing according to any one of claims 1 to 5.

7. A computer device comprising a memory and a processor, wherein: The memory stores the following instructions executable by the processor: used to execute the steps of the method for implementing CP testing as described in any one of claims 1 to 5.

8. A device for implementing CP testing, comprising: Preprocessing unit, testing unit; wherein, A pre-processing unit is configured to make the arrangement of the test points requiring CP test in the odd-numbered rows and the even-numbered rows of the memory storage array included in each IC in the wafer to be tested consistent through IC design; The test unit is configured to use a probe card to perform an odd-even row staggered CP test on the IC through the test points.

9. A CP testing system, comprising: A wafer to be tested, a probe card, and a test machine; wherein, The wafer to be tested is placed on a test machine; the wafer to be tested includes one or more exposed chips, and the test points requiring CP test in the odd-numbered rows and even-numbered rows of the memory storage array included in the chip are arranged in the same manner; The test machine, under the control of the moving mechanism, makes the wafer to be tested translate according to the corresponding TD. The test machine is provided with test drivers corresponding to different TDs for realizing different TDs. The probe card is set to correspond to different TD pins to connect the test points of the exposed chip with the test machine to complete different TDs to achieve CP testing.

10. The CP testing system according to claim 9, wherein: Each chip included in the wafer to be tested has a structure of an application specific integrated circuit ASIC+dynamic random access memory DRAM, and one chip includes 5×8 storage units; The test machine is provided with test drivers corresponding to different TDs for realizing different TDs; under the control of the moving mechanism, the test machine places the wafer to be tested at the initial position corresponding to the first TD; Corresponding to the second TD, the wafer to be tested is laterally translated by one chip position; corresponding to the third TD, the wafer to be tested is laterally translated by one chip position again; corresponding to the fourth TD, the wafer to be tested is placed in the initial position by one chip position in the direction of the third TD, or the wafer to be tested is translated by one chip position in the opposite direction based on the third TD; corresponding to the fifth TD, the wafer to be tested is laterally translated by one chip position; corresponding to the sixth TD, the wafer to be tested is laterally translated by one chip position again. Film location; The probe card corresponds to the first TD probe output, so as to connect the test points of the chip corresponding to the initial position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the second TD probe output, so as to connect the test points of the chip shifted by one chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the third TD probe output, so as to connect the test points of the chip shifted by another chip position with the test machine to complete the odd-numbered row test of the corresponding chip; corresponds to the fourth TD probe output, so as to connect the test points of the chip corresponding to the position of one chip in the third TD direction of the preset initial position or the test points of the chip corresponding to the position shifted by one chip in the opposite direction based on the third TD to the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the fifth TD probe output, so as to connect the test points of the chip shifted by one chip position with the test machine to complete the even-numbered row test of the corresponding chip; corresponds to the sixth TD probe output, so as to connect the test points of the chip shifted by another chip position with the test machine to complete the even-numbered row test of the corresponding chip.

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