Array substrate and display panel

Abstract

Disclosed in the embodiments of the present disclosure are an array substrate and a display panel. The array substrate is provided with a display area, and comprises a substrate and a thin-film transistor layer, which is located on the side of the substrate, wherein the thin-film transistor layer comprises a plurality of first thin-film transistors, which are distributed in a first direction, the first thin-film transistors are located in the display area, second gates of adjacent first thin-film transistors are connected in the first direction, and first gates of at least two first thin-film transistors are arranged spaced apart from each other.

Description

Array substrate and display panel Technical Field

[0001] The present invention relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of display technology, consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, VR (Virtual Reality), and AR (Augmented Reality) have emerged, all of which rely on display devices. Display devices in fields such as VR and AR, which require higher resolution, have increased the pixel density of display panels to achieve higher resolution, making it difficult to increase the aperture ratio.

[0003] Therefore, an array substrate and a display panel are urgently needed to solve the above technical problems. SUMMARY OF THE INVENTION

[0004] The present invention provides a display panel and a manufacturing method thereof, which can alleviate the technical problem that the aperture ratio of a display device with a high resolution requirement is difficult to improve. Technical Solutions

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present invention provides an array substrate having a display area, the array substrate comprising:

[0007] substrate;

[0008] a thin film transistor layer, located on one side of the substrate, the thin film transistor layer comprising a plurality of first thin film transistors arranged along a first direction, the first thin film transistors being located in the display area;

[0009] Wherein, the first thin film transistor includes a first gate and a second gate, and the second gate is located on a side of the first gate away from the substrate;

[0010] Along the first direction, the second gates of adjacent first thin film transistors are connected, and the first gates of at least two first thin film transistors are spaced apart.

[0011] Preferably, along the first direction, the first gate electrodes of adjacent first thin film transistors are spaced apart.

[0012] Preferably, the orthographic projection of the second gate on the substrate partially overlaps with the orthographic projection of the first gate on the substrate.

[0013] Preferably, along the first direction, a distance between the first gates of adjacent first thin film transistors is greater than or equal to 1 micron, and a distance between the first gates of adjacent first thin film transistors is less than or equal to 6.6 microns.

[0014] Preferably, the thin film transistor layer further includes a first via hole, the first via hole is located between the first gate and the second gate, and along the first direction, the first gate of each first thin film transistor and the second gate of the first thin film transistor are connected in the first via hole.

[0015] Preferably, the first thin film transistor further includes a first active layer, the first active layer is located between the first gate and the second gate, and the first via hole is located on one side of the first active layer in the first direction.

[0016] Preferably, in the first direction, the first gate includes a first side and a second side opposite to each other, the first active layer is located between the first side and the second side, and the first via hole is located between the first side and the first active layer;

[0017] In the first direction, a distance between the first side and an orthographic projection of the first active layer on the first gate is greater than a distance between the second side and the first active layer.

[0018] Preferably, in the first direction, a distance between the first side and an orthographic projection of the first active layer on the first gate is greater than or equal to 1.5 microns, and a distance between the first side and an orthographic projection of the first active layer on the first gate is less than or equal to 4 microns;

[0019] A distance between the second side and an orthographic projection of the first active layer on the first gate is greater than or equal to 0.5 micrometers, and a distance between the second side and an orthographic projection of the first active layer on the first gate is less than or equal to 2 micrometers.

[0020] Preferably, the first thin film transistor further includes a first source electrode and a first drain electrode located on opposite sides of the first active layer in a second direction, and the second direction intersects with the first direction;

[0021] The first source electrode and the first drain electrode are located on a side of the first active layer away from the substrate, and the first source electrode and the first drain electrode are respectively connected to the first active layer;

[0022] The array substrate further includes a pixel electrode layer, which is located on a side of the thin film transistor layer away from the substrate. The pixel electrode layer includes a pixel electrode, and one of the first source and the first drain is connected to the pixel electrode.

[0023] Preferably, the first source electrode is connected to the pixel electrode, and the material of the first source electrode is selected from transparent conductive materials.

[0024] Preferably, the first drain electrode is connected to the pixel electrode, and a material of the first drain electrode is selected from a transparent conductive material.

[0025] Preferably, the thin film transistor layer further comprises a plurality of the first thin film transistors arranged along a second direction, wherein along the second direction, the first gates of adjacent first thin film transistors are spaced apart, and the second gates of adjacent first thin film transistors are spaced apart;

[0026] Wherein, a distance between the first gate electrodes of the first thin film transistors adjacent to each other in the second direction is greater than a distance between the first gate electrodes of the first thin film transistors adjacent to each other in the first direction.

[0027] Preferably, along the first direction, a connecting portion is provided between the first gates of at least two first thin film transistors, and the connecting portion connects the first gates of the two first thin film transistors;

[0028] The orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the second gate on the substrate.

[0029] Preferably, along the first direction, the thin film transistor layer includes at least one first thin film transistor group, and each first thin film transistor group includes at least two first thin film transistors;

[0030] Wherein, along the first direction, the first gates of adjacent first thin film transistors in each first thin film transistor group are connected, and the first gates of the first thin film transistors in adjacent first thin film transistor groups are spaced apart.

[0031] Preferably, each of the first thin film transistor groups is correspondingly provided with a first via hole.

[0032] Preferably, the array substrate further comprises a non-display area located on at least one side of the display area, and the thin film transistor layer further comprises a second thin film transistor located in the non-display area;

[0033] The second thin film transistor includes a second source and a second drain, and one of the second source and the second drain of at least one second thin film transistor is connected to the second gate of at least one first thin film transistor.

[0034] The present invention further provides a display panel, comprising an array substrate, wherein the array substrate comprises:

[0035] substrate;

[0036] a thin film transistor layer, located on one side of the substrate, the thin film transistor layer comprising a plurality of first thin film transistors arranged along a first direction, the first thin film transistors being located in a display area;

[0037] Wherein, the first thin film transistor includes a first gate and a second gate, and the second gate is located on a side of the first gate away from the substrate;

[0038] Along the first direction, the second gates of adjacent first thin film transistors are connected, and the first gates of at least two first thin film transistors are spaced apart.

[0039] Preferably, along the first direction, the first gate electrodes of adjacent first thin film transistors are spaced apart.

[0040] Preferably, the orthographic projection of the second gate on the substrate partially overlaps with the orthographic projection of the first gate on the substrate.

[0041] Preferably, along the first direction, a connecting portion is provided between the first gates of at least two first thin film transistors, and the connecting portion connects the first gates of the two first thin film transistors;

[0042] The orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the second gate on the substrate. Beneficial effects

[0043] The present invention reduces light shielding by the first grids by arranging at least two first grids in a first direction at intervals, thereby increasing the aperture ratio of a display panel using the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic structural diagram of a first structure of an array substrate provided by an embodiment of the present invention;

[0045] FIG2 is a schematic structural diagram of a second structure of an array substrate provided by an embodiment of the present invention;

[0046] 3 is a schematic diagram of a first film layer structure of a first thin film transistor of an array substrate provided by an embodiment of the present invention;

[0047] 4 is a schematic diagram of a second film layer structure of a first thin film transistor of an array substrate provided by an embodiment of the present invention;

[0048] 5 is a schematic diagram of the film structure of the first planar layer of the array substrate provided by an embodiment of the present invention;

[0049] FIG6 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Modes for Carrying Out the Invention

[0050] The present application provides an array substrate and a display panel. To make the purpose, technical solutions, and effects of the present application more clear and explicit, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0051] Currently, due to the increase in pixel density to achieve high resolution, there is a technical problem that it is difficult to increase the aperture ratio of the display panel.

[0052] 1 to 5 , an embodiment of the present invention provides an array substrate 100 having a display area AA. The array substrate 100 includes:

[0053] substrate 101;

[0054] A thin film transistor layer 102 is located on one side of the substrate 101 . The thin film transistor layer 102 includes a plurality of first thin film transistors 103 arranged along a first direction X. The first thin film transistors 103 are located in the display area AA.

[0055] The first thin film transistor 103 includes a first gate 104 and a second gate 105 , and the second gate 105 is located on a side of the first gate 104 away from the substrate 101 ;

[0056] Along the first direction X, the second gate electrodes 105 of adjacent first thin film transistors 103 are connected, and the first gate electrodes 104 of at least two first thin film transistors 103 are spaced apart.

[0057] In the embodiment of the present invention, at least two first gates 104 are spaced apart in the first direction X, thereby reducing light shielding by the first gates 104 , thereby increasing the aperture ratio of the display panel using the array substrate 100 .

[0058] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0059] Referring to Figures 1 to 5, in this embodiment, the thin film transistor layer 102 further includes a plurality of first thin film transistors 103 arranged along a second direction Y. Along the second direction Y, the first gates 104 of adjacent first thin film transistors 103 are spaced apart, and the second gates 105 of adjacent first thin film transistors 103 are spaced apart. The second direction Y intersects with the first direction X.

[0060] In some embodiments, the first thin film transistor 103 further includes a first active layer 106, and the first active layer 106 is located between the first gate 104 and the second gate 105. The first thin film transistor 103 further includes a first source electrode 107 and a first drain electrode 108 located on opposite sides of the first active layer 106 in the second direction Y. The first source electrode 107 and the first drain electrode 108 are located on a side of the first active layer 106 away from the substrate 101, and the first source electrode 107 and the first drain electrode 108 are respectively connected to the first active layer 106.

[0061] In some embodiments, along the second direction Y, the first sources 107 of adjacent first thin film transistors 103 are connected; or, along the second direction Y, the first drains 108 of adjacent first thin film transistors 103 are connected.

[0062] In some embodiments, the first direction X is a row direction. Along the first direction X, the second gate electrodes 105 of adjacent first thin film transistors 103 are connected, that is, the second gate electrodes 105 of the first thin film transistors 103 in the same row are connected. The second gate electrodes 105 of the first thin film transistors 103 in the same row can be integrally provided to simplify the manufacturing process of the array substrate 100.

[0063] In some embodiments, the second direction Y is a column direction. Adjacent first source electrodes 107 or first drain electrodes 108 of the first thin-film transistors 103 are connected along the second direction Y. That is, the first source electrodes 107 or first drain electrodes 108 of the first thin-film transistors 103 in the same column are connected. The first source electrodes 107 or first drain electrodes 108 of the first thin-film transistors 103 in the same column can be integrated to simplify the manufacturing process of the array substrate 100.

[0064] In some embodiments, along the first direction X, the first gates 104 of adjacent first thin film transistors 103 are spaced apart, that is, the first gates 104 of the first thin film transistors 103 in the same row are spaced apart from each other, and the spacing therebetween is greater than 0.

[0065] Referring to FIG. 3 , in some embodiments, the orthographic projection of the second gate 105 on the substrate 101 partially overlaps with the orthographic projection of the first gate 104 on the substrate 101 .

[0066] In some embodiments, when the first gate electrodes 104 of adjacent first thin film transistors 103 are spaced apart along the first direction X, the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 is greater than or equal to 1 micron, and the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 is less than or equal to 6.6 microns. For example, the spacing can be 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5 microns, 5.5 microns, 6 microns, 6.5 microns, etc., to improve the aperture ratio of a display panel using the array substrate 100. At pixel densities corresponding to different resolutions, the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 in the first direction X varies. By adaptively adjusting the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 in the first direction X within the aforementioned range (for example, the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 in the first direction X increases as the pixel density increases), the aperture ratio of a display panel using the array substrate 100 can be effectively improved.

[0067] In some embodiments, the spacing between the first gate electrodes 104 of adjacent first thin-film transistors 103 in the second direction Y is greater than the spacing between the first gate electrodes 104 of adjacent first thin-film transistors 103 in the first direction X. By spacing the first gate electrodes 104 of adjacent first thin-film transistors 103 in the first direction X and the second direction Y, light blocking by the first gate electrodes 104 is significantly reduced, thereby improving the aperture ratio of a display panel using the array substrate 100. This helps the display panel using the array substrate 100 maintain high resolution while reducing power consumption. Specifically, by spacing the first gate electrodes 104 of adjacent first thin-film transistors 103 in the first direction X and the second direction Y, experiments have shown that the aperture ratio of a display panel originally having an aperture ratio of 25% can be increased to over 40%.

[0068] In some embodiments, in the second direction Y, the spacing between the first gates 104 of adjacent first thin film transistors 103 is greater than or equal to 12.7 microns, and the spacing between the first gates 104 of adjacent first thin film transistors 103 is less than or equal to 20.7 microns, for example, it can be 13.7 microns, 14.7 microns, 15.7 microns, 16.7 microns, 17.7 microns, 18.7 microns, 19.7 microns, etc.

[0069] 1 , in some embodiments, the first active layer 106 includes a first channel portion 109 and a first source contact portion 110 and a first drain contact portion 111 located on either side of the first channel portion 109 in the second direction Y. The first source electrode 107 is connected to the first source contact portion 110, and the first drain electrode 108 is connected to the first drain contact portion 111. The first gate electrode 104 blocks light from the substrate 101, and an orthographic projection of the first channel portion 109 on the first gate electrode 104 is located within the first gate electrode 104.

[0070] Please refer to Figure 3. In some embodiments, in the first direction X, the first gate 104 includes a first side 104a and a second side 104b relative to each other, and the first active layer 106 is located between the first side 104a and the second side 104b. The distance between the first active layer 106 and the first side 104a is greater than 0, and the distance between the first active layer 106 and the second side 104b is greater than 0, so that the first gate 104 completely blocks the light from one side of the substrate 101 from irradiating the first channel portion 109.

[0071] 2 and 3 , in some embodiments, the thin film transistor layer 102 further includes a first via 112, and the first via 112 is located between the first gate 104 and the second gate 105. When the first gates 104 of at least two first thin film transistors 103 are spaced apart in the first direction X, the at least two first vias 112 are respectively located between the first gates 104 and the second gates 105 of the at least two spaced apart first thin film transistors 103, so that the first gates 104 and the second gates 105 of the first thin film transistors 103 in the same row maintain the same potential.

[0072] When the first gates 104 of adjacent first thin film transistors 103 are spaced apart in the first direction X, along the first direction X, the first gate 104 of each first thin film transistor 103 and the second gate 105 of the first thin film transistor 103 are connected within the first via 112, so that the first gate 104 and the second gate 105 of the first thin film transistor 103 in the same row maintain the same potential.

[0073] Referring to FIG. 4 , in some embodiments, a connecting portion 138 is disposed between the first gate electrodes 104 of at least two first thin-film transistors 103 along the first direction X. The connecting portion 138 connects the first gate electrodes 104 of the two first thin-film transistors 103. The orthographic projection of the connecting portion 138 on the substrate 101 is located within the orthographic projection of the second gate electrode 105 on the substrate 101. This reduces light obstruction caused by the connecting portion 138 and facilitates increasing the aperture ratio of a display panel using the array substrate 100. When the orthographic projection of the connecting portion 138 on the substrate 101 is located within the orthographic projection of the second gate electrode 105 on the substrate 101, the width of the connecting portion 138 in the second direction Y is less than or equal to the width of the second gate electrode 105 in the second direction Y.

[0074] By setting the connecting portion 138, the first gates 104 of at least two first thin film transistors 103 in the first direction X are connected, which reduces the number of the first vias 112 and reduces the resistance generated by the connection between the second gate 105 and the first gate 104, thereby reducing the amount of electricity required to maintain the same potential between the first gate 104 and the second gate 105 of the first thin film transistors 103 in the same row, thereby reducing the power consumption of the display panel using the array substrate 100.

[0075] Referring to FIG. 4 , in some embodiments, along the first direction X, the thin-film transistor layer includes at least one first thin-film transistor group 137. Each first thin-film transistor group 137 includes at least two first thin-film transistors 103. The first gates 104 of adjacent first thin-film transistors 103 within each first thin-film transistor group 137 are connected. The first gates 104 of the first thin-film transistors 103 within adjacent first thin-film transistor groups 137 are spaced apart along the first direction X. Connecting portions 138 are provided between the first gates 104 of the first thin-film transistors 103 within each first thin-film transistor group 137 to connect the first gates 104 of the first thin-film transistors 103 within the first thin-film transistor group 137.

[0076] In some embodiments, along the first direction X, one first via hole 112 is disposed between the first gate 104 of one first thin-film transistor 103 and the second gate 105 of the first transistor within one first thin-film transistor group 137, thereby connecting the first gate 104 and the second gate 105 within the first thin-film transistor group 137. That is, one first via hole 112 is disposed corresponding to each first thin-film transistor group 137.

[0077] In some embodiments, along the first direction X, the first gates 104 of adjacent first thin-film transistors 103 are connected via the connecting portion 138. In this case, each row only requires one first via 112 to connect the first gates 104 of the first thin-film transistors 103 in the same row with the second gates 105 of the first thin-film transistors 103. This helps minimize the resistance generated by the connection between the second gates 105 and the first gates 104, reduces the amount of power required to maintain the same potential between the first gates 104 and the second gates 105 of the first thin-film transistors 103 in the same row, and reduces the power consumption of a display panel using the array substrate 100. Furthermore, the orthographic projection of the connecting portion 138 on the substrate 101 is located within the orthographic projection of the second gate 105 on the substrate 101, thereby reducing light obstruction by the connecting portion 138 and facilitating an increase in the aperture ratio of a display panel using the array substrate 100.

[0078] In some embodiments, along the first direction X, the spacing between the first gate electrodes 104 of adjacent first thin film transistor groups 137 is greater than or equal to 1 micron, and the spacing between the first gate electrodes 104 of adjacent first thin film transistor groups 137 is less than or equal to 6.6 microns, for example, 1.5 microns, 2 microns, 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5 microns, 5.5 microns, 6 microns, 6.5 microns, etc., to improve the aperture ratio of a display panel using the array substrate 100. At pixel densities corresponding to different resolutions, the spacing between the first gate electrodes 104 of adjacent first thin film transistor groups 137 in the first direction X varies. By adaptively adjusting the spacing between the first gate electrodes 104 of adjacent first thin film transistor groups 137 in the first direction X within the aforementioned range (for example, the spacing between the first gate electrodes 104 of adjacent first thin film transistors 103 in the first direction X increases as the pixel density increases), the aperture ratio of a display panel using the array substrate 100 can be effectively improved.

[0079] In some embodiments, the connecting portion 138 and the first gate electrodes 104 of the two first thin film transistors 103 connected to the connecting portion 138 are integrally provided, which is beneficial to simplifying the manufacturing process and saving manufacturing costs.

[0080] Referring to FIG. 3 , in some embodiments, the first via 112 is located between the first side 104a of the first gate 104 and the first active layer 106. In the first direction X, the distance between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104 is greater than the distance between the second side 104b and the first active layer 106, thereby facilitating the placement of the first via 112 and the connection between the first gate 104 and the second gate 105. In the first direction X, the distance between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104 is the maximum distance between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104 in the first direction X. In the first direction X, the distance between the second side 104b and the orthographic projection of the first active layer 106 on the first gate 104 is the maximum distance between the second side 104b and the orthographic projection of the first active layer 106 on the first gate 104 in the first direction X.

[0081] Referring to FIG. 1 , in some embodiments, the thin film transistor layer 102 includes a first gate insulating layer 113 and a second gate insulating layer 114. The first gate insulating layer 113 is located between the first gate 104 and the first active layer 106, and the second gate insulating layer 114 is located between the second gate 105 and the first active layer 106. The first via 112 penetrates the first gate insulating layer 113 and the second gate insulating layer 114. The first via 112 exposes the first gate 104. The second gate 105 includes a first extension portion that extends into the first via 112 and contacts the first gate 104, thereby establishing a connection between the first gate 104 and the second gate 105.

[0082] In some embodiments, in the first direction X, the difference between the spacing between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104, and the spacing between the second side 104b and the orthographic projection of the first active layer 106 on the first gate 104, is greater than or equal to 1 micron and less than or equal to 2 microns. For example, it can be 1.2 microns, 1.5 microns, 1.8 microns, etc., to facilitate the connection between the first gate 104 and the second gate 105.

[0083] In some embodiments, the spacing between the second side 104b and the orthographic projection of the first active layer 106 on the first gate 104 is greater than or equal to 0.5 microns, and the spacing between the second side 104b and the orthographic projection of the first active layer 106 on the first gate 104 is less than or equal to 2 microns. For example, it can be 0.6 microns, 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, 1.8 microns, etc., so as to prevent the first channel portion 109 from being exposed to light from one side of the substrate 101, thereby improving the product quality of the array substrate 100.

[0084] In the first direction X, the spacing between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104 is greater than or equal to 1.5 microns, and the spacing between the first side 104a and the orthographic projection of the first active layer 106 on the first gate 104 is less than or equal to 4 microns. For example, it can be 1.6 microns, 1.8 microns, 2 microns, 2.2 microns, 2.5 microns, 2.8 microns, 3 microns, 3.2 microns, 3.5 microns, 3.8 microns, etc., so as to prevent the first channel portion 109 from being exposed to light from one side of the substrate 101 while facilitating the connection between the first gate 104 and the second gate 105.

[0085] In some embodiments, the first gate 104 includes a third side 104c and a fourth side 104d opposite to each other in the second direction Y. The second gate 105 of the first thin-film transistor 103 is located between the third side 104c and the fourth side 104d. That is, the second gate 105 has a first width in the second direction Y, and the first width is smaller than the distance between the third side 104c and the fourth side 104d.

[0086] In some embodiments, in the second direction Y, the distance between the third side 104c and the orthographic projection of the second gate 105 on the first gate 104 is greater than or equal to 0.5 microns, and the distance between the third side 104c and the orthographic projection of the second gate 105 on the first gate 104 is less than or equal to 2 microns, and can be, for example, 0.6 microns, 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, 1.8 microns, etc., to prevent the first channel portion 109 from being illuminated by light from the side of the substrate 101. In the second direction Y, the distance between the third side 104c and the orthographic projection of the second gate 105 on the first gate 104 is the maximum distance between the third side 104c and the orthographic projection of the second gate 105 on the first gate 104.

[0087] In some embodiments, in the second direction Y, the distance between the fourth side 104 d and the orthographic projection of the second gate 105 on the first gate 104 is greater than or equal to 0.5 microns, and the distance between the fourth side 104 d and the orthographic projection of the second gate 105 on the first gate 104 is less than or equal to 2 microns, and can be, for example, 0.6 microns, 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, 1.8 microns, etc., to prevent the first channel portion 109 from being illuminated by light from the side of the substrate 101. In the second direction Y, the distance between the fourth side 104 d and the orthographic projection of the second gate 105 on the first gate 104 is the maximum distance between the fourth side 104 d and the orthographic projection of the second gate 105 on the first gate 104.

[0088] In some embodiments, the first active layer 106 includes a first end and a second end opposite each other in the second direction Y, and the first gate 104 and the second gate 105 are located between the first end and the second end. The first source contact 110 is located at the first end, and the first drain contact 111 is located at the second end.

[0089] In some embodiments, the thin film transistor further includes a second via 115 and a third via 116, the first source 107 is connected to the first source contact 110 of the first active layer 106 through the second via 115, and the first drain 108 is connected to the first drain contact 111 of the first active layer 106 through the third via 116.

[0090] Please refer to Figure 1. In some embodiments, the array substrate 100 also includes a pixel electrode layer 117. The pixel electrode layer 117 is located on the side of the thin film transistor layer 102 away from the substrate 101. The pixel electrode layer 117 includes a pixel electrode 118. One of the first source 107 and the first drain 108 is connected to the pixel electrode 118.

[0091] In some embodiments, the first source electrode 107 and the first drain electrode 108 are disposed in the same layer or in different layers. The materials of the first source electrode 107 and the first drain electrode 108 may be the same or different. When the materials of the first source electrode 107 and the first drain electrode 108 are the same, the first source electrode 107 and the first drain electrode 108 are preferably disposed in the same layer to facilitate formation of the first source electrode 107 and the first drain electrode 108 in the same process. When the materials of the first source electrode 107 and the first drain electrode 108 are different, the first source electrode 107 and the first drain electrode 108 are preferably disposed in different layers to prevent mutual interference in the formation processes of the first source electrode 107 and the first drain electrode 108, thereby improving product yield.

[0092] In some embodiments, the first source electrode 107 is connected to the pixel electrode 118 and is made of a transparent conductive material; alternatively, the first drain electrode 108 is connected to the pixel electrode 118 and is made of a transparent conductive material. By making the first drain electrode 108 or the first source electrode 107 connected to the pixel electrode 118 a transparent conductive material, light blocking by the first source electrode 107 or the first drain electrode 108 in the thickness direction of the array substrate 100 is avoided, thereby further improving the aperture ratio of a display panel using the array substrate 100. The transparent conductive material may be a conductive transparent metal oxide material such as indium tin oxide.

[0093] Referring to FIG. 1 , in some embodiments, the first drain electrode 108 is connected to the pixel electrode 118. The material of the first drain electrode 108 is selected from a transparent conductive material, and the material of the first source electrode 107 is selected from a metal material. The first drain electrode 108 and the first source electrode 107 are disposed in separate layers. The first drain electrode 108 is located on a side of the first source electrode 107 away from the substrate 101. In this case, the thin-film transistor layer 102 further includes a first interlayer insulating layer 119 and a second interlayer insulating layer 120. The first interlayer insulating layer 119 is located between the second gate electrode 105 and the first source electrode 107, and the second interlayer insulating layer 120 is located between the first source electrode 107 and the first drain electrode 108. The second via 115 penetrates the first interlayer insulating layer 119 and the second gate insulating layer 114, and the third via 116 penetrates the second interlayer insulating layer 120, the first interlayer insulating layer 119, and the second gate insulating layer 114. The second via 115 exposes the first source contact 110. The first source electrode 107 includes a second extension portion, which extends into the second via 115 and contacts the first source contact 110, thereby connecting the first source electrode 107 to the active layer. The third via 116 exposes the first drain contact 111. The first drain electrode 108 includes a third extension portion, which extends into the third via 116 and contacts the first drain contact 111, thereby connecting the first drain electrode 108 to the first active layer 106.

[0094] In some embodiments, the first drain 108 further includes a drain connecting sub-portion, the drain connecting sub-portion is located on a side of the second interlayer insulating layer 120 away from the substrate 101 , and the pixel electrode 118 is connected to the drain connecting sub-portion.

[0095] Please refer to Figure 1. In some embodiments, the array substrate 100 also includes a first flat layer 121 located between the pixel electrode layer 117 and the thin film transistor layer 102. The array substrate 100 also includes a fourth via hole 122 passing through the first flat layer 121. The pixel electrode 118 and the drain connecting sub-portion of the first drain 108 are connected in the fourth via hole 122.

[0096] In some embodiments, each of the fourth via holes 122 is correspondingly disposed between one of the first drain electrodes 108 and the pixel electrode 118 .

[0097] Referring to FIG. 5 , in some embodiments, the fourth vias 122 corresponding to the first drain electrodes 108 of a plurality of first thin-film transistors 103 are connected along the first direction X. That is, the fourth vias 122 corresponding to the first drain electrodes 108 of all first thin-film transistors 103 in each row are integrally arranged, which helps simplify the manufacturing process and facilitates the subsequent arrangement of a planarization layer.

[0098] Referring to FIG. 1 , in some embodiments, the array substrate 100 further includes a common electrode layer 123 located on a side of the pixel electrode layer 117 away from the substrate 101. The common electrode layer 123 includes a common electrode 124. The array substrate 100 further includes a passivation layer 125 located between the common electrode layer 123 and the pixel electrode layer 117. The passivation layer 125 is recessed toward the pixel electrode 118 at a position corresponding to the fourth via hole 122 to form a first opening located within the fourth via hole 122.

[0099] In some embodiments, the array substrate 100 further includes a second planarizing layer 126, which is filled within the first opening to provide a planarized common electrode 124, thereby preventing display abnormalities in the display panel caused by unevenness of the common electrode 124. A capacitor is formed between the common electrode 124 and the pixel electrode 118, the magnitude of which is determined by the spacing and facing area between the pixel electrode 118 and the common electrode 124. Both the common electrode 124 and the pixel electrode 118 are made of a transparent conductive material, such as indium tin oxide.

[0100] Please refer to Figure 1. In some embodiments, the common electrode 124 is recessed toward the pixel electrode 118 at a position corresponding to the fourth via hole 122 to form a second opening located within the fourth via hole 122. The second flattening layer 126 is filled in the second opening to flatten the surface of the array substrate 100 away from the substrate 101, so as to avoid display abnormalities of the display panel caused by the uneven surface of the array substrate 100 away from the substrate 101.

[0101] Referring to FIG. 1 , in some embodiments, the fourth via 122 is disposed opposite the second gate 105. Specifically, the orthographic projection of the fourth via 122 on the substrate 101 is located within the orthographic projection of the second gate 105 on the substrate 101, or the orthographic projection of the second gate 105 on the substrate 101 is within the orthographic projection of the fourth via 122 on the substrate 101. The second gate 105 is typically made of a metal material with low resistivity. For example, the second gate 105 may be composed of a stack of materials such as Al / Mo, Al / W, Mo / Al / Mo, W / Al / W, Al / Ti, Ti / Al / Ti, Mo / Cu, or Mo / Ti / Cu. Therefore, the second gate 105 has a low light transmittance and occupies a portion of the opening area. The material difference of different film layers in the fourth via hole 122 also results in a lower transmittance at the fourth via hole 122. The relative arrangement of the second gate 105 and the fourth via hole 122 is beneficial to reducing the occupation of the aperture ratio by the part with lower transmittance, thereby improving the aperture ratio of the display panel using the array substrate 100.

[0102] In some embodiments, the first gate 104 is made of a metal material that is resistant to high temperature, etch-resistant, and has low resistivity. For example, the first gate 104 can be composed of metals or metal stacks such as Mo, W, W / Mo, Al / Mo, Al / W, Mo / Al / Mo, W / Al / W, Al / Ti, and Ti / Al / Ti.

[0103] Referring to FIG. 1 , in some embodiments, the array substrate 100 further includes a non-display area FA located on at least one side of the display area AA, and the thin-film transistor layer 102 further includes a second thin-film transistor 127 located within the non-display area FA. The second thin-film transistor 127 includes a second source electrode 128 and a second drain electrode 129. One of the second source electrode 128 and the second drain electrode 129 of at least one second thin-film transistor 127 is connected to the second gate electrode 105 of at least one first thin-film transistor 103.

[0104] Please refer to Figure 1. In some embodiments, the second source 128 and the second drain 129 of the second thin film transistor 127 are arranged in the same layer as the second gate 105 of the first thin film transistor 103, so that one of the second source 128 and the second drain 129 of at least one second thin film transistor 127 is connected to the second gate 105 of at least one first thin film transistor 103.

[0105] In some embodiments, the array substrate 100 includes a gate drive circuit located in the non-display area FA and a pixel drive circuit located in the display area AA. The gate drive circuit is configured to provide a gate drive signal to the pixel drive circuit. The first thin-film transistor 103 of the pixel drive circuit may be a component of the pixel drive circuit, and the second thin-film transistor 127 may be a component of the gate drive circuit.

[0106] In some embodiments, the non-display area FA includes multiple stages of gate drive circuits, and each stage of the gate drive circuit can be electrically connected to a row of the pixel drive circuits. That is, each stage of the gate drive circuit can be electrically connected to a row of the first thin-film transistors 103. Specifically, one of the second source 128 or the second drain 129 of at least one of the second thin-film transistors 127 in the first stage of the gate drive circuit can be connected to the second gate 105 of the first thin-film transistors 103 in a row to transmit the gate drive signal to the first thin-film transistors 103 in the row.

[0107] Referring to FIG. 1 , in some embodiments, the second thin-film transistor 127 further includes a third gate electrode 130, which is disposed in the same layer as the first gate electrode 104. The second thin-film transistor 127 further includes a second active layer 131, which is located between the substrate 101 and the first gate electrode 104. The second active layer 131 includes a second channel portion 134, a second source contact portion 132 located on opposite sides of the second channel portion 134, and a second drain contact portion 133. The second source electrode 128 is connected to the second source contact portion 132, and the second drain electrode 129 is connected to the second drain contact portion 133. The thin-film transistor layer 102 further includes the fifth and sixth vias. The second source electrode 128 is in contact with the second source contact portion 132 and is connected within the fifth via, while the second drain electrode 129 is in contact with the second drain contact portion 133 and is connected within the sixth via. The thin film transistor layer 102 also includes a third gate insulating layer 135, which is located between the third gate 130 and the second active layer 131. The fifth via hole penetrates the first gate insulating layer 113, the second gate insulating layer 114 and the third gate insulating layer 135, and the sixth via hole penetrates the first gate insulating layer 113, the second gate insulating layer 114 and the third gate insulating layer 135.

[0108] In some embodiments, the first active layer 106 is formed of a metal oxide such as indium gallium zinc oxide, so that the first thin film transistor 103 has advantages such as low leakage current, low refresh rate, convenience in improving aperture ratio, and convenience in achieving high brightness display.

[0109] In some embodiments, the second active layer 131 is formed of polysilicon (eg, low-temperature polysilicon) material, so that the second thin film transistor 127 has advantages such as high mobility and fast response speed.

[0110] In some embodiments, the array substrate 100 further includes a buffer layer 136 located between the substrate 101 and the second active layer 131 , for blocking the invasion of water, oxygen, ions, etc. from one side of the substrate 101 .

[0111] In some embodiments, the substrate 101 may be a rigid substrate 101 or a flexible substrate 101. The constituent material of the rigid substrate 101 may include at least one of glass and quartz, and the constituent material of the flexible substrate 101 may include polymer resin, for example, polyimide.

[0112] The array substrate 100 provided by the embodiment of the present invention arranges at least two first gates 104 in a first direction X at intervals, thereby reducing light blocking by the first gates 104 and increasing the aperture ratio of a display panel using the array substrate 100 .

[0113] Referring to FIG. 6 , an embodiment of the present invention further provides a display panel 10 , comprising any of the above-mentioned array substrates 100 .

[0114] The specific structure of the array substrate 100 can be found in any of the above-mentioned embodiments and drawings of the array substrate, and will not be described in detail here.

[0115] In some embodiments, the display panel 10 further includes a liquid crystal layer 200 located on a side of the array substrate 100 away from the substrate 101 and away from the common electrode layer 123. The liquid crystal layer 200 includes liquid crystals. The pixel electrodes 118 and the common electrodes 124 form a capacitor, providing an electric field to drive the liquid crystals to rotate.

[0116] In some embodiments, the display panel 10 further includes a color filter substrate 300 located on a side of the liquid crystal layer 200 away from the array substrate 100. The color filter substrate 300 may include a color filter layer.

[0117] In some embodiments, the display panel 10 further includes a backlight assembly 400 , which is located on a side of the substrate 101 of the array substrate 100 away from the thin film transistor layer 102 . The backlight assembly 400 is used to provide light for the display panel to display images.

[0118] In some embodiments, the display panel further includes a first polarizer layer 500 and a second polarizer layer 600 , wherein the first polarizer layer 500 is located between the backlight assembly 400 and the array substrate 100 , and the second polarizer layer 600 is located on a side of the color film substrate 300 away from the liquid crystal layer 200 .

[0119] The display panel 10 can be applied to display devices such as mobile phones, tablets, televisions, digital cameras, and can also be applied to display devices in the fields of VR, AR, etc.

[0120] An embodiment of the present invention discloses an array substrate and a display panel; the array substrate has a display area and includes a substrate and a thin film transistor layer located on one side of the substrate, the thin film transistor layer includes a plurality of first thin film transistors arranged along a first direction, the first thin film transistors are located in the display area, and along the first direction, the second gates of adjacent first thin film transistors are connected, and the first gates of at least two first thin film transistors are arranged at intervals. The present invention reduces the blocking of light by the first gates by arranging at least two first gates in the first direction at intervals, thereby increasing the aperture ratio of the display panel using the array substrate.

[0121] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. An array substrate, characterized in that: The array substrate has a display area, and includes: substrate; A thin film transistor layer, located on one side of the substrate, the thin film transistor layer comprising a plurality of first thin film transistors arranged along a first direction, the first thin film transistors being located in the display area; Wherein, the first thin film transistor comprises a first gate and a second gate, and the second gate is located on a side of the first gate away from the substrate; Along the first direction, the second gates of adjacent first thin film transistors are connected, and the first gates of at least two first thin film transistors are arranged at intervals.

2. The array substrate according to claim 1, characterized in that: Along the first direction, the first gate electrodes of adjacent first thin film transistors are spaced apart from each other.

3. The array substrate according to claim 2, characterized in that: An orthographic projection of the second gate on the substrate partially overlaps with an orthographic projection of the first gate on the substrate.

4. The array substrate according to claim 2, characterized in that: Along the first direction, a distance between the first gate electrodes of adjacent first thin film transistors is greater than or equal to 1 micrometer, and a distance between the first gate electrodes of adjacent first thin film transistors is less than or equal to 6.6 micrometers.

5. The array substrate according to claim 2, characterized in that: The thin film transistor layer further includes a first via hole, which is located between the first gate and the second gate. Along the first direction, the first gate of each of the first thin film transistors and the second gate of the first thin film transistor are connected in the first via hole.

6. The array substrate according to claim 5, characterized in that: The first thin film transistor further includes a first active layer, the first active layer is located between the first gate and the second gate, and the first via hole is located at one side of the first active layer in the first direction.

7. The array substrate according to claim 6, characterized in that: In the first direction, the first gate includes a first side and a second side opposite to each other, the first active layer is located between the first side and the second side, and the first via hole is located between the first side and the first active layer; Wherein, in the first direction, a distance between the first side and an orthographic projection of the first active layer on the first gate is greater than a distance between the second side and the first active layer.

8. The array substrate according to claim 7, characterized in that: In the first direction, a distance between the first side and an orthographic projection of the first active layer on the first gate is greater than or equal to 1.5 micrometers, and a distance between the first side and an orthographic projection of the first active layer on the first gate is less than or equal to 4 micrometers; A distance between the second side and an orthographic projection of the first active layer on the first gate is greater than or equal to 0.5 micrometers, and a distance between the second side and an orthographic projection of the first active layer on the first gate is less than or equal to 2 micrometers.

9. The array substrate according to claim 6, characterized in that: The first thin film transistor further includes a first source electrode and a first drain electrode located at two opposite sides of the first active layer in a second direction, and the second direction intersects with the first direction; The first source electrode and the first drain electrode are located on a side of the first active layer away from the substrate, and the first source electrode and the first drain electrode are respectively connected to the first active layer; The array substrate further includes a pixel electrode layer, which is located on a side of the thin film transistor layer away from the substrate. The pixel electrode layer includes a pixel electrode, and one of the first source and the first drain is connected to the pixel electrode.

10. The array substrate according to claim 9, characterized in that: The first source electrode is connected to the pixel electrode, and a material of the first source electrode is selected from a transparent conductive material.

11. The array substrate according to claim 9, characterized in that: The first drain electrode is connected to the pixel electrode, and a material of the first drain electrode is selected from a transparent conductive material.

12. The array substrate according to claim 2, characterized in that: The thin film transistor layer further includes a plurality of the first thin film transistors arranged along a second direction, wherein the first gates of adjacent first thin film transistors are spaced apart from each other, and the second gates of adjacent first thin film transistors are spaced apart from each other along the second direction; Wherein, a distance between the first gate electrodes of the first thin film transistors adjacent to each other in the second direction is greater than a distance between the first gate electrodes of the first thin film transistors adjacent to each other in the first direction.

13. The array substrate according to claim 1, characterized in that: A connecting portion is provided between the first gates of at least two of the first thin film transistors along the first direction, and the connecting portion connects the first gates of the two first thin film transistors; The orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the second gate on the substrate.

14. The array substrate according to claim 13, characterized in that: Along the first direction, the thin film transistor layer includes at least one first thin film transistor group, and each of the first thin film transistor groups includes at least two first thin film transistors; Wherein, along the first direction, the first gates of adjacent first thin film transistors in each first thin film transistor group are connected, and the first gates of the first thin film transistors in adjacent first thin film transistor groups are spaced apart.

15. The array substrate according to claim 14, characterized in that: Each of the first thin film transistor groups is correspondingly provided with a first via hole.

16. The array substrate according to claim 1, characterized in that: The array substrate further comprises a non-display area located at least on one side of the display area, and the thin film transistor layer further comprises a second thin film transistor located in the non-display area; The second thin film transistor includes a second source and a second drain, and one of the second source and the second drain of at least one of the second thin film transistors is connected to the second gate of at least one of the first thin film transistors.

17. A display panel, characterized in that: The invention comprises an array substrate, wherein the array substrate comprises: substrate; A thin film transistor layer, located on one side of the substrate, the thin film transistor layer comprising a plurality of first thin film transistors arranged along a first direction, the first thin film transistors being located in a display area; Wherein, the first thin film transistor comprises a first gate and a second gate, and the second gate is located on a side of the first gate away from the substrate; Along the first direction, the second gates of adjacent first thin film transistors are connected, and the first gates of at least two first thin film transistors are arranged at intervals.

18. The display panel according to claim 17, characterized in that: Along the first direction, the first gate electrodes of adjacent first thin film transistors are spaced apart from each other.

19. The display panel according to claim 18, characterized in that: An orthographic projection of the second gate on the substrate partially overlaps with an orthographic projection of the first gate on the substrate.

20. The display panel according to claim 17, characterized in that: A connecting portion is provided between the first gates of at least two of the first thin film transistors along the first direction, and the connecting portion connects the first gates of the two first thin film transistors; The orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the second gate on the substrate.

Images