Memory array and preparation method therefor, and memory and electronic device

Abstract

The present application relates to the technical field of electronics. Provided are a memory array and a preparation method therefor, and a memory and an electronic device, which are used for simplifying the process of preparing a memory array, improving the degree of integration of the memory array and also improving the performance of the memory array. The memory array comprises at least one stack structure, which comprises a plurality of gate electrode layers, a plurality of semiconductor layers, a second electrode, a gate dielectric layer and an insulating layer. The plurality of gate electrode layers and the plurality of semiconductor layers are alternately arranged in a stacked manner, and each semiconductor layer comprises a floating body and a first electrode which is arranged around the floating body; the second electrode penetrates the gate electrode layers and the floating bodies; the gate dielectric layer is located between any adjacent gate electrode layer and semiconductor layer, and between the gate electrode layers and the second electrode; each adjacent gate electrode layer and semiconductor layer form a film layer pair; and the insulating layer is arranged between two adjacent film layer pairs. The memory array is used for storing data.

Description

Memory array and manufacturing method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 13, 2023, with application number 202311185101.6 and application name “Memory Array and Preparation Method thereof, Memory, Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0003] With the rapid development of artificial intelligence, big data, and big models, people are increasingly valuing the data generated by various activities. This data can be analyzed to obtain desired information. For example, by analyzing users' search, browsing, and purchase data on shopping websites, a profile of a specific user can be created, enabling precise advertising delivery, improving user experience and increasing ad conversion rates. Another example is obtaining information on subway, bus, and shared bike usage in a city to optimize subway and bus route planning, departure time intervals on the same route, and the deployment of shared bikes. Clearly, to achieve effective results, relying solely on algorithmic innovations in artificial intelligence, big data, and big models is far from enough. It also requires the provision of massive amounts of data and the analysis of this data. When analyzing this data, it is necessary to store it in computer memory or cache to increase processing speed.

[0004] Based on volatility, memory is categorized as either volatile or non-volatile. Volatile memory is typically used as internal memory or cache, while non-volatile memory is typically used as external storage. Volatile memory is a type of memory whose stored information disappears when the current or voltage is interrupted, whereas non-volatile memory does not. Dynamic Random Access Memory (DRAM) is a common type of volatile memory, widely used as computer memory.

[0005] In some technologies, 1T1C (1 transistor 1 capacitor) DRAM is used. Each bit of data in this DRAM is stored by charging and discharging a capacitor. Because each bit of data requires a capacitor, the manufacturing process for 1T1C DRAM is complex. Furthermore, as data volume increases, the demand for higher integration becomes increasingly demanding. The capacitors in this DRAM also limit further size reduction, making it difficult to further increase integration.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a memory array and a method for manufacturing the same, a memory, and an electronic device, which are used to simplify the manufacturing process of the memory array, increase the integration of the memory array, and improve the performance of the memory array.

[0008] To achieve the above objectives, this embodiment adopts the following technical solutions:

[0009] In a first aspect, a memory array is provided, comprising at least one stack structure, the stack structure comprising multiple gate layers, multiple semiconductor layers, a second electrode, a gate dielectric layer, and an insulating layer. The multiple gate layers and multiple semiconductor layers are alternately stacked, the semiconductor layer comprising a floating body and a first electrode surrounding the floating body; the second electrode penetrates the gate layer and the floating body; the gate dielectric layer is located between any adjacent gate layer and semiconductor layer, and between the gate layer and the second electrode; each adjacent gate layer and semiconductor layer form a film layer pair, and the insulating layer is located between two adjacent film layer pairs.

[0010] In the memory array provided by the embodiment of the present application, the semiconductor layer includes a floating body and a first electrode arranged around the floating body, and the second electrode penetrates the gate layer and the floating body, so that the gate layer, the floating body, the first electrode and the second electrode form a transistor, the first electrode serves as the source of the transistor, the second electrode serves as the drain of the transistor, or the first electrode serves as the drain of the transistor, and the second electrode serves as the source of the transistor. The transistor can be used to store data, that is, one transistor serves as a memory cell. Multiple gate layers and multiple semiconductor layers are stacked, so that the memory array includes multiple memory cells along the stacking direction. Each memory cell in the memory array uses the floating body of the transistor to store charge, thereby realizing data storage, eliminating the capacitor, so the preparation process is simple, and the size of the memory cell is reduced, which is conducive to 3D stacking and the integration of the memory array is improved.

[0011] By setting an insulating layer between two adjacent film layer pairs (a film layer pair includes an adjacent gate layer and a semiconductor layer), which is equivalent to setting an insulating layer between two adjacent memory cells in a memory array, it is possible to prevent the electric field generated by the gate layer of one memory cell from affecting the floating body storing data in the adjacent memory cell when reading and writing data. This electric field will affect the amount of charge in the floating body of the adjacent memory cell, and this amount of charge is used to characterize whether the stored data is "1" or "0". By setting an insulating layer to avoid affecting the amount of charge in the floating body in the adjacent memory cell, the accuracy of the data stored in the memory cell can be improved, and the time the charge in the floating body is maintained can be extended, thereby improving data retention capabilities, reducing the refresh frequency of the memory, and reducing energy consumption.

[0012] In one possible implementation of the first aspect, the gate layer in the film layer pair is further away from the lower surface of the memory array than the semiconductor layer. Based on this, the insulating layer is disposed on a side of the semiconductor layer closer to the lower surface of the memory array. Alternatively, the semiconductor layer in the film layer pair is further away from the lower surface of the memory array than the gate layer. Based on this, the insulating layer is disposed on a side of the semiconductor layer further away from the lower surface of the memory array.

[0013] In a possible implementation of the first aspect, an insulating layer is provided between any two adjacent film layer pairs, so that any two adjacent memory cells in the memory array along the stacking direction are isolated by the insulating layer, thereby greatly reducing the mutual influence between adjacent memory cells.

[0014] In a possible implementation of the first aspect, the insulating layer contacts the semiconductor layer. Thus, when preparing the memory array, the insulating layer and the semiconductor layer are stacked to achieve the purpose of inserting the insulating layer into the stack structure of the memory array.

[0015] In one possible implementation of the first aspect, the insulating layer at least overlaps the floating body in a direction perpendicular to the lower surface of the memory array, thereby ensuring that the insulating layer provides sufficient shielding for the floating body of the memory cell and shields the electric field affecting the floating body.

[0016] In a possible implementation of the first aspect, the distance from the gate layer to the second electrode is greater than the distance from the gate layer to the floating body, thereby reducing the influence between the gate layer and the second electrode and improving the reading and writing efficiency of the storage unit data.

[0017] In one possible implementation of the first aspect, the present invention further includes: a first spacer disposed between the second electrode and the gate layer. In this implementation, the first spacer ensures that the distance between the second electrode and the gate is greater than the distance between the gate layer and the floating body, thereby reducing the mutual influence between the gate layer and the second electrode.

[0018] In one possible implementation of the first aspect, the first spacer is made of the same material as the gate dielectric layer and is integrally provided with the gate dielectric layer. In this embodiment, the first spacer and the gate dielectric layer can be made of the same material and integrally provided, which can optimize stress within the memory array and improve the reliability of the memory array.

[0019] In one possible implementation of the first aspect, the distance between the gate layer and the second electrode is smaller than the distance between the first electrode and the second electrode. This reduces the overlap area between the gate layer and the first electrode, minimizing the mutual influence between the gate layer and the first electrode.

[0020] In one possible implementation of the first aspect, the stack structure further includes a second spacer disposed around the gate layer, and overlapping at least a portion of the first electrode along a direction perpendicular to the lower surface of the memory array. Thus, the second spacer is provided to reduce the overlapping area between the gate layer and the first electrode to a certain extent.

[0021] In one possible implementation of the first aspect, there are multiple stacked structures, each spaced apart from the other on the first surface. The memory array further includes an isolation structure disposed between two adjacent stacked structures. The isolation structure and the second spacer are made of the same material and are integrally provided. Thus, by integrally providing the second spacer with the isolation structure, the second spacer can be formed simultaneously with the isolation structure, thereby reducing process steps and improving production efficiency.

[0022] In a possible implementation of the first aspect, the insulating layer is SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, thereby providing multiple possible solutions for selecting the material of the insulating layer.

[0023] In a second aspect, the present application provides a memory comprising any memory array according to the first aspect and a controller, wherein the memory array is electrically connected to the controller.

[0024] The memory provided in this embodiment improves the storage performance of the memory and reduces energy consumption by adopting the memory array in the above technical solution.

[0025] In a third aspect, the present application provides an electronic device comprising the memory of the second aspect and a printed circuit board, wherein the memory is electrically connected to the printed circuit board.

[0026] The electronic device provided in this embodiment improves data storage accuracy and reduces device energy consumption by adopting the memory in the second aspect.

[0027] In a fourth aspect, a method for fabricating a memory array includes: forming a stacked structure and a second electrode, the stacked structure comprising a plurality of sacrificial layers, a plurality of semiconductor layers, and a plurality of insulating layers stacked in sequence, the semiconductor layers comprising a floating body and a first electrode surrounding the floating body, the second electrode penetrating the plurality of sacrificial layers, the floating bodies of the plurality of semiconductor layers, and the plurality of insulating layers; cutting the stacked structure along a stacking direction to form a plurality of sub-stacked structures, with isolation trenches between adjacent sub-stacked structures; removing the plurality of sacrificial layers through the isolation trenches to form a first gap, and sequentially forming a gate dielectric layer and a gate layer within the first gap. Thus, the plurality of sub-stacked structures form a plurality of stacked structures.

[0028] The memory array preparation method provided in this embodiment includes an insulating layer in the formed stacked structure to prevent the gate layer in the finally formed stacked structure memory cell from affecting the floating body of the adjacent memory cell, thereby improving data storage accuracy.

[0029] In one possible implementation of the fourth aspect, forming the second electrode includes: forming a through hole penetrating the stacked structure, forming the second electrode within the through hole; and after forming the through hole and before forming the second electrode, further including: removing a portion of the sacrificial layer and forming a first spacer at the location of the removed portion of the sacrificial layer. Based on this, the material of the first spacer can be the same as that of the gate dielectric layer, thereby optimizing stress in the stacked structure and improving stability of the memory array.

[0030] In one possible implementation of the fourth aspect, after forming the gate layer, the method further includes removing a portion of the gate layer via the isolation trench, and forming a second spacer at the location of the removed portion of the gate layer. This reduces the interaction between the gate layer and the first electrode, thereby improving the read and write capabilities of the memory array.

[0031] In a possible implementation of the fourth aspect, in the step of forming the second spacer, an isolation structure is formed in the isolation trench. In this implementation, the second spacer and the isolation structure can be formed simultaneously, saving process steps and improving manufacturing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1a is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0033] FIG1b is a schematic diagram of a memory provided by an embodiment of the present application;

[0034] FIG2 is a circuit diagram of a memory cell in a 1T1C static random access memory;

[0035] FIG3 is a circuit diagram of a memory cell in a 1TOC static random access memory;

[0036] FIG4 is a schematic diagram of a static random access memory cell with an NMOS structure floating body effect when writing “1”;

[0037] FIG5 is a schematic diagram of a static random access memory cell with an NMOS structure floating body effect when writing “0”;

[0038] FIG6 is a schematic structural diagram of a memory cell utilizing a floating body effect;

[0039] FIG7 is a schematic structural diagram of a memory array formed by stacking memory cells in FIG6 ;

[0040] FIG8 is a schematic circuit diagram of the stack unit in FIG7 ;

[0041] FIG9a is a schematic structural diagram of a memory array provided in an embodiment of the present application;

[0042] FIG9 b is a schematic structural diagram of another memory array provided in an embodiment of the present application;

[0043] FIG10 is a circuit diagram of a stack unit of a memory array provided in an embodiment of the present application;

[0044] FIG11 is a schematic structural diagram of another memory array provided in an embodiment of the present application;

[0045] FIG12 is a schematic structural diagram of another memory array provided in an embodiment of the present application;

[0046] FIG13 is a schematic structural diagram of another memory array provided in an embodiment of the present application;

[0047] FIG14 is a schematic diagram of the structure of another memory array provided in an embodiment of the present application;

[0048] FIG15 is a process flow chart of manufacturing a memory array according to an embodiment of the present application;

[0049] 16-25 are schematic diagrams of the structures in each step of preparing a memory array according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0051] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0052] The present application provides an electronic device, which is a type of electronic device with a data storage function, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, a vehicle-mounted device, etc.

[0053] Please refer to Figure 1a, which is a schematic diagram of an electronic device 10 provided in an embodiment of the present application. The electronic device 10 can be a terminal device. The electronic device 10 includes a printed circuit board (PCB) 100a, a bus 150 printed on the printed circuit board 100a, and a system on chip (SoC) 110 connected to the bus 150. The system on chip 110 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system on chip 110 may include an application processor (AP) 111 for processing applications, a graphics processing unit (GPU) 112 for processing image data, and a first memory 113 for caching high-speed data. The first memory 113 can be a static random access memory (SRAM) or an embedded flash memory (EFlash). The above-mentioned application processor 111, image processing unit 112 and first memory 113 can be integrated into a die, or they can be set separately in multiple dies. The electronic device 10 may further include a second memory 120, which is also disposed on the printed circuit board and electrically connected to the printed circuit board. Specifically, the second memory 120 is connected to the system-on-chip 110 via a bus 150. The second memory 120 may be a dynamic random access memory (DRAM). The second memory 120 may be used to store volatile data, such as temporary data generated by the system-on-chip 110. The storage capacity of the second memory 120 is generally greater than that of the first memory 113. In addition, the electronic device 10 may further include a communication chip 130 and a power management chip 140 connected to the system-on-chip 110 via the bus 150. The communication chip 130 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 140 may be used to power other chips. In one embodiment, the system-on-chip 110 and the second memory 120 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster data transmission rate between chips.

[0054] In addition, embodiments of the present application further provide a memory, which can be used as a second memory 120, for example. As shown in FIG1b , the memory 160 may include multiple memory arrays 3 (only one is shown) and a controller 161, wherein the multiple memory arrays 3 and the controller 161 are electrically connected via a printed circuit board 100b. In some embodiments, a memory 160 may include only one memory array 3. The controller 161 is used to control access to the memory array 3. Each memory array 3 may also include multiple stack structures 30, each stack structure 30 including multiple memory cells, each memory cell being used to store data information.

[0055] Figure 2 shows a circuit diagram of a memory cell in a 1T1C static random access memory (SRAM). The memory cell comprises a transistor Tr and a capacitor Cap. The charge stored in capacitor Cap represents data "0" or "1." The gate of transistor Tr is electrically connected to word line WL, the source is electrically connected to bit line BL, and the drain is electrically connected to capacitor Cap. The memory cell controls the on / off state of transistor Tr using the gate voltage. When word line WL inputs a high level (i.e., the gate is high, such as 5V), the transistor is on. At this time, the bit line BL inputs a high level (i.e., the source is connected to a high level), charging capacitor Cap. For example, the charged capacitor Cap stores charge, representing data "1." If the bit line BL inputs a low level (i.e., the source is connected to a low level), the charge stored in capacitor Cap flows out, and the absence of charge in capacitor Cap represents data "0." Each time data is read from bit line BL, transistor Tr is also turned on. If there is charge in capacitor Cap at this time, the charge will be lost. Therefore, after reading data, it must be written again. Each storage unit of the static random access memory has a capacitor Cap, which is not conducive to improving the integration of the static random access memory.

[0056] Therefore, another type of dynamic random access memory (DRAM) has been proposed: 1T0C (1 transistor 0 capacitor) DRAM. This memory utilizes the floating body effect (FBE) for data storage. By eliminating the capacitor structure, this type of memory can improve integration and data storage density. However, this type of memory also has its drawbacks and requires further optimization.

[0057] Figure 3 shows a circuit diagram of a memory cell in a 1TOC static random access memory (SRAM). This memory consists of a single transistor, Tr, with its gate electrically connected to a word line, WL, its source connected to a bit line, BL, and its drain connected to a source line, SL. This memory uses the floating body effect (FBE) to store data "0" and "1."

[0058] The following is an explanation using an NMOS structure floating body effect static random access memory as an example.

[0059] As shown in Figure 4, it is a schematic diagram of the state of writing "1" in a static random access memory cell with an NMOS structure floating body effect. The memory cell includes a transistor, which is arranged on an oxygen buried layer, including a gate 201, a first electrode 202 and a second electrode 203, a floating body 204 is arranged between the first electrode 202 and the second electrode 203, and a gate dielectric layer 205 is arranged between the floating body 204 and the gate 201. In some embodiments, the first electrode 202 is the source and the second electrode 203 is the drain. The gate 201 is electrically connected to the word line WL, the source is electrically connected to the source line SL, and the drain is connected to the bit line BL. With the source as the reference voltage, the source can be grounded, and a positive bias is applied to the gate 201 and the drain, and the transistor is turned on. In small-sized devices, a small source-drain voltage can form a very high lateral electric field near the drain end of the floating body 204. Due to the effect of this transverse electric field, channel electrons in the strong field region at the drain end of the floating body 204 acquire a large drift velocity and energy, becoming hot carriers. Some of these hot carriers collide with silicon atoms near the drain and ionize, generating electron-hole pairs 207. Some holes 208 are swept into the substrate (not shown) by the longitudinal electric field directed from the gate 201 to the substrate, forming substrate current. Due to the presence of the buried oxygen layer 206, the substrate current cannot be released, causing the holes 208 to accumulate in the floating body 204, reducing the threshold voltage Vth of the transistor, which is defined as the first storage state, for example, it can be defined as writing "1".

[0060] Figure 5 shows a schematic diagram of the "0" state of a floating-body SRAM cell in an NMOS structure. With the source as the reference voltage, a positive bias is applied to gate 201 and a negative bias is applied to the drain. This forward biases the PN junction, and holes 208 are emitted from floating body 204, creating the second storage state, for example, a "0" state.

[0061] Since the accumulation of substrate holes 208 changes the threshold voltage (Vth) of the device, the current of the transistor can be read to sense the difference in threshold voltage caused by the two states, that is, the data stored in the memory cell can be judged as "1" or "0" based on the level of the current.

[0062] Please refer to Figure 6, which is a schematic diagram of the structure of a memory cell utilizing the floating body effect. The memory cell 200 includes a gate 201, a first electrode 202, a second electrode 203, and a gate dielectric layer 205, wherein a floating body 204 is arranged around the second electrode 203, and the first electrode 202 is arranged around the floating body 204. The gate 201 is arranged directly below the first electrode 202 and the floating body 204. A through hole is provided in the middle of the gate 201, and a portion of the second electrode 203 is provided in the through hole. The gate dielectric layer 205 is provided between the first electrode 202, the second electrode 203, the floating body 204, and the gate 201, separating the first electrode 202, the second electrode 203, the floating body 204, and the gate 201.

[0063] Please refer to Figure 7, which is a schematic diagram of the structure of a memory array formed by stacking the memory cells 200 shown in Figure 6. For ease of description, a rectangular coordinate system is established as shown in Figure 7. The memory array 20 includes a plurality of memory cells 200, which are stacked in the Z-axis direction. Referring to Figures 7 and 8, the second electrodes 203 of the memory cells 200 serve as bit lines BL, the first electrodes 202 of the memory cells 200 serve as source lines SL (e.g., SL0-SL4 in Figure 8), and the gates 201 of the memory cells 200 serve as word lines WL (e.g., WL0-WL3).

[0064] FIG8 is a circuit diagram of the memory array shown in FIG7 . In conjunction with FIG7 and FIG8 , the gate 201 of memory cell 200, the first electrode 202, and the floating body 204 of the adjacent memory cell below it essentially form a transistor structure. Therefore, when reading or writing to the target memory cell 200, the adjacent memory cells below the target memory cell 200 are affected. For example, the memory array includes memory cells 200a through 200e, wherein memory cells 200b and 200c share a common word line WL1, i.e., a common gate 201. During a read or write operation on memory cell 200b, corresponding signals are provided to BL, WL1, and SL1 to select memory cell 200b. At this time, the gate 201 (i.e., WL1) of memory cell 200b also affects memory cell 200c. That is, the signal input to WL1 affects the charge of the floating body of memory cell 200c, thereby affecting the data stored in memory cell 200c.

[0065] Thus, when a read or write operation is performed on a memory cell 200, the storage state of the adjacent memory cell 200 is affected. This effect may cause errors in the data stored in the memory cell 200, or require an increase in the refresh frequency of the memory to ensure the accuracy of the stored data. Obviously, increasing the refresh frequency will increase power consumption.

[0066] In order to improve or avoid the impact on adjacent memory cells when performing read and write operations on one memory cell, the present application proposes a memory array, which is applied to the memory and electronic device proposed in the embodiments of the present application.

[0067] Figure 9a shows a memory array 3 provided in an embodiment of the present application. For ease of description, a rectangular coordinate system is established, where the lower surface of the memory array 3 is located on or parallel to the XY plane. As will be readily understood, in some embodiments, the memory array is formed on the surface of a substrate (not shown), and the lower surface of the memory array 3 refers to the substrate surface.

[0068] The memory array 3 includes a stack structure 30. The memory array 3 may include one or more stack structures 30. Figure 9a shows only one stack structure 30. A stack structure 30 may include multiple stack units s. The multiple stack units s are arranged along the Y-axis. Each stack unit s includes multiple memory cells 300. The multiple memory cells 300 are stacked along the Z-axis. Each memory cell 300 utilizes the floating body effect for data storage.

[0069] The stack structure 30 includes a gate layer 301, a semiconductor layer 324, a second electrode 303, a gate dielectric layer 305, and an insulating layer 306. In some embodiments, a layer here can be understood as a thin film that extends at least partially in the XY plane and has a certain size in the Z direction. The size of this portion in the Z direction is not necessarily completely equal, that is, the thickness of this portion is not necessarily uniform, and any surface of the layer is not limited to being a plane.

[0070] Semiconductor layer 324 includes a first electrode 302 and a floating body 304. Semiconductor layer 324 extends in the XY plane, and the orthographic projection of the floating body 304 on the XY plane is within a region enclosed by at least a portion of the orthographic projection of the first electrode 302 on the XY plane. It should be emphasized that this enclosed region does not belong to the orthographic projection of the first electrode 302 on the XY plane. That is, the first electrode 302 is disposed around the floating body 304 and is in contact with the floating body 304. In other words, the first electrode 302 is disposed around the floating body 304.

[0071] The gate layers 301 and semiconductor layers 324 are stacked alternately, i.e., a semiconductor layer 324 is disposed between any two adjacent gate layers 301, and a gate layer 301 is disposed between any two adjacent semiconductor layers 324. The gate layers 301 and semiconductor layers 324 do not contact each other. The gate layer 301 serves as the gate of the memory cell 300 and is made of a conductive material, such as a metal such as copper (Cu), aluminum (Al), or gold (Ag); an alloy such as nickel-manganese alloy, nickel-chromium alloy, or nickel-molybdenum-iron alloy; or a heavily doped semiconductor material. The semiconductor layer 324 is made of a semiconductor material such as silicon, polysilicon, silicon-germanium, or a III-V compound.

[0072] A gate dielectric layer 305 is disposed between the gate layer 301 and the semiconductor layer 324 to electrically insulate the gate layer 301 from the floating body 304 of the semiconductor layer 324. Therefore, the gate dielectric layer 305 is an insulating material. Exemplarily, the gate dielectric layer 305 may be made of silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), or any combination thereof. In some embodiments, the gate dielectric layer 305 completely overlaps the semiconductor layer 324, meaning that the gate dielectric layer 305 is disposed not only between the gate layer 301 and the floating body 304 of the semiconductor layer 324, but also between the gate layer 301 and the first electrode 302 of the semiconductor layer 324. In other embodiments, the gate dielectric layer 305 is disposed only between the floating body 304 of the semiconductor layer 324 and the gate layer 301, separating the floating body 304 from the gate layer 301. In a specific embodiment, the gate dielectric layer 305 may be further disposed between the gate layer 301 and the second electrode 303 to separate the gate layer 301 from the second electrode 303 .

[0073] The insulating layer 306 can be made of the same material as the gate dielectric layer, i.e., silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), or any combination thereof. In some embodiments, the insulating layer 306 can be made of a material with a strong electric field blocking capability. This allows the same effect to be achieved while reducing the size of the insulating layer 306 in the Z direction.

[0074] In some embodiments, in the Z direction, the size of the insulating layer 306 is larger than the size of the gate dielectric layer 324 . For example, the size of the insulating layer 306 is 1, 2, or 5 times the size of the gate dielectric layer 324 .

[0075] In some embodiments, the second pole 303 extends along the Z direction and penetrates the gate layer 301 and the floating body 304, that is, there is a through hole in the middle of the gate layer 301 and the floating body 304, and the second pole 303 passes through the through hole. In addition, the second pole 303 is also in contact with the floating body 304. Since the first pole 302 surrounds the floating body 304, the second pole 303 also passes through the first pole 302, that is, the second pole 303 is arranged on the inner side of the floating body 304, and the first pole 302 is arranged on the outer side of the floating body 304. In some embodiments, the second pole 303 penetrates the entire stack structure 30 along the Y-axis direction. The second pole 303 can be cylindrical, rectangular, or other shapes, which is not limited in this application.

[0076] Each memory cell 300 includes a gate layer 301 and a semiconductor layer 324. The gate layer 301 and the semiconductor layer 324 form a film layer pair 310. An insulating layer 306 is disposed between two adjacent film layer pairs 310. In some embodiments, an insulating layer 306 is disposed between any two adjacent film layer pairs 310 to minimize the effect of the gate of a memory cell 300 on the floating body 304 of an adjacent memory cell 300, thereby improving data storage accuracy and reducing refresh frequency.

[0077] In other embodiments, the insulating layer 306 is disposed only between some of the film layer pairs 310. Because the insulating layer 306 occupies a certain volume, or has a certain dimension in the Z direction, the number of memory cells 300 that can be stacked in the Z direction is limited in a memory array of the same size. Furthermore, the data retention capabilities of the memory cells 300 in the entire stack structure 30 or memory array 3 may not be uniform. Therefore, in this case, two adjacent film layer pairs 310 without an insulating layer 306 between them can be disposed in areas with good data retention, while two adjacent film layer pairs 310 with an insulating layer 306 between them can be disposed in areas with poor data retention. This ensures consistent data retention for the memory cells 300 in the entire stack structure 30 or memory array 3, avoids increasing the refresh frequency to maintain data accuracy in memory cells 300 with low retention, and reduces chip energy consumption.

[0078] For similar reasons, in some embodiments, the thickness of the insulating layer 306 is inconsistent. Adjusting the thickness of the insulating layer 306 can adjust the degree of influence of the insulating layer 306 on the data retention of adjacent memory cells 300. Therefore, by adjusting the thickness of the insulating layer 306, the data retention capabilities of the memory cells of the stack structure 30 or the entire memory array 3 can be made consistent, thereby selecting the optimal data refresh frequency and reducing the energy consumption of the memory.

[0079] In some embodiments, the insulating layer 306 can be disposed in contact with the semiconductor layer 324. This allows the insulating layer 306 and the semiconductor layer 324 to be deposited sequentially during the initial deposition of various film layers, avoiding the need for additional specific steps in subsequent processes to insert the insulating layer 306. Therefore, disposing the insulating layer 306 in contact with the semiconductor layer 324 can simplify the process flow.

[0080] In some embodiments, the relative positions of the semiconductor layer 324 and the gate layer 301 in the film layer pair 310 within each memory cell 300 are consistent. For example, with reference to the bottom surface of the memory array, the semiconductor layer 324 in each film layer pair 310 is stacked above the gate layer 301. Because the memory cells 300 are stacked, the insulating layer 306 of one memory cell 300 is positioned adjacent to the gate layer 301 of another memory cell 300. To prevent the influence of the gate layer 301, the insulating layer 306 should cover the floating body 304 in its orthographic projection on the XY plane. That is, the insulating layer 306 should at least overlap the floating body 304 along the Z direction. As will be readily understood, in other embodiments, regardless of the arrangement of the film layer pairs within each memory cell 300, as long as the insulating layer 306 at least overlaps the floating body 304 along the Z direction, the insulating layer 306 can, to a certain extent, protect the floating body 304 from the influence of the gate layer 301 in the adjacent memory cell 300.

[0081] In some embodiments, in the Z direction, the insulating layer 306 not only completely overlaps the floating body 304, but also may overlap the first electrode 302. Alternatively, the insulating layer 306 and the first electrode 302 may also completely overlap. In this way, the semiconductor layer 324 and the insulating layer 306 can be directly stacked and deposited, saving process steps. In other embodiments, in the Z direction, the insulating layer 306 only overlaps the floating body 304, that is, the first electrode 302 does not overlap the insulating layer 306.

[0082] In an embodiment of the present application, the first electrode 302 can serve as the source of the memory cell 300, and the second electrode 303 can serve as the drain of the memory cell 300. The first electrode 302 and the second electrode 303 are N-type doped semiconductors, and the floating body 304 is a P-type doped semiconductor, thereby forming an NPN transistor with a floating body effect to achieve data storage. In other embodiments, the first electrode 302 can serve as the drain of the memory cell 300, and the second electrode 303 can serve as the source of the memory cell 300.

[0083] FIG10 is a circuit diagram of a stacked cell s in a memory array. Referring to FIG9a through FIG10 , the first electrode 302 is electrically connected to the source line SL, the second electrode 303 is electrically connected to the bit line BL, and the gate layer 301 is connected to the word line WL. In this stacked cell s, an insulating layer 306 is provided between any adjacent pairs of film layers 324. In other words, an insulating layer 306 is provided between any adjacent memory cells 300. Due to the presence of insulating layer 306, adjacent memory cells 300 do not share a common gate layer 301. For example, transistor cell0 (i.e., one memory cell) is independently controlled by word line WL0, and transistor cell1 (i.e., another memory cell) is independently controlled by word line WL1. This prevents read and write operations on one memory cell 300 from affecting another adjacent memory cell 300.

[0084] For example, when performing a write "1" operation, with the second electrode 303 as the reference level, a high level is input to the gate layer 301 and the first electrode 302, thereby generating a transverse electric field between the first electrode 302 and the second electrode 303. Due to the effect of this transverse electric field, in the strong field region near one end of the floating body 304 of the second electrode 303, the channel electrons obtain a large drift velocity and energy, becoming hot carriers. Some of these hot carriers collide with silicon atoms near the second electrode 303 and ionize, generating electron-hole pairs. Some of the holes are pushed by the longitudinal electric field away from the gate layer 301 to the side of the floating body 304 away from the gate layer 301, forming a current. Since there is no conductive loop on the other side, this current cannot be released, causing the holes to accumulate in the floating body 304, thereby reducing the threshold voltage Vth of the transistor.

[0085] Furthermore, due to the provision of the insulating layer 306, the longitudinal electric field generated by the gate layer 301 will not affect the holes in the other floating body, that is, it will not affect the data stored in the other storage unit 300. When performing a write "0" operation, the second pole 303 is used as the reference level, the gate layer 301 inputs a high level, and the first pole 302 inputs a level lower than the second pole 303. Since the gate layer 301 inputs a high level, the transistor is turned on, and the level of the second pole 303 lower than the second pole 303 absorbs the holes, so that there are no holes in the floating body 304, so that the threshold voltage Vth of the transistor returns to normal. Due to the provision of the insulating layer 306, the gate layer 301 will not turn on the transistor of another adjacent storage unit 300, thereby avoiding affecting its storage state.

[0086] The film layers in the memory array 3 are formed on a substrate. Different material layers are deposited on the substrate, and the stresses between the different material layers and the substrate vary. The magnitude of these stresses can affect the film quality, and thus the reliability and stability of the memory array 3. Therefore, in some embodiments, the film layer in the film layer pair 310 that experiences the lowest stress after being deposited on the substrate surface can be positioned closer to the bottom surface of the memory array 3. For example, when the bonding stress between the semiconductor layer 324 and the substrate is relatively low, as shown in FIG9a , in the film layer pair 310, the semiconductor layer 324 is positioned below the gate layer 301. That is, the gate layer 301 in the film layer pair 310 is further away from the bottom surface of the stack structure 30, or the bottom surface of the memory array 3, than the semiconductor layer 324. In this case, the insulating layer 306 closest to the semiconductor layer 324 is located on the side of the semiconductor layer 324 that is closest to the bottom surface of the stack structure 30. In this case, the film layer of the stack structure 30 that is closest to the substrate is the semiconductor layer 324. For another example, when the bonding stress between the gate layer 301 and the substrate is relatively low, as shown in FIG9 b , in the film layer pair 310, the gate layer 301 is located below the semiconductor layer 324. That is, the semiconductor layer 324 in the film layer pair 310 is further away from the lower surface of the stack structure 30 than the gate layer 301. In this case, the insulating layer 306 closest to the semiconductor layer 324 is located on the side of the semiconductor layer 324 that is further away from the lower surface of the stack structure 30. It is easy to understand that regardless of how the semiconductor layer 324 and the gate layer 301 are arranged, the insulating layer 306 is disposed between adjacent film layer pairs 310, and this embodiment does not impose any limitation on this.

[0087] In the same storage cell 300, the gate layer 301 generates an electric field after being electrically connected to a high level. This electric field will affect the floating body effect generated in the floating body 304. The stronger the electric field, the more significant the floating body effect, and the higher the accuracy of the stored data. At the same time, the electric field generated by the gate layer 301 will also affect the second pole 303. Therefore, as shown in Figure 11, in some embodiments, the distance d2 from the gate layer 301 to the second pole 303 is greater than the distance d1 to the floating body 304. In some specific embodiments, the distance between the gate layer 301 and the second pole 303 can be increased by providing a first spacer 411 between the gate layer 301 and the second pole 303. By providing the first spacer 411, the distance between the gate layer 301 and the second pole 303 can be increased, so that when the gate layer 301 is connected to a high level to generate an electric field, the influence of the electric field on the second pole 303 can be reduced, thereby improving the data reading and writing speed and accuracy.

[0088] For example, as shown in FIG11 , the first spacer 411 may be disposed on a side of the gate dielectric layer 305 close to the second electrode 303 and may be disposed in contact with the second electrode 303, that is, the first spacer 411 is disposed around the second electrode 303. In this case, the dimension of the first spacer 411 in the Z direction may be greater than or equal to the dimension of the gate layer 301 in the Z direction.

[0089] 12 , the first spacer 411 may also be disposed on a side of the gate dielectric layer 305 close to the gate layer 301 and may be in contact with the gate layer 301. In this case, the size of the first spacer 411 in the Z direction may be smaller than or equal to the size of the gate layer 301.

[0090] The first spacer 411 can be made of the same material as the gate dielectric layer 305 and be disposed in contact with the gate dielectric layer 305. This means that the first spacer 411 and the gate dielectric layer 305 are integrally formed. This "integrated" design means that the first spacer 411 and the gate dielectric layer 305 are structurally connected, but they are not required to be formed using the same or identical process. The first spacer 411 can also be made of a material with superior electric field blocking properties to the gate dielectric layer 305, thereby minimizing the impact of the electric field generated by the gate layer 301 and achieving a better effect.

[0091] The electric field generated by gate layer 301 when it is connected to a high level not only affects second electrode 303 but also first electrode 302. For the same reason, referring again to FIG12 , to reduce the impact of the electric field generated by gate layer 301 on first electrode 302, the distance d3 between the boundary of gate layer 301 away from second electrode 303 and second electrode 303 can be made smaller than the distance d4 between the boundary of first electrode 302 away from second electrode 303 and second electrode 303. As shown in FIG12 , a second spacer 412 can optionally be provided on the side of gate layer 301 away from second electrode 303. The second spacer 412 can be provided in contact with gate layer 301, i.e., the second spacer 412 can be provided around gate layer 301.

[0092] The size of the second spacer in the Z direction may be equal to the size of the gate layer 301 in the Z direction.

[0093] The second spacer 412 can be made of a material with better electric field blocking performance than the gate dielectric layer 305, thereby ensuring that the influence of the electric field generated by the gate layer 301 is reduced to a greater extent and achieving better results. In other embodiments, the second spacer 412 can be made of the same material as the gate dielectric layer 305.

[0094] It is easy to understand that the memory array 3 may include multiple stack structures 30 to increase the storage capacity of the memory array.

[0095] Referring to FIG. 13 , multiple stack structures 30 are spaced apart from each other in the XY plane. For example, multiple stack units s in each stack structure 30 are repeatedly arranged in the Y direction. Multiple stack structures 30 are arranged in the X direction, and adjacent stack structures 30 are spaced apart by a predetermined distance. The spacing between any two stack structures 30 can be equal or unequal. Adjacent stack structures 30 are spaced apart by providing an isolation structure 420 between the two stack structures 30.

[0096] Referring to FIG. 14 , in some embodiments, a second spacer 412 is provided on a side of the gate layer 301 away from the second electrode 303. The second spacer 412 may contact the isolation structure 420. Optionally, the second spacer 412 and the isolation structure 420 are formed using the same process. In other words, the isolation structure 420 and the second spacer 412 are made of the same material and are integrally formed. Using the same process to form the second spacer 412 and the isolation structure 420 can save steps and improve production efficiency.

[0097] The present invention also provides a method for preparing the memory array. Referring to FIG. 15 , the method includes the following steps:

[0098] S10. Form a stacked structure and a second pole, wherein the stacked structure includes a plurality of sacrificial layers, a plurality of semiconductor layers and a plurality of insulating layers stacked in sequence, the semiconductor layer includes a floating body and a first pole surrounding the floating body, and the second pole penetrates the plurality of sacrificial layers, the floating bodies of the plurality of semiconductor layers and the plurality of insulating layers.

[0099] Specifically, as shown in FIG16 , a semiconductor material layer 314, an insulating layer 306, and a sacrificial layer 308 can be stacked in sequence on a substrate (not shown) to form a stacked structure 50. Depending on specific product requirements, the semiconductor material layer 314, the insulating layer 306, and the sacrificial layer 308 can be stacked multiple times, that is, multiple semiconductor material layers 314, multiple insulating layers 306, and multiple sacrificial layers 308 can be stacked in sequence. Depending on the specific materials selected for each film layer, a corresponding deposition process can be selected. For example, if the material of the semiconductor material layer 314 is silicon (Si), a chemical vapor deposition (CVD) process can be used as the deposition process. The film material that can be selected for the insulating layer 306 is as described above. The semiconductor material layer 314 can be made of the same material as the aforementioned semiconductor layer 324 (the doping elements may be different). The sacrificial layer 308 can be made of organic dielectric layer materials or amorphous carbon, but it should be noted that since the sacrificial layer 308 will be removed and replaced with a gate material in a subsequent process, the material of the sacrificial layer 308 should be selected to meet the requirement that other film layers will not be affected when the sacrificial layer 308 is removed, that is, the process of removing the sacrificial layer 308 will not corrode other film layers. For example, the sacrificial layer 308 can be made of phosphosilicate glass (PSG), and a hydrofluoric acid (HF) solution is used for etching when removing the sacrificial layer 308.

[0100] Furthermore, it should be noted that when depositing the semiconductor material layer 314, the semiconductor material layer 314 can be doped directly during the deposition process. For example, when depositing the semiconductor material layer 314 using a chemical vapor deposition process, a doping gas can be added to the reaction gas. For example, when the first electrode is an N-type semiconductor, the doping gas can be phosphorus. It will be readily understood that the doping process can also be performed after each deposition of the semiconductor material layer 314, and this application is not limited thereto. A portion of the semiconductor material layer 314 serves as the first electrode in the ultimately formed memory array.

[0101] As shown in FIG17 , after forming the stacked structure 50, a through hole 510 is formed that passes through the stacked structure 50. The shape of the through hole 510 will determine the formation of the second pole. As mentioned above, the shape of the second pole can be cylindrical, rectangular, or other shapes, so the shape of the through hole 510 can be cylindrical, rectangular, or other shapes. The through hole 510 can be formed by a plasma etching process. Specifically, a mask layer can be formed on the top surface of the stacked structure 50. After the position of the through hole 510 is located by a photolithography process, the mask layer is etched by a first plasma etching process to expose the stacked structure 50; then, a second plasma etching process is used to etch the stacked structure 50 to form the through hole 510. Finally, the mask layer remaining on the stacked structure 50 is removed.

[0102] As shown in FIG18 , semiconductor material layer 314 is doped through through-hole 510. For example, if semiconductor material layer 314 is an N-type semiconductor, a portion of semiconductor material layer 314 needs to be doped to form a P-type semiconductor. This portion serves as floating body 304, while the other portion serves as first electrode 302. This forms semiconductor layer 324, which includes first electrode 302 and floating body 304, with first electrode 302 surrounding floating body 304. Specifically, boron can be diffused and doped through through-hole 510 to form floating body 304. As will be readily understood, floating body 304 is exposed to through-hole 510.

[0103] 19a , a semiconductor material is filled in the through hole 510 to form the second electrode 303. For example, an N-type semiconductor material may be filled in the through hole 510 to form an N-type second electrode 303. It can be seen that the second electrode 303 penetrates the stacked structure 50, that is, penetrates the floating body 304 of the multiple semiconductor layers 324, the multiple sacrificial layers 308, and the multiple insulating layers 306.

[0104] In some embodiments, as shown in FIG19b , before filling the through hole 510 with semiconductor material to form the second electrode 303, the sacrificial layer 308 can be etched through the through hole 510. The etching can be performed using an isotropic etching method, such as a wet etching method. After etching a portion of the sacrificial layer 308, the space formed by the etching is filled with an insulating material to form the first spacer 411.

[0105] The insulating material forming the first spacer 411 can be the same material as the gate dielectric layer (the gate dielectric layer is formed in a subsequent process, as shown by reference numeral 305 in FIG. 22 ). Thus, after the gate dielectric layer is formed in a subsequent process, the gate dielectric layer and the first spacer 411 are integrally formed. Then, the through hole 510 is filled, for example, with a semiconductor material to form the second electrode 303.

[0106] In some embodiments, to increase the conductivity of the second electrode 303, a through-hole can be etched through the middle of the formed second electrode 303 to form a through-hole. This through-hole can then be filled with a metal material to form a conductive wire, thereby reducing resistance. In other words, the second electrode 303 can be tubular, with a conductor inside to reduce resistance and thus heat generation.

[0107] S20 , cutting the stacked structure 50 along the stacking direction to form a plurality of sub-stacked structures, with isolation trenches between the sub-stacked structures.

[0108] As shown in FIG20 , the stacked structure 50 is cut along the stacking direction to form a plurality of sub-stacked structures 51. The orthographic projections 621 of the sub-stacked structures 51 parallel to the bottom surface of the stacked structure can be of the same size. Isolation trenches 621 are formed between the sub-stacked structures 51. The isolation trenches 621 also penetrate the entire stacked structure 50, namely, the first electrodes 302 of the plurality of semiconductor layers 324, the plurality of sacrificial layers 308, and the plurality of insulating layers 306.

[0109] S30 , removing a plurality of sacrificial layers through the isolation trench 621 to form a first gap, and sequentially forming a gate dielectric layer and a gate layer in the first gap.

[0110] As shown in FIG21 , after the stacked structure 50 is cut into a plurality of sub-stacked structures 51 by the isolation trenches 621, the sacrificial layer 308 is removed through the isolation trenches 621 to form first gaps 631. The sacrificial layer 308 can be removed by isotropic etching. For example, when the sacrificial layer 308 is made of phosphosilicate glass (PSG), the stacked structure 50 can be immersed in a hydrofluoric acid (HF) solution for etching.

[0111] Referring to FIG. 22 , in order to separate the gate 301 from the floating body 304, a gate dielectric layer 305 is formed in the first gap 631. The gate dielectric layer 305 may be formed by an atomic layer deposition (ALD) process. When the gate dielectric layer 305 is formed by the ALD process, it can be considered that the gate dielectric layer 305 is formed on the surface exposed by the stacked structure 50, not limited to the first gap. That is, the gate dielectric layer 305 is not only formed on the surface of the semiconductor layer 324, the insulating layer 306, and the second pole 303 exposed in the first gap 631, but also formed on the portion of the semiconductor layer 324 and the insulating layer 306 exposed in the isolation trench 621. Furthermore, the thickness of the gate dielectric layer 305 formed by the ALD process can be considered to be uniform, that is, the thickness of the gate dielectric layer on the surfaces of the semiconductor layer 324, the insulating layer 306, and the second pole 303 is equal. After the gate dielectric layer 305 is deposited on the first gap 631 , since the gate dielectric layer 305 does not completely fill the first gap 631 , a second gap 632 is formed on the gate dielectric layer 305 on the first gap 631 .

[0112] As shown in Figure 23a, the gate layer 301 is deposited in the second gap 632. The materials that can be used for the gate layer 301 are as described above. The process for depositing the gate layer 301 can be selected according to the material used. For example, if the material of the gate layer 301 is aluminum, the corresponding deposition process can be evaporation, sputtering and other process methods.

[0113] In some embodiments, before depositing the gate layer 301 in the second gap 632, the second gap 632 may be filled with a material different from the gate dielectric layer 305. After filling, a portion of the material in the second gap 632 is etched away using an isotropic etching method. The remaining material, located near the second electrode 303, forms the first isolation portion 411, as shown in FIG23b. It will be appreciated that the size of the first isolation portion 411 can be controlled by controlling the etching of the material in the second gap 632. Finally, the gate layer 301 is deposited in the second gap 632.

[0114] It can be understood that the methods of forming the first isolation portion 411 corresponding to Figures 19b and 23b are two optional methods, which can be selected according to actual needs, and the present application is not limited thereto.

[0115] During the deposition of the gate layer 301, the isolation trench 621 may be filled with the same material as the gate layer 301. For example, the sidewalls of the isolation trench 621 may be adhered to the material of the gate layer 301. To prevent the same gate layer 301 from affecting different stacked structures 30, or to reduce energy consumption, the material formed during the deposition of the gate layer 301 in the isolation trench 621 is removed to separate the different stacked structures 30. This removal method may employ an anisotropic etching method, such as plasma etching.

[0116] After removing the material formed by depositing the gate layer 301 , the structure is filled with an insulating material to form an isolation structure 420 , as shown in FIG. 24 .

[0117] In some embodiments, as shown in FIG25 , when removing the gate layer material in the isolation trench 621, a portion of the gate layer 301 in the second gap 632 may also be removed, so that the distance between the gate layer 301 and the boundary of the corresponding second electrode 303 is smaller than the distance between the boundary of the first electrode 302 and the second electrode 303. Based on this, when filling the isolation trench 621 with insulating material to form the isolation structure 420, the space formed by the partial removal of the gate layer 301 may also be filled with insulating material, thereby forming the second spacer 412 in this space. In this case, the second spacer 412 and the isolation structure 420 are made of the same material. Simultaneously forming the second spacer 412 and the isolation structure 420 can save process steps and improve manufacturing efficiency.

[0118] At this time, an isotropic etching method, such as wet etching, can be used to remove the gate layer 301 material. The distance between the boundary of the gate layer 301 away from the corresponding second electrode 303 and the second electrode 303 in the second gap 632 can be controlled by controlling the wet etching time. In other words, the size of the second spacer 412 can be controlled by controlling the wet etching time.

[0119] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory array, characterized in that: The method comprises at least one stack structure, wherein: A plurality of gate layers and a plurality of semiconductor layers are alternately stacked, wherein the semiconductor layer comprises a floating body and a first electrode arranged around the floating body; A second electrode penetrating the gate layer and the floating body; A gate dielectric layer, located between any adjacent gate layer and semiconductor layer, and between the gate layer and the second electrode; Insulating layer, each adjacent gate layer and semiconductor layer forms a film layer pair, and the insulating layer is arranged between two adjacent film layer pairs.

2. The memory array according to claim 1, wherein: The gate layer in the film layer pair is farther from the lower surface of the memory array than the semiconductor layer, or the semiconductor layer in the film layer pair is farther from the lower surface of the memory array than the gate layer.

3. The memory array according to claim 1, wherein: The insulating layer is arranged between any two adjacent pairs of film layers.

4. The memory array according to claim 1, wherein: The insulating layer is in contact with the semiconductor layer.

5. The memory array according to claim 1, wherein: Along a direction perpendicular to a lower surface of the memory array, the insulating layer at least overlaps with the floating body.

6. The memory array according to any one of claims 1 to 5, characterized in that: The distance from the gate layer to the second electrode is greater than the distance from the gate layer to the floating body.

7. The memory array according to claim 6, wherein: The stack structure further includes: a first spacer, which is arranged between the second electrode and the gate layer.

8. The memory array according to claim 7, wherein: The first spacer is made of the same material as the gate dielectric layer and is integrally formed with the gate dielectric layer.

9. The memory array according to any one of claims 1 to 8, characterized in that: A distance between a boundary of the gate layer away from the second electrode and the second electrode is smaller than a distance between a boundary of the first electrode away from the second electrode and the second electrode.

10. The memory array according to claim 9, wherein: Also includes: The second spacer is disposed around the gate layer, and along a direction perpendicular to the lower surface of the memory array, the second spacer overlaps with at least a portion of the first electrode.

11. The memory array according to claim 10, wherein: There are multiple stack structures, and the multiple stack structures are arranged on the first surface at intervals. The memory array further comprises: The isolation structure is arranged between two adjacent stack structures; the isolation structure is made of the same material as the second spacer and is arranged integrally.

12. The memory array according to any one of claims 1 to 11, characterized in that: The insulating layer is SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 or any combination thereof.

13. A memory, characterized in that: The invention comprises a memory array and a controller as claimed in any one of claims 1 to 12, wherein the memory array is electrically connected to the controller.

14. An electronic device, characterized in that: The invention comprises the memory as claimed in claim 13 and a printed circuit board, wherein the memory is electrically connected to the printed circuit board.

15. A method for preparing a memory array, characterized in that: include: forming a stacked structure and a second pole, the stacked structure comprising a plurality of sacrificial layers, a plurality of semiconductor layers and a plurality of insulating layers stacked in sequence, the semiconductor layer comprising a floating body and a first pole surrounding the floating body, and the second pole penetrating the plurality of sacrificial layers, the floating body of the plurality of semiconductor layers and the plurality of insulating layers; Cutting the stacked structure along the stacking direction to form a plurality of sub-stacked structures, with an isolation groove between two adjacent sub-stacked structures; The plurality of sacrificial layers are removed through the isolation groove to form a first gap, and a gate dielectric layer and a gate layer are sequentially formed in the first gap.

16. The preparation method according to claim 15, characterized in that: Forming the second pole includes: forming a through hole penetrating the stacked structure, and forming the second pole in the through hole; After forming the through hole and before forming the second pole, the method further includes: removing a portion of the sacrificial layer, and forming a first spacer at the position of the removed portion of the sacrificial layer.

17. The preparation method according to claim 15 or 16, characterized in that: After forming the gate layer, the method further includes: removing a portion of the gate layer through the isolation groove, and forming a second spacer at the position of the removed portion of the gate layer.

18. The preparation method according to claim 17, characterized in that: In the step of forming the second spacer, an isolation structure is formed in the isolation trench.

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