Method for adjusting service performance and related device therefor

Abstract

The present application relates to a method for adjusting service performance and a related device therefor. The method comprises: during a process in which a computer system runs an application program, executing a pre-configured disturbance function to disturb the processing performance of a processor micro-architecture in the computer system, such that first indicator data for measuring the processing performance changes under the disturbance of the disturbance function; collecting second indicator data and indicator change data present in the first indicator data change process, the second indicator data being data for measuring the service performance of the computer system with respect to the indicator change data; and, on the basis of the second indicator data and the indicator change data, adjusting the service performance to target service performance. The present application solves the problem that the service performance of computer systems cannot be accurately measured.

Description

Method for adjusting service performance and related equipment Technical Field

[0001] The present application relates to the field of cloud computing technology, and in particular to a method for adjusting service performance and related equipment. Background Art

[0002] With the rapid development of cloud computing technology and the continuous expansion of data centers, performance bottlenecks in computer systems are becoming increasingly prominent. As the core component of a computer system, the CPU's data processing capabilities significantly impact system performance. This ability is influenced by many factors, including the network interface card (NIC), memory response speed, and the CPU's microarchitecture design. Microarchitecture, also known as microprocessor architecture, refers to the internal design and implementation of the CPU and significantly impacts computer system performance.

[0003] The CPU's microarchitecture includes cache memory, a translation lookaside buffer (TLB), and a branch prediction unit (BPU). Cache is used to accelerate access to data and instructions. Cache typically has a multi-level structure, such as icache for accessing instructions, dcache for accessing data, and L2 cache shared by both instructions and data. The higher the cache hit rate (when the CPU accesses memory, if the content to be accessed is in the cache, it is a hit; otherwise, it is a cache miss), the faster the computing unit can access data.

[0004] The page tables stored in memory are generally large, so after the processor introduces a memory management unit, the memory management unit needs to access the memory twice to read instructions and data: first, it obtains the physical address by querying the page table, and then accesses the physical address to read the instructions and data. In order to reduce the performance degradation of the processor caused by the memory management unit, the TLB was introduced. The TLB is used to accelerate the translation of data / instruction addresses. Simply put, the TLB is a cache of the page table, which stores a copy of the page table consisting of the page table entries that are most likely to be accessed. When the CPU wants to access a virtual address / linear address, the CPU will first search in the page table copy of the TLB based on the high 20 bits of the virtual address (20 is x86-specific and has different values ​​for different architectures). If there is no corresponding table entry in the page table copy, it is called a TLB miss, otherwise it is a hit. The higher the TLB hit rate, the faster the memory management unit can translate the virtual address into the physical address. The branch prediction unit (BPU) is used to predict the direction of branches in the processor pipeline. The higher the success rate of branch prediction, the lower the number of penalties for pipeline clearing due to incorrect predictions (branch misses).

[0005] Current research focuses on improving service performance by increasing microarchitecture specifications, improving program locality, and implementing prefetching. However, in cache-insensitive application scenarios, such as where network I / O (primarily socket reading and writing) is a bottleneck, these methods, while incurring significant costs to reduce the cache miss rate (i.e., the cache miss rate), may have little effect on improving service performance and cannot accurately measure service performance.

[0006] Currently, no effective solution has been proposed to address the problem that related technologies cannot accurately measure service performance.

[0007] Summary of the Invention

[0008] The method for adjusting service performance and related devices provided by the embodiments of the present invention at least solve the problem of being unable to accurately measure the service performance of a computer system.

[0009] According to one aspect of the present invention, a method for adjusting service performance is provided, the method comprising:

[0010] During the process of running an application program in the computer system, interfering with the processing performance of a processor microarchitecture in the computer system by executing a pre-configured interference function, so that first indicator data used to measure the processing performance changes under the interference of the interference function;

[0011] Collecting indicator change data and second indicator data in a process in which the first indicator data changes, wherein the second indicator data is data used to measure the service performance of the computer system under the indicator change data;

[0012] The service performance is adjusted to a target service performance based on the second indicator data and the indicator change data.

[0013] In some embodiments, the step of adjusting the service performance to a target service performance based on the second indicator data and the indicator change data includes:

[0014] Determine the change amount of the second indicator data under different change values ​​of the first indicator data, so as to adjust the service performance to the target service performance based on the change value and the change amount.

[0015] In some embodiments, the step of interfering with the processing performance of the processor microarchitecture in the computer system by executing a preconfigured interference function includes:

[0016] The interference function is periodically executed based on a pre-acquired interference frequency to interfere with the processing performance of the micro-architecture, so that the size of the first indicator data changes according to a predetermined change trend at the interference frequency.

[0017] In some embodiments, the step of periodically executing the interference function based on the pre-acquired interference frequency to interfere with the processing performance of the micro-architecture includes:

[0018] A preset timer is periodically started according to the interference frequency, and in response to the start information of the timer, the interference function is executed to interfere with the processing performance of the micro-architecture.

[0019] In some embodiments, the micro-architecture includes a cache memory, and the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function further includes:

[0020] A first interference function is configured for the cache memory to interfere with the processing performance of the cache memory by executing the first interference function, wherein the first interference function includes a function for invalidating predetermined content stored in the cache memory and required to run the application.

[0021] In some embodiments, the predetermined content includes predetermined instructions and predetermined data, and the first interference function further includes:

[0022] The function replaces the predetermined instruction with a predetermined replacement instruction, and replaces the predetermined data with pre-read replacement data.

[0023] In some embodiments, the micro-architecture further includes an address translation lookaside buffer, wherein the address translation lookaside buffer is provided with a page table copy, wherein the page table copy is used to read predetermined content required to run the application from the memory of the computer system, and the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function further includes:

[0024] A second interference function is configured for the address translation lookaside buffer to interfere with the processing performance of the address translation lookaside buffer by executing the second interference function, wherein the second interference function includes a function for invalidating page table entries in the page table copy.

[0025] In some embodiments, the predetermined content includes predetermined instructions and predetermined data, the address translation lookaside buffer includes an instruction buffer for accelerating physical address translation of the predetermined instructions and a data buffer for accelerating physical address translation of the predetermined data, the page table copy includes a first page table copy of the instruction buffer and a second page table copy of the data buffer, and before interfering with processing performance of the address translation lookaside buffer by executing the second interference function, the method further includes:

[0026] Applying a predetermined number of target page table entries from the page table of the memory, and constructing a circular linked list based on the target page table entries, wherein the physical address storing the predetermined data in the memory does not exist in the target page table entries;

[0027] Then, the second interference function further includes:

[0028] The page table entry read from the first page table copy is replaced with a function of a predetermined designated entry, and, when accessing the page table entry in the second page table copy, the page table entry of the second page table copy is replaced with a function of the target page table entry by accessing the circular linked list.

[0029] In some embodiments, the microarchitecture further includes a branch prediction unit for predicting branch instructions in an instruction stream generated during the execution of the application program, wherein instruction information of the branch instruction is stored in a branch target cache, and the branch prediction unit predicts the branch instruction based on the instruction information. The step of interfering with the processing performance of the processor microarchitecture in the computer system by executing a preconfigured interference function further includes:

[0030] A third interference function is configured for the branch prediction unit to interfere with the processing performance of the branch prediction unit by executing the third interference function, wherein the third interference function includes a function for reading the instruction information that does not belong to the branch instruction from a predetermined position in the branch target cache when the branch prediction unit reads the instruction information from the branch target cache.

[0031] In some embodiments, the step of reading the instruction information that does not belong to the branch instruction from a predetermined location in the branch target buffer includes:

[0032] When reading the instruction information of the branch instruction from the branch target buffer, the instruction information that does not belong to the branch instruction is read by executing a preset jump instruction to jump to the predetermined position.

[0033] In some embodiments, the step of interfering with the processing performance of the branch prediction unit by executing the third interference function includes:

[0034] The interference degree of the third interference function on the processing performance of the branch prediction unit is adjusted by adjusting the number of the jump instructions, wherein the change trend of the processing performance of the branch prediction unit is different under different interference degrees.

[0035] According to another aspect of the present invention, a device for adjusting service performance is provided, wherein the device is configured to execute the method for adjusting service performance.

[0036] According to another aspect of the present invention, a computer system is provided, wherein the computer system includes the apparatus for adjusting service performance.

[0037] According to another aspect of the present invention, an electronic device is provided, comprising: a processor, and a memory storing a program, wherein the program comprises instructions, and when the instructions are executed by the processor, the processor executes the method for adjusting service performance.

[0038] Beneficial effects of the embodiments of the present invention:

[0039] In the process of actually running an application program on a computer system, an embodiment of the present invention interferes with the processing performance of the processor micro-architecture through a configured interference function, causing a change in the first indicator data for measuring the processing performance, thereby causing a change in the service performance of the computer system. By constructing a change curve graph of the second indicator data of the service performance as the first indicator data changes, the change relationship between the processing performance of the micro-architecture and the service performance is determined, thereby accurately quantifying the quality of the service performance based on the change curve graph, and achieving the purpose of adjusting the service performance to the target service performance.

[0040] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below so that other features, objects, and advantages of the invention are more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other embodiments can be derived from these drawings without inventive effort.

[0042] FIG1 is a schematic flow chart of a method for adjusting service performance according to an embodiment of the present invention;

[0043] FIG2 is a schematic diagram of a system architecture provided by an embodiment of the present invention;

[0044] FIG3 is a diagram showing the working principle of an interference module according to an embodiment of the present invention;

[0045] FIG4 is a curve diagram showing how CPU overhead changes with icache MPKI according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following describes embodiments of the present invention in more detail with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0047] To improve the service performance of computer systems, the focus has been on increasing the microarchitecture's specifications, improving program locality, and implementing prefetching. However, there is a lack of methods to measure service performance by quantifying the processing performance generated by the microarchitecture when running applications on the computer system. The metrics used to measure processing performance vary depending on the microarchitecture type. For example, when the microarchitecture is a cache memory, metrics such as the cache hit rate may have little effect on improving service performance even at a significant cost, especially in scenarios where the computer system's service performance is insensitive to cache (i.e., service performance varies little under varying miss rates). However, in computing applications, even a small reduction in the cache miss rate may significantly improve the computer system's service performance. Therefore, quantifying the impact of microarchitecture processing performance metrics on service performance is of practical significance.

[0048] To quantify the processing performance of the microarchitecture and determine the impact of corresponding microarchitecture metrics on service performance, verification can be performed using hardware emulation (EMU). EMU simulates one type of hardware on another. Through a customized process, the microarchitecture simulated at the register transfer level (RTL) is mapped to the hardware emulation platform. Modifying the RTL can modify the scale of the simulated CPU microarchitecture. RTL is an abstract level of hardware description language used to describe the behavior and structure of digital circuits. However, verification using hardware emulation (EMU) has a significant drawback: EMU emulation is still not fast enough to run real services. Although EMU has dedicated hardware acceleration, real services require higher CPU speeds, and excessive runtimes can cause some service code to fail.

[0049] In response to the above problem, a first embodiment of the present invention provides a method for adjusting service performance, which includes the following steps:

[0050] Step S11: During the process of the computer system running the application, the processing performance of the processor micro-architecture in the computer system is interfered with by executing a pre-configured interference function, so that the first indicator data used to measure the processing performance changes under the interference of the interference function. In the scenario where the computer system actually runs the application, the embodiment of the present invention uses an interference function to interfere with the processing performance of the micro-architecture. For example, when the micro-architecture is a cache, the processing performance of the process of accelerating the access of data and instructions performed by the cache during the running of the application is interfered with, so that the cache hit rate (i.e., the first indicator data) is higher or lower. When the micro-architecture is a TLB, the processing performance of accelerating the translation of data / instruction addresses performed by the TLB is interfered with, so that the miss rate of the TLB (i.e., the first indicator data) is increased or decreased.

[0051] Step S12: collecting the indicator change data and the second indicator data existing in the process of the first indicator data changing, wherein the second indicator data is data used to measure the service performance of the computer system under the indicator change data.

[0052] Secondary metrics for measuring service performance may include: instructions per cycle (IPC), I / O operations per second (IOPS), throughput, and response time (RT). IPC is a metric for measuring CPU service performance. A higher IPC indicates that the CPU executes more instructions in the same amount of time, and thus, the service performance is better. IOPS is a metric for measuring computer storage device performance. A higher IOPS indicates that the storage device handles more I / O operations in the same amount of time, and thus, the service performance of the computer system is better. Throughput refers to the amount of data processed by a computer system within a specified timeframe, typically measured by the amount of data transmitted per unit time. A higher throughput indicates that the computer system handles more data in the same amount of time, and thus, the service performance is better. RT represents the time interval from when a user initiates a request to when the computer system completes its response, and includes CPU processing time, I / O operation time, network transmission time, etc. A shorter RT indicates a faster computer system response and better service performance. When the first indicator data of the micro-architecture changes, the second indicator data of the service performance generates a corresponding value. Therefore, it is of practical significance to judge the impact on the service performance through the first indicator data of the micro-architecture.

[0053] Step S13: Adjust the service performance to the target service performance based on the second indicator data and the indicator change data. Specifically, when adjusting the service performance based on the second indicator data and the indicator change data, in order to facilitate accurate and intuitive adjustment of the service performance, a change curve diagram of the second indicator data as the indicator change data changes can be drawn. From the change curve diagram, it can be seen how the service performance changes with the micro-architecture processing performance. According to the change, it can be judged how much the first indicator data of the corresponding micro-architecture plays a role in improving the service performance, and thus a corresponding adjustment strategy is adopted to adjust the service performance according to the size of the role. When adjusting the service performance based on the quantified first indicator data of the micro-architecture in this way, the adjustment strategy is more intuitive, accurate and clear, and can achieve higher service performance at a lower cost.

[0054] It can be seen that in the process of the computer system actually running the application, the embodiment of the present invention interferes with the processing performance of the processor microarchitecture through the configured interference function, so that the first indicator data for measuring the processing performance changes, and then the service performance of the computer system changes. By constructing a change curve chart of the second indicator data of the service performance as the first indicator data changes, the change relationship between the processing performance and the service performance of the microarchitecture is determined, and the quality of the service performance is accurately quantified based on the change curve chart, thereby achieving the purpose of adjusting the service performance to the target service performance.

[0055] In step S13, the step of adjusting the service performance to the target service performance based on the second indicator data and the indicator change data includes: determining the amount of change in the second indicator data at different change values ​​of the first indicator data, and adjusting the service performance to the target service performance based on the change value and the change amount. For example, if it can be determined based on the change curve that the first indicator data is within a predetermined change value range (e.g., x1% to x2%), each increase or decrease in the first indicator data by a predetermined value will cause the service performance to increase or decrease by x3% (i.e., the amount of change in the second indicator data). In this case, if the service performance is desired to be improved by x6%, the first indicator data can be increased or decreased based on the predetermined value until the service performance is improved by x6%. If the service performance deteriorates sharply when the first indicator data reaches x5%, it is necessary to prevent the first indicator data of the microarchitecture from approaching x5% to ensure that the service performance does not deteriorate sharply and is maintained at the target service performance expected by the user. In cases where the service performance is not sensitive to the processing performance of a microarchitecture, the processing performance of the corresponding microarchitecture can be disregarded when adjusting the service performance, thereby achieving precise adjustment of the service performance.

[0056] In step S11, the step of interfering with the processing performance of the processor microarchitecture in the computer system by executing a pre-configured interference function includes: periodically executing the interference function based on a pre-acquired interference frequency to interfere with the processing performance of the microarchitecture, so that the magnitude of the first indicator data changes according to a predetermined change trend at the interference frequency. For example, the greater the interference frequency, the greater the first indicator data, thereby quantifying the processing performance of the microarchitecture according to the expected target. Then, the indicator change data of the quantified first indicator data is used to determine the influence of the corresponding microarchitecture on the service performance of the computer system, thereby accurately adjusting the service performance to the performance expected by the user.

[0057] Among them, the step of periodically executing an interference function based on a pre-acquired interference frequency to interfere with the processing performance of the micro-architecture includes: periodically starting a pre-set timer according to the interference frequency, and executing the interference function to interfere with the processing performance of the micro-architecture in response to the start information of the timer. The timer provided by the embodiment of the present invention may include a high-precision timer hrtimer provided by the Linux operating system kernel and a timer constructed using a Linux kernel thread kthread (kthread is a thread structure working in the kernel space and does not belong to any process). Among them, when using a high-precision timer hrtimer to implement the interference frequency, the timing accuracy is high and nanosecond timing can be provided. The timer constructed using the Linux kernel thread kthread can distinguish between the data corresponding to the kernel thread and the running process of the application when collecting indicator data, and the extracted data is more accurate.

[0058] In an embodiment of the present invention, the microarchitecture includes a cache memory (hereinafter referred to as a cache). In step S11, the step of interfering with the processing performance of the processor microarchitecture in the computer system by executing a preconfigured interference function further includes configuring a first interference function for the cache memory to interfere with the processing performance of the cache memory by executing the first interference function, wherein the first interference function includes a function for invalidating predetermined content stored in the cache memory and required for running an application. The predetermined content includes predetermined instructions and predetermined data. When the predetermined content is invalidated by the first interference function, the predetermined content to be accessed in the current cache can be invalidated by executing a cache invalidation maintenance instruction. Subsequently, when the CPU accesses the memory, the predetermined content to be accessed will not be hit because it is invalid, resulting in a cache miss. For example, using the ic iallu instruction to clear the predetermined instructions in the icache and the dc cisw instruction to clear the predetermined data in the dcache. This invalidation method has a high execution speed and can achieve a higher interference frequency, resulting in a higher cache MPKI (i.e., the number of CPU misses per thousand instructions).

[0059] Among them, the first interference function also includes: replacing the predetermined instruction with a predetermined replacement instruction, and replacing the predetermined data with pre-read replacement data. That is, the embodiment of the present invention can replace the predetermined instruction of the current icache by executing any other instruction, and load other data to replace the predetermined data of the current dcache, thereby causing subsequent access to fail to hit. For example, using several empty instructions nop as replacement instructions can replace the predetermined instruction in the icache. Use the load instruction to read the replacement data from the next level cache or memory, and use the replacement data to replace the original predetermined data in the dcache. Among them, the number of empty instructions can be determined according to the storage size of the icache and the instruction length of the empty instruction, and the number of load instructions can be determined according to the storage size of the dcache and the length of the accessed data (such as 8 bytes).

[0060] The micro-architecture provided by the embodiment of the present invention also includes an address translation lookaside buffer (abbreviated as TLB), and the address translation lookaside buffer is provided with a page table copy, which is used to read predetermined content required for running the application from the memory of the computer system, that is, the page table copy stores the page table entries in the page table of the memory that are most likely to be accessed at present. In step S11, the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function also includes: configuring a second interference function for the address translation lookaside buffer to interfere with the processing performance of the address translation lookaside buffer by executing the second interference function, wherein the second interference function includes a function for invalidating the page table entries in the page table copy. The CUP includes multiple cores, each of which is configured with a micro-architecture. If the embodiment of the present invention defines the core to which the micro-architecture that needs to be interfered belongs as a load core, the core to which the micro-architecture that does not need to be interfered is located is defined as an idle core. When the embodiment of the present invention invalidates the page table entries through the second interference function, all page table entries in the page table copy of the TLB on the load core can be invalidated by executing the TLB invalidation operation instruction TLBI on the idle core. The invalidation operation instruction is implemented at the hardware level and will not occupy the CPU time slice on the load core. It will also affect the processing performance of the TLB micro-architecture, thereby accurately quantifying various types of micro-architectures and achieving precise adjustment of service performance.

[0061] In some embodiments, the predetermined content includes predetermined instructions and predetermined data, the address translation lookaside buffer includes an instruction buffer ITLB for accelerating physical address translation of predetermined instructions and a data buffer DTLB for accelerating physical address translation of predetermined data, and the page table copy includes a first page table copy in the instruction buffer ITLB and a second page table copy in the data buffer DTLB. Prior to interfering with the processing performance of the address translation lookaside buffer by executing the second interference function, the method provided by the embodiment of the present invention further includes:

[0062] A predetermined number of target page table entries are requested from the page table entries in the memory's page table, and a circular linked list is constructed based on the target page table entries. The physical address storing the predetermined data in the memory does not exist in the target page table entry, effectively replacing the contents of the page table copy and improving the TLB miss rate. A circular linked list is a single linked list connected end to end, with the pointer of the last node in the circular linked list pointing to the front of the linked list. That is, the pointer of the last target page table entry in the circular linked list points to the target page table entry at the beginning of the linked list. The second interference function provided in this embodiment of the present invention also includes: a function that replaces a page table entry read from the first page table copy with a predetermined designated entry; and, when accessing a page table entry in the second page table copy, a function that replaces the page table entry accessed in the second page table copy with the target page table entry by accessing the circular linked list. Thus, by accessing the circular linked list, the target page table entry accessed cyclically from the circular linked list is replaced with the page table entry in the second page table copy, making the replacement process efficient and accurate. As a result, the CPU will not be able to find the physical address in memory of the corresponding predetermined data mapped by the page table entry, and thus will not be able to read the corresponding data. As a result, not only is the effect of interfering with the TLB processing performance achieved, but the ITLB and DTLB can also be interfered with separately, further improving the TLB miss rate. The first indicator data obtained is more accurate, thereby accurately controlling the service performance based on multiple levels (ITLB level, DTLB level).

[0063] Specifically, embodiments of the present invention can interfere with the DTLB by applying for a predetermined number of target page table entries from the memory page table (when applying, the memory page table can be set to an aligned state to avoid allocating target page table entries from the middle of the page table. When applying, one page table applies for a page table entry at the physical address, and the next application jumps to another page table to ensure that when each page table applies for a page table entry, even if it is offset by a certain amount, it can still correspond to the other page table for the application of the page table entry). Then, a circular linked list connected end to end is constructed, and the circular linked list pointer is allowed to chase across pages. While improving the TLB miss rate, it can achieve the effect of replacing all page table entries in the original DTLB within a limited number of accesses, thereby effectively interfering with the DTLB. For interference with the ITLB, a certain amount of assembly code can be written, which consists of jump instructions and no-op instructions. By allowing the register (Program Counter, PC) to jump to the predetermined instruction across pages, the predetermined instruction is read across pages, replacing the page table entries in the original ITLB, and achieving the effect of interfering with the ITLB.

[0064] The micro-architecture provided by an embodiment of the present invention also includes a branch prediction unit (BPU) for predicting branch instructions in an instruction stream generated during the execution of an application. Instruction information for the branch instruction is stored in a branch target buffer. The branch prediction unit predicts the branch instruction based on the instruction information recorded by the BPU. The instruction information also includes information such as the target address, register value, and historical prediction results of the branch instruction. The next time the branch prediction unit executes the branch instruction, it makes a prediction based on the instruction information recorded in the BPU history, thereby improving the execution efficiency of the application. In this embodiment of the present invention, to effectively interfere with the branch prediction unit and reduce the prediction success rate of the branch prediction unit, the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function in step S11 further includes: configuring a third interference function for the branch prediction unit to interfere with the processing performance of the branch prediction unit by executing the third interference function. The third interference function includes a function that, when the branch prediction unit reads instruction information from the branch target buffer, reads instruction information that does not belong to the branch instruction from a predetermined location in the branch target buffer. The branch prediction unit may fail to predict the branch instruction based on other instruction information. That is, the embodiment of the present invention effectively interferes with the branch prediction unit by reading instruction information that does not belong to the current branch instruction.

[0065] The step of reading instruction information that does not belong to a branch instruction from a predetermined location in the branch target buffer includes: when reading the instruction information of the branch instruction from the branch target buffer, executing a preset jump instruction to jump to the predetermined location to read the instruction information that does not belong to the branch instruction. There are three types of jump methods: one is to jump to the next row address (i.e., the predetermined location) when executing the jump instruction; one is to jump to a random address (i.e., the predetermined location is randomly selected); and the other is to pre-set several fixed addresses and have the program jump to the predetermined fixed addresses (i.e., the predetermined location is a pre-selected fixed address and is fixedly adjusted to one of the selected fixed addresses each time). The step of interfering with the processing performance of the branch prediction unit by executing a third interference function includes: adjusting the degree of interference of the third interference function on the processing performance of the branch prediction unit by adjusting the number of jump instructions, wherein the trend of change in the processing performance of the branch prediction unit varies under different interference degrees. That is, the severity of interference is changed by adjusting the number of jump instructions during each interference period. The principle is to occupy the CPU's BTB space by continuously constructing jump instructions, causing the application's branch prediction to miss, thereby achieving effective interference with the branch prediction unit, and making the processing performance of the branch prediction unit change within the expected range of variation, thereby achieving accurate quantification of the processing performance and thus achieving precise adjustment of the service performance.

[0066] A second embodiment of the present invention provides an apparatus for adjusting service performance, which is used to execute the method for adjusting service performance provided by the first embodiment of the present invention.

[0067] The device provided by the embodiment of the present invention can interfere with the processing performance of the processor microarchitecture through the configured interference function during the actual operation of the application program on the computer system, so that the first indicator data for measuring the processing performance changes, and then the service performance of the computer system changes. By constructing a change curve graph of the second indicator data of the service performance as the first indicator data changes, the change relationship between the processing performance of the microarchitecture and the service performance is determined, and the quality of the service performance is accurately quantified based on the change curve graph, thereby achieving the purpose of adjusting the service performance to the target service performance.

[0068] A third embodiment of the present invention provides a computer system, which includes the device for adjusting service performance provided by the second embodiment of the present invention.

[0069] The computer system provided by the embodiment of the present invention uses a device to interfere with the processing performance of the processor microarchitecture through a configured interference function during the actual operation of an application program in the computer system, so that the first indicator data for measuring the processing performance changes, thereby changing the service performance of the computer system. By constructing a change curve graph of the second indicator data of the service performance as the first indicator data changes, the change relationship between the processing performance and the service performance of the microarchitecture is determined, and the degree of quality of the service performance is accurately quantified based on the change curve graph, thereby achieving the purpose of adjusting its own service performance to the target service performance.

[0070] A fourth embodiment of the present invention provides an electronic device, comprising: a processor, and a memory for storing a program, wherein the program comprises instructions, and when the instructions are executed by the processor, the processor executes the method for adjusting service performance provided by the first embodiment of the present invention.

[0071] The fifth embodiment of the present invention further provides a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to execute the method for adjusting service performance provided by the first embodiment of the present invention.

[0072] A sixth embodiment of the present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor of a computer, the computer is used to enable the computer to execute the method for adjusting service performance provided by the first embodiment of the present invention.

[0073] The seventh embodiment of the present invention provides an application embodiment of a method for adjusting service performance based on the six aforementioned embodiments. This application embodiment of the present invention uses the system architecture shown in FIG2 to implement software-based quantification of micro-architecture processing performance indicator data, thereby adjusting service performance. The system architecture in this embodiment of the present invention may be a computer system or a device interconnected with a computer system to adjust service performance. The present embodiment of the present invention does not limit its specific architecture. Compared to existing methods in the industry, the core of this application embodiment of the present invention is to provide a software interference method for the CPU micro-architecture. This method effectively interferes with the processing performance of key modules of the CPU micro-architecture (such as the cache, TLB, and BPU) through a configured interference function, causing changes in the first indicator data that measures processing performance. For example, when the first indicator data of the cache is a cache miss, the first indicator data of the TLB is a TLB miss, and the first indicator data of the BPU is a branch miss, the corresponding cache miss, TLB miss, branch miss, etc. values ​​change, thereby affecting the service performance of the computer system. Finally, a change curve chart showing the change relationship between the first indicator data of the microarchitecture and the second indicator data measuring the service performance is established. Based on the change curve chart, the quality of the service performance is accurately quantified to achieve the purpose of adjusting the service performance to the target service performance.

[0074] The input module in the system architecture provides an interactive interface for user control and interaction. This interface receives user input for controlling the interference module and data acquisition module. The first control parameter for controlling the interference module primarily includes the CPU core (i.e., the load core) to be interfered with, the microarchitecture modules within the load core that need to be interfered with (e.g., cache, TLB, BPU), and the interference frequency. The second control parameter for controlling the data acquisition module primarily includes the sampling frequency, the acquisition duration, and the process identifier (PID) of the process for which interference data is to be collected.

[0075] As shown in Figure 3, the interference module in the system architecture is used to implement interference with the processing performance of the microarchitecture based on the configured interference function. The interference module's operational functions include user-mode startup operations and kernel-mode interference operations. Based on a first control parameter input by the user, the interference module determines the CPU core to be interfered with and the type of microarchitecture under that core. It then periodically starts a kernel-mode timer configured at the interference frequency specified in the first control parameter. During the timer startup period, the interference function is executed, thereby interfering with the microarchitecture (e.g., cache, TLB, BPU, etc.).

[0076] Timer principle: The timer provided by the embodiment of the present invention may include a high-precision timer hrtimer provided by the Linux operating system kernel and a timer constructed using the Linux kernel thread kthread (kthread is a thread structure working in the kernel space and does not belong to any process). Among them, when the high-precision timer hrtimer is used to implement the interference frequency, the timing accuracy is high and nanosecond timing can be provided. The timer constructed using the Linux kernel thread kthread can distinguish between the data corresponding to the kernel thread and the running process of the application when collecting indicator data. Data collection during the timer startup period will not be executed on the interrupted application process, so that the extracted data is more accurate and free of impurities.

[0077] The interference module provided in the embodiment of the present invention is configured with corresponding first, second, and third interference functions for the cache, TLB, and BPU, respectively. The interference module executes the corresponding interference function based on the microarchitecture to be interfered with, that is, selects the more appropriate interference function based on the actual situation to interfere with the corresponding microarchitecture. The method for implementing the first interference function for interfering with the processing performance of the cache includes:

[0078] One approach is to invalidate the cache contents currently waiting to be accessed by the CPU by executing a cache invalidation instruction. This invalidation instruction, implemented at the hardware level, sets the cache's invalid bit to 1, thereby invalidating the contents currently in the cache. Subsequently, when the CPU accesses memory, the intended contents will be invalid and thus miss, resulting in a cache miss. For example, using the ic iallu instruction to clear the intended instructions in the icache, or the dc cisw instruction to clear the intended data in the dcache, this invalidation method executes quickly, achieving a higher interference frequency and resulting in a higher cache MPKI (the number of misses per thousand instructions).

[0079] The embodiment of the present invention can replace the predetermined instruction of the current icache by executing any other instruction, and load other data to replace the predetermined data of the current dcache, thereby causing subsequent access to fail to hit. For example, a number of empty instructions nop can be used as replacement instructions to replace the predetermined instruction in the icache. The load instruction is used to read the replacement data from the next level cache or memory, and the replacement data is used to replace the original predetermined data in the dcache. Among them, the number of empty instructions can be determined according to the storage size of the icache and the instruction length of the empty instructions, and the number of load instructions is determined according to the storage size of the dcache and the length of the accessed data (such as 8 bytes). Specifically, the calculation method of the number of empty instructions (number of nop instructions) and the number of load instructions (number of load instructions) is as follows:

[0080] Where icache size is the storage size of icache, instruction size is the instruction length of the empty instruction, dcache size is the storage size of dcache, and load data size is the length of the accessed data.

[0081] In the interference module, a method for implementing the second interference function for interfering with the processing performance of the TLB includes:

[0082] The first method executes a TLBI maintenance instruction on an uninterrupted, idle core, invalidating all page table entries in the TLB copy on the load core. Because this invalidation instruction is implemented at the hardware level, it does not occupy CPU time slices on the load core and does not affect the processing performance of the TLB microarchitecture. This allows accurate quantification of various microarchitectures and precise adjustment of service performance.

[0083] The second approach is to interfere with the DTLB and ITLB separately. Specifically, for DTLB interference, a predetermined number of target page table entries can be requested from the memory page table (during the request, the memory page table can be set to an aligned state to avoid allocating target page table entries from the middle of the page table. During the request, one page table requests a page table entry for the physical address, and the next request jumps to the next page table. This ensures that even if a certain amount of offset occurs when requesting a page table entry from each page table, it can still be matched to the other page table for the request). A circular linked list is then constructed, with the circular linked list pointers chasing across pages. This improves the TLB miss rate while replacing all page table entries in the original DTLB within a limited number of accesses, effectively interfering with the DTLB. For ITLB interference, a certain amount of assembly code can be written, consisting of jump instructions and no-op instructions. By having the register (Program Counter, PC) jump to the predetermined instruction across pages, the predetermined instruction is read across pages, replacing the page table entries in the original ITLB and interfering with the ITLB.

[0084] In the interference module, a method for implementing the third interference function for interfering with the processing performance of the BPU includes:

[0085] The most basic jump instruction can be used for implementation. When reading the instruction information of the branch instruction from the branch target cache, a pre-set jump instruction is executed to jump to a predetermined location to read the instruction information that does not belong to the branch instruction. There are three types of jump methods: one is to jump to the next row address (i.e., the predetermined location) when executing the jump instruction; one is to jump to a random address (i.e., the predetermined location is randomly selected); and the other is to pre-set several fixed addresses and let the program jump to the pre-set fixed address (i.e., the predetermined location is a pre-selected fixed address, and it can be fixedly adjusted to one of the selected fixed addresses each time). The step of interfering with the processing performance of the branch prediction unit by executing the third interference function includes: adjusting the degree of interference of the third interference function on the processing performance of the branch prediction unit by adjusting the number of jump instructions, wherein the trend of change in the processing performance of the branch prediction unit is different under different interference degrees. That is, the severity of interference is changed by adjusting the number of jump instructions during each interference period. The principle is to occupy the CPU's BTB space by continuously constructing jump instructions, causing the application's branch prediction to miss, thereby achieving effective interference with the branch prediction unit, and making the processing performance of the branch prediction unit change within the expected range of variation, thereby achieving accurate quantification of the processing performance and thus achieving precise adjustment of the service performance.

[0086] The data collection module uses the perf data collection tool to read the required basic indicator data from the Performance Monitoring Unit (PMU) register based on the indicator data to be quantified. The PMU is a hardware module configured to collect and record CPU performance data. Perf is a performance analyzer that can collect process stack information within a fixed time period to calculate the current device operation status. The collected basic indicator data may include:

[0087] Cycles: The number of clock cycles it takes for the CPU to execute a piece of code.

[0088] Instructions: The number of instructions executed by the CPU.

[0089] L1i_cache: Number of first-level instruction cache accesses.

[0090] L1i_cache_refill: Cache refill operation triggered by a L1 instruction cache miss, usually refers to the number of L1 instruction cache misses.

[0091] L1d_cache: Level 1 data cache.

[0092] L1d_cache_refill: Cache refill operation triggered by a L1 data cache miss, usually refers to the number of L1 data cache misses.

[0093] L2d_cache: Number of L2 data cache accesses.

[0094] L2d_cache_refill: Cache refill operation triggered by a L2 cache miss, usually refers to the number of L2 cache misses.

[0095] L1d_tlb: Number of first-level data page table cache accesses.

[0096] L1d_tlb_refill: Cache fill operation triggered when the first-level data page table cache is missed, usually refers to the number of first-level data page table cache misses.

[0097] L1i_tlb: Number of first-level instruction page table cache accesses.

[0098] L1i_tlb_refill: Cache fill operation triggered when the first-level instruction page table cache is missed, usually refers to the number of first-level instruction page table cache misses.

[0099] L2d_tlb: Number of L2 data page table cache accesses.

[0100] L2d_tlb_refill: Cache fill operation triggered by a L2 data page table cache miss, usually refers to the number of L2 data page table cache misses.

[0101] Br_mis_pred: Number of branch mispredictions.

[0102] Br_pred: The total number of branches predicted by the CPU, including branches predicted correctly and incorrectly.

[0103] Stall_backend: The number of cycles in which the CPU backend is stalled, including stalls due to data dependencies, resource contention, branch prediction, etc.

[0104] Stall_frontend: The number of cycles in which the CPU front end is stalled, including stalls due to instruction cache misses, branch prediction errors, etc.

[0105] The embodiment of the present invention can calculate the first indicator data of the corresponding microarchitecture based on the above-mentioned basic indicator data. The first indicator data can be the miss rate of the corresponding microarchitecture. For example, the miss rate of the first-level instruction cache icache can be calculated based on the above-mentioned two basic indicator data L1i_cache and L1i_cache_refill, that is, the ratio of L1i_cache_refill to L1i_cache is the miss rate of icache; the miss rate of the first-level data cache dcache is the ratio of L1d_cache_refill to L1d_cache. The corresponding indicator data of other microarchitectures can be calculated accordingly, and the embodiment of the present invention will not enumerate them one by one here.

[0106] The specific form of the first indicator data can be selected according to the actual situation. For example, the first indicator data can also be the MPKI value of the corresponding microarchitecture (MPKI is the number of CPU misses per thousand instructions). If the microarchitecture is a cache, when icache MPKI (i.e., the MPKI of the CPU in the icache) is used as the first indicator data, the first indicator data = l1i_cache_refill /

[0107] instructions*1000 (here " / " is the division symbol and "*" is the multiplication symbol), instructions is the number of instructions executed by the CPU. Similarly, based on the above basic indicator data, the following first indicator data can be obtained:

[0108] dcache MPKI=l1d_cache_refill / instructions*1000.

[0109] L2 MPKI=l2d_cache_refill / instructions*1000.

[0110] iTLB MPKI=l1i_tlb_refill / instructions*1000.

[0111] dTLB MPKI=l1d_tlb_refill / instructions*1000.

[0112] branch MPKI=br_mis_pred / instructions*1000.

[0113] When the data collection module collects basic indicator data using perf record, you need to set an appropriate sampling frequency and duration. A higher sampling frequency isn't necessarily better, as excessively high sampling frequencies increase overhead. The duration should be determined based on the application type. Ensure that the data collected over multiple tests is stable within this duration. Some applications, such as e-commerce applications, require data sampling over a longer period of time.

[0114] If the interference module uses hrtimer as the timer, the data acquisition tool of the data acquisition module (perf is used as an example here) cannot distinguish between the hitmer and the application. Therefore, the various microarchitecture indicators collected by perf are mixed data of the two. Therefore, it is necessary to extract the data belonging to the application in the data acquisition module. Taking perf as an example, data denoising can be achieved by distinguishing symbols, because the symbol data acquisition tool can determine which program the symbol belongs to.

[0115] The output module provides a data display interface to display the corresponding first indicator data of different microarchitectures (such as icache MPKI / dcache MPKI / L2 MPKI / TLB MPKI / branch MPKI) and the second indicator data of service performance (such as CPU overhead, IPC, IOPS, throughput, RT, etc. output by the application itself or obtained from other monitoring software. CPU overhead is the second indicator data of CPU utilization obtained when running the corresponding application. Then, the changes in the second indicator data of service performance under different first indicator data are analyzed, and a change curve chart of the impact of the first indicator data of the CPU microarchitecture on service performance can be quantified.

[0116] Taking icache interference quantification as an example, Figure 4 shows a curve showing how service performance varies with icache MPKI. Based on this curve, we can draw the following conclusions: When the icache MPKI ranges from x1% to x2%, each increase or decrease in icache MPKI by 1% results in a x3% change in the second service performance metric. When the icache MPKI reaches x4%, service performance deteriorates dramatically, and it is important to avoid icache MPKIs approaching x4%. Depending on whether an application is sensitive or insensitive to icache MPKI, it may be appropriate to consider increasing or not increasing the icache specification accordingly.

[0117] In this regard, specific implementation steps performed by the application embodiment of the present invention based on the above system architecture may include:

[0118] Step 1: The input module obtains the first control parameter and the second control parameter input by the user on the interactive interface.

[0119] Step 2: The interference module starts the corresponding interference function according to the first control parameter input by the user. The start time interval of the timer in the interference module is determined according to the interference frequency.

[0120] Step 3: The data acquisition module collects data of the specified process PID and sets the sampling frequency and sampling duration of the data acquisition tool perf according to the second control parameter set by the user. Perf performs the collection work according to the corresponding sampling frequency and sampling duration.

[0121] Step 4: Perform data analysis. When analyzing, keep the symbol and its corresponding number of samples (the symbol is used when removing noise data), as well as the actual sampling duration. Save the analysis results.

[0122] Step 5: Continue executing the interference function, data collection, and data analysis at other interference time intervals until all interference frequencies are processed.

[0123] Step 6: Perform data extraction and decide whether to remove the impurity data brought by the interference module based on the user input parameters (if hrtimer is not used as the timer, removal is not required).

[0124] Step 7: Data display and storage. Output the first indicator data for each microarchitecture and the second indicator data for service performance. Perform quantitative analysis and plot a curve showing how the second indicator data changes with the first indicator data.

[0125] Therefore, the application embodiment of the present invention can interfere with the processing performance of the processor microarchitecture through the configured interference function during the actual operation of the application program on the computer system, so that the first indicator data for measuring the processing performance changes, and then the service performance of the computer system changes. By constructing a change curve graph of the second indicator data of the service performance as the first indicator data changes, the change relationship between the processing performance of the microarchitecture and the service performance is determined, and the degree of quality of the service performance is accurately quantified based on the change curve graph, thereby achieving the purpose of adjusting the service performance to the target service performance.

[0126] The computer programs for implementing the methods of the embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer programs are executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer programs may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0127] In the context of an embodiment of the present invention, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0128] It should be noted that the term "including" and its variations used in the embodiments of the present invention are open-ended, i.e., "including but not limited to." The term "based on" means "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; and the term "some embodiments" means "at least some embodiments." The modifications of "one" and "a plurality of" mentioned in the embodiments of the present invention are illustrative and non-restrictive. Those skilled in the art should understand that, unless the context clearly indicates otherwise, they should be understood as "one or more."

[0129] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0130] The various steps described in the method implementation scheme provided in the embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method implementation scheme may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0131] The term "embodiment" in this specification refers to specific features, structures, or characteristics described in conjunction with the embodiment that can be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments are referenced to each other. In particular, for the embodiments of the device, equipment, and system, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts are referred to the partial description of the method embodiment.

[0132] The above-described embodiments represent several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, and such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for adjusting service performance, the method comprising: During the process of the computer system running the application, the processing performance of the processor micro-architecture in the computer system is interfered with by executing a pre-configured interference function, so that the first indicator data used to measure the processing performance changes under the interference of the interference function; Collecting indicator change data and second indicator data existing in the process of changing the first indicator data, wherein the second indicator data is data used to measure the service performance of the computer system under the indicator change data; The service performance is adjusted to a target service performance based on the second indicator data and the indicator change data.

2. The method according to claim 1, wherein: The step of adjusting the service performance to the target service performance based on the second indicator data and the indicator change data comprises: Determine the change amount of the second indicator data under different change values ​​of the first indicator data, so as to adjust the service performance to the target service performance based on the change value and the change amount.

3. The method according to claim 1, wherein: The step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function comprises: The interference function is periodically executed based on a pre-acquired interference frequency to interfere with the processing performance of the micro-architecture, so that the size of the first indicator data changes according to a predetermined change trend at the interference frequency.

4. The method according to claim 3, wherein: The step of periodically executing the interference function based on the pre-acquired interference frequency to interfere with the processing performance of the micro-architecture includes: A pre-set timer is started periodically according to the interference frequency, and in response to the start information of the timer, the interference function is executed to interfere with the processing performance of the micro-architecture.

5. The method according to claim 1, wherein: The micro-architecture includes a cache memory, and the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function also includes: A first interference function for the cache memory is configured to interfere with the processing performance of the cache memory by executing the first interference function, wherein the first interference function includes a function for invalidating predetermined content stored in the cache memory required to run the application.

6. The method according to claim 5, wherein: The predetermined content includes predetermined instructions and predetermined data, and the first interference function also includes: The predetermined instruction is replaced by a predetermined replacement instruction, and the predetermined data is replaced by a function of pre-read replacement data.

7. The method according to claim 1, wherein: The micro-architecture further includes an address translation lookaside buffer, the address translation lookaside buffer is provided with a page table copy, the page table copy is used to read predetermined content required to run the application from the memory of the computer system, and the step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function also includes: A second interference function for the address translation lookaside buffer is configured to interfere with the processing performance of the address translation lookaside buffer by executing the second interference function, wherein the second interference function includes a function for invalidating a page table entry in the page table copy.

8. The method according to claim 7, wherein: The predetermined content includes predetermined instructions and predetermined data, the address translation backup buffer includes an instruction buffer for accelerating the physical address translation of the predetermined instruction and a data buffer for accelerating the physical address translation of the predetermined data, the page table copy includes a first page table copy of the instruction buffer and a second page table copy of the data buffer, and before interfering with the processing performance of the address translation backup buffer by executing the second interference function, the method further includes: Applying a predetermined number of target page table entries from the page table entries of the memory, and constructing a circular linked list based on the target page table entries, wherein the physical address storing the predetermined data in the memory does not exist in the target page table entry; Then, the second interference function also includes: The page table entry read from the first page table copy is replaced with a function of a predetermined designated entry, and, when accessing the page table entry in the second page table copy, the page table entry accessed in the second page table copy is replaced with a function of the target page table entry by accessing the circular linked list.

9. The method according to claim 1, wherein: The micro-architecture further includes a branch prediction unit for predicting branch instructions in an instruction stream generated during the running of the application program, wherein instruction information of the branch instruction is stored in a branch target cache, and the branch prediction unit predicts the branch instruction based on the instruction information. The step of interfering with the processing performance of the processor micro-architecture in the computer system by executing a pre-configured interference function also includes: A third interference function is configured for the branch prediction unit to interfere with the processing performance of the branch prediction unit by executing the third interference function, wherein the third interference function includes a function for reading the instruction information that does not belong to the branch instruction from a predetermined position of the branch target cache when the branch prediction unit reads the instruction information from the branch target cache.

10. The method according to claim 9, wherein: The step of reading the instruction information not belonging to the branch instruction from a predetermined position of the branch target buffer comprises: When the instruction information of the branch instruction is read from the branch target buffer, the instruction information not belonging to the branch instruction is read by jumping to the predetermined position through executing a preset jump instruction.

11. The method according to claim 10, wherein: The step of interfering with the processing performance of the branch prediction unit by executing the third interference function comprises: The interference degree of the third interference function on the processing performance of the branch prediction unit is adjusted by adjusting the number of the jump instructions, wherein the change trend of the processing performance of the branch prediction unit is different under different interference degrees.

12. A device for adjusting service performance, the device being configured to execute the method for adjusting service performance according to any one of claims 1 to 11.

13. A computer system, comprising the device for adjusting service performance according to claim 12.

14. An electronic device comprising: A processor, and a memory storing a program, the program comprising instructions which, when executed by the processor, cause the processor to perform the method of any one of claims 1 to 11.

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