Data processing method, processor, and computer device

Abstract

A data processing method, a processor, and a computer device, relating to the technical field of computers. The processor comprises a plurality of sub-processors and a data transfer unit; and each sub-processor comprises a control unit and a processing unit. The method comprises: in response to a first processing instruction, a first control unit sends a data acquisition instruction to the data transfer unit (201); in response to the data acquisition instruction, the data transfer unit acquires first data, and sends the first data to a first sub-processor (202); the first control unit sends a second processing instruction to a first processing unit on the basis of the first processing instruction (203); and in response to the second processing instruction, the first processing unit runs a first function to process the first data to obtain a first processing result (204). According to the method, the plurality of sub-processors are completely independent and do not affect each other, and parallel processing of the plurality of sub-processors can be realized, thereby improving the data processing efficiency.

Description

Data processing method, processor and computer device

[0001] This application claims priority to Chinese patent application No. 202311176208.4, filed on September 13, 2023, entitled “Data processing method, processor and computer device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of the present application relate to the field of computer technology, and in particular to a data processing method, a processor, and a computer device. Background Art

[0003] With the development of computer technology, network models are increasingly being applied in a wide range of scenarios. In any scenario, a processor typically runs the functions in the network model, processes data, and generates results, thereby realizing the network model's functionality. However, due to the limitations of existing processor architectures, processing efficiency is low.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a data processing method, a processor, and a computer device, which can improve processing efficiency. The technical solution includes the following aspects.

[0006] In one aspect, a data processing method is provided. The method is performed by a computer device, the computer device including a processor, the processor including multiple sub-processors and a data handling unit, each sub-processor including a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions. The method includes:

[0007] In response to the first processing instruction, the first control unit sends a data acquisition instruction to the data handling unit, wherein the data acquisition instruction instructs the acquisition of first data, where the first data is the data to be processed indicated by the first processing instruction, and the first control unit is included in a first sub-processor of the plurality of sub-processors;

[0008] The data handling unit obtains the first data in response to the data obtaining instruction, and sends the first data to the first sub-processor;

[0009] The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to execute a first function to process the first data;

[0010] The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result.

[0011] In another aspect, a processor is provided, wherein the processor includes a plurality of sub-processors and a data handling unit, each sub-processor includes a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions;

[0012] a first control unit, configured to send a data acquisition instruction to the data handling unit in response to a first processing instruction, wherein the data acquisition instruction instructs the acquisition of first data, where the first data is data to be processed indicated by the first processing instruction, and the first control unit is included in a first sub-processor of the plurality of sub-processors;

[0013] The data handling unit is configured to obtain the first data in response to the data obtaining instruction, and send the first data to the first sub-processor;

[0014] the first control unit is configured to send a second processing instruction to the first processing unit based on the first processing instruction, the first processing unit being included in the first sub-processor, the second processing instruction instructing to execute a first function to process the first data;

[0015] The first processing unit is configured to execute the first function in response to the second processing instruction to process the first data and obtain a first processing result.

[0016] In some embodiments, the first processing unit is configured to, in response to the second processing instruction, execute the first function to process the i-th sub-data in the first data to obtain an i-th first processing result, where i is an integer greater than 0 and less than n, and n is the number of sub-data included in the first data, where n is an integer greater than 1; and execute the first function to process the i+1-th sub-data in the first data to obtain an i+1-th first processing result;

[0017] The data transfer unit is further configured to, when the first processing unit obtains the jth first processing result, obtain the jth first processing result from the first sub-processor in response to the first transfer instruction, and send the jth first processing result to the second sub-processor, where j is an integer greater than 0 and not greater than n;

[0018] The second processing unit is configured to execute a second function to process the jth first processing result to obtain the jth second processing result when a third processing instruction is received and the second sub-processor receives the jth first processing result. The third processing instruction instructs executing the second function to process the first processing result. The third processing instruction is sent by the second control unit. The second sub-processor includes the second processing unit and the second control unit.

[0019] In some embodiments, the first control unit is further configured to send a first handling instruction to the data handling unit based on the first processing instruction; or

[0020] The second control unit is further configured to send the first transport instruction to the data transport unit.

[0021] In some embodiments, the data transport unit is configured to send the first data to a first memory, where the first memory is included in the first sub-processor and stores the first data;

[0022] The first processing unit is configured to obtain the first data from the first memory in response to the second processing instruction; and run the first function to process the first data to obtain the first processing result.

[0023] In some embodiments, the first processing unit includes a processing subunit and a first transfer subunit, and the first transfer subunit is used to transfer data in the first memory to a register included in the first sub-processor;

[0024] The first control unit is further configured to send a second transport instruction to the first transport sub-unit based on the first processing instruction, wherein the second transport instruction instructs to store the first data in the first memory into a register;

[0025] The first transfer sub-unit is configured to, in response to the second transfer instruction, obtain, from the first memory, a k-th sub-data included in the first data, and send the k-th sub-data to the register, where the data size of the sub-data is equal to the data size corresponding to the storage space of the register, where k is an integer greater than 0 and not greater than n, and n is the number of sub-data included in the first data;

[0026] The register is used to store the k-th sub-data;

[0027] The processing sub-unit is configured to, in response to the second processing instruction, obtain the k-th sub-data from the register, run the first function to process the k-th sub-data, and obtain a k-th first processing result.

[0028] In some embodiments, the first processing unit further includes a second transfer sub-unit, and the second transfer sub-unit is used to transfer the data in the register to the first memory;

[0029] The processing subunit is further configured to send the kth first processing result to the register;

[0030] The register is used to store the kth first processing result;

[0031] The first control unit is further configured to send a third transport instruction to the second transport sub-unit, wherein the third transport instruction instructs the first processing result in the register to be stored in the first memory;

[0032] the second transfer sub-unit is configured to obtain the kth first processing result from the register in response to a third transfer instruction, and send the kth first processing result to the first memory;

[0033] The first memory is further used to store the kth first processing result.

[0034] In some embodiments, the first processing unit is further configured to send the first processing result to a second memory, where the second memory is included in the first sub-processor;

[0035] The second memory is further used to store the first processing result.

[0036] In some embodiments, the first control unit is further configured to send a fourth transport instruction to the data transport unit;

[0037] The data transfer unit is further used to obtain the first processing result from the first sub-processor in response to the fourth transfer instruction, and send the first processing result to the third memory so that the third memory stores the first processing result. The third memory is included in the third sub-processor of the at least multiple sub-processors.

[0038] In some embodiments, the data handling unit is used to obtain the first data from a memory included in a fourth sub-processor in response to the data acquisition instruction, where the fourth sub-processor is any sub-processor among the multiple sub-processors except the first sub-processor; or, in response to the data acquisition instruction, obtain the first data from an external memory, where the external memory is a memory other than the memory in the processor.

[0039] In some embodiments, the first control unit is configured to send a second processing instruction to the first processing unit based on the first processing instruction in response to the first sub-processor receiving the first data.

[0040] On the other hand, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the data processing method described in the above aspects.

[0041] The solution provided in the embodiment of the present application is that the processor includes multiple sub-processors for implementing different functions and a data handling unit for implementing a data handling function. Each sub-processor includes a control unit and a processing unit. Each control unit can control the data handling unit and the processing unit belonging to the same sub-processor to control the data handling unit to perform data handling and thus provide data to the sub-processor, and control the processing unit to run a certain function to process data. In this processor structure, the multiple sub-processors are completely independent of each other and do not affect each other. Parallel processing between the multiple sub-processors can be achieved, and thus when the multiple sub-processors run functions in the network model to process data, the data processing efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0043] FIG2 is a flow chart of a data processing method provided in an embodiment of the present application;

[0044] FIG3 is a flow chart of another data processing method provided in an embodiment of the present application;

[0045] FIG4 is a flow chart of another data processing method provided in an embodiment of the present application;

[0046] FIG5 is a flow chart of another data processing method provided in an embodiment of the present application;

[0047] FIG6 is a flowchart of another data processing method provided in an embodiment of the present application;

[0048] FIG7 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0049] FIG8 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0050] FIG9 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0051] FIG10 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0052] FIG11 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0053] FIG12 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0054] FIG13 is a schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0055] FIG14 is a schematic structural diagram of a terminal device provided in an embodiment of the present application;

[0056] FIG15 is a schematic diagram of the structure of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0058] As used herein, the terms "first," "second," "third," "fourth," and the like may be used to describe various concepts herein, but unless otherwise specified, these concepts are not limited by these terms. These terms are merely used to distinguish one concept from another. For example, a first sub-processor may be referred to as a second sub-processor, and similarly, a second sub-processor may be referred to as a first sub-processor without departing from the scope of this application.

[0059] As used herein, the terms "at least one," "a plurality," "each," and "any" include one, two, or more, "a plurality" include two or more, "each" refers to each of the corresponding plurality, and "any" refers to any one of the plurality. For example, the plurality of sub-processors includes three sub-processors, and "each" refers to each of the three sub-processors. "Any" refers to any one of the three sub-processors, which may be the first sub-processor, the second sub-processor, or the third sub-processor.

[0060] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data and functions involved in this application are obtained with full authorization.

[0061] The data processing method provided in the embodiment of the present application is executed by a processor, and the processor includes multiple sub-processors and a data handling unit, each sub-processor includes a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions. In some embodiments, the processor is set in a computer device. In some embodiments, the computer device is a terminal device or a server. In some embodiments, the server is an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. In some embodiments, the terminal device is a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, smart voice interaction device, smart home appliance and vehicle-mounted terminal device, etc., but is not limited to this.

[0062] FIG1 is a schematic diagram of the structure of a processor provided by an embodiment of the present application. As shown in FIG1 , the processor includes multiple sub-processors 101 and a data handling unit 102 , and each sub-processor 101 includes a control unit 103 and a processing unit 104 .

[0063] Each sub-processor 101 can interact with the data handling unit 102. That is, the control unit 103 in each sub-processor 101 can send data handling instructions to the data handling unit 102, so that the data handling unit 102 can handle data based on the data handling instructions, thereby providing data to be processed to the processing unit 104. The control unit 103 in each sub-processor 101 can also send processing instructions to the processing unit 104 belonging to the same sub-processor 101, so that the processing unit 104 can process data based on the processing instructions.

[0064] In some embodiments, the sub-processor 101 further includes a memory 105 , and the data handling unit 102 can interact with the memory 105 , and can obtain stored data from the memory 105 , or send data to the memory 105 so that the memory 105 stores the data.

[0065] In some possible implementations, the data handling unit 102 can also interact with an external memory other than the memory in the processor, that is, the data handling unit 102 can obtain data from the external memory, or send data to the external memory so that the external memory stores the data.

[0066] Figure 2 is a flowchart of a data processing method provided in an embodiment of the present application. The method is executed by a processor, and the processor includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions; as shown in Figure 2, the method includes the following steps.

[0067] 201. In response to a first processing instruction, a first control unit sends a data acquisition instruction to a data handling unit. The data acquisition instruction instructs the acquisition of first data. The first data is the data to be processed indicated by the first processing instruction. The first control unit is included in a first sub-processor among a plurality of sub-processors.

[0068] In an embodiment of the present application, the processor includes multiple sub-processors and a data handling unit. The data handling unit is used to handle data. For example, the data handling unit is used to handle data stored in other memories to the sub-processor, that is, to provide data for the processing unit of the sub-processor, or to handle the processing results output by the processing unit in the sub-processor to other memories for storage.

[0069] The function is the function corresponding to the network layer in the network model, for example, the function is a convolution function, a pooling function, a fully connected function, an activation function, etc. The convolution function is the function corresponding to the convolution layer in the network model, the pooling function is the function corresponding to the pooling layer in the network model, the fully connected function is the function corresponding to the fully connected layer in the network model, and the activation function is the function corresponding to the activation layer in the network model. The function indicates how the corresponding network layer processes the input data, that is, the function includes the parameters of the network layer in the network model and the corresponding operator (Operator). The operator is the calculation logic of the corresponding network layer. For example, the calculation logic of the convolution layer (Convolution Layer) is an operator; the calculation logic of the fully connected layer (FC layer) is an operator. The parameters of the network layer are equivalent to the weights of the network layer. The weights are used to adjust the relationship between the input data and output data of the network layer. When the network layer processes the input data, it is equivalent to using the weights of the network layer to process the input data according to the calculation logic indicated by the operator. The network model is any AI (Artificial Intelligence) network model, and the processor is an AI processor. The processing units in different sub-processors are used to run different types of functions. That is, the processing units in different sub-processors run different types of functions to process data, that is, different sub-processors are used to implement different functions. For example, the processing unit in one sub-processor is used to run a convolution function or a matrix multiplication function, while the processing unit in another sub-processor is used to run a transposition function, a fusion function, an expansion function, or a data transformation function.

[0070] The control unit in any sub-processor can control the processing unit and data handling unit included in the sub-processor. The control unit can send instructions to the processing unit belonging to the same sub-processor to control the processing unit to run a certain function to process data, and the control unit can send instructions to the data handling unit to control the data handling unit to perform data handling and thus provide data to the sub-processor, or control the data handling unit to handle the processing results output by the processing unit to a memory outside the sub-processor.

[0071] Among them, the first processing instruction indicates the situation of the first sub-processor processing data. For example, the first processing instruction indicates the function run by the processing unit and the data to be processed. Then, when the first control unit receives the first processing instruction, it can know which data the processing unit processes and can know which function to run to process the data. The first data is the input data of the network layer corresponding to the function indicated by the first processing instruction. For example, the network layer corresponding to the function indicated by the first processing instruction is the first network layer in the network model, then the first data is the input data of the network model. If the network model is an image processing model, the first data is the image to be processed; or, if the network model is a speech processing model, the first data is the speech data to be processed. For another example, if the network layer corresponding to the function indicated by the first processing instruction is not the first network layer in the network model, then the first data is the output data of the previous network layer of the network layer corresponding to the first processing instruction.

[0072] In an embodiment of the present application, when the first control unit receives the first processing instruction, it can obtain the data to be processed indicated by the first processing instruction. Therefore, based on the first processing instruction, a data acquisition instruction is sent to the data handling unit to instruct the data handling unit to handle the data to be processed for the first sub-processor so that the subsequent processing unit can process the data to be processed.

[0073] 202. The data handling unit obtains first data in response to a data acquisition instruction, and sends the first data to the first sub-processor.

[0074] In an embodiment of the present application, the data acquisition instruction has indicated which data to acquire, and the data handling unit can acquire the first data indicated by the data acquisition instruction in response to the data acquisition instruction, and then send the first data to the first sub-processor so that the first sub-processor can subsequently process the first data.

[0075] 203. The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data.

[0076] In an embodiment of the present application, the first control unit sends a second processing instruction to the first processing unit based on the first processing instruction to instruct the first processing unit which function to run to process which data, so that the first processing unit subsequently runs the function indicated by the second processing instruction to process the data indicated by the second processing instruction, thereby realizing the first control unit's control over the processing units belonging to the same sub-processor.

[0077] The first function belongs to the category of the function executed by the first processing unit. For example, if the first processing unit executes a convolution function or a matrix multiplication function, the first function is a convolution function or a matrix multiplication function.

[0078] 204. The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result.

[0079] In the embodiment of the present application, the first processing unit is configured to execute a function that can be executed to process data. When the first processing unit receives a second processing instruction, it executes the first function indicated by the second processing instruction to process the first data, thereby obtaining a first processing result.

[0080] It should be noted that the embodiment of the present application is only described by taking the first sub-processor among the multiple sub-processors included in the processor as an example. For each sub-processor among the multiple sub-processors, when the control unit included in the sub-processor receives a processing instruction, it can process data in accordance with the above-mentioned steps 201 to 204.

[0081] The solution provided in the embodiment of the present application is that the processor includes multiple sub-processors for implementing different functions and a data handling unit for implementing a data handling function. Each sub-processor includes a control unit and a processing unit. Each control unit can control the data handling unit and the processing unit belonging to the same sub-processor to control the data handling unit to perform data handling and thus provide data to the sub-processor, and control the processing unit to run a certain function to process data. In this processor structure, the multiple sub-processors are completely independent of each other and do not affect each other. Parallel processing between the multiple sub-processors can be achieved, and thus when the multiple sub-processors run functions in the network model to process data, the data processing efficiency can be improved.

[0082] Based on the embodiment shown in Figure 2, the first sub-processor in the embodiment of the present application also includes a first memory and a second memory. The first memory can store data to be processed by the first processing unit, and the second memory can store the processing results output by the first processing unit. The specific process is detailed in the following embodiment.

[0083] Figure 3 is a flowchart of another data processing method provided in an embodiment of the present application. The method is executed by a processor, and the processor includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions; as shown in Figure 3, the method includes the following steps.

[0084] 301. In response to a first processing instruction, a first control unit sends a data acquisition instruction to a data handling unit. The data acquisition instruction instructs to acquire first data. The first data is the data to be processed indicated by the first processing instruction. The first control unit is included in a first sub-processor of a plurality of sub-processors.

[0085] In some embodiments, the first processing instruction is sent by a processor, that is, the process of sending the first processing instruction to the first control unit includes: the processor sends the first processing instruction to the first control unit.

[0086] In an embodiment of the present application, the processor is capable of controlling each sub-processor. The processor controls each sub-processor to execute a function to process data by sending a processing instruction to each sub-processor.

[0087] In some embodiments, the processor includes functions in the network model, and the process of sending the first processing instruction to the first control unit includes: the processor sending the first processing instruction to the first control unit based on the order of the functions in the network model.

[0088] In an embodiment of the present application, the processor includes a function in a network model so that the processor responds to a target processing instruction and sends processing instructions to multiple sub-processors based on the order of functions in the network model. During this process, when a certain function is executed, the function is a function run by the first processing unit in the first sub-processor, and a first processing instruction is sent to the first control unit to instruct the first sub-processor to run the function to process data.

[0089] The target processing instruction instructs the network model to process target data. The target data can be any type of data. For example, if the network model is an image processing model, the target data is the image to be processed; or if the network model is a speech processing model, the target data is speech data to be processed. The order of functions in the network model can reflect the connection relationship between the network layers in the network model. For example, each network layer corresponds to a function, and the connection relationship between the network layers in the network model is the order of the functions in the network model.

[0090] In some embodiments, when the processor receives a target processing instruction, it determines the first sub-processor to run the first function based on the order of functions in the network model, and sends a first processing instruction to the first control unit. The target processing instruction instructs running the network model to process the target data.

[0091] In other embodiments, when the processor receives the target processing instruction, it determines the second sub-processor to run the second function based on the order of functions in the network model, and sends a fourth processing instruction to the second control unit, where the fourth processing instruction instructs the second sub-processor to run the second function to process the processing results output by the first sub-processor.

[0092] The first data is the data output by the previous function, or the data to be processed that is input to the network model. For example, if the first function indicated by the first processing instruction is the first function in the network model, then the first data is the data to be processed that is input to the network model. For another example, if the first function indicated by the first processing instruction is not the first function in the network model, then the first data is the data output by the function before the first function.

[0093] In an embodiment of the present application, in the process of deploying a network model in a processor, the processor loads the network model, obtains the various functions included in the network model and the order between the various functions, and when the processor receives a target processing instruction, determines the fifth sub-processor to run the first function, sends a processing instruction to the fifth sub-processor to instruct the fifth sub-processor to run the first function to process the target data; the processor determines the sixth sub-processor to run the second function, and sends a processing instruction to the sixth sub-processor to instruct the sixth sub-processor to run the second function to process the processing result output by the fifth sub-processor after the fifth sub-processor completes processing the target data, and so on. In response to the target processing instruction, the processor can control multiple sub-processors to run the functions in the network model to process the target data, and then obtain the processing result obtained by running the last function. In an embodiment of the present application, when the processor receives a target processing instruction, it determines the first sub-processor to run the first function and the second sub-processor to run the second function based on the order of the functions in the network model, which is conducive to improving the determination accuracy and efficiency of the sub-processors corresponding to the functions, thereby improving data processing efficiency.

[0094] In some embodiments, the processor includes a central control unit, and in the process of running the network model to process data, the central control unit can distribute processing instructions to the control units in each sub-processor. That is, the central control unit sends a first processing instruction to the first control unit.

[0095] 302. A data handling unit obtains first data in response to a data acquisition instruction, and sends the first data to a first memory included in a first sub-processor.

[0096] In the embodiment of the present application, the first sub-processor includes a first memory, which has the function of storing input data. That is, the first memory is used to store data to be processed by the first processing unit. Therefore, when the data transfer unit obtains the first data to be processed by the first processing unit, it sends the first data to the first memory, so that the first memory stores the first data.

[0097] In some embodiments, step 302 includes: the data handling unit obtains the first data from the memory included in the fourth sub-processor in response to the data acquisition instruction, and the fourth sub-processor is any sub-processor among the multiple sub-processors except the first sub-processor; or, the data handling unit obtains the first data from the external memory in response to the data acquisition instruction, and the external memory is a memory other than the memory in the processor.

[0098] In an embodiment of the present application, the first data is data stored in a memory in other sub-processors, or an external memory other than the memory in the processor. The data acquisition instruction indicates the storage location of the first data, which is a storage location in the memory in the fourth sub-processor, or a storage location in the external memory. The data handling unit responds to the data acquisition instruction, obtains the first data from the indicated storage location, and sends the first data to the first memory so that the first memory stores it.

[0099] In an embodiment of the present application, the data handling unit can not only interact with each sub-processor, but also interact with an external memory to realize the data handling function, ensuring that the data handling unit can provide each sub-processor with data to be processed, thereby ensuring that the processor can process data normally and ensuring the stability of the processor operation.

[0100] 303. The first memory stores first data.

[0101] In some embodiments, the data acquisition instruction also instructs to obtain parameters in the first function, then steps 302 and 303 include: the data handling unit responds to the data acquisition instruction, obtains the first data and the parameters in the first function, sends the first data and the parameters to the first memory, and the first memory stores the first data and the parameters.

[0102] In the embodiment of the present application, the first function is the function indicated by the first processing instruction, that is, the first sub-processor subsequently runs the first function to process the first data. The first memory stores the first data and the parameter for subsequent calling by the first processing unit.

[0103] In some embodiments, the first processing instruction indicates the storage location of the parameters in the first function, and the storage location indicates a location in the external memory. The process of the data handling unit obtaining the parameters in the first function includes: the data handling unit responds to the data acquisition instruction and obtains the parameters in the first function from the external memory.

[0104] In some embodiments, the first processing instruction also indicates the storage location of the first function, and the data acquisition instruction sent by the first control unit to the first memory also indicates the storage location of the first function, and the storage location indicates a location in the external memory. Then steps 302 and 303 include: the data handling unit responds to the data acquisition instruction, acquires the first data and the first function, sends the first data and the first function to the first memory, and the first memory stores the first data and the first function.

[0105] In an embodiment of the present application, the first function is stored in an external memory, and the first processing instruction received by the first control unit has indicated the storage location of the first function. The data acquisition instruction sent to the data transport unit indicates the storage location of the first function to instruct the data transport unit to transport the first function to the first memory, so that the first processing unit can subsequently run the first function in the first memory to process the first data in the first memory.

[0106] It should be noted that the embodiment of the present application is described using the example of the first sub-processor including the first memory. In another embodiment, there is no need to execute the above steps 302-303, but other methods are adopted. The data handling unit responds to the data acquisition instruction, obtains the first data, and sends the first data to the first sub-processor.

[0107] 304. The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data.

[0108] In some embodiments, step 304 includes: in response to the first sub-processor receiving the first data, the first control unit sends a second processing instruction to the first processing unit based on the first processing instruction.

[0109] In an embodiment of the present application, when the first sub-processor receives the first data, it indicates that the first processing unit is able to process the first data. The first control unit sends a second processing instruction to the first processing unit in response to the first sub-processor receiving the first data based on the first processing instruction to instruct the first processing unit to process the first data, so as to ensure that the first processing unit can process the first data in a timely manner, thereby ensuring the real-time nature of data processing and improving processing efficiency.

[0110] In some embodiments, step 304 includes: when the first memory stores the first data, the first memory sends a storage success notification to the first control unit, the storage success notification indicating that the first memory has successfully stored the first data, and the first control unit sends a second processing instruction to the first processing unit in response to receiving the storage success notification; or, when the data handling unit has sent the first data to the first memory, the data handling unit sends an acquisition success notification to the first control unit, the acquisition success notification indicating that the first sub-processor has successfully acquired the first data, and the first control unit sends a second processing instruction to the first processing unit in response to receiving the acquisition success notification.

[0111] In an embodiment of the present application, the first control unit receives a storage success notification or a retrieval success notification, both of which indicate that the first sub-processor has received the first data. At this time, the first processing unit can start processing the first data. Therefore, a second processing instruction is sent to the first processing unit to instruct the first processing unit to start processing the first data.

[0112] In some embodiments, step 304 includes: the first control unit generates a second processing instruction based on the first processing instruction, and sends the second processing instruction to the first processing unit.

[0113] In an embodiment of the present application, the first processing instruction instructs the first sub-processor which function to run, which data to process, and the storage location of the data, while the second processing instruction generated based on the first processing instruction only instructs the first processing unit which network model to run and which data in a memory to process, so that the first processing unit can obtain accurate data based on the second processing instruction and run the accurate function to process the data.

[0114] In some embodiments, the second processing instruction indicates a storage location of the first data, where the storage location indicates a storage location of the first data in the first memory.

[0115] 305. The first processing unit obtains first data from the first memory in response to the second processing instruction; runs the first function to process the first data, and obtains a first processing result.

[0116] In an embodiment of the present application, the second processing instruction has indicated the first data stored in the first memory and instructed to run the first function to process the first data. Then, the first sub-processor can respond to the second processing instruction, read the first data from the first memory, and run the first function to process the first data to obtain the first processing result.

[0117] In the embodiment of the present application, the first memory in the first sub-processor has the function of storing input data, that is, the first memory is used to store data to be processed by the first processing unit. Therefore, when the data transfer unit obtains the first data to be processed by the first processing unit, it sends the first data to the first memory, so that the first memory stores the first data, and then the first processing unit can read the first data from the first memory and process the first data, thereby avoiding the loss of the first data, ensuring the stability of the data processing process, and thus ensuring the accuracy of the data processing.

[0118] For example, the first data is data output by the previous function, and the first function is a convolution function. The first processing unit runs the convolution function to convolve the first data to obtain the convolved data, and the convolved data is the first processing result.

[0119] In some embodiments, the first memory stores parameters in the first function and first data, then step 305 includes: the first processing unit responds to the second processing instruction, obtains the first data and parameters in the first function from the first memory, runs the first function including the function to process the first data, and obtains a first processing result.

[0120] In an embodiment of the present application, based on a first function including the parameter, the first data is processed to obtain a first processing result by implementing a network layer corresponding to the first function.

[0121] In some embodiments, the first memory stores a first function and first data, and step 305 includes: the first processing unit responds to the second processing instruction, obtains the first data and the first function from the first memory, runs the first function to process the first data, and obtains a first processing result.

[0122] In an embodiment of the present application, the first function is moved to the first memory so that the first processing unit can directly run the first function to process the first data, thereby ensuring processing efficiency.

[0123] It should be noted that the embodiment of the present application is described by taking the example of the first processing unit obtaining the first data from the first memory. In another embodiment, there is no need to execute the above step 305, but other methods are adopted. The first processing unit responds to the second processing instruction, runs the first function to process the first data, and obtains the first processing result.

[0124] 306. The first processing unit sends the first processing result to a second memory, where the second memory is included in the first sub-processor.

[0125] In an embodiment of the present application, the first sub-processor further includes a second memory having the function of storing output data, that is, the second memory is used to store the processing results output by the first processing unit. After the first processing unit completes processing of the first data, it sends the first processing result to the second memory, so that the second memory stores the first processing result, thereby avoiding loss of the first processing result and ensuring the stability of the first sub-processor.

[0126] 307. The second memory stores the first processing result.

[0127] It should be noted that the embodiment of the present application is described by taking the first sub-processor including the second memory as an example. In another embodiment, there is no need to execute the above steps 306-307, but other methods are adopted to store the first processing result, or the first processing result is directly output.

[0128] The solution provided in the embodiment of the present application is that the processor includes multiple sub-processors for implementing different functions and a data handling unit for implementing a data handling function. Each sub-processor includes a control unit and a processing unit. Each control unit can control the data handling unit and the processing unit belonging to the same sub-processor to control the data handling unit to perform data handling and thus provide data to the sub-processor, and control the processing unit to run a certain function to process data. In this processor structure, the multiple sub-processors are completely independent of each other and do not affect each other. Parallel processing between the multiple sub-processors can be achieved, and thus when the multiple sub-processors run functions in the network model to process data, the data processing efficiency can be improved.

[0129] In the embodiment of the present application, the first memory in the first sub-processor has the function of storing input data, that is, the first memory is used to store data to be processed by the first processing unit. Therefore, when the data transfer unit obtains the first data to be processed by the first processing unit, it sends the first data to the first memory, so that the first memory stores the first data, and then the first processing unit can read the first data from the first memory and process the first data, thereby avoiding the loss of the first data, ensuring the stability of the data processing process, and thus ensuring the accuracy of the data processing.

[0130] In an embodiment of the present application, the first sub-processor further includes a second memory having the function of storing output data, that is, the second memory is used to store the processing results output by the first processing unit. After the first processing unit completes processing of the first data, it sends the first processing result to the second memory, so that the second memory stores the first processing result, thereby avoiding loss of the first processing result and ensuring the stability of the first sub-processor.

[0131] In addition, the data handling unit provides a flexible data path, reducing the bandwidth requirements of the sub-processor for the external memory and improving bandwidth utilization.

[0132] Moreover, the result of the processor provided by the embodiment of the present application can make each sub-processor completely decoupled, and multiple sub-processors do not affect each other, realizing loose coupling between different types of functions in the network model, making it easy for developers to configure the processor. It is only necessary to configure the data path of the data handling unit between the sub-processors used to process different types of functions. The data handling unit supports data handling between all memories, so that the data handling unit can interact with each sub-processor and the external memory to ensure that different types of functions are concurrent. Data can be efficiently transmitted within the processor, achieving a tight integration of different types of functions in data interaction, saving configuration time, ensuring that the processor can be applied to various network models, and ensuring the ease of use of the processor. In addition, each sub-processor in the processor includes a control unit to control the sub-processor to which it belongs, realizing an architecture that is loosely coupled in instruction control and supports the tight integration of different types of functions in data flow interaction, giving full play to the computing power of the processing unit used to run different types of functions, and greatly reducing the complexity of software deployment.

[0133] Based on the embodiment shown in Figure 2, in the embodiment of the present application, the processor also includes a first memory and a register. The first memory can store the data to be processed and the storage results of the first processing unit. The register can serve as a transfer memory between the first memory and the first processing unit to ensure the data transmission efficiency between the first processing unit. The specific process is detailed in the following embodiment.

[0134] Figure 4 is a flowchart of another data processing method provided in an embodiment of the present application. The method is executed by a processor, and the processor includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions; as shown in Figure 4, the method includes the following steps.

[0135] 401. The first control unit sends a data acquisition instruction to the data handling unit in response to the first processing instruction. The data acquisition instruction instructs to acquire first data. The first data is the data to be processed indicated by the first processing instruction. The first control unit is included in the first sub-processor of the plurality of sub-processors.

[0136] 402. A data handling unit obtains first data in response to a data acquisition instruction, and sends the first data to a first memory included in a first sub-processor.

[0137] 403. The first memory stores first data.

[0138] It should be noted that the embodiment of the present application is described using the example of the first sub-processor including the first memory. In another embodiment, there is no need to execute the above steps 402-403, but other methods are adopted. The data handling unit responds to the data acquisition instruction, obtains the first data, and sends the first data to the first sub-processor.

[0139] 404. The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data.

[0140] It should be noted that the above steps 401 to 404 are similar to the above steps 301 to 304 and will not be repeated here.

[0141] 405. The first control unit sends a second transport instruction to the first transport sub-unit based on the first processing instruction, where the second transport instruction instructs to store the first data in the first memory into the register.

[0142] In an embodiment of the present application, the first processing unit includes a processing subunit and a first transfer subunit. The first transfer subunit is used to transfer data in the first memory to a register included in the first sub-processor; the processing subunit is used to run a first function to process the first data. The first transfer subunit (Load unit) can be any type of unit.

[0143] In an embodiment of the present application, since the first data to be processed by the first processing unit is stored in the first memory, and considering that the data transmission rate between the first memory and the first processing unit is low, a register is also set in the first sub-processor, and a first transport sub-unit is set in the first processing unit, so that the first transport sub-unit first transports the first data in the first memory to the register, and then the processing sub-unit processes and obtains the first data from the register. This can avoid the processing sub-unit from wasting time by obtaining data directly from the first memory, thereby improving data transmission efficiency and further improving data processing efficiency.

[0144] In an embodiment of the present application, the first processing instruction instructs the first processing unit which function to run to process which data, and when the first data is stored in the first memory, based on the first processing instruction, a second transport instruction is sent to the first transport subunit, so that the second transport instruction can instruct the first transport subunit which data to transport, so as to ensure the accuracy of data transportation.

[0145] In some embodiments, step 405 includes: the first control unit generates a second transport instruction based on the first processing instruction, and sends the second transport instruction to the first transport subunit, where the second transport instruction instructs to store the first data in the first memory into the register.

[0146] The second transfer instruction further indicates the storage location of the first data in the first memory and the storage location in the register. The storage location in the register indicates the location where the first data is stored in the register, that is, indicates the location in the register to which the first data is transferred.

[0147] In some embodiments, step 405 includes: in response to the first sub-processor receiving the first data, the first control unit sends a second transport instruction to the first transport sub-unit based on the first processing instruction.

[0148] In an embodiment of the present application, when the first sub-processor receives the first data, it indicates that the first processing unit is able to process the first data. The first control unit sends a second transport instruction to the first transport sub-unit in response to the first sub-processor receiving the first data based on the first processing instruction, to instruct the first transport sub-unit to transport the first data to the register, so as to enable the processing sub-unit to read and process the data in the register, so as to ensure that the first processing unit can process the first data in a timely manner, thereby ensuring the real-time nature of data processing and improving processing efficiency.

[0149] In some embodiments, step 405 includes: when the first memory stores the first data, the first memory sends a storage success notification to the first control unit, the storage success notification indicating that the first memory has successfully stored the first data, and the first control unit sends a second transport instruction to the first transport sub-unit in response to receiving the storage success notification based on the first processing instruction; or, when the data transport unit has sent the first data to the first memory, the acquisition success notification sends the first control unit, the acquisition success notification indicating that the first sub-processor has successfully acquired the first data, and the first control unit sends a second transport instruction to the first transport sub-unit in response to receiving the acquisition success notification based on the first processing instruction.

[0150] In an embodiment of the present application, the first control unit receives a storage success notification or a retrieval success notification, both of which indicate that the first sub-processor has received the first data. At this time, the first processing unit can start processing the first data. Therefore, the second processing unit is sent to the first processing unit to instruct the first processing unit to start processing the first data.

[0151] 406. In response to the second transport instruction, the first transport sub-unit obtains the kth sub-data included in the first data from the first memory and sends the kth sub-data to the register. The data amount of the sub-data is equal to the data amount corresponding to the storage space of the register, where k is an integer greater than 0 and not greater than n, and n is the number of sub-data included in the first data.

[0152] In an embodiment of the present application, the storage space of the register is limited, and the amount of the first data is greater than the amount of data corresponding to the storage space of the register. Therefore, the first transport sub-unit will transport the first data to the register in multiple times to avoid insufficient registers and ensure processing efficiency.

[0153] 407. The register stores the kth sub-data.

[0154] 408. The processing sub-unit obtains the kth sub-data from the register in response to the second processing instruction, runs the first function to process the kth sub-data, and obtains the kth first processing result.

[0155] In an embodiment of the present application, when the first transport sub-unit transports the kth sub-data to the register, the processing sub-unit can obtain and process the kth sub-data from the register, and then obtain the first processing result corresponding to the kth sub-data, that is, the kth first processing result.

[0156] In the embodiment of the present application, the first sub-processor includes a processing sub-unit, and the first control unit sends the second processing instruction to the first sub-processor, that is, sends the second processing instruction to the processing sub-unit.

[0157] It should be noted that the embodiment of the present application is described by taking the example of the first processing unit including a processing sub-unit and a first transport sub-unit. In another embodiment, there is no need to execute the above steps 405-408, but other methods are adopted. The first processing unit responds to the second processing instruction and obtains the first data from the first memory; runs the first function to process the first data and obtains the first processing result.

[0158] 409. The processing subunit sends the kth first processing result to the register, and the register stores the kth first processing result.

[0159] In the embodiment of the present application, the processing sub-unit can read the data in the register and can send the first processing result to the register so that the register stores the first processing result.

[0160] 410. The first control unit sends a third transport instruction to the second transport sub-unit, where the third transport instruction instructs to store the first processing result in the register into the first memory.

[0161] In an embodiment of the present application, the first processing unit further includes a second transport subunit, which is used to transport the data in the register to the first memory. Since the data transmission efficiency between the register and the processing subunit is high, but the storage space of the register is limited, when the processing subunit stores the first processing result in the register, the second transport subunit transports the first processing result to the first memory for storage, thereby freeing up the storage space of the register, thereby ensuring that data can continue to be stored from the register. Wherein, the second transport subunit (Store unit) is a unit of any type.

[0162] In some embodiments, the third transfer instruction also indicates the storage location of the first processing result in the register and the storage location in the first memory. The storage location in the first memory indicates the location where the first processing result is stored in the first memory, that is, indicates to which location in the first memory the first processing result is transferred.

[0163] In some embodiments, step 410 includes: the first control unit sends a third transport instruction to the second transport sub-unit in response to the register receiving the kth first processing result.

[0164] In an embodiment of the present application, when the register receives the kth first processing result, it indicates that the processing sub-unit has completed processing the kth sub-data. The first control unit generates a third transfer instruction in response to the register receiving the kth first processing result, and sends the third transfer instruction to the second transfer sub-unit to instruct the second transfer sub-unit to transfer the kth first processing result to the first memory to release the storage space of the register, thereby ensuring that data can continue to be stored from the register subsequently, and that the first processing result can be stored in a stable first memory to avoid the loss of processing results and ensure the stability of the processor operation.

[0165] In some embodiments, step 410 includes: when the register stores the kth first processing result, the register sends a storage success notification to the first control unit, and the storage success notification indicates that the register has successfully stored the kth first processing result. In response to receiving the storage success notification, the first control unit generates a third transport instruction and sends the third transport instruction to the second transport sub-unit; or, when the processing sub-unit has sent the kth first processing result to the register, the processing completion notification indicates that the processing sub-unit has completed processing the kth sub-data. In response to receiving the processing completion notification, the first control unit generates a third transport instruction and sends the third transport instruction to the second transport sub-unit.

[0166] In an embodiment of the present application, the first control unit receives a storage success notification or a processing completion notification, which indicates that the register has received the kth first processing result. At this time, the second transport sub-unit can transport the kth first processing result from the register to the first memory. Therefore, a third transport instruction is sent to the second transport sub-unit to instruct the second transport sub-unit to start transporting the kth first processing result.

[0167] 411. In response to the third transport instruction, the second transport sub-unit obtains the kth first processing result from the register and sends the kth first processing result to the first memory.

[0168] 412. The first memory stores the kth first processing result.

[0169] It should be noted that the above steps 406 to 412 are only explained by taking the kth sub-data included in the first data as an example. According to the above steps 406 to 412, starting from the first sub-data included in the first data, the first first processing result can be stored in the first memory. Then, according to the above steps 406 to 412, the second sub-data is processed, and the second first processing result can be obtained and stored in the first memory. And so on. When the first sub-processor completes processing of the first data, n first processing results are stored in the first memory, and the n first processing results are the first processing results corresponding to the first data.

[0170] In addition, in the process of processing the first data according to the above steps 406 to 412, the second transport instruction and the third transport instruction are triggered only once, or are triggered once each time a sub-data in the first data is processed.

[0171] It should be noted that the embodiment of the present application is described by taking the example of the first processing unit including a processing sub-unit, a first transport sub-unit and a second transport sub-unit. In another embodiment, there is no need to execute the above steps 405-412, but other methods are adopted. The first processing unit responds to the second processing instruction, runs the first function to process the first data, and obtains the first processing result.

[0172] The solution provided in the embodiment of the present application is that the processor includes multiple sub-processors for implementing different functions and a data handling unit for implementing a data handling function. Each sub-processor includes a control unit and a processing unit. Each control unit can control the data handling unit and the processing unit belonging to the same sub-processor to control the data handling unit to perform data handling and thus provide data to the sub-processor, and control the processing unit to run a certain function to process data. In this processor structure, the multiple sub-processors are completely independent of each other and do not affect each other. Parallel processing between the multiple sub-processors can be achieved, and thus when the multiple sub-processors run functions in the network model to process data, the data processing efficiency can be improved.

[0173] In an embodiment of the present application, since the data transmission efficiency between the register and the processing sub-unit is high, the storage space of the register is limited, and the data amount of the first data is greater than the data amount corresponding to the storage space of the register, the first transport sub-unit will transport the first data to the register in multiple times to avoid the situation where the register is insufficient, so that the processing sub-unit can read the sub-data from the register and store the first processing result in the register, so as to ensure the data transmission efficiency between the register and the processing sub-unit, and thus ensure the data processing efficiency.

[0174] Moreover, when the processing sub-unit obtains the first processing result, the first processing result is stored in the register, and the second transport sub-unit transports the first processing result from the register to the first memory, so that the first memory can store the first processing result. Due to the good stability of the first memory, the loss of the first processing result is avoided, and the security of the processing result can be guaranteed.

[0175] It should be noted that the embodiment shown in FIG. 4 is described by taking the example that the first sub-processor includes one register.

[0176] In some embodiments, the register includes a first type of register. The first transport subunit, in response to a second transport instruction, obtains the kth sub-data included in the first data from the first memory and sends the kth sub-data to the first type of register; the first type of register stores the kth sub-data; the processing subunit, in response to the second processing instruction, obtains the kth sub-data from the first type of register; and runs a first function to process the kth sub-data, thereby obtaining a kth first processing result.

[0177] In some embodiments, the register includes a second type of register. The processing subunit sends the kth first processing result to the second type of register; the second type of register stores the kth first processing result; the first control unit sends a third transfer instruction to the second transfer subunit, the third transfer instruction instructing the first processing result in the second type of register to be stored in the first memory; the second transfer subunit, in response to the third transfer instruction, obtains the kth first processing result from the second type of register and sends the kth first processing result to the first memory; and the first memory stores the kth first processing result.

[0178] In other embodiments, the first sub-processor includes a first-type register and a second-type register, the first-type register being used to store sub-data of the first data, and the second-type register being used to store the first processing result. Based on the embodiment shown in FIG4 , the first transfer sub-unit can transfer the kth sub-data to the first-type memory. Upon obtaining the kth first processing result, the processing sub-unit sends the kth first processing result to the second-type register, which stores the kth first processing result. The second transfer sub-unit then transfers the kth first processing result stored in the second-type register to the first memory. Furthermore, upon obtaining the kth sub-data from the first-type register, the first transfer sub-unit can store the next sub-data included in the first data in the first storage into the first-type memory. This ensures that the first-type register always stores the sub-data to be processed by the processing sub-unit, thereby avoiding the situation where the processing sub-unit has to wait for the sub-data to be processed. This ensures that upon completing processing of any sub-data, the processing sub-unit can promptly obtain and process the next sub-data, thereby saving time waiting for the transmission of sub-data and thereby ensuring data processing efficiency.

[0179] For example, when the first data is stored in the first memory, according to the embodiment shown in FIG4 , the first transfer subunit, in response to the second transfer instruction, transfers the first sub-data of the first data from the first memory to the first-type register. The processing subunit, in response to the second processing instruction, retrieves the first sub-data from the first-type register, processes the first sub-data, obtains the first first processing result, and stores the first first processing result in the second-type register. Furthermore, once the processing subunit retrieves the first sub-data from the first-type register, the first transfer subunit immediately transfers the second sub-data of the first data from the first memory to the first-type register, so that the first-type register stores the next sub-data to be processed by the processing subunit. This allows the processing subunit to retrieve and process the second sub-data from the first-type register while storing the first first processing result in the second-type register. Furthermore, the second transfer subunit, in response to the third transfer instruction, transfers the first first processing result stored in the second-type register to the first memory. Once the next first processing result is stored in the second-type register, the processing subunit immediately transfers the newly stored first processing result to the first memory.

[0180] In some embodiments, the first sub-processor includes multiple first-class registers and multiple second-class registers, and the first processing unit includes first transport sub-units equal to the number of first-class registers and second transport sub-units equal to the number of second-class registers, each first transport sub-unit corresponds to a first-class register, and each second transport sub-unit corresponds to a second-class register.

[0181] In some embodiments, the processing sub-unit obtains the i+1th sub-data from the first type of register included in the first sub-processor; runs the first function to process the i+1th sub-data, obtains the i+1th first processing result, sends the i+1th first processing result to the second type of register included in the first sub-processor, and the second type of register stores the i+1th first processing result; the second transport sub-unit obtains the i+1th first processing result from the second type of register, and sends the i+1th first processing result to the first memory; the first memory stores the i+1th first processing result.

[0182] In an embodiment of the present application, multiple first transfer sub-units can sequentially transfer multiple sub-data in the first data from the first memory to the corresponding first-class registers. The processing sub-unit sequentially obtains and processes the sub-data from each first-class register in the order of the multiple first-class registers, and stores the obtained first processing results in the multiple second-class registers in the order of the multiple second-class registers. Furthermore, when the sub-data in any first-class register is obtained by the processing sub-unit, the corresponding first transfer sub-unit obtains the next sub-data from the first memory and stores it in the first-class memory, so that each first register always stores the sub-data that has not been processed by the processing sub-unit.

[0183] In an embodiment of the present application, taking into account the possibility that the processing sub-unit is efficient in processing sub-data, while the first transport sub-unit is inefficient in transporting the sub-data from the first memory to the first type of register, multiple first type registers and multiple second type registers are set to ensure that after the processing sub-unit completes processing of any sub-data, it can promptly obtain and process the next sub-data from the first type register, thereby ensuring data processing efficiency.

[0184] For example, the first sub-processor includes two first-class registers and two second-class registers, and the first processing unit includes two first transfer sub-units and two second transfer sub-units. The first first transfer sub-unit responds to the second transfer instruction and transfers the first sub-data to the first first-class register, and the second first transfer sub-unit responds to the second transfer instruction and transfers the second sub-data to the second first-class register. The processing sub-unit obtains the first sub-data from the first first-class register and processes it, and the first first transfer sub-unit immediately transfers the third sub-data to the first first-class register. After the processing sub-unit obtains the first first processing result, it stores the first first processing result in the first second-class register, and the first second transfer sub-unit responds to the third transfer instruction and transfers the first first processing result from the first second-class register to the first memory. After the processing sub-unit has sent the first first processing result to the first second-category register, it retrieves and processes two sub-data from the second first-category register. The second first transfer sub-unit then immediately transfers the fourth sub-data to the second first-category register. After obtaining the second first processing result, the processing sub-unit stores the second first processing result in the second second-category register. The second second transfer sub-unit, in response to the third transfer instruction, transfers the second first processing result from the second second-category register to the first memory. After the processing sub-unit has sent the second first processing result to the second second-category register, it retrieves and processes three sub-data from the first first-category register. This continues in this manner until n sub-data are processed and n first processing results are transferred to the first memory.

[0185] Based on the embodiment shown in FIG2 above, in an embodiment of the present application, when the first processing unit obtains the first processing result, the data transfer unit can also transfer the first processing result to other memories. The specific process is detailed in the following embodiment.

[0186] Figure 5 is a flowchart of another data processing method provided in an embodiment of the present application. The method is executed by a processor, and the processor includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions. As shown in Figure 5, the method includes the following steps.

[0187] 501. The first control unit sends a data acquisition instruction to the data handling unit in response to the first processing instruction. The data acquisition instruction instructs to acquire first data. The first data is the data to be processed indicated by the first processing instruction. The first control unit is included in the first sub-processor of the plurality of sub-processors.

[0188] 502. The data handling unit obtains first data in response to a data acquisition instruction, and sends the first data to the first sub-processor.

[0189] 503. The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data.

[0190] 504. The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result.

[0191] It should be noted that steps 501 to 504 are similar to the above steps 201 to 204 and will not be described in detail here.

[0192] 505. The first control unit sends a fourth transfer instruction to the data transfer unit.

[0193] In an embodiment of the present application, after the first processing unit completes processing of the first data, the first control unit can control the data transport unit to store the first processing result in other memories so that other sub-processors can process the first processing result again, thereby ensuring the implementation of data transmission without the need for other sub-processors to wait.

[0194] The fourth transfer instruction instructs the data transfer unit to transfer the first processing result to the third memory. In some embodiments, the fourth transfer instruction indicates a storage location in the third memory, which indicates the location in the third memory where the first processing result is stored.

[0195] In some embodiments, step 505 includes: the first control unit generates a fourth transport unit based on the first processing instruction, and sends the fourth transport instruction to the data transport unit.

[0196] In an embodiment of the present application, the first processing instruction also indicates the storage location of the first processing result obtained by processing the first data. Based on the first processing instruction, a fourth transport unit is generated to instruct the data transport unit where to transport the first processing result.

[0197] In some embodiments, step 505 includes: the first control unit generates a fourth transport unit in response to the first processing result obtained by the first sub-processor based on the first processing instruction, and sends the fourth transport instruction to the data transport unit.

[0198] In an embodiment of the present application, the first sub-processor obtains the first processing result. At this time, the data transfer unit is able to transfer the first processing result. Therefore, the first control unit will send a fourth transfer instruction to the data transfer unit to ensure the real-time transfer of the first processing result by the data transfer unit.

[0199] 506. The data transfer unit obtains a first processing result from the first sub-processor in response to the fourth transfer instruction, and sends the first processing result to a third memory so that the third memory stores the first processing result. The third memory is included in a third sub-processor of the multiple sub-processors.

[0200] In an embodiment of the present application, the third memory can be a memory in the third sub-processor or an external memory, and the external memory is a memory other than the memory in the processor. In the case where the third memory is a memory in the third sub-processor, the data transfer unit transfers the first processing result to the third memory, so that the first processing result is used as input data of the third sub-processor, and the processing unit in the third processor runs a function to process the first processing result. In the case where the third memory is an external memory, the other sub-processors no longer process the first processing result, or the other sub-processors obtain the first processing result from the external memory and process it.

[0201] It should be noted that the embodiment of the present application is described by taking the fourth transfer instruction sent by the first control unit as an example, while in another embodiment, the third memory is the memory in the third sub-processor, and the fourth transfer instruction is sent by the control unit in the third sub-processor.

[0202] It should be noted that the embodiment of the present application is described by taking the example of the first sub-processor obtaining the first processing result and the data transfer unit transferring the first processing result to the third memory. In another embodiment, there is no need to execute the above steps 505-506, but other methods are adopted, and the first sub-processor stores the first processing result, or other methods are adopted to transfer the first processing result.

[0203] According to the solution provided in the embodiment of the present application, after the first processing unit completes processing of the first data, the first control unit can control the data transport unit to store the first processing result in other memories so that other sub-processors can process the first processing result again, thereby ensuring the embodiment of data transmission without the need for other sub-processors to wait, thereby improving processing efficiency.

[0204] Based on the embodiment shown in Figure 2, in an embodiment of the present application, after the first sub-processor processes the first data to obtain the first processing result, the data transfer unit will transfer the first processing result to the second sub-processor. The first processing result serves as input data for the second sub-processor, and the second sub-processor processes the first processing result. The specific process is detailed in the following embodiment.

[0205] Figure 6 is a flowchart of another data processing method provided in an embodiment of the present application. The method is executed by a processor, and the processor includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions; as shown in Figure 6, the method includes the following steps.

[0206] 601. The first control unit sends a data acquisition instruction to the data handling unit in response to the first processing instruction. The data acquisition instruction instructs to obtain first data. The first data is the data to be processed indicated by the first processing instruction. The first control unit is included in the first sub-processor of the plurality of sub-processors.

[0207] 602. The data handling unit obtains first data in response to a data acquisition instruction, and sends the first data to the first sub-processor.

[0208] 603. The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, where the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data.

[0209] It should be noted that steps 601 to 603 are similar to the above steps 201 to 203 and will not be described in detail here.

[0210] 604. The first processing unit runs the first function in response to the second processing instruction to process the i-th sub-data in the first data, and obtains the i-th first processing result, where i is an integer greater than 0 and less than n, and n is the number of sub-data included in the first data, and n is an integer greater than 1.

[0211] In an embodiment of the present application, due to the large amount of first data, the first processing unit will process the first data in batches, processing only one sub-data of the first data at a time, so as to avoid the first processing unit being blocked due to excessive amount of first data, thereby ensuring data processing efficiency.

[0212] 605. The first processing unit runs the first function to process the (i+1)th sub-data in the first data to obtain the (i+1)th first processing result.

[0213] For example, the first processing unit responds to the second processing instruction, extracts the first sub-data from the first data, runs the first function to process the first sub-data in the first data, and obtains the first first processing result; extracts the second sub-data from the remaining first data, runs the first function to process the second sub-data in the first data, and obtains the second first processing result, and so on. The first processing result corresponding to each sub-data in the first data can be obtained, that is, n first processing results are obtained.

[0214] In some embodiments, the n sub-data included in the first data are pre-split, or are split by the first sub-processor when processing the first data.

[0215] In some embodiments, the first data is split when the first sub-processor processes the first data, then step 604 includes: the first processing unit responds to the second processing instruction, extracts the i-th sub-data from the first data, runs the first function to process the i-th sub-data in the first data, and obtains the i-th first processing result.

[0216] In an embodiment of the present application, since the amount of data that the first processing unit can process each time is smaller than the amount of the first data, when processing the first data, the first data is divided into multiple batches, and part of the data is extracted from the first data each time as a sub-data, so as to avoid the first processing unit from processing the first data with too large a data amount and causing congestion, thereby ensuring data processing efficiency.

[0217] In some embodiments, the data size of the i-th sub-data extracted from the first data is a first data size, and the first data size is a data size that can be processed by the first processing unit at a single time.

[0218] For example, in response to the second processing instruction, the first processing unit extracts data of the first data amount from the first data as the first sub-data, runs the first function to process the first sub-data in the first data, and obtains the first first processing result; extracts data of the first data amount from the remaining first data as the second sub-data, runs the first function to process the second sub-data in the first data, and obtains the second first processing result, and so on. The first processing result corresponding to each sub-data in the first data can be obtained, that is, n first processing results are obtained.

[0219] It should be noted that the embodiment of the present application is described by taking the example of the first processing unit processing the first data in multiple batches. In another embodiment, there is no need to execute the above steps 604-605, but other methods are adopted. The first processing unit responds to the second processing instruction, runs the first function to process the first data, and obtains the first processing result.

[0220] 606. When the first processing unit obtains the jth first processing result, the data transfer unit responds to the first transfer instruction, obtains the jth first processing result from the first sub-processor, and sends the jth first processing result to the second sub-processor, where j is an integer greater than 0 and not greater than n.

[0221] In an embodiment of the present application, the first sub-processor processes the first data and obtains the first processing result. The first processing result is used as input data for the second sub-processor, and the second sub-processor processes the first processing result. In this case, the first sub-processor processes the first data in batches, and when the first processing result corresponding to any sub-data is obtained, the data transfer unit transfers the obtained first processing result to the second sub-processor for processing. When the first sub-processor processes the first data, the second sub-processor can synchronously process the first processing result. This allows the second sub-processor to process the first data without having to wait for the first sub-processor to complete processing the first data before processing. This can save waiting time and ensure data processing efficiency.

[0222] In some embodiments, the method of sending the first transport instruction to the data transport unit includes: the first control unit sending the first transport instruction to the data transport unit based on the first processing instruction; or the second control unit sending the first transport instruction to the data transport unit.

[0223] In an embodiment of the present application, when the first processing result output by the first sub-processor is input data of the second sub-processor, if the first processing instruction received by the first control unit indicates that the first processing result is to be transferred to the second sub-processor, the first control unit sends the first transfer instruction to the data transfer unit based on the first processing instruction; if the fourth processing instruction received by the second control unit indicates that the first processing result is to be obtained from the first sub-processor, the second control unit sends the first transfer instruction to the data transfer unit based on the fourth processing instruction. The present application provides multiple ways to trigger the first transfer instruction, which can be applied to multiple situations to ensure that the subsequent data transfer unit can transfer data based on the first transfer instruction and ensure the normal operation of the processor.

[0224] The second control unit is included in the second sub-processor of the multiple sub-processors.

[0225] In some embodiments, the processor includes a central control unit. During the process of running the network model on data, the central control unit can distribute processing instructions to the control units in each sub-processor, so that each sub-processor can process the data based on the processing instructions, thereby implementing the network model to process the data. That is, the central control unit will send a first processing instruction to the first control unit and a fourth processing instruction to the second control unit, so that after the first sub-processor completes processing of the first data, the data transfer unit will transfer the first processing result to the second sub-processor, and the second sub-processor will process the first processing result.

[0226] In an embodiment of the present application, a central control unit controls each sub-processor to process data so that each sub-processor can cooperate with each other to implement a network model data processing solution, and only multiple sub-processors need to interact with each other, without the need to interact with the memory outside the processor, saving the time required for data transmission to improve data processing efficiency.

[0227] 607. When the second processing unit receives the third processing instruction and the second sub-processor receives the j-th first processing result, the second processing unit runs the second function to process the j-th first processing result to obtain the j-th second processing result. The third processing instruction instructs running the second function to process the first processing result. The third processing instruction is sent by the second control unit. The second sub-processor includes the second processing unit and the second control unit.

[0228] The second function belongs to the type of function executed by the second processing unit. The process of the second processing unit executing the second function to process the j-th first processing result is similar to the process of the first processing unit executing the first function to process the j-th sub-data, and will not be repeated here.

[0229] In some embodiments, the process of the second control unit sending the third processing instruction to the second processing unit includes: the second control unit sending the third processing instruction to the second processing unit based on the fourth processing instruction.

[0230] Among them, the fourth processing instruction is the same as the first processing instruction received by the above-mentioned first control unit, the third processing instruction is the same as the second processing instruction sent to the above-mentioned first processing unit, and the process of the second control unit sending the third processing instruction to the second processing unit based on the fourth processing instruction is the same as the process of the first control unit sending the second processing instruction to the first processing unit based on the first processing instruction, which will not be repeated here.

[0231] In some embodiments, a method for determining that the second sub-processor has received the jth first processing result includes: the second sub-processor includes a memory, the data transfer unit transfers the jth first processing result to the memory, and determining that the second sub-processor has received the jth first processing result. The memory is used to store input data of the second sub-processor.

[0232] In an embodiment of the present application, the first sub-processor processes the first data and obtains the first processing result. The first processing result is used as input data for the second sub-processor, and the second sub-processor processes the first processing result. In this case, the first sub-processor processes the first data in batches, and when the first processing result corresponding to any sub-data is obtained, the data transfer unit transfers the obtained first processing result to the second sub-processor for processing. When the first sub-processor processes the first data, the second sub-processor can synchronously process the first processing result. This allows the second sub-processor to process the first data without waiting for the first sub-processor to complete processing the first data before processing. This can save waiting time, avoid idle processing resources, and ensure data processing efficiency.

[0233] In addition, there is a flexible data path between the first processing unit and the second processing unit. Regardless of the combination of the first function and the second function, or the combination of the second function and the first function, data can interact directly within the processor, reducing access to the processor's external memory, thereby saving data access time and improving data processing efficiency.

[0234] For example, in AI business scenarios, the network layer of the network model corresponds to two types of functions, that is, the network layer of the network model corresponds to two types of operators. One is a matrix-type operator based on two-dimensional matrix operations, such as a convolution operator or a matrix multiplication operator. The other is a vector-type operator based on one-dimensional vector operations, such as a fully connected operator, a transposition operator, a fusion operator, an expansion operator, or a data transformation operator. In the network model, the network layers corresponding to these two operators may be adjacent, that is, the output of the matrix-type operator is the input of the vector-type operator, or the output of the vector-type operator is the input of the matrix-type operator, such as the combination of Convolution (convolution) + Relu (activation function) in the network model; or the combination of Convolution (convolution) + Max Pooling (maximum pooling), where Convolution is a matrix-type operator and Relu and Max Pooling are vector-type operators. The first sub-processor runs Convolution to process the first data, and the second sub-processor runs Relu to process the first processing result. Alternatively, the first sub-processor runs Convolution to process the first data, and the second sub-processor runs Max Pooling to process the first processing result.

[0235] It should be noted that the embodiment shown in FIG6 is merely an example of the first processing unit processing the first data and the second processing unit processing the first processing result. In another embodiment, the first processing unit may also need other data when processing the first data. The first processing unit processes the first data and the other data, and the data transfer unit obtains the other data from the external memory or the memory included in other sub-processors and sends the other data to the first sub-processor. Similarly, the second processing unit may also need other data when processing the first processing result. The second processing unit processes the first processing result and the other data. The data transfer unit obtains the other data from the external memory or the memory included in other sub-processors and sends the other data to the second sub-processor.

[0236] It should be noted that the embodiment shown in Figure 6 above is only illustrated by taking the first processing result output by the first sub-processor as the input data of the second sub-processor as an example. In another embodiment, the second processing result output by the second sub-processor is the input data of other sub-processors, and data transmission and data processing can be performed according to the embodiment shown in Figure 6 above.

[0237] In some embodiments, when the first sub-processor completes processing of the nth sub-data of the first data, the first sub-processor, in response to a fifth processing instruction, uses the second processing result output by the second sub-processor as input data and executes a third function to process the second processing result. The fifth processing instruction instructs executing the third function to process the second processing result.

[0238] It should be noted that the embodiments shown in Figures 2 to 6 above can be combined arbitrarily. For example, taking the example of a processor including two sub-processors, the two sub-processors being a matrix operator processor and a vector operator processor, the structure of the processor is shown in Figure 7. The processor includes multiple data paths: (1) a data path from an external memory to a matrix input memory; (2) a data path from an external memory to a vector memory; (3) a data path from a matrix output memory to a matrix input memory; (4) a data path from a matrix output memory to an external memory; (5) a data path from a matrix output memory to a vector memory; (6) a data path from a vector memory to an external memory; and (7) a vector memory to a matrix input memory. By flexibly switching data paths through the data handling unit, different sub-processors can be supported to run different types of functions and interact within the processor, i.e., matrix operators and vector operators interact with each other within the processor; or, vector operators and matrix operators interact with each other within the processor.

[0239] When the first sub-processor is a matrix operator processor, the matrix operator processor includes a matrix input memory, a matrix operation unit, a matrix input memory, and a control unit. The first memory is a matrix input memory, the first processing unit is a matrix operation unit, the first processing unit is used to run a convolution function or a matrix multiplication function, and the second memory is a matrix output memory. When the first sub-processor is a vector operator processor, the quantity operator processor includes a vector memory, a register, a vector operation unit, and a control unit. The first memory is a vector memory, and the first processing unit is a vector operation unit.

[0240] In the case where the processor includes a matrix operator processor and a vector operator processor, as shown in Figure 8, the process of processing data by the matrix operator processor includes: the data handling unit transfers data from the processor's external memory to the matrix input memory; the matrix operation unit reads data from the matrix input memory, processes the data, and writes the processing result back to the matrix output memory; the data handling unit transfers the processing result in the matrix output memory to the external memory. The process of processing data by the vector operator processor includes: the data handling unit transfers data from the processor's external memory to the vector memory; the load unit in the vector operation unit transfers data in the vector memory to the register; the vector operation unit reads data from the register, processes the data, and writes the processing result back to the register; the store unit in the vector operation unit transfers the processing result in the register to the vector memory; and the data handling unit transfers the processing result from the vector memory to the external memory.

[0241] Taking the first sub-processor as a matrix operator processor and the second sub-processor as a vector operator processor as an example, as shown in Figure 9, the process of data processing by the matrix operator processor and the vector operator processor includes: the data handling unit handles data from the external memory of the processor to the matrix input memory; the matrix operation unit reads data from the matrix input memory, processes the data, and writes the processing result back to the matrix output memory; the data handling unit handles the processing result in the matrix output memory to the vector memory; the Load unit in the vector operation unit handles the data in the vector memory to the register; the vector operation unit reads data from the register, processes the data, and writes the processing result back to the register; the Store unit in the vector operation unit handles the processing result in the register to the vector memory; the data handling unit handles the processing result from the vector memory to the external memory.

[0242] Compared to independent matrix and vector operator processors, the matrix and vector operator processors work together to process the first data, achieving the fusion of matrix and vector operators. That is, the matrix and vector operator processors work together to run the fusion operator to process data, and the data flow within the matrix and vector operator processors during the processing process is the same as the data flow when the matrix and vector operator processors process data independently, ensuring that independent operators can quickly adapt to the fusion operator. This design ensures that the matrix and vector operator processors can quickly exchange data without going through external memory.

[0243] Taking the first sub-processor as a vector operator processor and the second sub-processor as a matrix operator processor as an example, as shown in Figure 10, the process of data processing by the vector operator processor and the matrix operator processor includes: the data handling unit handles data from the external memory of the processor to the vector memory; the Load unit in the vector operation unit handles the data in the vector memory to the register; the vector operation unit reads data from the register, processes the data, and writes the processing result back to the register; the Store unit in the vector operation unit handles the processing result in the register to the vector memory; the data handling unit handles the processing result from the vector memory to the matrix input memory; the matrix operation unit reads data from the matrix input memory, processes the data, and writes the processing result back to the matrix output memory; the data handling unit handles the processing result in the matrix output memory to the external memory.

[0244] Compared to independent vector and matrix operator processors, the vector and matrix operator processors collaboratively process the first data, achieving the fusion of vector and matrix operators. That is, the vector and matrix operator processors collaboratively run the fused operator to process data, and the data flow within the vector and matrix operator processors during the processing process is the same as when the vector and matrix operator processors independently process data, ensuring that independent operators can quickly adapt to the fused operator. This design ensures that the vector and matrix operator processors can quickly exchange data without going through external memory.

[0245] The data processing method provided in the embodiments of the present application can be applied in a variety of scenarios, for example, in image processing scenarios, speech processing scenarios, etc. Taking the application in the image processing scenario as an example, the network model is an image processing model, the processor loads the image processing model, obtains the functions corresponding to each network layer in the image processing model and the connection relationship between the network layers, and determines the execution order between each function. In response to receiving an image processing instruction, the image processing instruction indicates an image to be processed. The processor determines a fifth sub-processor that runs a function corresponding to the first network layer and sends a processing instruction to the fifth sub-processor, so that the fifth sub-processor processes the image and outputs a processing result according to the embodiments shown in Figures 2 to 6 above. The processor determines a sixth sub-processor that runs a function corresponding to the second network layer and sends a processing instruction to the sixth sub-processor, so that the sixth processor processes the data output by the fifth sub-processor. Similarly, in response to the image processing instruction, the processor can control multiple sub-processors to run functions corresponding to each network layer in the image processing model to process data. When any sub-processor runs the function corresponding to the last network layer in the image processing model and outputs a processing result, it means that the image processing model has completed image processing. The processing result output by running the function corresponding to the last network layer in the image processing model is the final image processing result. The final image processing result is stored in the memory of the corresponding sub-processor, or the data transfer unit transfers the final image processing result to an external memory so that a user can subsequently obtain the final image processing result from the external memory through the device.

[0246] FIG11 is a schematic diagram of the structure of another processor provided in an embodiment of the present application. As shown in FIG11 , the processor includes multiple sub-processors and a data handling unit 1101. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions.

[0247] A first control unit 1102 is configured to send a data acquisition instruction to the data handling unit 1101 in response to the first processing instruction, where the data acquisition instruction instructs the acquisition of first data, where the first data is the data to be processed indicated by the first processing instruction. The first control unit 1102 is included in a first sub-processor 1103 of the plurality of sub-processors;

[0248] The data handling unit 1101 is configured to obtain first data in response to a data obtaining instruction and send the first data to the first sub-processor 1103;

[0249] A first control unit 1102 is configured to send a second processing instruction to a first processing unit 1104 based on the first processing instruction, where the first processing unit 1104 is included in the first sub-processor 1103, and the second processing instruction instructs to execute a first function to process the first data;

[0250] The first processing unit 1104 is configured to execute a first function to process the first data in response to the second processing instruction to obtain a first processing result.

[0251] In some embodiments, as shown in FIG. 12 or 13 , the first processing unit 1104 is configured to, in response to the second processing instruction, execute the first function to process the i-th sub-data in the first data to obtain the i-th first processing result, where i is an integer greater than 0 and less than n, and n is the number of sub-data included in the first data, where n is an integer greater than 1; and execute the first function to process the i+1-th sub-data in the first data to obtain the i+1-th first processing result;

[0252] The data handling unit 1101 is also used to, when the first processing unit 1104 obtains the jth first processing result, respond to the first handling instruction, obtain the jth first processing result from the first sub-processor 1103, and send the jth first processing result to the second sub-processor 1105, where j is an integer greater than 0 and not greater than n.

[0253] In some embodiments, as shown in Figure 12 or 13, the second processing unit 1106 is used to run the second function to process the jth first processing result to obtain the jth second processing result when the third processing instruction is received and the second sub-processor 1105 receives the jth first processing result. The third processing instruction instructs to run the second function to process the first processing result. The third processing instruction is sent by the second control unit 1107. The second sub-processor 1105 includes the second processing unit 1106 and the second control unit 1107.

[0254] In some embodiments, as shown in FIG. 12 or 13 , the first control unit 1102 is further configured to send a first transport instruction to the data transport unit 1101 based on the first processing instruction; or

[0255] The second control unit 1107 is further configured to send a first transport instruction to the data transport unit 1101 .

[0256] In some embodiments, as shown in FIG12 or 13 , the data handling unit 1101 is configured to send first data to a first memory 1108 , which is included in the first sub-processor 110 ;

[0257] A first memory 1108, configured to store first data;

[0258] The first processing unit 1104 is configured to obtain first data from the first memory 1108 in response to the second processing instruction; and execute a first function to process the first data to obtain a first processing result.

[0259] In some embodiments, as shown in FIG12 , the first processing unit 1104 includes a processing sub-unit 1109 and a first transfer sub-unit 1110 . The first transfer sub-unit 1110 is configured to transfer data in the first memory 1108 to a register 1111 included in the first sub-processor 1103 .

[0260] The first control unit 1102 is further configured to send a second transport instruction to the first transport sub-unit 1110 based on the first processing instruction, where the second transport instruction instructs to store the first data in the first memory 1108 into the register 1111;

[0261] The first transfer sub-unit 1110 is configured to, in response to the second transfer instruction, obtain the kth sub-data included in the first data from the first memory 1108 and send the kth sub-data to the register 1111. The amount of the sub-data is equal to the amount of data corresponding to the storage space of the register 1111, where k is an integer greater than 0 and not greater than n, and n is the number of sub-data included in the first data.

[0262] Register 1111, used for storing the kth sub-data;

[0263] The processing sub-unit 1109 is configured to, in response to the second processing instruction, obtain the kth sub-data from the register 1111 , run the first function to process the kth sub-data, and obtain the kth first processing result.

[0264] In some embodiments, as shown in FIG12 , the first processing unit 1104 further includes a second transfer subunit 1112 , and the second transfer subunit 1112 is configured to transfer data in the register 1111 to the first memory 1108 ;

[0265] The processing subunit 1109 is further configured to send the kth first processing result to the register 1111;

[0266] Register 1111, used to store the kth first processing result;

[0267] The first control unit 1102 is further configured to send a third transport instruction to the second transport sub-unit 1112 , where the third transport instruction instructs the first processing result in the register 1111 to be stored in the first memory 1108 ;

[0268] The second transfer subunit 1112 is configured to obtain the kth first processing result from the register 1111 in response to the third transfer instruction, and send the kth first processing result to the first memory 1108;

[0269] The first memory 1108 is further used to store the kth first processing result.

[0270] In some embodiments, as shown in FIG13 , the first processing unit 1104 is further configured to send the first processing result to the second memory 1113 , where the second memory 1113 is a memory included in the first sub-processor 1103 ;

[0271] The second memory 1113 is also used to store the first processing result.

[0272] In some embodiments, the first control unit 1102 is further configured to send a fourth transport instruction to the data transport unit 1101;

[0273] The data transfer unit 1101 is also used to respond to the fourth transfer instruction, obtain the first processing result from the first sub-processor 1103, and send the first processing result to the third memory so that the third memory stores the first processing result. The third memory is included in the third sub-processor of the multiple sub-processors.

[0274] In some embodiments, the data handling unit 1101 is used to obtain first data from a memory included in a fourth sub-processor in response to a data acquisition instruction, where the fourth sub-processor is any sub-processor among multiple sub-processors except the first sub-processor 1103; or, in response to a data acquisition instruction, obtain first data from an external memory, where the external memory is a memory other than the memory in the processor.

[0275] In some embodiments, the first control unit 1102 is configured to send a second processing instruction to the first processing unit 1104 based on the first processing instruction in response to the first sub-processor 1103 receiving the first data.

[0276] It should be noted that the processor and data processing method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, which will not be repeated here.

[0277] An embodiment of the present application further provides a computer device, which includes a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the data processing method of the above embodiment.

[0278] In some embodiments, the computer device is provided as a terminal device. FIG14 shows a block diagram of a terminal device 1400 provided in an exemplary embodiment of the present application. The terminal device 1400 includes: a processor 1401 and a memory 1402.

[0279] Processor 1401 includes multiple sub-processors and a data handling unit. Each sub-processor includes a control unit and a processing unit. The processing units in different sub-processors are used to run different types of functions. Processor 1401 includes one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 1401 can be implemented using at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). Processor 1401 can also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, processor 1401 can be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, processor 1401 can also include an AI (Artificial Intelligence) processor, which is responsible for processing computing operations related to machine learning.

[0280] The memory 1402 may include one or more computer-readable storage media, which may be non-transitory. The memory 1402 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1402 is used to store at least one computer program, which is executed by the processor 1401 to implement the data processing method provided in the method embodiment of the present application.

[0281] In some embodiments, terminal device 1400 may optionally include a peripheral device interface 1403 and at least one peripheral device. Processor 1401, memory 1402, and peripheral device interface 1403 may be connected via a bus or signal lines. Each peripheral device may be connected to peripheral device interface 1403 via a bus, signal lines, or circuit boards. Specifically, the peripheral device may include at least one of a radio frequency circuit 1404, a display screen 1405, a camera assembly 1406, an audio circuit 1407, and a power supply 1408.

[0282] The peripheral device interface 1403 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 1401 and the memory 1402. In some embodiments, the processor 1401, the memory 1402, and the peripheral device interface 1403 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1401, the memory 1402, and the peripheral device interface 1403 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0283] RF circuit 1404 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. RF circuit 1404 communicates with communication networks and other communication devices via electromagnetic signals. RF circuit 1404 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. In some embodiments, RF circuit 1404 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. RF circuit 1404 can communicate with other terminal devices via at least one wireless communication protocol. Such wireless communication protocols include, but are not limited to, the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, RF circuit 1404 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0284] The display screen 1405 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1405 is a touch screen display, the display screen 1405 also has the ability to collect touch signals on the surface or above the surface of the display screen 1405. The touch signal can be input as a control signal to the processor 1401 for processing. At this time, the display screen 1405 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, there can be one display screen 1405, which is set on the front panel of the terminal device 1400; in other embodiments, there can be at least two display screens 1405, which are respectively set on different surfaces of the terminal device 1400 or in a folding design; in other embodiments, the display screen 1405 can be a flexible display screen, which is set on the curved surface or folding surface of the terminal device 1400. Even more, the display screen 1405 can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 1405 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0285] The camera assembly 1406 is used to capture images or videos. In some embodiments, the camera assembly 1406 includes a front camera and a rear camera. The front camera is arranged on the front panel of the terminal device, and the rear camera is arranged on the back of the terminal device. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1406 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0286] The audio circuit 1407 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals that are input into the processor 1401 for processing, or input into the radio frequency circuit 1404 to achieve voice communication. For the purpose of stereo sound collection or noise reduction, there can be multiple microphones, each located in different parts of the terminal device 1400. The microphone can also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert the electrical signal from the processor 1401 or the radio frequency circuit 1404 into sound waves. The speaker can be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1407 may also include a headphone jack.

[0287] Power supply 1408 is used to power various components in terminal device 1400. Power supply 1408 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1408 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is charged via a wired line, while a wireless rechargeable battery is charged via a wireless coil. The rechargeable battery can also support fast charging technology.

[0288] Those skilled in the art will understand that the structure shown in FIG14 does not constitute a limitation on the terminal device 1400 , and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0289] In some embodiments, a computer device is provided as a server. Figure 15 is a structural diagram of a server provided in an embodiment of the present application. The server 1500 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1501 and one or more memories 1502. The processor 1501 includes multiple sub-processors and data handling units, each sub-processor includes a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions. Among them, at least one computer program is stored in the memory 1502, and at least one computer program is loaded and executed by the processor 1501 to implement the methods provided by the above-mentioned various method embodiments. Of course, the server may also have components such as a wired or wireless network interface, a keyboard and an input and output interface for input and output. The server may also include other components for implementing device functions, which will not be described in detail here.

[0290] An embodiment of the present application further provides a computer-readable storage medium, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor to implement the operations performed by the data processing method of the above embodiment.

[0291] An embodiment of the present application further provides a computer program product, including a computer program, which implements the operations performed by the data processing method of the above embodiment when the computer program is executed by a processor.

[0292] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0293] The above description is only an optional embodiment of the embodiment of the present application and is not intended to limit the embodiment of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiment of the present application should be included in the scope of protection of the present application.

Claims

1. A data processing method, the method is executed by a computer device, the computer device comprises a processor, the processor comprises a plurality of sub-processors and a data handling unit, each sub-processor comprises a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions; the method comprises: In response to the first processing instruction, the first control unit sends a data acquisition instruction to the data handling unit, wherein the data acquisition instruction instructs to acquire first data, the first data being the data to be processed indicated by the first processing instruction, and the first control unit is included in a first sub-processor of the plurality of sub-processors; The data handling unit acquires the first data in response to the data acquisition instruction, and sends the first data to the first sub-processor; The first control unit sends a second processing instruction to a first processing unit based on the first processing instruction, the first processing unit is included in the first sub-processor, and the second processing instruction instructs to run a first function to process the first data; The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result.

2. The method according to claim 1, wherein: The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result, including: The first processing unit executes the first function in response to the second processing instruction to process the i-th sub-data in the first data to obtain the i-th first processing result, where i is an integer greater than 0 and less than n, and n is the number of sub-data included in the first data, and n is an integer greater than 1; The first processing unit runs the first function to process the i+1th sub-data in the first data to obtain the i+1th first processing result.

3. The method according to claim 2, wherein: The method further comprises: When receiving the target processing instruction, the processor determines the first sub-processor that runs the first function based on the order of functions in the network model, and sends the first processing instruction to the first control unit. The target processing instruction instructs running the network model to process target data.

4. The method according to claim 2 or 3, wherein: The method further comprises: When the first processing unit obtains the jth first processing result, the data handling unit obtains the jth first processing result from the first sub-processor in response to the first handling instruction, and sends the jth first processing result to the second sub-processor, where j is an integer greater than 0 and not greater than n; When the second processing unit receives the third processing instruction and the second sub-processor receives the j-th first processing result, the second processing unit runs the second function to process the j-th first processing result to obtain the j-th second processing result. The third processing instruction instructs running the second function to process the first processing result. The third processing instruction is sent by the second control unit. The second sub-processor includes the second processing unit and the second control unit.

5. The method according to claim 4, wherein: The data handling unit obtains the j-th first processing result from the first sub-processor in response to the first handling instruction, and before sending the j-th first processing result to the second sub-processor, the method further includes: The first control unit sends the first handling instruction to the data handling unit based on the first processing instruction; or, The second control unit sends the first transport instruction to the data transport unit.

6. The method according to claim 4 or 5, wherein: The method further comprises: The processor determines the second sub-processor to run the second function, and sends a fourth processing instruction to the second control unit, where the fourth processing instruction instructs the second sub-processor to run the second function to process a processing result output by the first sub-processor.

7. The method according to any one of claims 2 to 6, wherein: The first processing unit runs the first function to process the i+1th sub-data in the first data to obtain the i+1th first processing result, including: The processing sub-unit obtains the i+1th sub-data from the first type register included in the first sub-processor; runs the first function to process the i+1th sub-data, obtains the i+1th first processing result, and sends the i+1th first processing result to the second type register included in the first sub-processor, and the second type register stores the i+1th first processing result; The second transport sub-unit obtains the i+1th first processing result from the second-type register, and sends the i+1th first processing result to the first memory; the first memory stores the i+1th first processing result.

8. The method according to any one of claims 1 to 7, wherein: The sending the first data to the first sub-processor includes: Sending the first data to a first memory, where the first memory is included in the first sub-processor and stores the first data; The first processing unit executes the first function in response to the second processing instruction to process the first data and obtain a first processing result, including: The first processing unit obtains the first data from the first memory in response to the second processing instruction; runs the first function to process the first data, and obtains the first processing result.

9. The method according to claim 8, wherein: The first processing unit includes a processing subunit and a first transport subunit, wherein the first transport subunit is used to transport the data in the first memory to the register included in the first subprocessor; the first processing unit obtains the first data from the first memory in response to the second processing instruction; Before running the first function to process the first data and obtaining the first processing result, the method further includes: The first control unit sends a second transport instruction to the first transport subunit based on the first processing instruction, wherein the second transport instruction instructs to store the first data in the first memory into a register; The first transport sub-unit, in response to the second transport instruction, obtains the kth sub-data included in the first data from the first memory, and sends the kth sub-data to the register, wherein the data amount of the sub-data is equal to the data amount corresponding to the storage space of the register, k is an integer greater than 0 and not greater than n, n is the number of sub-data included in the first data, and n is an integer greater than 1; the register stores the kth sub-data; The first processing unit obtains the first data from the first memory in response to the second processing instruction; and runs the first function to process the first data to obtain the first processing result, including: The processing sub-unit obtains the k-th sub-data from the register in response to the second processing instruction, runs the first function to process the k-th sub-data, and obtains the k-th first processing result.

10. The method according to claim 9, wherein: The register includes a first type of register; the first transport sub-unit, in response to the second transport instruction, obtains the kth sub-data included in the first data from the first memory, and sends the kth sub-data to the register, including: The first transport sub-unit, in response to the second transport instruction, obtains the kth sub-data included in the first data from the first memory, and sends the kth sub-data to the first type register; the first type register stores the kth sub-data; The processing sub-unit, in response to the second processing instruction, obtains the k-th sub-data from the register, and operates Executing the first function to process the k-th sub-data to obtain a k-th first processing result includes: The processing sub-unit obtains the kth sub-data from the first type of register in response to the second processing instruction; runs the first function to process the kth sub-data, and obtains the kth first processing result.

11. The method according to claim 10, wherein: The first processing unit further includes a second transport subunit, and the second transport subunit is used to transport the data in the register to the first memory; the register includes a second type of register; The processing sub-unit obtains the k-th sub-data from the first-type register in response to the second processing instruction; runs the first function to process the k-th sub-data, and after obtaining the k-th first processing result, the method further includes: The processing subunit sends the kth first processing result to the second type register; the second type register stores the kth first processing result; The first control unit sends a third transport instruction to the second transport subunit, wherein the third transport instruction instructs to store the first processing result in the second type register into the first memory; The second transport subunit obtains the kth first processing result from the second type register in response to the third transport instruction, and sends the kth first processing result to the first memory; the first memory stores the kth first processing result.

12. The method according to any one of claims 8 to 11, wherein: The first processing unit acquires the first data from the first memory in response to the second processing instruction; After running the first function to process the first data and obtaining the first processing result, the method further includes: The first processing unit sends the first processing result to a second memory, and the second memory is included in the first sub-processor; The second memory stores the first processing result.

13. The method according to any one of claims 1 to 12, wherein: After the first processing unit executes the first function to process the first data in response to the second processing instruction and obtains a first processing result, the method further includes: The first control unit sends a fourth transport instruction to the data transport unit; The data transfer unit obtains the first processing result from the first sub-processor in response to the fourth transfer instruction, and sends the first processing result to a third memory so that the third memory stores the first processing result. The third memory is included in a third sub-processor of the at least multiple sub-processors.

14. The method according to any one of claims 1 to 13, wherein: The data handling unit acquires the first data in response to the data acquisition instruction, including: The data handling unit acquires the first data from a memory included in a fourth sub-processor in response to the data acquisition instruction, and the fourth sub-processor is any sub-processor among the plurality of sub-processors except the first sub-processor; or The data transport unit acquires the first data from an external memory in response to the data acquisition instruction, where the external memory is a memory other than the memory in the processor.

15. The method according to any one of claims 1 to 14, wherein: The first control unit sends a second processing instruction to the first processing unit based on the first processing instruction, including: In response to the first sub-processor receiving the first data, the first control unit sends a second processing instruction to the first processing unit based on the first processing instruction.

16. A processor, comprising a plurality of sub-processors and a data handling unit, each sub-processor comprising a control unit and a processing unit, and the processing units in different sub-processors are used to run different types of functions; A first control unit, configured to send a data acquisition instruction to the data handling unit in response to a first processing instruction, wherein the data acquisition instruction instructs to acquire first data, the first data being data to be processed indicated by the first processing instruction, and the first control unit is included in a first sub-processor of the plurality of sub-processors; The data handling unit is configured to obtain the first data in response to the data obtaining instruction, and send the first data to the first sub-processor; The first control unit is configured to send a second processing instruction to a first processing unit based on the first processing instruction, the first processing unit being included in the first sub-processor, the second processing instruction instructing to execute a first function to process the first data; The first processing unit is used to execute the first function to process the first data in response to the second processing instruction to obtain a first processing result.

17. The processor of claim 16, wherein: The first processing unit is used to respond to the second processing instruction, run the first function to process the i-th sub-data in the first data, and obtain the i-th first processing result, where i is an integer greater than 0 and less than n, and n is the number of sub-data included in the first data, and n is an integer greater than 1; run the first function to process the i+1-th sub-data in the first data, and obtain the i+1-th first processing result.

18. The processor of claim 17, wherein: The processor further comprises: The data transfer unit is further configured to, when the first processing unit obtains the jth first processing result, obtain the jth first processing result from the first sub-processor in response to the first transfer instruction, and send the jth first processing result to the second sub-processor, where j is an integer greater than 0 and not greater than n; A second processing unit is used to run a second function to process the jth first processing result to obtain a jth second processing result when a third processing instruction is received and the second sub-processor receives the jth first processing result, wherein the third processing instruction instructs running the second function to process the first processing result, and the third processing instruction is sent by a second control unit, and the second sub-processor includes the second processing unit and the second control unit.

19. The processor of claim 18, wherein: The first control unit is further configured to send the first handling instruction to the data handling unit based on the first processing instruction; or The second control unit is used to send the first transport instruction to the data transport unit.

20. The processor of claim 16, wherein: The data transport unit is configured to send the first data to a first memory, where the first memory is included in the first sub-processor; The first memory is used to store the first data; The first processing unit is configured to obtain the first data from the first memory in response to the second processing instruction; Run the first function to process the first data and obtain the first processing result.

21. The processor of claim 20, wherein: The first processing unit includes a processing subunit and a first transport subunit, and the first transport subunit is used to transport the data in the first memory to the register included in the first sub-processor; The first control unit is further configured to send a second transport instruction to the first transport subunit based on the first processing instruction, wherein the second transport instruction instructs storing the first data in the first memory into a register; The first transport sub-unit is used to, in response to the second transport instruction, obtain the kth sub-data included in the first data from the first memory, and send the kth sub-data to the register, wherein the data amount of the sub-data is equal to the data amount corresponding to the storage space of the register, k is an integer greater than 0 and not greater than n, n is the number of sub-data included in the first data, and n is an integer greater than 1; The register is used to store the k-th sub-data; The processing sub-unit is used to obtain the kth sub-data from the register in response to the second processing instruction, run the first function to process the kth sub-data, and obtain the kth first processing result.

22. The processor of claim 21, wherein: The first processing unit further includes a second transport subunit, and the second transport subunit is used to transport the data in the register to the first memory; The processing subunit is further used to send the kth first processing result to the register; The register is used to store the kth first processing result; The first control unit is further used to send a third transport instruction to the second transport subunit, wherein the third transport instruction instructs to store the first processing result in the register into the first memory; The second transport subunit is configured to obtain the kth first processing result from the register in response to the third transport instruction, and send the kth first processing result to the first memory; The first memory is also used to store the kth first processing result.

23. The processor of claim 20, wherein: The first processing unit is further configured to send the first processing result to a second memory, wherein the second memory is included in the first sub-processor; The second memory is also used to store the first processing result.

24. A computer device, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the operations performed by the data processing method according to any one of claims 1 to 15.

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