Improved stack structure and method of manufacture thereof for retention of low resistive state (LRS) of a resistive random- access memory (RERAM)

Abstract

A resistive random-access memory (ReRAM) comprises a resistive cell that toggles between low-resistive state (LRS) after a SET, or at a high-resistive state (HRS) after a RESET. The resistive filament thereof risks recombination of vacant oxygen of a resistive layer and oxygen in a scavenging layer. As a result of the recombination process the cell may switch, over time, and further as a function of temperature and applied voltage, from LRS to HRS. An improved structure comprises an inert electrode over which a resistive layer is formed. Over the resistive layer a mitigation layer of Zirconium Oxide (ZrO2) is formed over which a scavenging layer is formed. The resistive layer together with the ZrO2 layer are typically 5nm thick, with the ZrO2 layer ranging between 1 -2.5nm. The ZrO2 layer may be further doped with a trivalent like Aluminum (al) or Lanthanum (La) at a 1- 15% doping range.

Description

IMPROVED STACK STRUCTURE AND METHOD OF MANUFACTURE THEREOF FOR RETENTION OF LOW RESISTIVE STATE (LRS) OF A RESISTIVE RANDOMACCESS MEMORY (RERAM) TECHNICAL FIELD

[0001] The present disclosure generally relates to resistive random-access memory (ReRAM) cells, and more particularly to an improvement arrangement of the resistive stack of the ReRAM cell. BACKGROUND

[0002] The retention problem of a resistive layer of a resistive random-access memory (ReRAM) is a significant issue that affects the stability and reliability of these devices. In ReRAM, information storage is achieved by controlling the resistive state of a thin resistive layer sandwiched between two electrodes, namely, a high resistive state (HRS) and a low resistive state (LRS). The resistive layer consists of metal oxides, typically containing oxygen vacancies that can migrate within the layer.

[0003] Fig. 1 is a cross section of a ReRAM resistive filament stack 100 operating between SET 100B and RESET 100A states according to current solutions. Voltages are applied to the ReRAM resistive filament stack 100 to perform a SET operation 160 and a RESET operation 170. The ReRAM resistive filament stack 100 includes a scavenging layer 110, a resistive layer 120, and an inert electrode 130. In a typical application the scavenging layer 110 is 5nm thick and made of Titanium (Ti). In a typical application the resistive layer 120 is 5nm thick and made of Hafnium Oxide (HfO ). In a typical application, the inert electrode 130 is greater than 5nm in thickness and made of Titanium Nitride (TiN). At a SET operation 160, vacant oxygen (VO) 150 are created in the resistive layer 120 and oxygen (O) 140 is trapped in the scavenging layer 110. The result of a SET operation 160 is therefore a conductive filament between the scavenging layer 110 and the inert electrode 130.

[0004] Fig. 2 is a schematic cross-section showing recombination occurring in a ReRAM resistive filament stack 200, increasing resistivity of the ReRAM filament according to current solutions. While theoretically, the SET 100B and RESET 100A states are stationary, this is not necessarily the case, and, in the SET state, recombination mayoccur. That is, VOs 150 recombine 210 with Os 140 and as a result, the resistance of the filament increases, even to a point where the identified state of the ReRAM cell switches from SET, i.e., LRS, to RESET, i.e., HRS.

[0005] One of the challenges in ReRAM operation is the recombination of oxygen within the resistive layer. During programming of the resistive stack, a voltage is applied to the device, causing the migration of oxygen vacancies towards the electrode. This migration creates conductive filaments, leading to a low resistive state (LRS) in the resistive layer. However, over time, oxygen vacancies can recombine with oxygen in the resistive layer, resulting in the dissolution of the conductive filaments and a resistance increase. This phenomenon is known as filament dissolution or retention loss.

[0006] The recombination of oxygen can occur due to various factors such as thermal effects and electrical stress. High temperatures accelerate the recombination process, leading to faster filament dissolution. Electrical stress can also promote oxygen recombination, as the migration of oxygen vacancies generates heat, which further facilitates the recombination process.

[0007] To resolve the retention problem and enhance the stability of ReRAM devices, several techniques have been proposed and explored. One approach is the introduction of an oxygen scavenging layer 110 adjacent to the resistive layer 120. The purpose of the scavenging layer 110 is to capture and neutralize the oxygen species that diffuse from the resistive layer 120, preventing them from recombining with the vacant oxygen (VO).The oxygen scavenging layer 110 acts as a sink for oxygen, reducing the likelihood of filament dissolution.

[0008] Various materials have been investigated as oxygen scavenging layers, including metals, metal alloys, and metal oxides. These materials have different oxygen affinity properties, allowing them to effectively scavenge oxygen species. By carefully selecting the composition and thickness of the oxygen scavenging layer 110, it is possible to tailor the scavenging layer 110 oxygen uptake capability and optimize its performance in reducing filament dissolution. However, this solution has drawbacks and does not provide a robust solution to the problem.

[0009] Another approach to mitigate the retention problem is by optimizing the device fabrication process and materials. For instance, the use of oxygen-rich depositionconditions or post-processing techniques can enhance the oxygen content in the resistive layer. Similarly, modifying the electrode materials and interfaces can minimize the migration of oxygen species, reducing the retention loss.

[0010] Although such approaches provide some guidance to reduce retention losses, room for improvements exists in the various layers of the resistive stack to modify, for example, configuration, material, structure, fabrication process, and the like, and more. Optimization of the resistive layer is desired for the stability and reliability of ReRAM devices, enabling their wider adoption in various memory applications.

[0011] It would therefore be advantageous to provide a solution that overcomes the challenges noted above.SUMMARY

[0012] A summary of several example embodiments of the disclosure follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term “some embodiments” or “certain embodiments” may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[0013] Certain embodiments disclosed herein include a resistive stack of a resistive randomaccess memory (ReRAM) cell, the resistive stack comprising: an inert electrode having a first thickness; a resistive layer formed over the inert electrode having a second thickness, the resistive layer having a first migration energy; a mitigation layer formed over the resistive layer having a third thickness, wherein the mitigation layer having a second migration energy which is higher than the first migration energy; and, a scavenging layer formed over the mitigation layer having a fourth thickness; wherein the third thickness is between 20% and 60% of a combined thickness of the second thickness and the third thickness.

[0014] Certain embodiments disclosed herein also include a method of manufacture of a resistive stack of a resistive random-access memory (ReRAM) cell, the method comprises: forming an inert electrode having a first thickness; forming a resistive layer formed over the inert electrode having a second thickness, the resistive layer having a first migration energy; forming a mitigation layer formed over the resistive layer having a third thickness, wherein the mitigation layer having a second migration energy which is higher than the first migration energy, and wherein the third thickness is between 20% and 60% of a combined thickness of the second thickness and the third thickness; and, forming a scavenging layer formed over the mitigation layer having a fourth thickness.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 is a schematic cross-section of a conventional ReRAM resistive filament stack operating between set and reset states.

[0017] Figure 2 is a schematic cross-section showing recombination occurring in a conventional ReRAM resistive filament stack, increasing resistivity of the ReRAM filament.

[0018] Figure 3 is a schematic cross-section of a ReRAM resistive filament stack according to an embodiment.

[0019] Figure 4 is a diagram showing an impact of trivalent doping or implantation into a mitigation layer of a ReRAM resistive filament stack according to an embodiment.

[0020] Figure 5 is a flowchart of a process of forming a ReRAM resistive filament stack according to an embodiment.DETAILED DESCRIPTION

[0021] It is important to note that the embodiments disclosed herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of thevarious claims. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

[0022] A resistive random-access memory (ReRAM) includes a resistive cell that toggles between low-resistive state (LRS) after a SET, or at a high-resistive state (HRS) after a RESET. The resistive filament thereof risks recombination of vacant oxygen of a resistive layer and oxygen in a scavenging layer. As a result of the recombination process, the cell may switch, over time, and further as a function of temperature and applied voltage, from LRS to HRS.

[0023] A resistive filament structure of the ReRAM, according to the disclosed embodiments includes a mitigation layer to reduce retention loss. The resistive filament structure includes an inert electrode over which a resistive layer is formed. Over the resistive layer a mitigation layer of Zirconium Oxide (ZrO ) is formed, over which a scavenging layer is formed. The resistive layer together with the mitigation layer of ZrO layer are, for example, 5nm thick, with the ZrO layer, for example, ranging between 1 -2.5nm. The ZrO layer may be further doped with a trivalent element such as, but not limited to, Aluminum (Al) or Lanthanum (La) at a 1-15% doping range. The doping range is presented, for example but not by way of limitation, as the percentage of dopant atoms with respect to the total atoms in the doped material. Doping is an intentional introduction of impurity atoms (or dopants) into a semiconductor (the doped material) to modify the semiconductor electrical properties. In an embodiment, the resistive layer may be doped similarly to the doping performed on the mitigation layer.

[0024] Fig. 3 is an example schematic cross-section 300 of a ReRAM resistive filament stack according to an embodiment. The resistive filament stack 300 includes four layers, an inert electrode 310 at the bottom of the stack and having a thickness THi. Over it, there is a resistive layer 320 having a thickness TH2, over which a mitigation layer 330 is formed and has a thickness TH3. Over the mitigation layer 330, a scavenging layer 340 having a thickness TH4 is formed. It should be noted that entire semiconductor layers in a ReRAM cell, other than those described herein, are not described as they do not add to the understanding of the embodiments described herein. One of ordinary skill in the art wouldunderstand a general semiconductor manufacturing process and other semiconductor layers, apart from the resistive filament, associated to the ReRAM cell.

[0025] In an embodiment, the various layers are formed from a variety of materials. The inert electrode layer 310 is made of Titanium Nitride (TiN). The resistive layer is formed of Hafnium Oxide (HfO ). The mitigation layer 330 is formed of ZrO . Experiments have shown that the use of ZrCh as the mitigation layer provides for a better distinction between the LRS and HRS of the memory. ZrCh is a good candidate for the mitigation layer 330 as it is required that there will exist a high migration energy (Em) for oxygen (O) 360 and vacant oxygen (VO) 390, typically exceed 2eV. The higher the energy the better the retention gain. However, it is limited as a too high of an Em will lead to too much LRS tails which are an unwanted phenomenon. The scavenging layer 340 is formed of Titanium (Ti). It should be noted that these are typical materials, however, other materials may be used to achieve the results described herein when adhering to the conditions discussed in greater detail herein.

[0026] The mitigation layer 330 is a layer that has a higher migration energy for vacant oxygen (VO) 350, 390 and oxygen (O) 360 when in contact with the scavenging layer 340. VO 350 may move 370 from the resistive layer 320 to the mitigation layer 330. Likewise, VO 390 may recombine 380 with oxygen 360 in the scavenging layer 340. The use of the mitigation layer 330 reduces the dissolution rate of the resistive filament and therefore improves retention of the ReRAM cell. There is a challenge that needs to be addressed and that is the thickness of the layers, and in particular the thickness TH3 in order to keep, beyond retention of the LRS, a desired RESET speed. Therefore, a nominal migration energy ought to be kept at the boundary between the resistive layer 320 and the mitigation layer 330. It should be noted that an unoptimized resistive stack may create that LRS tails that can degrade memory functionality.

[0027] In a typical embodiment of the resistive stack, the thickness TH1 of the inert electrode is typically greater than 5nm. The thickness TH4 of the scavenging layer 340 is typically 5nm. The combined thickness of both the resistive layer 320 and the mitigation layer 330, i.e., TH2+TH3, is 5nm. It should be noted that the SET may degrade (increased resistance) when the mitigation layer 330 is too thick. It should be further noted that when the mitigation layer 330 is too thin, then no gain in performance (i.e., no reduction in retentionloss) may be measured. In an embodiment, the ZrC>2 mitigation layer 330 thickness (TH3) ranges between 1 nm and 3nm. In the same embodiment, the resistive layer thickness (TH2) ranges between 4nm and 2nm. In one example embodiment, TH2 is 2.5nm and TH3 is 2.5nm. In another example embodiment, TH2 is 3.5nm and TH3 is 1.5nm. In an embodiment, other like dimensions of TH2 and TH3 that satisfies the condition of a ratio TH3 / (TH2+THS) to be between 0.2 and 0.6 (or in percent 20% and 60%) may be implemented.

[0028] Fig. 4 is an example diagram 400 showing an impact of a trivalent doping or implantation into a mitigation layer of a ReRAM resistive filament stack according to an embodiment and is based on a similar chart from Zhang et al. paper titled “Effects of Ionic Doping on the Behaviors of Oxygen Vacancies in HfO2 and ZrO2: A First Principles Study”. The vertical axis of the chart shows the 410 shows the Em of materials used for a mitigation layer. The horizontal axis 420 shows a dopant radius. An undoped ZrO2 430 exhibits a Em of ~6.3eV. By using various trivalent dopants such as Ti, Al, La, or the like, a reduced Em may be achieved. In the case of Ti 460, the reduction of Em is minimal to ~6eV. Using either Al 440 or La 450, the reduction of Em is to ~3.8eV. It should be noted that dosages of dopant (i.e. , the amount of dopant used) impact the level of Em reached, and hence there is more control of Em when using Al or La than using Ti.

[0029] According to an embodiment, a doping by a trivalent dopant is typically in the range of 1 %-15%. Doping can be performed by deposition using the likes of, but not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. Alternatively, a direct implant may take place by implanting the selected dopant element at, for example, a ~1-5KeV doping energy and at a 115-515ions / cm2doping dose. Other processes may also be used without departing from the scope of the disclosed embodiments. In one embodiment, the mitigation layer (e.g., the mitigation layer 330, Fig. 3) is implanted or doped for the purpose of defect creation after ZrO2 deposition. Such implantation or deposition may be performed with silicon (Si), e.g., at 3KeV 215ions / cm2from the top, Argon (Ar) or Nitrogen (N), after ZrC>2 deposition. By having less Si in the mitigation layer, there are less tails that cause crossover between LRS and HRS. In an embodiment, doping of the mitigation layer 330 may further result in some degree of deposition of the resistive layer 320 thereunder.

[0030] Fig 5 is an example flowchart 500 of a process of forming a ReRAM resistive filament stack according to an embodiment.

[0031] At S510, an inert electrode (e.g., the inert electrode 310, Fig. 3) is formed having a first thickness, for example THi.

[0032] At S520, a resistive layer (e.g., the resistive layer 320, Fig. 3) having a second thickness, TH2, is formed over the inert electrode.

[0033] At S530, a mitigation layer (e.g., the resistive layer 320, Fig. 3), having a third thickness TH3, is formed over the resistive layer. In an embodiment, a ratio between TH3 / (TH2+THS) is between 0.2 and 0.6 (or in percentage, between 20% and 60%).

[0034] In an embodiment, S530 further includes doping or implanting the mitigation layer 530 with a trivalent element. Such trivalent elements include, for example, but not limited to, Al, La, Ti, and the like. Furthermore, in an embodiment, the mitigation layer may also be doped with Si, Ar, N, or the like, as further explained herein above.

[0035] At S540, a scavenging layer (e.g., the scavenging layer 340, Fig 3) is formed over the mitigation layer, having a fourth thickness of TH4.

[0036] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0037] It should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in somemanner. Also, unless stated otherwise, a set of elements comprises one or more elements.

[0038] As used herein, the phrase “at least one of” followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including “at least one of A, B, and C,” the system can include A alone; B alone; C alone; 2A; 2B; 2C; 3A; A and B in combination; B and C in combination; A and C in combination; A, B, and C in combination; 2A and C in combination; A, 3B, and 2C in combination; and the like.

Claims

CLAIMSWhat is claimed is:1 . A resistive stack of a resistive random-access memory (ReRAM) cell, the resistive stack comprising: an inert electrode having a first thickness; a resistive layer formed over the inert electrode having a second thickness, the resistive layer having a first migration energy; a mitigation layer formed over the resistive layer having a third thickness, wherein the mitigation layer having a second migration energy which is higher than the first migration energy; and a scavenging layer formed over the mitigation layer having a fourth thickness, wherein the third thickness is between 20% and 60% of a combined thickness of the second thickness and the third thickness.

2. The resistive stack of claim 1 , wherein the inert electrode is a Titanium Nitride (TiN) layer.

3. The resistive stack of claim 1 , wherein the resistive layer is a Hafnium Oxide (HfO ) layer.

4. The resistive stack of claim 1 , wherein the mitigation layer is a Zirconium Oxide (ZrO ) layer.

5. The resistive stack of claim 4, wherein at least the mitigation layer is doped with a trivalent element.

6. The resistive stack of claim 5, wherein the trivalent element is any one of: Aluminum (Al) and Lanthanum (La). io7. The resistive stack of claim 5, wherein a doping range is between 1 % and 15%.

8. The resistive stack of claim 5, wherein a doping is performed by any one of: deposition and implantation.

9. The resistive stack of claim 5, wherein a doping further comprises use of any one of: Silicon (Si), Argon (Ar), and Nitrogen (N).

10. The resistive stack of claim 1 , wherein the scavenging layer is a Titanium (Ti) layer.

11. A method of manufacture of a resistive stack of a resistive random-access memory (ReRAM) cell, the method comprises: forming an inert electrode having a first thickness; forming a resistive layer formed over the inert electrode having a second thickness, the resistive layer having a first migration energy; forming a mitigation layer formed over the resistive layer having a third thickness, wherein the mitigation layer having a second migration energy which is higher than the first migration energy, and wherein the third thickness is between 20% and 60% of a combined thickness of the second thickness and the third thickness; and forming a scavenging layer formed over the mitigation layer having a fourth thickness.

12. The method of claim 11 , wherein the inert electrode is a Titanium Nitride (TiN) layer.

13. The method of claim 11 , wherein the resistive layer is a Hafnium Oxide (HfO ) layer.

14. The method of claim 11 , wherein the mitigation layer is a Zirconium Oxide (ZrO ) layer.

15. The method of claim 14, further comprises: doping at least the mitigation layer with a trivalent element.

16. The method of claim 15, wherein the trivalent element is any one of: Aluminum (Al) and Lanthanum (La).

17. The method of claim 15, wherein a doping range is between 1 % and 15%.

18. The method of claim 15, wherein doping is performed by any one of: deposition and implantation.

19. The method of claim 15, wherein doping at least the mitigation layer further comprises use of any one of: Silicon (Si), Argon (Ar), and Nitrogen (N).

20. The method of claim 11 , wherein the scavenging layer is a Titanium (Ti) layer.

Images