Partially-plated holes in printed circuit board and method of manufacture

Abstract

A multilayer printed circuit board (PCB) includes at least one through hole that is partially-plated along its length. The hole is plated only up to a barrier layer that is disposed between two PCB cores. During preparation of the PCB stack, the barrier layer is etched more aggressively away from the center of the hole than the PCB cores, such that the width across the hole at the barrier layer is greater than at the PCB cores. A seed conducting layer on the hole sidewall adheres poorly to the barrier layer. When the hole is electroplated, the electroplating extends from one end of the hole only as far as the barrier layer.

Description

PARTIALLY-PLATED HOLES IN PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTUREFIELD OF THE DISCLOSURE

[0001] The invention relates generally to printed multilayer circuit boards (PCBs) and more particularly to PCBs that incorporate partially-plated holes that extend through the PCB. The invention is also directed to a method of manufacturing partially-plated holes in a multilayer PCB.BACKGROUND

[0002] A printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads and other features etched from electrically conductive sheets, such as copper sheets, laminated onto a non-conductive substrate. Multi-layered printed circuit boards are formed by stacking and laminating multiple such etched conductive sheet / non-conductive substrates. Conductors on different layers are interconnected with plated-through holes called vias.

[0003] A PCB includes a plurality of stacked layers made of alternating non-conductive layers and conductive layers. The non-conductive layers can be made of prepreg or base material that is part of a core structure. Prepreg is a reinforced material impregnated or coated with a resin binder and consolidated and partially cured to an intermediate stage semi- solid product. Prepreg is reinforced with, for example, glass fibers or a non-woven material such as paper, film, ceramic filler or the like. Prepreg is used as an adhesive layer to bond discrete layers of multilayer PCB construction, where a multilayer PCB consists of alternative layers of conductors and base materials bonded together, including at least one internal conductive layer. A base material is a fully cured organic or inorganic material used to support a pattern of conductor material. A core is a metal clad base material where the base material has integral metal conductor material on one or both sides. A laminated stack is formed by stacking multiple core structures with intervening prepreg and then laminating the stack to fully cure the prepreg and bond the adjacent layers together. A via can then beformed by drilling a hole through the laminated stack and plating the wall of the hole with electrically conductive material, such as copper. The resulting plating interconnects the conductive layers in the laminated stack.

[0004] In some cases it is desired that the plating in the via extends only between some of the conducting layers, not all of them. One approach to making a multilayer PCB having such a partially-plated via is to form a first sub-PCB stack having a via in which all the layers are plated. This may then be mated to a second sub-PCB stack having an unplated via. The first and second sub-PCB stacks may then be laminated together with the plated and unplated vias in alignment with each other. However, this approach requires a large number of steps and requires precise alignment of the plated and unplated vias. As multilayer PCBs are used with electronic components operating at increasingly higher frequencies, any misalignment between the plated and unplated vias can compromise the electrical quality of the circuit.

[0005] In another approach, a single via can be formed in a multilayer PCB, which is then plated along the length of the via. The plating can subsequently be removed from those portions of the via that are required to have no plating. This removal process, often performed by drilling, can result in a stub extending beyond the last conducting layer that is plated. The presence of the stub can be a detriment to the electrical properties of the multilayered PCB, especially at high frequencies.

[0006] There is a need, therefore, for a method of manufacturing a partially-plated via in a multilayer PCB that avoids the aforementioned problems, and that maintains high electrical quality.SUMMARY OF THE INVENTION

[0007] A first embodiment of the invention is directed to a multilayer printed circuit board (PCB) formed of a first inner assembly that comprises a first PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the third conducting layer of the second PCB core facing the second conducting layerof the first PCB core; and a first barrier layer between the second conducting layer and the third conducting layer, the first barrier layer being formed of an unreinforced material. A channel extends through the first inner assembly. A width of the channel at the first barrier layer is greater than a width of the channel at the first PCB core and greater than a width of the channel at the second PCB core. There is a sidewall conducting layer on a sidewall of the channel between at least the first and second conducting layers, the sidewall conducting layer terminating at the first barrier layer.

[0008] A second embodiment of the invention is directed to a multilayer printed circuit board (PCB) having a first inner assembly that includes a first PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the third conducting layer of the second PCB core facing the second conducting layer of the first PCB core; and a first barrier layer between the second conducting layer and the third conducting layer, the first barrier layer being formed of an unreinforced material. A channel extends through the inner assembly, the channel having a sidewall formed by at least the first PCB core, the first barrier layer and the second PCB core. A portion of the sidewall formed by the first barrier layer is undercut relative to a portion of the sidewall formed by the first PCB core and is undercut relative to a portion of the sidewall formed by the second PCB core. A sidewall conducting layer is on a sidewall of the channel between at least the first and second conducting layers, the sidewall conducting layer terminating at the first barrier layer.

[0009] Another embodiment of the invention is directed to a method of manufacturing a multilayer printed circuit board (PCB). The method includes forming a stack comprising at least a first PCB core, a first barrier layer and a second PCB core. The first PCB core includes first and second conducting layers on a first insulating core layer. The second PCB core includes third and fourth conducting layers on a second insulating core layer. The first barrier layer is formed of an unreinforced material and is disposed between the second conducting layer and the third conducting layer. The method also includes forming a channel through the stackand removing first barrier layer material at a sidewall of the channel so that a width of the channel at the first barrier material is greater than a width of the channel at the first PCB core and greater a width of the channel at the second PCB core. Metal is electroplated metal on the sidewall of the channel between the first and second conductive layers after removing the barrier material.

[0010] Another embodiment of the invention is directed to a multilayer printed circuit board (PCB) that has a first inner assembly comprising a first PCB core, the first PCB core comprising first and second metallic layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth metallic layers on a second insulating core layer, the third metallic layer of the second PCB core facing the second metallic layer of the first PCB core; and a first barrier layer between the second metallic layer and the third metallic layer. A channel extends through the first inner assembly. A width of the channel at the first barrier layer is greater than a width of the channel at the first PCB core. A sidewall conducting layer is on a sidewall of the channel between at least the first and second conducting layers, but does not extend from the second conducting layer to the third conducting layer.

[0011] Another embodiment of the invention is directed to a multilayer printed circuit board (PCB) that includes a first inner assembly. The first inner assembly includes a first PCB core, the first PCB core comprising first and second metallic layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth metallic layers on a second insulating core layer, the third metallic layer of the second PCB core facing the second metallic layer of the first PCB core; and a first barrier layer between the second metallic layer and the third metallic layer, the first barrier layer being formed of a fiberless material. A channel extends through the first inner assembly. There is a sidewall conducting layer on a sidewall of the channel between at least the first and second conducting layers, but it does not extend from the second conducting layer to the third conducting layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings, in which:

[0013] FIGs. 1A-1G schematically illustrate process steps in forming a partially-plated via in a laminated printed circuit board (PCB) stack using a prior art method which results in the presence of a conductive stub;

[0014] FIGs. 2A-2J schematically illustrate process steps in forming a partially-plated hole in a laminated PCB stack using a process according to an embodiment of the present invention;

[0015] FIG 3 schematically illustrates a cross-section through a laminated PCB stack having a partially-plated hole according to an embodiment of the present invention;

[0016] FIG 4 schematically illustrates a cross-section through a laminated PCB stack having a partially plated hole according to another embodiment of the present invention; and

[0017] FIG 5 schematically illustrates a cross-section through a laminated PCB stack having at least two partially-plated holes, where the plating extends from different sides of the stack in different channels, according to another embodiment of the present invention.

[0018] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features that are believed to be characteristic of the invention, bothas to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.DETAILED DESCRIPTION

[0019] The present invention is directed to a multilayer printed circuit board (PCB) that includes a partially-plated hole that extends through the PCB, but which lacks the stub of conventionally fabricated PCBs, and a method of manufacturing such a PCB. Such partially -plated holes may be plated through holes, which can be component holes that receive leads, press-fit holes that receive compliant pins, or vias for interconnection.

[0020] FIGs. 1A-1F show steps in a conventional approach to providing a partially-plated hole, or channel, in an embodiment of a multilayer printed circuit board (PCB). FIG. 1A schematically illustrates a cross-section through a PCB core 100, also referred to as a core. The core 100 comprises a non-conducting layer 102 between first and second conducting layers 104, 106. The non-conducting layer 102 is typically relatively rigid and is formed of a fiberglass -reinforced sheet of cured resin or epoxy, sometimes referred to as a base layer. FR4 material is widely used as core material, although other types of material may also be used. The conducting layers 104, 106 are typically metallic layers and may be formed of any suitable metal. Copper is widely used for the conducting layer of a PCB core. The conducting layers 104, 106 may be patterned to form electrically conductive interconnects. In other examples, the core 100 may be provided with only a single conducting layer or can have more than two conductive layers laminated together with respective fully cured non-conductive layers therebetween.

[0021] FIG. IB schematically illustrates a cross section of different elements that are stacked together for the formation of a multilayer PCB. The stack 110 includes a first core 112 having conducting layers on either side of a base layer, and asecond core 114, also having conducting layers on either side of a base layer. On either side of the stack 110, and between the cores 112, 114, are layers of prepreg 116, 118, 120. Prepreg is a reinforced material impregnated or coated with a resin binder and consolidated and partially cured to an intermediate semi- solid product. The resin in prepreg is only partially cured and therefore flows during lamination. After being sufficiently heated during a lamination process, the resin in prepreg cools into a fully cured state. The base material of the cores 112, 114 is composed of a fully cured resin and as such does not flow during lamination.

[0022] The different layers in the stack 110 are laminated through the application of heat and pressure. The outer layers of the stack 110 may be provided with outer conducting layers 122, 124, for example copper layers, as shown in FIG. 1C.

[0023] A channel 126 is formed through the stack 120 by drilling a hole through the stack, as schematically illustrated in FIG. ID. After the drilling process, the channel 126 is cleaned of debris and resin is removed around the inner sidewall 128 to ensure that subsequently deposited conductive material adheres to connection points 112 and 114.

[0024] A seed layer of copper 130 is then provided on the sidewall 128 of the channel, as shown in FIG. IE, for example through electroless plating. A copper layer 132 is then electroplated on top of the seed layer 130, as shown in FIG. IF.

[0025] At this point in the manufacturing process, the channel 126 is plated from one side, the first outer conducting layer 128, to the other side, the second outer conducting layer 124. A drill is used to remove unwanted copper plating in the channel 126 to produce a partially-plated channel 126. Where it is desired that the plating extends within the channel 126 only between the first outer conducting layer 122 and the conducting layers of the first core 112, a drill can be used to remove the unwanted plating within the channel 126 by advancing the drill within the channel 126 from the side of the second outer conducting layer 124. This requires a drill having a slightly larger diameter than was used to make the channel, typically about 150-200 pm larger, in order to ensure that all copper is removed in the drilling process.However, in order to account for manufacturing tolerances, such as accuracy in the plunge depth of the drill and variations in the thicknesses of the cores and prepreg used in the manufacture of the PCB, the drilling process leaves a stub 134. The stub 134 constitutes unwanted plating material that extends beyond the last conducting layer that is intended to be plated. In the illustrated example, the last conducting layer that is intended to be plated is the lower conducting layer 112b of the first core 112. The stub 134 may be more than about 100 pm (about 0.004 inch, or 4 mil) long and may be about 200 pm (about 8 mil) or longer. In some cases, the stub 134 is nominally 200 ± 150 pm (about 8 + 6 mil).

[0026] The stub, and the variation in its size from board to board, is detrimental to consistent operation of the finished PCB. This is due, in part, to impedance matching issues which become increasingly more important at higher frequencies, such as GHz and multi-GHz frequencies. It is preferred that the length of any stub remaining in a partially-plated channel should be no more than 75 pm (3 mil) in length, and more preferably less than that.

[0027] FIGs. 2A-2G schematically illustrate steps of a new manufacturing process for a multilayer PCB having a partially-plated hole in which the stub size is substantially reduced, if not eliminated altogether.

[0028] FIG. 2A schematically illustrates an arrangement 200 of first core 202, having first and second conducting 204, 206 layers on either side of a first base layer 208, and a second core 210, having third and fourth conducting layers 212, 214 on either side of a second base layer 216. The conducting layers 204, 206, 212, 214 may be patterned to form electrically conductive interconnects.

[0029] A barrier layer 218 is placed on one of the second and third conducting layers 206, 212 which are facing each other, at a location where a channel is intended to be formed. In the illustrated embodiment, the barrier layer is on the third conducting layer 212 of the second core 210. The barrier layer 218 is formed of a material that is free of reinforcement, in other words it does not contain glass fibers, unwovens, paper or any other added matter to reinforce the basic barrier material, and may be referred to as being formed of an unreinforced material. In contrast, prepregcontains glass fiber reinforcement. In some embodiments, the barrier layer is an acrylic material or an epoxy material and may be tack-cured to the third conducting layer 212 while the different layers are being assembled to form the multilayer PCB. One example of suitable acrylic material is DuPont™ Pyralux® FR Sheet Adhesive, available from DuPont Electronic Materials, Research Triangle Park, North Carolina, USA, in various thicknesses, including 13 pm (0.5 mil), 25 pm (1 mil), 51 pm (2 mil), 76 pm (3 mil) and 102 pm (4 mil).

[0030] FIG. 2B schematically illustrates the arrangement of the first and second cores 202, 210 and barrier layer 218, included in a layered stack 220 with layers of prepreg ready for lamination. A first prepreg layer 222 is provided above the first core 202. A second prepreg layer 224 is provided below the second core 210. A third prepreg layer 226 is provided between the first and second cores 202, 210. The third prepreg layer 226 is provided with an aperture to permit the barrier layer 218 access to the first core 202 during lamination. The stack 220 is laminated via the application of pressure and heat to form what may be referred to as an inner assembly, and is provided with first and second outer conducting layers 228, 230, as schematically shown in FIG. 2C.

[0031] A portion of the second outer conducting layer 230 is etched away in the region where the channel is to be formed, below the barrier layer 218, as schematically shown in FIG. 2D. This results in an etched area 232 of the outer surface of the second prepreg layer 224 that lacks metallization.

[0032] A channel 234 is formed by drilling a hole through the stack 220, as schematically illustrated in FIG. 2E. The channel 234 may be formed using a mechanical drill or a laser. The channel 234 penetrates the upper side of the stack through the first outer conducting layer 228 and terminates at the second side of the stack 220 at the etched area 232. The channel 234 has a sidewall 236 formed of the different layers in the stack 220. The outer surface of the second prepreg layer 224 is free of the second outer conducting layer 230 around the channel opening in the second prepreg layer 224.

[0033] The sidewall 236 of the channel 234 is then cleaned by desmearing.Desmearing is typically carried out following a mechanical or laser machining process and can be either a wet or dry process. Desmearing is used to clean the holes after they have been formed in order to clean the sidewall of the hole and to promote adhesion of a subsequent layer, such as electroless metal, polymer or carbon applied to the sidewall to make it conductive. Wet desmearing is often used to the clean resin smear on the sidewall generated by heat and friction during the machining process, such as drilling or routing. The wet desmear may also include a material to frost or etch glass at the sidewall. The frosting or etching of the glass fibers results in a roughening of the sidewall and promotes adhesion to the glass fibers exposed at the sidewall. The desmear may include an alkali etch, for example, a NaOH or KOH glass etch solution. Dry desmearing, also referred to as plasma desmearing, is less aggressive than wet desmearing but works well with non-conventional epoxy resins. A plasma desmear may also be used to clean the hole of ash and other contaminants in laser machined holes and promotes copper adhesion to the sidewalls of laser and mechanically drilled holes.

[0034] In the illustrated example, the sidewall 236 has been desmeared using an alkali etch. It has been found that an unreinforced barrier material is etched more readily than reinforced prepreg or core layers. Thus, the barrier layer 218 has been etched back more aggressively from the center of the channel 234, such that the sidewall 236a at the barrier layer 218 is undercut relative to the sidewall 236b at the first core 218 and the sidewall 236c at the second core 210, as schematically illustrated in FIG 2F.

[0035] FIG. 2G schematically illustrates the stack 220 at the same step in the manufacturing process, following desmearing. The channel 234 has an axis 237, which is equidistant from the two sides of the channel 234. The distance dl is the distance between the axis 237 and the sidewall at the first core 202. The distance d2 is the distance between the axis 237 and the sidewall at the barrier layer 218. The distance d3 is the distance between the axis 237 and the sidewall at the second core 210. The distance d2 is greater than the distance dl and is greater than the distance d3. Thus, the width of the channel 234 at the barrier layer 218 is greater than at the firstcore 202 or the second core 210.

[0036] Following the desmearing process, the sidewall 236 is provided with a conducting seed layer 238 covering all surfaces of the sidewall 236, including the portions of the sidewall 236 formed by the first and second prepreg layers 222, 224, the first and second cores 202, 210, and the barrier layer 218, as schematically illustrated in FIG. 2H. The seed layer 238 may be formed by electroless plating a metal such as copper, or by depositing any other suitable material, such as a conducting polymer or carbon deposit. The seed layer 238 also covers the etched area 232 on the outside surface of the second prepreg layer 224. The seed layer 238 may be less than 1 pm thick, and may be as thin as a few nanometers.

[0037] An area of the seed layer 238 is subsequently removed, for example by laser ablation, to expose the lower surface of the second prepreg layer 224, thus electrically isolating the seed layer 238 from the second outer conducting layer 230, as schematically illustrated in FIG, 21.

[0038] A plated layer 240 of metal, for example copper, is electroplated on to the stack 220, using standard electroplating procedures, where the first outer conductive layer 228, or another conducting layer electrically connected to the first outer conductive layer 228, is used as the electroplating cathode. Because of the thin seed layer 238, the metallic layers of the first core 202 are held at a similar potential as the first outer conductive layer 228 and so that portion of the channel 234 between the first outer conducting layer 228 and the lower conducting layer of the first core 202 is plated to form a sidewall conducting layer, as schematically illustrated in FIG. 2J. The metal used in the electroplating process may be any suitable metal, however in many cases copper is the metal used for the plated layer 240.

[0039] The seed layer 238 does not adhere well to the barrier layer 218, however, and so little or no electroplating takes place within the channel 234 at, or beyond, the barrier layer 218, leaving the sidewall of the lower portion 242 of the channel 234 unplated. The unplated portion of the seed layer 238 may subsequently be removed in a washing or cleaning step after electroplating. The resulting PCB stack 220 has a channel 234 that is partially-plated between its outer ends.Furthermore, the plating is substantially free of a stub or, in some cases, may form a stub that is no longer in length than the thickness of the barrier layer 218. As such, the plating may be said to terminate at the barrier layer 218. Therefore, in an example where the barrier layer 218 is a 25 pm thick layer of acrylic adhesive material, then any stub that may form is no more than 25 pm long, which meets the current industrial goal of having a stub length of no more than 75 pm.

[0040] The use of a barrier layer to prevent electroplating of a channel sidewall is not limited to PCB stacks containing only two cores. An embodiment of a laminated PCB stack 300 containing a first core, 302, a second core 304 and a third core 306, and fabricated using the techniques discussed above, is schematically illustrated in FIG. 3. A first prepreg layer 308 lies between a first outer conducting layer 310 and the first core 302. A second prepreg layer 312 lies between the first core 302 and the second core 304. A third prepreg layer 314 is disposed between the second and third cores 304, 306, and a fourth prepreg layer is disposed between the third core 306 and a second outer conducting layer 318. A channel 320 having a sidewall 322 has been formed through the stack 300. A barrier layer 324, formed of an unreinforced material, is disposed between the second and third cores 304, 306 close to the channel 320, separating the third prepreg layer 314 from the channel 320. The sidewall 322a at the barrier layer 322 has been etched during a desmearing process so as to be undercut relative to the sidewall 322b at the second core 304 and relative to the sidewall 322c at the third core 306. The upper portion of the sidewall 324 has been electroplated in the manner described above, between the first outer conducting layer 310 and the second core 304, while the lower portion of the sidewall 324, including the barrier layer 324, the third core 306 and the fourth prepreg layer 316, remains substantially free of electroplating.

[0041] A barrier layer may also be used to isolate electroplating within a channel to a region separated from the outer conducting layers. An embodiment of a laminated PCB stack 400 containing a first core 402, a second core 404, a third core 406, and a fourth core 408, and fabricated using the techniques discussed above, is schematically illustrated in FIG. 4. A first prepreg layer 410 lies between a first outerconducting layer 412 and the first core 402. A second prepreg layer 414 lies between the first core 402 and the second core 404. A third prepreg layer 416 is disposed between the second and third cores 404, 406. A fourth prepreg layer 418 is disposed between the third core 406 and the fourth core 408. A fifth prepreg layer 420 is disposed between the fourth core 408 and a second outer conducting layer 422. A channel 424 having a sidewall 426 has been formed through the stack 400.

[0042] A first barrier layer 428, formed of an unreinforced material, is disposed between the first and second cores 402, 404 close to the channel 424, separating the second prepreg layer 414 from the channel 424. A second barrier layer 430, also formed of an unreinforced material and which may be formed of the same material as the first barrier layer 428, is disposed between the third and fourth cores 406, 408 close to the channel 424, separating the fourth prepreg layer 418 from the channel 424. During the electroplating process, the second and / or third cores 404, 406 were biased as cathodes so that metal was electroplated on the sidewall between the second and third cores 404, 406. However, the first and second barrier layers 428, 430 effectively isolated the ends of the channel 424 from being plated. Consequently, the center portion of the channel sidewall 426a, including the second and third cores 404, 406, along with the third prepreg layer 416 is electroplated. The upper portion of the channel sidewall 426b, including the first barrier layer 428, the first core 402 and the first prepreg layer 410 is substantially free of electroplating. Likewise, the lower portion of the channel sidewall 426c, including the second barrier layer 430, fourth core 408, and fifth prepreg layer 420 is substantially free of electroplating. Thus the PCB stack 400 includes a partially-plated channel where the plating does not extend to the outer conducting layers.

[0043] The technique described above may be used to provide homes in a PCB stack that are partially-plated from different sides of the stack. FIG. 5 schematically illustrates a cross-section through an embodiment of a PCB stack 500 that includes a first PCB core 502 and a second PCB core 504. A first prepreg layer 506 lies above the first core 502, a second prepreg layer 508 lies below the second core 504. The first and second cores 502, 504 are separated by a barrier layer 510 and a third prepreglayer 512. There is a first outer conducting layer 514 on one side of the stack 500 and a second outer conducting layer 516 on the other side of the stack 500.

[0044] The PCB stack 500 includes first and second channels 518, 520 that pass through the stack 500. The first and second channels 518, 520 have respective first and second sidewalls 522, 524. An etched area 526 of the outer surface of the second prepreg layer 508 surrounds the opening of the first channel 518 in the second prepreg layer 508. An etched area 528 of the outer surface of the first prepreg layer 506 surrounds the opening of the second channel 520 in the first prepreg layer 506. In the manner described above, the first and second channels 518, 520 have a width at the barrier layer 510 that is greater than at the first core 504 or at the second core 504.

[0045] A first sidewall conducting layer 530 is present on the first sidewall 522 between the first outer conducting layer 514 and the lower conducting layer of the first core 502. The first sidewall conducting layer 530 may be provided via electroplating in a manner like that described above, where the first outer conducting layer 514 is connected as the cathode in the electroplating process. A second sidewall conducting layer 532 is present on the second sidewall 524 of the second channel 520 between the second outer conducting layer 516 and the upper conducting layer of the second core 504. The second sidewall conducting layer 532 may be provided via electroplating in a manner like that described above, where the second outer conducting layer 516 is connected as the cathode in the electroplating process. The second channel 520 is prepared for electroplating in a manner like that as the first channel 528, but where the seed layer is laser etched in the etched region 528 on the first prepreg layer 506, to electrically isolate the first outer conductive layer 514 from the seed layer in the second channel 520. Thus, a PCB stack may include a hole that is partially-plated from one side of the stack and another hole that is partially-plated form the other side.

[0046] In some of the descriptions above, words such as top, bottom, upper and lower have been used to described the relative position of elements in the drawings. It should be understood that these descriptions were given only to provide clarity to the drawings, and that no limitation is intended to the invention. The PCBs of the presentinvention may be used in different orientations than those shown in the drawings.

[0047] Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art to which the present invention is directed upon review of the present specification. The claims are intended to cover such modifications and devices. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present invention, disclosure, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0048] As noted above, the present invention is applicable to PCBs and their manufacture. Accordingly, the present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims.

Claims

CLAIMS1.A multilayer printed circuit board (PCB), comprising a first inner assembly comprising a first PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the third conducting layer of the second PCB core facing the second conducting layer of the first PCB core; a first barrier layer between the second conducting layer and the third conducting layer, the first barrier layer being formed of an unreinforced material; a first channel extending through the first inner assembly, a width of the first channel at the first barrier layer being greater than a width of the first channel at the first PCB core and greater than a width of the first channel at the second PCB core; and a first sidewall conducting layer on a sidewall of the first channel between at least the first and second conducting layers, the first sidewall conducting layer terminating at the first barrier layer.2.The multilayer PCB as recited in claim 1, further comprising a first outer conducting layer on a first side of the first inner assembly, the first outer conducting layer separated from the first conducting layer by at least a first prepreg insulting layer, and a second outer conducting layer on a second side of the first inner assembly, the second outer conducting layer separated from the fourth conducting layer by at least a second prepreg insulting layer.

3. The multilayer PCB as recited in claim 2, wherein the first channel extends through the first outer conducting layer and the first sidewall conducting layer connects between the first conducting layer of the first PCB core and the first outer conducting layer.

4. The multilayer PCB as recited in claim 3, further comprising a third core disposed between the first inner assembly and the first outer conducting layer, the firstchannel passing through the third core, the first sidewall conducting layer connecting to at least one metallic layer of the third core.

5. The multilayer PCB as recited in claim 2, wherein the first channel extends to an outer surface of the second prepreg insulating layer and wherein the outer surface of the second prepreg insulating layer is free of the second outer conducting layer proximate the first channel.

6. The multilayer PCB as recited in claim 1, further comprising a second channel extending through the first inner assembly, a width of the second channel at the first barrier layer being greater than a width of the second channel at the first PCB core and greater than a width of the second channel at the second PCB core; and a second sidewall conducting layer on a sidewall of the second channel between at least the third and fourth conducting layers, the second sidewall conducting layer terminating at the first barrier layer.

7. The multilayer PCB as recited in claim 6, further comprising a first outer conducting layer on a first side of the first inner assembly and a second outer conducting layer on a second side of the first inner assembly, the first sidewall conducting layer connecting to the first outer conducting layer and the second sidewall conducting layer connecting to the second outer conducting layer.8.A multilayer printed circuit board (PCB), comprising a first inner assembly comprising a first PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the third conducting layer of the second PCB core facing the second conducting layer of the first PCB core; a first barrier layer between the second conducting layer and the third conducting layer, the first barrier layer being formed of an unreinforced material;a first channel extending through the inner assembly, the first channel having a first sidewall formed by at least the first PCB core, the first barrier layer and the second PCB core, a portion of the first sidewall formed by the first barrier layer being undercut relative to a portion of the first sidewall formed by the first PCB core and being undercut relative to a portion of the first sidewall formed by the second PCB core; and a first sidewall conducting layer on a sidewall of the first channel between at least the first and second conducting layers, the first sidewall conducting layer terminating at the first barrier layer.

9. The multilayer PCB as recited in claim 8, further comprising a first outer conducting layer on a first side of the first inner assembly, the first outer conducting layer separated from the first conducting layer by at least a first prepreg insulting layer, and a second outer conducting layer on a second side of the first inner assembly, the second outer conducting layer separated from the fourth conducting layer by at least a second prepreg insulting layer.10.The multilayer PCB as recited in claim 9, wherein the first channel extends through the first outer conducting layer and the first sidewall conducting layer connects between the first conducting layer of the first PCB core and the first outer conducting layer.

11. The multilayer PCB as recited in claim 10, further comprising a third PCB core disposed between the first inner assembly and the first outer conducting layer, the first channel passing through the third core, the first sidewall conducting layer connecting to at least one metallic layer of the third core.12.The multilayer PCB as recited in claim 9, wherein the first channel extends to an outer surface of the second prepreg insulating layer and wherein the outer surface of the second prepreg insulating layer is free of the second outer conducting layer proximate the channel.

13. The multilayer PCB as recited in claim 8, further comprising a second channel extending through the first inner assembly, the second channel having a second sidewall formed by at least the first PCB core, the first barrier layerand the second PCB core, a portion of the second sidewall formed by the first barrier layer being undercut relative to a portion of the second sidewall formed by the first PCB core and being undercut relative to a portion of the second sidewall formed by the second PCB core; and a second sidewall conducting layer on a sidewall of the second channel between at least the third and fourth conducting layers, the second sidewall conducting layer terminating at the first barrier layer.

14. The multilayer PCB as recited in claim 13, further comprising a first outer conducting layer on a first side of the first inner assembly and a second outer conducting layer on a second side of the first inner assembly, the first sidewall conducting layer connecting to the first outer conducting layer and the second sidewall conducting layer connecting to the second outer conducting layer.

15. A method of manufacturing a multilayer printed circuit board (PCB), comprising forming a stack comprising at least a first PCB core, a first barrier layer and a second PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the first barrier layer being formed of an unreinforced material and being disposed between the second conducting layer and the third conducting layer; forming a first channel through the stack; removing first barrier layer material at a first sidewall of the first channel so that a width of the first channel at the first barrier material is greater than a width of the first channel at the first PCB core and greater than a width of the first channel at the second PCB core; and electroplating metal on the first sidewall of the first channel between the first and second conductive layers after removing the first barrier layer material.

16. The method as recited in claim 15, further comprising providing a first outer conducting layer on a first side of the stack and a second outer conducting layer on a second side of the stack.17.The method as recited in claim 16, wherein electroplating the metal on the first sidewall further comprises electroplating metal on the first channel sidewall between the second conductive layer and the first outer conductive layer.

18. The method as recited in claim 16, further comprising etching the second outer conductive layer away from the first channel at the second side of the stack.19.The method as recited in claim 17, further comprising depositing a conducting seed layer within the first channel after removing the first barrier layer material and before electroplating the sidewall.20.The method as recited in claim 19, further comprising removing the conducting seed layer from the second side of the stack so that there is no electrical connection between the seed layer in the first channel and the second outer conductive layer.

21. The method as recited in claim 15, wherein removing first barrier layer material comprises exposing the channel to an alkali etch.22.A multilayer printed circuit board (PCB), comprising a first inner assembly comprising a first PCB core, the first PCB core comprising first and second metallic layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth metallic layers on a second insulating core layer, the third metallic layer of the second PCB core facing the second metallic layer of the first PCB core; a first barrier layer between the second metallic layer and the third metallic layer; a channel extending through the first inner assembly, a width of the channel at the first barrier layer being greater than a width of the channel at the first PCB core; and a sidewall conducting layer on a sidewall of the channel between at least the first and second conducting layers, but not extending from the second conducting layer to the third conducting layer.23.A multilayer printed circuit board (PCB), comprising a first inner assembly comprising a first PCB core, the first PCB core comprising first and second metallic layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth metallic layers on a second insulating core layer, the third metallic layer of the second PCB core facing the second metallic layer of the first PCB core; a first barrier layer between the second metallic layer and the third metallic layer, the first barrier layer being formed of an unreinforced material; a channel extending through the first inner assembly; and a sidewall conducting layer on a sidewall of the channel between at least the first and second conducting layers, but not extending from the second conducting layer to the third conducting layer.24.A multilayer printed circuit board (PCB), comprising a first inner assembly comprising a first PCB core, the first PCB core comprising first and second conducting layers on a first insulating core layer; a second PCB core arranged proximate the first PCB core, the second PCB core comprising third and fourth conducting layers on a second insulating core layer, the third conducting layer of the second PCB core facing the second conducting layer of the first PCB core; a first barrier layer between the second conducting layer and the third conducting layer, the first barrier layer being formed of an unreinforced material; a second inner assembly, the second inner assembly comprising a third PCB core, the third PCB core comprising fifth and sixth conducting layers on a third insulating core layer, the fifth conducting layer facing the fourth conducting layer of the first inner assembly;a fourth PCB core arranged proximate the third PCB core, the fourth PCB core comprising seventh and eighth conducting layers on a fourth insulating core layer, the seventh conducting layer of the fourth PCB core facing the sixth conducting layer of the third PCB core; a second barrier layer between the sixth conducting layer and the seventh conducting layer, the second barrier layer being formed of an unreinforced material, a channel extending through the first inner assembly and the second inner assembly, a width of the channel at the first barrier layer being greater than a width of the channel at the first PCB core and greater than a width of the channel at the second PCB core, a width of the sidewall at the second barrier layer being greater than a width of the sidewall at the third PCB core and greater than a width of the sidewall at the fourth PCB core; and a sidewall conducting layer on a sidewall of the first channel between at the third conducting layer and the sixth, the sidewall conducting layer terminating at the first barrier layer and at the second barrier layer.

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