Reception device and transmission / reception system

Abstract

Provided is a reception device that has a deskew function which enables estimation of an accurate skew amount in a short time at wide data rates. A reception device 20 comprises a clock delay unit 21, a sampling unit 22, and a delay amount setting unit 23. The clock delay unit 21 provides a received clock with a delay and outputs the clock with the delay. The sampling unit 22 samples a received data signal at a timing indicated by the clock output from the clock delay unit 21. The delay amount setting unit 23 sequentially sets a clock delay amount to each value in a training period in which a training data signal and the clock are transmitted from a transmission device 10, acquires a data string that the sampling unit 22 has output by sampling the training data signal at each setting value, and, after the end of the training period, sets a clock delay amount within a matching range in which the data string acquired at each setting value matches the training data signal.

Description

Receiving device and transmitting / receiving system

[0001] The present invention relates to a receiving device and a transmitting / receiving system.

[0002] In a transmission / reception system including a transmitter and a receiver, a digital data signal and a clock signal sent from the transmitter are transmitted to the receiver via a transmission line and received by the receiver, where the received data signal is sampled based on the received clock signal.

[0003] In some cases, separate transmission paths are provided between a transmitting device and a receiving device for a data signal and a clock (see Patent Document 1). In this case, in order for the receiving device to accurately sample the data signal based on the clock (i.e., to suppress the occurrence of data reception errors), it is essential that the difference between the timing of the data signal and the clock when received by the receiving device is sufficiently small compared to the timing of the data signal and the clock when sent by the transmitting device.

[0004] The propagation time (sec) for the data signal and clock sent from the transmitter to the receiver via the transmission line is expressed as the transmission line length (m) divided by the propagation speed (m / sec). Therefore, to prevent data reception errors, it is necessary to ensure that the difference in transmission line length between the data signal transmission line and the clock transmission line is sufficiently small, and that the difference in propagation speed between the data signal and the clock is sufficiently small.

[0005] In applications where large amounts of data are transmitted from a transmitter to a receiver, the data rate of the signal may exceed Gbps. In this case, the signal wavelength is short, on the order of a few centimeters. Therefore, both the difference in transmission path length and the difference in propagation speed between the data signal and the clock must be strictly controlled.

[0006] On the other hand, a technique known as CDR (clock data recovery) is one that avoids the strict requirements of providing separate transmission paths for the data signal and the clock. In CDR, the clock is recovered from the received data signal at the receiving device, and the data signal is sampled based on this clock.

[0007] CDR does not require a transmission path for clock propagation, and the above problems that arise when separate transmission paths are provided for the data signal and the clock do not occur. However, CDR requires additional circuits such as an oscillator and a phase detection circuit in the receiving device, which inevitably increases power consumption.

[0008] In applications requiring low power consumption, a configuration in which separate transmission paths are provided for the data signal and the clock, rather than CDR, is preferable. One standard for such a configuration is MIPI (registered trademark). MIPI (Mobile Industry Processor Interface) is used for communication between a camera sensor and a processor in devices requiring video communication, such as mobile terminals and personal computers, as well as industrial equipment and in-vehicle equipment. MIPI D-PHY, one of the MIPI physical layer standards, provides a high data rate of several Gbps. For this reason, it is specified that the receiving device must compensate for (deskew) the timing difference (skew) between the data signal and the clock.

[0009] A deskew circuit is implemented in a receiving device to compensate for the propagation time difference between a data signal and a clock. The deskew circuit estimates the amount of skew between the data signal and the clock when the receiving device receives it, sets a skew compensation amount based on the estimated skew amount, and compensates (deskews) the skew based on the set skew compensation amount. By compensating for the skew based on an appropriate skew compensation amount, the occurrence of data reception errors can be suppressed.

[0010] The data rate of a data signal transmitted from a transmitting device to a receiving device is not fixed but may vary over a wide range. For example, in the transmission of images and videos assumed in MIPI D-PHY, the image size changes from moment to moment depending on the scene used by the user, and the amount of data transmitted and received changes to FHD, 4K, etc. as needed, and the data rate of the data signal may change accordingly.

[0011] When the data rate of a data signal changes in this way, the deskew circuit must appropriately compensate for the skew at various data rates. For example, MIPI D-PHY version 3.0 specifies that deskew must be performed smoothly over a data rate range of approximately 1.5 Gbps to 4.5 Gbps.

[0012] U.S. Patent No. 9,281,935

[0013] As described above, in applications requiring low power consumption, it is preferable to provide separate transmission paths for the data signal and the clock. However, in this case, a deskew circuit that compensates for the skew in the receiving device is required. This deskew circuit is required to properly compensate for the skew over a wide range of data rates, as well as to be able to estimate the amount of skew in a short time and accurately. However, it is not easy to realize a deskew circuit that can satisfy all of these requirements.

[0014] The present invention has been made to solve the above problems, and aims to provide a receiver with a deskew function that can accurately estimate the amount of skew in a short time over a wide range of data rates, and a transmission / reception system including such a receiver and transmitter.

[0015] The receiving device of the present invention is a receiving device that receives a data signal and a clock sent from a transmitting device, and samples the received data signal based on the received clock.

[0016] A first aspect of the receiving device of the present invention includes (1) a clock delay unit that delays a received clock and outputs the delayed clock, (2) a sampling unit that samples a received data signal at a timing indicated by the clock output from the clock delay unit and outputs the sampled data, and (3) a delay setting unit that sets the delay amount to be applied to the clock by the clock delay unit. The delay setting unit (a) sets the delay amount to each value in sequence from an initial value to an end value during a training period in which a known training data signal and clock are sent from the transmitting device, and acquires a data sequence output by the sampling unit by sampling the training data signal at each delay setting value, and (b) after the training period ends, sets the delay amount within a matching range in which the data sequence acquired during the training period at each delay setting value is consistent with the training data signal.

[0017] In a second aspect of the receiving device of the present invention, in addition to the first aspect, if the delay amount setting value has not reached the end value at the end of a first training period among the multiple training periods, the delay amount setting unit (a) sets the delay amount to each value in sequence in the next second training period, following the first training period, and acquires the data sequence output by the sampling unit by sampling the training data signal at each delay amount setting value, and (b) after the end of the second training period, sets the delay amount within a matching range in which the data sequence acquired at each delay amount setting value in past training periods including the first training period and the second training period is consistent with the training data signal.

[0018] In a third aspect of the receiving apparatus of the present invention, in addition to the first or second aspect, the delay amount setting unit sets the delay amount to the center of the matching range after the training period ends.

[0019] In a fourth aspect of the receiving device of the present invention, in addition to any of the first to third aspects, the delay amount setting unit sets the delay amount within the widest matching range of the multiple matching ranges after the end of the training period if there are multiple matching ranges.

[0020] In a fifth aspect of the receiving device of the present invention, in addition to any one of the first to fourth aspects, the clock delay unit includes a delay element including a first inverter unit and a second inverter unit connected in series. Each of the first inverter unit and the second inverter unit includes a PMOS transistor and an NMOS transistor whose drains are connected to each other, a first resistor circuit with a variable resistance provided between the source of the PMOS transistor and the high-potential supply terminal, and a second resistor circuit with a variable resistance provided between the source of the NMOS transistor and the low-potential supply terminal. Each of the first inverter unit and the second inverter unit outputs a clock, which is a logical inversion of a clock input to the gate of the PMOS transistor and the NMOS transistor, from the drain of the PMOS transistor and the NMOS transistor, and provides a delay to the clock according to the resistance of the first resistor circuit and the second resistor circuit.

[0021] In a sixth aspect of the receiving device of the present invention, in addition to the fifth aspect, the clock delay section includes a plurality of delay elements connected in series.

[0022] In a seventh aspect of the receiving device of the present invention, in addition to the fifth or sixth aspect, the clock delay unit further includes a driving buffer that receives the clock delayed by the delay element and outputs it to the sampling unit.

[0023] In an eighth aspect of the receiving device of the present invention, in addition to any one of the first to seventh aspects, the receiving device complies with the MIPI standard.

[0024] The transmitting / receiving system of the present invention comprises (1) a transmitting device that transmits a data signal and a clock, and (2) the above-mentioned receiving device of the present invention that receives the data signal and clock sent from the transmitting device and samples the received data signal based on the received clock.

[0025] According to the present invention, it is possible to provide a receiving device having a deskew function that can estimate the amount of skew accurately in a short time over a wide range of data rates.

[0026] FIG. 1 is a diagram illustrating a configuration of the transmission / reception system 1. FIG. 2 is a timing chart (FIGS. 2-(a), 2-(b), 2-(c), 2-(d), 2-(e), 2-(f), 2-(g), and 2-(h)) illustrating an example of the operation of the sampling unit 22. FIG. 3 is a diagram illustrating an example of the configuration of the clock delay unit 21. FIG. 4 is a diagram (FIGS. 4-(a) and 4-(b)) illustrating schematic waveform examples of the input clock and output clock in the clock delay unit 21A. FIG. 5 is a diagram illustrating another example of the configuration of the clock delay unit 21. FIG. 6 is a diagram illustrating yet another example of the configuration of the clock delay unit 21. FIG. 7 is a diagram illustrating yet another example of the configuration of the clock delay unit 21. FIG. 8 is a flowchart illustrating the processing content of the delay amount setting unit 23 during a training period. FIG. 9 is a diagram (FIGS. 9-(a) and 9-(b)) illustrating the processing content of the delay amount setting unit 23 after the training period ends. 10A and 10B are diagrams for explaining the processing contents of the delay amount setting unit 23 when there are multiple training periods.

[0027] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicated explanations will be omitted.

[0028] 1 is a diagram showing the configuration of a transmission / reception system 1. The transmission / reception system 1 includes a transmission device 10 and a reception device 20. A transmission path 31 and a transmission path 32 are provided between the transmission device 10 and the reception device 20. The transmission path 31 transmits a data signal output from the transmission device 10 to the reception device 20. The transmission path 32 transmits a clock output from the transmission device 10 to the reception device 20.

[0029] The transmitting device 10 includes a selection unit 11. The selection unit 11 receives a data signal and a clock, selects either the data signal or the clock according to the logical value of a CALEN signal, and sends the selected signal to a transmission path 31. During the training period, the selection unit 11 selects the clock and outputs it to the transmission path 31 as a training data signal. During normal periods other than the training period, the selection unit 11 selects the data signal and outputs it to the transmission path 31.

[0030] The training period is a period for estimating the amount of skew in the receiving device 20. For example, the training period is set immediately after the system is started up, or set periodically or irregularly during the operation of the system.

[0031] The receiving device 20 receives the data signal (or training data signal) and clock sent from the transmitting device 10. The receiving device 20 includes a clock delay unit 21, a sampling unit 22, and a delay amount setting unit 23. The clock delay unit 21 delays the received clock and outputs the delayed clock to the sampling unit 22. The sampling unit 22 samples the received data signal at the timing indicated by the clock output from the clock delay unit 21 and outputs the sampled data. The delay amount setting unit 23 estimates the amount of skew based on the data output from the sampling unit 22, and sets the amount of delay (skew compensation amount) that the clock delay unit 21 will impart to the clock based on this estimation result.

[0032] The clock delay unit 21 and the delay amount setting unit 23 constitute a deskew circuit. That is, the clock delay unit 21 and the delay amount setting unit 23 estimate the amount of skew between the training data signal and the clock when the receiving device 20 receives the signal, set a skew compensation amount based on the estimated skew amount, and compensate (deskew) the skew based on the set skew compensation amount.

[0033] The sampling unit 22 preferably includes flip-flops 41 to 44 and a conversion unit 45. FIG. 2 is a timing chart illustrating an example of the operation of the sampling unit 22. This diagram shows an example of the operation of the sampling unit 22 in a state where skew is compensated. The diagram shows the data signal (FIG. 2-(a)), the output of the clock delay unit 21 (FIG. 2-(b)), the output of the flip-flop 41 (FIG. 2-(c)), the output of the flip-flop 42 (FIG. 2-(d)), the output of the flip-flop 43 (FIG. 2-(e)), the output of the flip-flop 44 (FIG. 2-(f)), the output of the conversion unit 45 (FIG. 2-(g)), and the clock for outputting the conversion unit 45 (FIG. 2-(h)).

[0034] Each of the flip-flops 41, 43, and 44 latches input data at the rising edge of the clock output from the clock delay unit 21. The flip-flop 42 latches input data at the falling edge of the clock output from the clock delay unit 21.

[0035] Flip-flop 41 latches the data signal received by receiving device 20 at the timing of the rising edge of the clock and outputs the latched data to flip-flop 43. Flip-flop 42 latches the data signal received by receiving device 20 at the timing of the falling edge of the clock and outputs the latched data to flip-flop 44.

[0036] Flip-flop 43 latches the data output from flip-flop 41 at the timing of the rising edge of the clock and outputs the latched data to conversion unit 45. Flip-flop 44 latches the data output from flip-flop 42 at the timing of the rising edge of the clock and outputs the latched data to conversion unit 45.

[0037] The conversion unit 45 receives the 2-bit parallel data output from the flip-flops 43 and 44 during each of four cycles of the clock output from the clock delay unit 21, and outputs 8-bit parallel data consisting of these data. The delay amount setting unit 23 receives the 8-bit parallel data output from the conversion unit 45.

[0038] 2 shows a timing chart in which the conversion unit 45 converts 2-bit parallel data into 8-bit parallel data. However, this is not limiting. For example, the conversion unit 45 may convert the 2-bit parallel data output from the flip-flops 43 and 44 into 4-bit parallel data during each of two cycles of the clock output from the clock delay unit 21. By converting the 2-bit parallel data into multi-bit parallel data using the conversion unit 45, the frequency of the clock for driving the delay amount setting unit 23 can be slowed. The conversion unit 45 may also convert the 2-bit parallel data output from the flip-flops 43 and 44 into serial data. The conversion unit 45 may not be provided, and the 2-bit parallel data output from the flip-flops 43 and 44 may be output as is and input to the delay amount setting unit 23.

[0039] 3 is a diagram showing an example configuration of the clock delay unit 21. The clock delay unit 21A shown in this diagram is a delay element 50 consisting of a first inverter unit 51 and a second inverter unit 52 connected in series. The first inverter unit 51 and the second inverter unit 52 have a common configuration. The first inverter unit 51 and the second inverter unit 52 each include a PMOS transistor 61, an NMOS transistor 62, a first resistor circuit 63, and a second resistor circuit 64. The PMOS transistor is a P-channel metal oxide semiconductor transistor and is a field effect transistor (FET). The NMOS transistor is an N-channel metal oxide semiconductor transistor and is also a field effect transistor (FET).

[0040] The drains of the PMOS transistor 61 and the NMOS transistor 62 are connected to each other. The gates of the PMOS transistor 61 and the NMOS transistor 62 are connected to each other. The first resistor circuit 63 is provided between the source of the PMOS transistor 61 and a high potential supply terminal. The second resistor circuit 64 is provided between the source of the NMOS transistor 62 and a low potential supply terminal (ground potential supply terminal). The resistance values ​​of the first resistor circuit 63 and the second resistor circuit 64 are variable and are adjusted by instructions from the delay amount setting unit 23. The resistor circuits 63 and 64 may have a common configuration.

[0041] The first inverter unit 51 and the second inverter unit 52 each output a clock that is the logical inversion of the clock input to the gate of the PMOS transistor 61 and the NMOS transistor 62, which are connected to each other, from the drain of the PMOS transistor 61 and the NMOS transistor 62, which are connected to each other.

[0042] In the clock delay unit 21A, the delay of the output clock relative to the input clock depends on the resistance values ​​of the resistance circuits 63 and 64 of the first inverter unit 51 and the second inverter unit 52. It is preferable that the resistance values ​​of the resistance circuits 63 and 64 are set to the same value.

[0043] 4A and 4B are diagrams showing examples of waveforms of the input clock and the output clock in the clock delay unit 21A. Fig. 4A shows that the delay amount of the output clock relative to the input clock is d when the resistance value R of the resistor circuits 63 and 64 of the first inverter unit 51 and the second inverter unit 52 is set to approximately 0. Fig. 4B shows that the delay amount of the output clock relative to the input clock is d+Δt when the resistance value R of the resistor circuits 63 and 64 of the first inverter unit 51 and the second inverter unit 52 is set to a certain value.

[0044] Each of the resistance circuits 63 and 64 includes a plurality of resistors and one or more switches, and the resistance value can be set by turning on / off each switch. The current flowing through the inverter units 51 and 52 during operation is determined by the potential difference between the high potential supply terminal and the low potential supply terminal and the resistance values ​​of the resistance circuits 63 and 64. Therefore, the clock delay amount (d+Δt) in the clock delay unit 21A can be adjusted by turning on / off each switch in the resistance circuits 63 and 64.

[0045] The larger the resistance value R of the resistor circuits 63 and 64, the longer the delay amount (d+Δt) of the output clock relative to the input clock in the clock delay unit 21A. By appropriately setting the resistance values ​​of the resistor circuits 63 and 64, the delay amount (d+Δt) of the output clock relative to the input clock can have good linearity with respect to the resistance value R. The delay adjustment amount Δt is approximately proportional to the resistance value R. The adjustment step Δt of the delay amount of the output clock relative to the input clock min corresponds to the adjustment step of the resistance value R.

[0046] To prevent the clock from being damaged by the delay provided by the clock delay unit 21A, it is preferable to adjust the resistance value R of the resistance circuits 63 and 64 so that the delay adjustment amount Δt does not exceed 1 UI (unit interval). To achieve a larger delay amount, the clock delay unit may have the configuration example shown in FIG.

[0047] 5 is a diagram showing another example of the configuration of the clock delay unit 21. The clock delay unit 21B shown in this figure has N delay elements 50 connected in series. １ ~50 Ｎ and a driving buffer 70. N is an integer equal to or greater than 2. N delay elements 50 １ ~50 Ｎ Each of them has a configuration similar to that of the delay element 50 (clock delay unit 21A) shown in FIG.

[0048] The larger N or the larger the resistance value R, the larger the delay element 50 ＮThe slew rate (the rate of change of the output voltage value over time) of the clock output from the sampling section 22 is small. On the other hand, it is preferable that the slew rate of the clock supplied to the sampling section 22 is large in order to determine the timing of sampling data in the sampling section 22. Therefore, it is preferable to provide a driving buffer 70. The driving buffer 70 is a clock that is supplied to the delay element 50 at the final stage. Ｎ The clock output from the clock delay unit 21B is input and output to the sampling unit 22. By providing the driving buffer 70, the slew rate of the output clock from the clock delay unit 21B can be increased.

[0049] N delay elements 50 １ ~50 Ｎ The n-th delay element 50 ｎ The delay amount at ｎ Then, the delay of the output clock relative to the input clock is Nd+Δt １ +Δt ２ + ... +Δt Ｎ Among these, the delay adjustment amount ΔT=Δt １ +Δt ２ + ... +Δt Ｎ is N delay elements 50 １ ~50 Ｎ This can be adjusted by setting the resistance values ​​of the respective resistor circuits 63 and 64 .

[0050] 6 is a diagram showing yet another example configuration of the clock delay unit 21. The clock delay unit 21C shown in this diagram includes a plurality of inverters 80 connected in series and a voltage adjustment unit 81. The voltage adjustment unit 81 adjusts the voltage value applied to each of the plurality of inverters in response to an instruction from the delay amount setting unit 23. In the clock delay unit 21C, the delay of the output clock relative to the input clock corresponds to the voltage value applied to each of the plurality of inverters.

[0051] 7 is a diagram showing yet another example configuration of the clock delay unit 21. The clock delay unit 21D shown in this diagram includes a plurality of inverters 80 connected in series and a selection unit 82. The selection unit 82 selects and outputs a clock output from one of the plurality of inverters 80 in response to an instruction from the delay amount setting unit 23. In the clock delay unit 21D, the delay of the output clock relative to the input clock depends on the number of inverters 80 that the clock passes through from input to output.

[0052] Of clock delay unit 21A (FIG. 3), clock delay unit 21B (FIG. 5), clock delay unit 21C (FIG. 6), and clock delay unit 21D (FIG. 7), the configurations of clock delay unit 21A (FIG. 3) and clock delay unit 21B (FIG. 5) are preferable for the following reasons.

[0053] In the clock delay unit 21C (FIG. 6), the terminal voltage of the transistor of the nonlinear element that constitutes each inverter changes directly, so the delay amount does not have good linearity with the voltage value applied to each inverter, making it difficult to estimate the skew amount. To properly deskew over a wide range of data rates, a wide variable range of delay amount is required, which requires a large number of inverters connected in series. This undesirably increases power consumption.

[0054] In the clock delay unit 21D (FIG. 7), the delay adjustment step is the sum of the delays of the two inverter stages. Therefore, the maximum data rate at which deskewing is possible is determined by the performance of the transistors constituting each inverter, which is a significant constraint. Furthermore, deskewing at low data rates requires a large number of inverters connected in series. This is undesirable because it increases power consumption.

[0055] Compared to clock delay unit 21C (FIG. 6) and clock delay unit 21D (FIG. 7), clock delay unit 21A (FIG. 3) and clock delay unit 21B (FIG. 5) are preferable because they consume less power, have excellent linearity in the amount of delay, and can accommodate a wide range of data rates.

[0056] In the flip-flops 41 to 44 included in the sampling unit 22, a setup violation or a hold violation occurs depending on the input timing of the data and the clock, and erroneous data is latched. The clock delay unit 21 gives an appropriate delay to the received clock so that neither a setup violation nor a hold violation occurs, and outputs the delayed clock to the sampling unit 22. To achieve this, the amount of delay that the clock delay unit 21 gives to the clock is adjusted by an adjustment width MΔt min In the range of the adjustment step Δt min If it is possible to set (M+1) steps, the delay amount adjustment step Δt min is preferably smaller than "1 UI - (setup time + hold time)", and the delay amount adjustment width MΔt min is preferably greater than the "setup time + hold time".

[0057] Next, the processing contents of the delay amount setting unit 23 will be described in detail. The processing of the delay amount setting unit 23 includes processing during a training period and processing after the end of the training period. The training period is a period during which the receiving device 20 receives a training data signal to estimate the amount of skew. In MIPI, immediately after the system is started, １５ A training period of at least 20 minutes is provided, and training sessions are held periodically or irregularly during system operation. １０ A training period of at least 1000 Mbps is provided. The frequency of the training periods depends on the requirements of the application. The receiving device is MIPI standard compliant.

[0058] During the training period, a known training data signal and clock are sent from the transmitting device 10 to the receiving device 20. The training data signal is preferably a signal in which a data sequence of a fixed pattern is repeated. In MIPI, a signal whose logical value is inverted every UI is sent as the training data signal. The training data signal sent from the transmitting device 10 may have the same waveform as the clock sent from the transmitting device 10. In the configuration shown in FIG. 1, during the training period, a clock is selected by the selector 11 in the transmitting device 10, and this is sent to the transmission path 31 as the training data signal.

[0059] During the training period, the delay amount setting unit 23 adjusts the delay amount given to the clock in the clock delay unit 21 by a fixed amount (adjustment step Δt min ) to set each set value in turn. The delay setting section 23 then acquires the data string output by the sampling section 22 after sampling the training data signal at each set value of the delay amount.

[0060] After the training period ends, the delay amount setting unit 23 sets the delay amount to be given to the clock in the clock delay unit 21 thereafter within a matching range in which the data sequence acquired at each delay amount setting value during the training period is matched with the training data signal.

[0061] The processing contents of the delay amount setting unit 23 during the training period are specifically as follows: The delay amount given to the clock by the clock delay unit 21 is adjusted by an adjustment width MΔt min In the range of the adjustment step Δt min The delay adjustment amount ΔT can be set in (M+1) steps. ｍ is ΔT ｍ = mΔt min where m is a parameter that can take an integer between 0 and M. The initial value ΔT of the delay adjustment amount ０ is 0, and the final value of the delay adjustment amount ΔT Ｍ is MΔt min is.

[0062] 8 is a flowchart illustrating the processing contents of the delay amount setting unit 23 during the training period. In step S1, the delay amount setting unit 23 sets m to 0. In step S2, the delay amount setting unit 23 sets the delay adjustment amount ΔT corresponding to the value of m. ｍ In step S3, the delay amount setting unit 23 sets the delay adjustment amount ΔT ｍ With m set, the sampling unit 22 samples the data sequence output from the sampling unit 22 to obtain it. In step S4, the delay amount setting unit 23 increments the value of m by 1. In step S5, the delay amount setting unit 23 determines whether m exceeds M. If the delay amount setting unit 23 determines in step S5 that m exceeds M, it determines that the end value of the delay adjustment amount has been reached and ends the processing. If the delay amount setting unit 23 determines in step S5 that m does not exceed M, it returns to step S2. In this way, the processing of steps S2 and S3 is performed for each value of m in the range from m=0 to m=M.

[0063] Specifically, the processing performed by the delay setting unit 23 after the training period is as follows: The delay setting unit 23 determines whether the data sequence acquired during the training period at each delay setting value is consistent with the training data signal. This determination may be made if the training data signal contains a data sequence of the same pattern as the acquired data sequence at each delay setting value.

[0064] For example, when a training data signal is used in which the logical value is inverted every UI (i.e., the logical value of each bit is repeated as 10101010...), if the data sequence output from the sampling unit 22 has a pattern in which the logical value is inverted every UI (10101010... or 01010101...), then the data sequence output from the sampling unit 22 is consistent with the training data signal, and a delay amount sufficient to enable appropriate deskew has been given to the clock in the clock delay unit 21.

[0065] When a training data signal whose logical value inverts every UI is used, if the pattern obtained when taking the bit-wise exclusive OR of the data sequence output from the sampling unit 22 and the pattern of the training data signal is 00000000... or 11111111..., then the data sequence output from the sampling unit 22 is consistent with the training data signal, and a delay amount sufficient to enable appropriate deskew has been given to the clock in the clock delay unit 21.

[0066] Therefore, the delay amount setting unit 23 counts the number of bits for which the value of the exclusive OR for each bit of the data sequence of the number K of bits output from the sampling unit 22 and the pattern of the training data signal is 1 for each set value of the delay amount, and calculates the count value (C ０ ) is 0 or K, it can be determined that the clock delay unit 21 has given the clock an amount of delay that enables appropriate deskew.

[0067] 9A and 9B are diagrams for explaining the processing contents of the delay amount setting unit 23 after the end of the training period. ０ ) is shown. FIG. 9-(b) shows the waveform of the training data signal input to the sampling unit 22. The horizontal axis of FIG. 9-(b) represents the sampling timing in the sampling unit 22 as an m value. In the example shown in this figure, in each of the first matching range (RG1) from m=0 to m=2, the second matching range (RG2) from m=4 to m=8, and the third matching range (RG3) from m=9 to m=15, the data sequence acquired at each set value of the delay amount is matched with the training data signal, and a delay amount is applied to the clock in the clock delay unit 21 that enables appropriate deskew.

[0068] The delay amount setting unit 23 sets the delay amount to be given to the clock in the clock delay unit 21 thereafter to anywhere within the first matching range (RG1) to the third matching range (RG3). The delay amount setting unit 23 preferably sets the delay amount to be given to the clock in the clock delay unit 21 thereafter to the center of any of the first matching range (RG1) to the third matching range (RG3). Also, the delay amount setting unit 23 preferably sets the delay amount to be given to the clock in the clock delay unit 21 thereafter to within the third matching range (RG3), which is the widest of the first matching range (RG1) to the third matching range (RG3). In this example, ΔT corresponding to m=12, which is the center of the third matching range (RG3), is set to 0. １２ It is most preferable to set it to

[0069] Since the length of the training period is limited, the delay amount setting unit 23 changes the delay amount given to the clock in the clock delay unit 21 by a fixed amount from the initial value toward the end value to set each setting value in sequence. However, there are cases where the set value of the delay amount does not reach the end value within the training period. In such cases, if there are multiple training periods, the delay amount setting unit 23 can perform the following processing.

[0070] If the delay setting value has not reached the end value at the end of a first training period among the multiple training periods, the delay setting unit 23 sets the delay to each value in sequence during the following second training period, following the first training period, and acquires the data sequence output by the sampling unit 22 after sampling the training data signal at each delay setting value. Then, after the end of the second training period, the delay setting unit 23 sets the delay to be applied to the clock by the clock delay unit 21 within a matching range in which the data sequence acquired at each delay setting value during past training periods including the first training period and the second training period is matched with the training data signal. In this case, too, if there are multiple matching ranges after the end of each training period, it is most preferable to set the delay corresponding to the m value that is at the center of the widest matching range among these multiple matching ranges.

[0071] 10A and 10B are diagrams for explaining the processing contents of the delay amount setting unit 23 when there are multiple training periods. ０ ) is shown. Figure 10-(b) shows the transition of the optimal m value after the end of each training period. In this figure, training periods A to F are set in order. The delay amount setting unit 23 sets the delay amount to each value from m = 0 to m = 2 in training period A, sets the delay amount to each value from m = 3 to m = 5 in training period B, sets the delay amount to each value from m = 6 to m = 8 in training period C, sets the delay amount to each value from m = 9 to m = 11 in training period D, sets the delay amount to each value from m = 12 to m = 14 in training period E, and sets the delay amount to each value from m = 15 to m = 17 in training period F. Then, the delay amount setting unit 23 acquires the data sequence output by the sampling unit 22 by sampling the training data signal at each delay amount setting value during each training period.

[0072] In this case, after the end of the training period A, the delay amount setting unit 23 sets ΔT corresponding to m=1, which is the center of the matching period from m=0 to m=2. １ After the end of the training period C, the matching period from m=4 to m=8 is longer than the matching period from m=0 to m=2, so the delay amount setting unit 23 sets ΔT corresponding to m=6, which is the center of the matching period from m=4 to m=8. ６ After the end of the training period E, the matching period from m=9 to m=14 is the longest, so the delay amount setting unit 23 sets ΔT corresponding to m=11, which is the center of this matching period. １１ (Or, ΔT corresponding to m=12 １２ )

[0073] In this way, even if the set value of the delay amount does not reach the end value within a certain training period, the delay amount setting unit 23 continues to set the delay amount to each value in turn within the next training period, and by acquiring the data string output by the sampling unit 22 after sampling the training data signal at each set value of the delay amount, it is possible to optimally set the delay amount to be given to the clock in the clock delay unit 21 thereafter. The delay amount setting unit 23 can be configured from a logic circuit, and can set the delay amount in the clock delay unit 21 (delay circuit) according to the output signal of the sampling unit 22 (sampler).

[0074] As described above, the receiving device of this embodiment has a deskew function that can estimate an accurate amount of skew in a short time over a wide range of data rates. Furthermore, even if the training period is short, the receiving device has a function that can pause training and resume training when a training pattern is input again, allowing for accurate estimation of the amount of skew and providing a deskew function.

[0075] A signal indicating the delay amount specified by the delay amount setting unit 23 can be input to the control terminal of the variable resistance resistor circuit in Figure 3. If multiple resistors are connected in series or parallel in the resistor circuit, the overall resistance value may be changed by applying a potential to the gate of a transistor so that a current flows through the corresponding resistor. In this case, each gate serves as a delay amount control terminal. Each flip-flop in the receiving device 20 in Figure 1 has an input terminal for a data signal and an input terminal for a sampling clock. The receiving device 20 includes a delay circuit (clock delay unit 21) connected to a clock receiving terminal, a sampler (sampling unit 22) connected to a data signal receiving terminal (data input terminal of flip-flop 41), and a delay setting unit 23 connected to the output terminal of the sampling unit 22. The output terminal of the delay setting unit 23 is connected to a delay control terminal of the clock delay unit 21, and the output terminal of the clock delay unit 21 is connected to a sampling clock input terminal of the sampling unit 22 (clock input terminal of each flip-flop in FIG. 1). The delay setting unit 23 sets the delay to each value in sequence from an initial value to an end value, acquires the data sequence output by the sampling unit 22 at each delay setting value, and can set a delay that matches the data sequence with a known training data signal. Note that the present invention is not limited to the above examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0076] 1...Transmission and reception system, 10...Transmitter, 11...Selector, 20...Receiver, 21, 21A to 21D...Clock delay unit, 22...Sampling unit, 23...Delay amount setting unit, 31, 32...Transmission path, 41 to 44...Flip-flops, 45...Converter, 50, 50 １ ~50 Ｎ ...delay element, 51...first inverter section, 52...second inverter section, 61...PMOS transistor, 62...NMOS transistor, 63...first resistance circuit, 64...second resistance circuit, 70...drive buffer, 80...inverter, 81...voltage adjustment section, 82...selection section.

Claims

1. A receiving device that receives a data signal and a clock sent from a transmitting device and samples the received data signal based on the received clock, comprising: a clock delay unit that delays the received clock and outputs the delayed clock; a sampling unit that samples the received data signal at a timing indicated by the clock output from the clock delay unit and outputs the sampled data; and a delay amount setting unit that sets the amount of delay that the clock delay unit gives to the clock, wherein the delay amount setting unit sets the amount of delay to each value in sequence from an initial value to an end value during a training period in which a known training data signal and clock are sent from the transmitting device, and obtains a data sequence output by the sampling unit by sampling the training data signal at each set value of the delay amount, and after the training period ends, sets the delay amount within a consistency range in which the data sequence obtained during the training period at each set value of the delay amount is consistent with the training data signal.

2. The receiving device of claim 1, wherein the delay amount setting unit, if the set value of the delay amount has not reached an end value at the end of a first training period among a plurality of training periods, sets the delay amount to each value in sequence following the first training period in the next second training period, and acquires a data sequence output by the sampling unit by sampling the training data signal at each set value of the delay amount, and after the end of the second training period, sets the delay amount within a consistency range in which the data sequence acquired at each set value of the delay amount in past training periods including the first training period and the second training period is consistent with the training data signal.

3. The receiving device according to claim 1, wherein the delay amount setting unit sets the delay amount to the center of the matching range after the training period ends.

4. The receiving device according to claim 1, wherein, when there are multiple matching ranges after the end of the training period, the delay amount setting unit sets the delay amount within the widest matching range among the multiple matching ranges.

5. The receiving device according to claim 1, wherein the clock delay section comprises a delay element including a first inverter section and a second inverter section connected in series, each of the first inverter section and the second inverter section comprising: a PMOS transistor and an NMOS transistor whose drains are connected to each other; a first resistance circuit which is provided between the source of the PMOS transistor and a high potential supply end and has a variable resistance; and a second resistance circuit which is provided between the source of the NMOS transistor and a low potential supply end and has a variable resistance; a clock which is logically inverted from a clock input to the gates of the PMOS transistor and the NMOS transistor, is output from the drains of the PMOS transistor and the NMOS transistor, and a delay is given to the clock according to the resistance values ​​of the first resistance circuit and the second resistance circuit, 6. The receiving device according to claim 5, wherein the clock delay section comprises a plurality of the delay elements connected in series.

7. The receiving device according to claim 5, wherein said clock delay section further comprises a driving buffer which receives as input the clock delayed by said delay element and outputs to said sampling section.

8. The receiving device according to claim 1, which is compliant with the MIPI standard.

9. A transmitting / receiving system comprising: a transmitting device that transmits a data signal and a clock; and a receiving device according to claim 1 that receives the data signal and clock sent from the transmitting device and samples the received data signal based on the received clock.

10. A receiving device comprising: a delay circuit connected to a clock receiving terminal; a sampler connected to a data signal receiving terminal; and a delay amount setting unit connected to an output terminal of the sampler, wherein the output terminal of the delay amount setting unit is connected to a delay amount control terminal of the delay circuit, and the output terminal of the delay circuit is connected to a sampling clock input terminal of the sampler, and the delay amount setting unit sets the delay amount to each value in sequence from an initial value to an end value, acquires a data sequence output by the sampler at each set value of the delay amount, and sets a delay amount that matches the data sequence with a known training data signal.

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