Semiconductor storage device

Abstract

A semiconductor storage device according to an embodiment of the present disclosure comprises: a first via which is provided in a path connecting a first connection terminal and a connecting node, and which is capable of irreversibly adopting a high resistance state as a result of a current being passed therethrough; a second via which is provided in a path connecting the connecting node and a second connection terminal, and which is capable of irreversibly adopting a high resistance state as a result of a current being passed therethrough; a third via which is provided in a path connecting the connecting node and a third connection terminal, and which is capable of irreversibly adopting a high resistance state as a result of a current being passed therethrough; and a write circuit which is connected to the first connection terminal, the second connection terminal, and the third connection terminal, and which is capable of causing a write current to flow in both directions between the first connection terminal and the second connection terminal, and is capable of causing a write current to flow in both directions between the first connection terminal and the third connection terminal.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device capable of storing data.

[0002] Semiconductor memory devices include one-time programmable (OTP) memory devices that can write data only once. In such OTP memory devices, data is stored by, for example, passing a current through a memory element to change the resistance value of the memory element. For example, Patent Document 1 discloses a semiconductor memory device that uses an electrical fuse configured to include a via.

[0003] JP 2009-252870 A

[0004] In such an OTP type memory device, current consumption can be high when writing data, so it is desirable to be able to reduce power consumption while shortening the writing time.

[0005] It is desirable to provide a semiconductor memory device that can reduce power consumption while shortening the write time.

[0006] A semiconductor memory device according to an embodiment of the present disclosure includes a first via, a second via, a third via, and a write circuit. The first via is provided in a path connecting a first connection terminal and a connection node, and is capable of irreversibly becoming a high resistance state when a current is passed through the first via. The second via is provided in a path connecting a connection node and a second connection terminal, and is capable of irreversibly becoming a high resistance state when a current is passed through the second via. The third via is provided in a path connecting a connection node and a third connection terminal, and is capable of irreversibly becoming a high resistance state when a current is passed through the third via. The write circuit is connected to the first connection terminal, the second connection terminal, and the third connection terminal, and is capable of bidirectionally passing a write current between the first connection terminal and the second connection terminal, and is capable of bidirectionally passing a write current between the first connection terminal and the third connection terminal.

[0007] In a semiconductor memory device according to an embodiment of the present disclosure, a first via is provided in a path connecting a first connection terminal and a connection node, a second via is provided in a path connecting a connection node and a second connection terminal, and a third via is provided in a path connecting a connection node and a third connection terminal. For example, a write current flows bidirectionally between the first connection terminal and the second connection terminal by a write circuit. Also, for example, a write current flows bidirectionally between the first connection terminal and the third connection terminal by a write circuit.

[0008] FIG. 1 is a block diagram illustrating an example configuration of a semiconductor memory device according to an embodiment of the present disclosure. FIG. 2 is an explanatory diagram illustrating an example configuration of the memory circuit illustrated in FIG. 1. FIG. 3 is another explanatory diagram illustrating an example configuration of the memory circuit illustrated in FIG. 1. FIG. 4A is an explanatory diagram illustrating an example of a write operation in the memory circuit illustrated in FIG. 1. FIG. 4B is an explanatory diagram illustrating another example of a write operation in the memory circuit illustrated in FIG. 1. FIG. 4C is an explanatory diagram illustrating another example of a write operation in the memory circuit illustrated in FIG. 1. FIG. 5 is an explanatory diagram illustrating the relationship between the memory circuit illustrated in FIG. 1 and two bits stored therein. FIG. 6 is a circuit diagram illustrating an example configuration of the write circuit illustrated in FIG. 1. FIG. 7 is a circuit diagram illustrating an example configuration of the read circuit illustrated in FIG. 1. FIG. 8 is a table illustrating an example of a write operation in the semiconductor memory device illustrated in FIG. 1. FIG. 9A is an explanatory diagram illustrating an example of a write operation in the semiconductor memory device illustrated in FIG. 1. FIG. 9B is an explanatory diagram illustrating another example of a write operation in the semiconductor memory device illustrated in FIG. 1. FIG. 9C is an explanatory diagram illustrating another example of a write operation in the semiconductor memory device illustrated in FIG. 1. FIG. 10A is an explanatory diagram illustrating an example of a read operation in the semiconductor memory device shown in FIG. 1 . FIG. 10B is an explanatory diagram illustrating another example of a read operation in the semiconductor memory device shown in FIG. 1 . FIG. 11A is an explanatory diagram illustrating an example of a write operation in a memory circuit according to a modified example. FIG. 11B is an explanatory diagram illustrating an example of a write operation in a memory circuit according to another modified example. FIG. 11C is an explanatory diagram illustrating an example of a write operation in a memory circuit according to another modified example. FIG. 12A is an explanatory diagram illustrating an example of a write operation in a memory circuit according to another modified example. FIG. 12B is an explanatory diagram illustrating another example of a write operation in a memory circuit according to another modified example. FIG. 12C is an explanatory diagram illustrating another example of a write operation in a memory circuit according to another modified example. FIG. 13 is a circuit diagram illustrating an example configuration of a write circuit according to another modified example. FIG. 14 is a table illustrating an example of a write operation in a semiconductor memory device according to another modified example. FIG. 15A is an explanatory diagram illustrating an example of a write operation in a semiconductor memory device according to another modified example. FIG. 15B is an explanatory diagram illustrating another example of a write operation in a semiconductor memory device according to another modified example. FIG. 15C is an explanatory diagram illustrating another example of a write operation in a semiconductor memory device according to another modification.Fig. 16 is an explanatory diagram showing an example of the configuration of a memory circuit according to another modified example. Fig. 17 is another explanatory diagram showing an example of the configuration of a memory circuit according to another modified example. Fig. 18 is an explanatory diagram showing an example of the configuration of a memory circuit according to another modified example.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0010] 1 shows an example of the configuration of a semiconductor memory device (semiconductor memory device 1) according to an embodiment. The semiconductor memory device 1 is an OTP-type memory device. The semiconductor memory device 1 includes a memory circuit 10, switches 11 to 13, transistors MN14 and MN15, a write circuit 20, a read circuit 30, and a control circuit 16.

[0011] The memory circuit 10 is configured to store two bits of data. The memory circuit 10 has vias V1 to V3. In FIG. 1, each of the vias V1 to V3 is represented by a symbol of a resistive element. One end of the via V1 is connected to a terminal T1, and the other end is connected to a node NN. One end of the via V2 is connected to the node NN, and the other end is connected to a terminal T2. One end of the via V3 is connected to the node NN, and the other end is connected to a terminal T3. As will be described later, each of the vias V1 to V3 is configured to be destroyed by passing a write current Iw through it, and to become irreversibly in a high resistance state.

[0012] 2 shows an example of the configuration of the memory circuit 10. The memory circuit 10 has interconnects 111, 112, 121, and 131. In this semiconductor memory device 1, a metal interconnect layer ML1, a via layer VL1, a metal interconnect layer ML2, a via layer VL2, and a metal interconnect layer ML3 are stacked in this order. The metal interconnect layer ML1 is the bottommost metal interconnect layer, the metal interconnect layer ML2 is the second metal interconnect layer from the bottom, and the metal interconnect layer ML3 is the third metal interconnect layer from the bottom.

[0013] The wiring 131 corresponds to the terminal T1 and is provided in the metal wiring layer ML3. The via V1 is provided in the via layer VL2. The wiring 121 corresponds to the node NN and is provided in the metal wiring layer ML2. The vias V2 and V3 are provided in the via layer VL1. The wirings 111 and 112 correspond to the terminals T2 and T3, respectively, and are provided in the metal wiring layer ML1.

[0014] One end of the via V1 is connected to the wiring 131, and the other end is connected to the wiring 121. One end of the via V2 is connected to the wiring 121, and the other end is connected to the wiring 111. One end of the via V3 is connected to the wiring 121, and the other end is connected to the wiring 112.

[0015] 3 shows an example of the arrangement of vias V1 to V3. This FIG. 3 shows the positions of vias V1 to V3 as viewed from above in the stacking direction. Via V2 is arranged near one end of wiring 121 in the extension direction, and via V3 is arranged near the other end of wiring 121 in the extension direction. Via V1 is provided at a position between the positions of via V2 and via V3. In this example, vias V2 and V3 are provided at positions symmetrical to each other as viewed from via V2.

[0016] In the memory circuit 10, a write operation selectively destroys one of the vias V1 to V3, and the via changes from a low resistance state (low resistance state) to a high resistance state (high resistance state), thereby storing data in the memory circuit 10.

[0017] 4A to 4C show an example of a data write operation in the memory circuit 10. Before being destroyed, the vias V1 to V3 are in a state where the resistance value is low (low resistance state).

[0018] 4A , when the power supply voltage VDD is applied to the wiring 131, the ground voltage VGND is applied to the wiring 111, and the wiring 112 is in a floating state, the write current Iw flows in the order of the wiring 131, the via V1, the wiring 121, the via V2, and the wiring 111. In this case, in this example, the via V2 is destroyed, and the resistance state of the via V2 becomes a high resistance state.

[0019] 4B , when the power supply voltage VDD is applied to the wiring 131, the wiring 111 is in a floating state, and the ground voltage VGND is applied to the wiring 112, the write current Iw flows in the order of the wiring 131, the via V1, the wiring 121, the via V3, and the wiring 112. In this case, in this example, the via V3 is destroyed, and the resistance state of the via V3 becomes a high resistance state.

[0020] 4C , when the ground voltage VGND is applied to the wiring 131, the power supply voltage VDD is applied to the wiring 111, and the wiring 112 is in a floating state, the write current Iw flows in the order of the wiring 111, the via V2, the wiring 121, the via V1, and the wiring 131. In this case, in this example, the via V1 is destroyed, and the resistance state of the via V1 becomes a high resistance state.

[0021] In this example, as shown in Figures 4A and 4B, when a write current Iw flows from the wiring 131 in the metal wiring layer ML3 toward the wiring 111 or 112 in the metal wiring layer ML1, the via V1 in the via layer VL2 is not destroyed, but the via V2 or the via V3 in the via layer VL1 is destroyed. Also, as shown in Figure 4C, when a write current Iw flows from the wiring 111 or 112 in the metal wiring layer ML1 toward the wiring 131 in the metal wiring layer ML3, the vias V2 and V3 in the via layer VL1 are not destroyed, but the via V1 in the via layer VL2 is destroyed. This operation is one example, and can be set by, for example, the distance between the memory circuit 10 and the write circuit 20, the heat distribution in the memory circuit 10, the structure of the vias V1 to V3, etc. Such a memory circuit 10 was prototyped, and the reproducibility of this operation was confirmed.

[0022] 5 shows the relationship between the memory circuit 10 and two bits of data that can be stored in the memory circuit 10. This memory circuit 10 can store two bits of data including bits B1 and B2. Bit B1 corresponds to the resistance value in the path connecting terminal T1 (wiring 131) and terminal T2 (wiring 111), and bit B2 corresponds to the resistance value in the path connecting terminal T1 (wiring 131) and terminal T3 (wiring 112).

[0023] 4A, when the resistance state of via V2 is high and the resistance states of vias V1 and V3 are low, the resistance value of the path connecting terminals T1 and T2 is high and the resistance value of the path connecting terminals T1 and T3 is low. Therefore, in this example, bit B1 is "1" and bit B2 is "0".

[0024] 4B, when the resistance state of via V3 is high and the resistance states of vias V1 and V2 are low, the resistance value of the path connecting terminals T1 and T2 is small, and the resistance value of the path connecting terminals T1 and T3 is large. Therefore, in this example, bit B1 is "0" and bit B2 is "1".

[0025] 4C , when the resistance state of via V1 is high and the resistance states of vias V2 and V3 are low, the resistance values ​​of the path connecting terminals T1 and T2 and the path connecting terminals T1 and T3 are both large. Therefore, in this example, bit B1 is “1” and bit B2 is “1.”

[0026] Furthermore, for example, when the resistance states of all of the vias V1 to V3 are in the low resistance state, the resistance value in the path connecting the terminals T1 and T2 and the resistance value in the path connecting the terminals T1 and T3 are both small. Therefore, in this example, bit B1 is "0" and bit B2 is "0".

[0027] In this way, the memory circuit 10 is capable of storing two bits of data according to the resistance states of the three vias V1 to V3.

[0028] The switch 11 (FIG. 1) is configured to connect the terminal T1 of the memory circuit 10 to the write circuit 20 or the read circuit 30 based on the control signal CTL. The switch 12 is configured to connect the terminal T2 of the memory circuit 10 to the write circuit 20 or the drain of the transistor MN14 based on the control signal CTL. The switch 13 is configured to connect the terminal T3 of the memory circuit 10 to the write circuit 20 or the drain of the transistor MN15 based on the control signal CTL. When the semiconductor memory device 1 writes data to the memory circuit 10, the switches 11 to 13 connect the terminals T1 to T3 of the memory circuit 10 to the write circuit 20 based on the control signal CTL. In addition, when the semiconductor memory device 1 reads data from the memory circuit 10, the switches 11 to 13 connect the terminal T1 of the memory circuit 10 to the read circuit 30, connect the terminal T2 of the memory circuit 10 to the drain of the transistor MN14, and connect the terminal T3 of the memory circuit 10 to the drain of the transistor MN15 based on the control signal CTL.

[0029] The transistors MN14 and MN15 are N-type MOS (Metal Oxide Semiconductor) transistors. A control signal supplied from the control circuit 16 is applied to the gate of the transistor MN14, the drain is connected to the switch 12, and the source is grounded. A control signal supplied from the control circuit 16 is applied to the gate of the transistor MN15, the drain is connected to the switch 13, and the source is grounded.

[0030] The write circuit 20 is configured to write data to the memory circuit 10 based on signals SB1 and SB2 supplied from the control circuit 16. The signal SB1 corresponds to bit B1, and the signal SB2 corresponds to bit B2.

[0031] 6 shows an example of the configuration of the write circuit 20. Also shown in FIG. 6 are the memory circuit 10, switches 11 to 13, and transistors MN14 and MN15. The write circuit 20 includes inverters 41 and 42, NAND circuits (NAND) 43 and 44, a transistor MN49, an inverter 51, a NAND circuit 52, an inverter 53, a NAND circuit 54, a transistor MN59, an inverter 61, and a logical product circuit (AND) 62. The transistors MN49, MN59, and MN69 are N-type MOS transistors.

[0032] The inverter 41 is configured to obtain the negation of the signal SB1. The inverter 42 is configured to obtain the negation of the signal SB2. The NAND circuit 43 is configured to obtain the NAND of the output signal of the inverter 41 and the output signal of the inverter 42. The NAND circuit 44 is configured to obtain the NAND of the signal SB1 and the signal SB2. The output signal of the NAND circuit 43 is supplied to the gate of the transistor MN49, the output signal of the NAND circuit 44 is supplied to the source of the transistor MN49, and the drain is connected to the switch 11.

[0033] The inverter 51 is configured to obtain the negation of the signal SB1. The NAND circuit 52 is configured to obtain the NAND of the output signal of the inverter 51 and the signal SB2. The inverter 53 is configured to obtain the negation of the signal SB2. The NAND circuit 54 is configured to obtain the NAND of the signal SB1 and the output signal of the inverter 53. The output signal of the NAND circuit 52 is supplied to the gate of the transistor MN59, the output signal of the NAND circuit 54 is supplied to the source, and the drain is connected to the switch 12.

[0034] The inverter 61 is configured to obtain the negation of the signal SB1. The logical product circuit 62 is configured to obtain the logical product of the output signal of the inverter 61 and the signal SB2. The output signal of the logical product circuit 62 is supplied to the gate of the transistor MN69, the ground voltage VGND is applied to the source, and the drain is connected to the switch 13.

[0035] With this configuration, the write circuit 20 writes data into the memory circuit 10 based on the signals SB 1 and SB 2 supplied from the control circuit 16 .

[0036] The read circuit 30 (FIG. 1) is configured to read data stored in the memory circuit 10 based on a control signal supplied from the control circuit 16 .

[0037] 7 shows an example of the configuration of the readout circuit 30. Also shown in FIG. 7 are the memory circuit 10, switches 11 to 13, and transistors MN14 and MN15. The readout circuit 30 includes transistors MP31, MN32, MP33, and MN34, a resistive element 35, a transistor MN36, a comparator 37, and a readout control circuit 38. The transistors MP31 and MP33 are P-type MOS transistors, and the transistors MN32, MN34, and MN36 are N-type MOS transistors.

[0038] A control signal is supplied to the gate of transistor MP31 from the read control circuit 38, the power supply voltage VDD is supplied to the source, and the drain is connected to the drain of transistor MN32 and the positive input terminal of comparator 37. A control signal is supplied to the gate of transistor MN32 from the read control circuit 38, the drain is connected to the drain of transistor MP31 and the positive input terminal of comparator 37, and the source is connected to switch 11. A control signal is supplied to the gate of transistor MP33 from the read control circuit 38, the power supply voltage VDD is supplied to the source, and the drain is connected to the drain of transistor MN34 and the negative input terminal of comparator 37. A control signal is supplied to the gate of transistor MN34 from the read control circuit 38, the drain is connected to the drain of transistor MP33 and the negative input terminal of comparator 37, and the source is connected to resistor 35. One end of resistor 35 is connected to the source of transistor MN34, and the other end is connected to the drain of transistor MN36. The resistance value of the resistor element 35 is set to, for example, an intermediate value between the resistance value when the vias V1 to V3 are in a high resistance state and the resistance value when the vias V1 to V3 are in a low resistance state. A control signal is supplied to the gate of the transistor MN36 from the read control circuit 38, the drain is connected to the other end of the resistor element 35, and the source is grounded. The positive input terminal of the comparator 37 is connected to the drains of the transistors MP31 and MN32, and the negative input terminal is connected to the drains of the transistors MP33 and MN34. The comparator 37 compares the voltage at the positive input terminal with the voltage at the negative input terminal and outputs the comparison result as a signal OUT. The read control circuit 38 is configured to control the operation of the transistors MP31, MN32, MP33, MN34, and MN36 based on the control signal supplied from the control circuit 16, thereby controlling the operation of the read circuit 30.

[0039] With this configuration, the read circuit 30 reads out the data stored in the memory circuit 10 .

[0040] The control circuit 16 (FIG. 1) is configured to control the operation of the semiconductor memory device 1 based on signals supplied from the outside. Specifically, when the control circuit 16 receives a write instruction from the outside, it generates signals SB1 and SB2 based on write data included in the write instruction and supplies these signals SB1 and SB2 to the write circuit 20, and controls the operation of the switches 11 to 13 so that the switches 11 to 13 connect terminals T1 to T3 of the memory circuit 10 to the write circuit 20. When the control circuit 16 receives a read instruction from the outside, it controls the operation of the switches 11 to 13 so that the switch 11 connects terminal T1 of the memory circuit 10 to the read circuit 30, the switch 12 connects terminal T2 of the memory circuit 10 to the drain of transistor MN14, and the switch 13 connects terminal T3 of the memory circuit 10 to the drain of transistor MN15. The control circuit 16 then controls the operation of the transistors MN14 and MN15, as well as the operation of the read circuit 30.

[0041] Here, via V1 corresponds to a specific example of a "first via" in an embodiment of the present disclosure. Terminal T1 corresponds to a specific example of a "first connection terminal" in an embodiment of the present disclosure. Node NN corresponds to a specific example of a "connection node" in an embodiment of the present disclosure. Via V2 corresponds to a specific example of a "second via" in an embodiment of the present disclosure. Terminal T2 corresponds to a specific example of a "second connection terminal" in an embodiment of the present disclosure. Via V3 corresponds to a specific example of a "third via" in an embodiment of the present disclosure. Terminal T3 corresponds to a specific example of a "third connection terminal" in an embodiment of the present disclosure. Write circuit 20 corresponds to a specific example of a "write circuit" in an embodiment of the present disclosure. Read circuit 30 corresponds to a specific example of a "read circuit" in an embodiment of the present disclosure. Ground voltage VGND corresponds to a specific example of a "first voltage" in an embodiment of the present disclosure. Power supply voltage VDD corresponds to a specific example of a "second voltage" in an embodiment of the present disclosure. The via layer VL2 corresponds to a specific example of a "first via layer" in an embodiment of the present disclosure. The via layer VL1 corresponds to a specific example of a "second via layer" in an embodiment of the present disclosure. The metal wiring layer ML2 corresponds to a specific example of a "wiring layer" in an embodiment of the present disclosure.

[0042] [Operation and Function] Next, the operation and function of the semiconductor memory device 1 of this embodiment will be described.

[0043] (Overall Operation Overview) First, an overview of the overall operation of the semiconductor memory device 1 will be described with reference to FIG. 1 . The memory circuit 10 stores two bits of data. When the semiconductor memory device 1 writes data to the memory circuit 10, the switches 11 to 13 connect terminals T1 to T3 of the memory circuit 10 to the write circuit 20 based on a control signal CTL. The write circuit 20 writes data to the memory circuit 10 based on signals SB1 and SB2 supplied from the control circuit 16. When the semiconductor memory device 1 reads data from the memory circuit 10, the switches 11 to 13 connect terminal T1 of the memory circuit 10 to the read circuit 30, connect terminal T2 of the memory circuit 10 to the drain of transistor MN14, and connect terminal T3 of the memory circuit 10 to the drain of transistor MN15 based on the control signal CTL. The read circuit 30 reads the data stored in the memory circuit 10 based on the control signal supplied from the control circuit 16. The control circuit 16 controls the operation of the semiconductor memory device 1 based on a signal supplied from the outside.

[0044] (Detailed Operation) Next, the write operation in the semiconductor memory device 1 will be described in detail.

[0045] 8 shows an example of a write operation in the semiconductor memory device 1. In this Fig. 8, "VDD" indicates that the power supply voltage VDD is applied to the terminal, "VGND" indicates that the ground voltage VGND is applied to the terminal, and "-" indicates that the terminal is in a floating state.

[0046] For example, when signal SB1 is "1" and signal SB2 is "0", the write circuit 20 applies the power supply voltage VDD to terminal T1, applies the ground voltage VGND to terminal T2, and sets terminal T3 in a floating state, as shown in FIG. 8.

[0047] 9A shows an example of the operation of the write circuit 20 when the signal SB1 is "1" and the signal SB2 is "0." In the write operation, the control circuit 16 controls the operations of the switches 11 to 13 so that the switches 11 to 13 connect the terminals T1 to T3 of the memory circuit 10 to the write circuit 20.

[0048] When signal SB1 is "1" and signal SB2 is "0," NAND circuit 43 outputs a high-level voltage, turning transistor MN49 on. The power supply voltage VDD output from NAND circuit 44 is applied to terminal T1 of memory circuit 10 via transistor MN49 and switch 11. NAND circuit 52 outputs a high-level voltage, turning transistor MN59 on. The ground voltage VGND output from NAND circuit 54 is applied to terminal T2 of memory circuit 10 via transistor MN59 and switch 12. AND circuit 62 outputs a low-level voltage, turning transistor MN69 off, and terminal T3 floating. In this way, write circuit 20 applies power supply voltage VDD to terminal T1, applies ground voltage VGND to terminal T2, and leaves terminal T3 floating.

[0049] As a result, the write current Iw flows through the wiring 131, via V1, wiring 121, via V2, and wiring 111 in this order, destroying the via V2 and causing the via V2 to enter a high resistance state. At this time, the resistance value in the path connecting the terminals T1 and T2 is high, and the resistance value in the path connecting the terminals T1 and T3 is low. In this way, the bit B1 becomes "1" and the bit B2 becomes "0."

[0050] For example, when signal SB1 is "0" and signal SB2 is "1", the write circuit 20 applies the power supply voltage VDD to terminal T1, puts terminal T2 in a floating state, and applies the ground voltage VGND to terminal T3, as shown in FIG. 8.

[0051] FIG. 9B shows an example of the operation of the write circuit 20 when the signal SB1 is "0" and the signal SB2 is "1".

[0052] When signal SB1 is "0" and signal SB2 is "1," NAND circuit 43 outputs a high-level voltage, turning transistor MN49 on. The power supply voltage VDD output from NAND circuit 44 is applied to terminal T1 of memory circuit 10 via transistor MN49 and switch 11. NAND circuit 52 outputs a low-level voltage, turning transistor MN59 off, and terminal T2 floating. AND circuit 62 outputs a high-level voltage, turning transistor MN69 on, and ground voltage VGND is applied to terminal T3 of memory circuit 10 via transistor MN69 and switch 13. In this way, write circuit 20 applies power supply voltage VDD to terminal T1, floats terminal T2, and applies ground voltage VGND to terminal T3.

[0053] As a result, the write current Iw flows through the wiring 131, via V1, wiring 121, via V3, and wiring 112 in this order, destroying the via V3 and causing the via V3 to enter a high resistance state. At this time, the resistance value in the path connecting the terminals T1 and T2 is small, and the resistance value in the path connecting the terminals T1 and T3 is large. In this way, the bit B1 becomes "0" and the bit B2 becomes "1."

[0054] For example, when signal SB1 is "1" and signal SB2 is "1", the write circuit 20 applies the ground voltage VGND to terminal T1, applies the power supply voltage VDD to terminal T2, and sets terminal T3 in a floating state, as shown in FIG. 8.

[0055] FIG. 9C shows an example of the operation of the write circuit 20 when the signal SB1 is "1" and the signal SB2 is "1".

[0056] When signals SB1 and SB2 are both "1," NAND circuit 43 outputs a high-level voltage, turning transistor MN49 on. The ground voltage VGND output from NAND circuit 44 is applied to terminal T1 of memory circuit 10 via transistor MN49 and switch 11. NAND circuit 52 outputs a high-level voltage, turning transistor MN59 on. The power supply voltage VDD output from NAND circuit 54 is applied to terminal T2 of memory circuit 10 via transistor MN59 and switch 12. AND circuit 62 outputs a low-level voltage, turning transistor MN69 off, and terminal T3 floating. In this way, write circuit 20 applies ground voltage VGND to terminal T1, power supply voltage VDD to terminal T2, and floating terminal T3.

[0057] As a result, the write current Iw flows through the wiring 111, via V2, wiring 121, via V3, and wiring 131 in this order, destroying the via V1 and causing the via V1 to change to a high resistance state. At this time, the resistance value of the path connecting the terminals T1 and T2 and the resistance value of the path connecting the terminals T1 and T3 are both large. In this way, both bits B1 and B2 become "1".

[0058] For example, when the signal SB1 is "0" and the signal SB2 is "0", the write circuit 20 sets the terminal T1 to a floating state, applies the power supply voltage VDD to the terminal T2, and sets the terminal T3 to a floating state, as shown in Fig. 8. In this case, the write current Iw does not flow, and the resistance states of the vias V1 to V3 are maintained.

[0059] In this way, when setting both bits B1 and B2 to "1," the write circuit 20 sets the resistance state of via V1 to a high resistance state, as shown in FIGS. 4C and 9C. That is, the write circuit 20 does not set both vias V2 and V3 to a high resistance state by sequentially performing the operations shown in FIGS. 4A and 9A and the operations shown in FIGS. 4B and 9B, for example, but sets the resistance state of via V1 to a high resistance state, as shown in FIGS. 4C and 9C. This allows the semiconductor memory device 1 to set both bits B1 and B2 to "1" in a single write operation. As a result, the semiconductor memory device 1 can reduce power consumption while shortening the write time during the write operation.

[0060] Next, the read operation in the semiconductor memory device 1 will be described in detail.

[0061] 10A shows an example of a read operation of bit B1 in semiconductor memory device 1. FIG. 10B shows an example of a read operation of bit B2 in semiconductor memory device 1. In the read operation, control circuit 16 controls the operations of switches 11 to 13 so that switch 11 connects terminal T1 of memory circuit 10 to read circuit 30, switch 12 connects terminal T2 of memory circuit 10 to the drain of transistor MN14, and switch 13 connects terminal T3 of memory circuit 10 to the drain of transistor MN15. Furthermore, in read circuit 30, read control circuit 38 turns on transistors MN32, MN34, and MN36 based on instructions from control circuit 16, and sets the gate voltages of transistors MP31 and MP33 to predetermined voltages that allow transistors MP31 and MP33 to operate as current sources. The current value of the current (read current Ir) passed by the transistor MP31 and the current value of the current (reference current Iref) passed by the transistor MP33 are equal to each other.

[0062] 10A , when reading data for bit B1, the control circuit 16 turns on transistor MN14 and turns off transistor MN15. In the semiconductor memory device 1, a reference current Iref flows through transistor MP33, transistor MN34, resistor element 35, and transistor MN36 in this order, while a read current Ir flows through transistor MP31, transistor MN32, switch 11, wiring 131, via V1, wiring 121, via V2, wiring 111, switch 12, and transistor MN14 in this order. A voltage corresponding to the resistance value of resistor element 35 is generated at the negative input terminal of comparator 37, and a voltage corresponding to the resistance value of the path connecting terminals T1 and T2 is generated at the positive input terminal of comparator 37. For example, when bit B1 is “1,” the resistance state of either via V1 or via V2 is high, and therefore the voltage at the positive input terminal of comparator 37 is higher than the voltage at the negative input terminal of comparator 37. Therefore, the signal OUT output from the comparator 37 is at a high level ("1"). For example, when the bit B1 is "0", the resistance state of both the via V1 and the via V2 is a low resistance state, and therefore the voltage at the positive input terminal of the comparator 37 is lower than the voltage at the negative input terminal of the comparator 37. Therefore, the signal OUT output from the comparator 37 is at a low level ("0").

[0063] Similarly, when reading data for bit B2, as shown in FIG. 10B , the control circuit 16 turns on transistor MN15 and turns off transistor MN14. In the semiconductor memory device 1, a reference current Iref flows through transistor MP33, transistor MN34, resistor element 35, and transistor MN36 in this order, while a read current Ir flows through transistor MP31, transistor MN32, switch 11, wiring 131, via V1, wiring 121, via V3, wiring 112, switch 13, and transistor MN15 in this order. A voltage corresponding to the resistance value of resistor element 35 is generated at the negative input terminal of comparator 37, and a voltage corresponding to the resistance value of the path connecting terminals T1 and T3 is generated at the positive input terminal of comparator 37. For example, when bit B2 is “1,” the resistance state of either via V1 or via V3 is high, and therefore the voltage at the positive input terminal of comparator 37 is higher than the voltage at the negative input terminal of comparator 37. Therefore, the signal OUT output from the comparator 37 is at a high level ("1"). For example, when the bit B2 is "0", the resistance state of both the via V1 and the via V3 is a low resistance state, and therefore the voltage at the positive input terminal of the comparator 37 is lower than the voltage at the negative input terminal of the comparator 37. Therefore, the signal OUT output from the comparator 37 is at a low level ("0").

[0064] In this way, the read circuit 30 can read out two bits of data stored in the memory circuit 10 .

[0065] In this way, the semiconductor memory device 1 is provided with a first via (via V1) that is provided in the path connecting the first connection terminal (terminal T1) and the connection node (node ​​NN) and can be irreversibly set to a high resistance state by passing a current through it, a second via (via V2) that is provided in the path connecting the connection node (node ​​NN) and the second connection terminal (terminal T2) and can be irreversibly set to a high resistance state by passing a current through it, a third via (via V3) that is provided in the path connecting the connection node (node ​​NN) and the third connection terminal (terminal T3) and can be irreversibly set to a high resistance state by passing a current through it, and a write circuit 20 that is connected to the first connection terminal (terminal T1), the second connection terminal (terminal T2), and the third connection terminal (terminal T3) and can pass a write current Iw in both directions between the first connection terminal and the second connection terminal, and can pass a write current Iw in both directions between the first connection terminal and the third connection terminal. As a result, in the semiconductor memory device 1, the resistance state of any of the vias V1 to V3 can be selectively set to a high resistance state. For example, when the resistance state of the via V1 is set to a high resistance state, both the bit B1 and the bit B2 can be set to "1." This makes it possible to reduce power consumption while shortening the write time, compared to, for example, sequentially performing an operation to set the resistance state of the via V2 to a high resistance state and an operation to set the resistance state of the via V3 to a high resistance state.

[0066] Furthermore, in the semiconductor memory device 1, the first via (via V1) can be set to a high resistance state when the write current Iw flows in one of a first direction from the first connection terminal (terminal T1) to the second connection terminal (terminal T2) and a second direction from the second connection terminal (terminal T2) to the first connection terminal (terminal T1), and the second via (via V2) can be set to a high resistance state when the write current Iw flows in the other of the first and second directions. As a result, for example, as shown in FIGS. 4A and 9A , when the write current Iw flows from terminal T1 to terminal T2, the resistance state of the via V2 can be set to a high resistance state, and bit B1 can be set to "1." Furthermore, when the write current Iw flows from terminal T2 to terminal T1, the resistance state of the via V1 can be set to a high resistance state, and both bits B1 and B2 can be set to "1." By setting the resistance state of the via V1 to a high resistance state in this way, it is possible to reduce the power consumption while shortening the write time.

[0067] In the semiconductor memory device 1, the write circuit 20 applies a first voltage (e.g., ground voltage VGND) to the first connection terminal (terminal T1) and a second voltage (e.g., power supply voltage VDD) to the second connection terminal (terminal T2), thereby placing the first via (via V1) in a high resistance state. The write circuit 20 also applies a second voltage (e.g., power supply voltage VDD) to the first connection terminal (terminal T1) and a first voltage (e.g., ground voltage VGND) to the second connection terminal (terminal T2), thereby placing the second via (via V2) in a high resistance state. The write circuit 20 also applies a second voltage (e.g., power supply voltage VDD) to the first connection terminal (terminal T1) and a first voltage (e.g., ground voltage VGND) to the third connection terminal (terminal T3), thereby placing the third via (via V3) in a high resistance state. As a result, for example, when the resistance state of via V1 is set to a high resistance state, both bit B1 and bit B2 can be set to "1", thereby shortening the write time and reducing power consumption.

[0068] [Effect] As described above, in the present embodiment, there are provided a first via that is provided in a path connecting the first connection terminal and the connection node and that can be irreversibly set to a high resistance state by passing a current through it, a second via that is provided in a path connecting the connection node and the second connection terminal and that can be irreversibly set to a high resistance state by passing a current through it, a third via that is provided in a path connecting the connection node and the third connection terminal and that can be irreversibly set to a high resistance state by passing a current through it, and a write circuit that is connected to the first connection terminal, the second connection terminal, and the third connection terminal and that can pass a write current in both directions between the first connection terminal and the second connection terminal and can pass a write current in both directions between the first connection terminal and the third connection terminal. This makes it possible to reduce power consumption while shortening the write time.

[0069] In this embodiment, the first via can be in a high resistance state when a write current flows in one of a first direction from the first connection terminal to the second connection terminal and a second direction from the second connection terminal to the first connection terminal, and the second via can be in a high resistance state when a write current flows in the other of the first direction and the second direction, thereby making it possible to reduce power consumption while shortening the write time.

[0070] In this embodiment, the write circuit is capable of putting the first via into a high resistance state by applying a first voltage to the first connection terminal and a second voltage to the second connection terminal. The write circuit is also capable of putting the second via into a high resistance state by applying a second voltage to the first connection terminal and a first voltage to the second connection terminal. The write circuit is also capable of putting the third via into a high resistance state by applying a second voltage to the first connection terminal and a first voltage to the third connection terminal. This allows for a shorter write time and reduced power consumption.

[0071] [Variation 1] In the above embodiment, as shown in Figure 4C, when the ground voltage VGND is applied to the wiring 131, the power supply voltage VDD is applied to the wiring 111, and the wiring 112 is in a floating state, only the via V1 is destroyed, but this is not limited to this. Instead, for example, as shown in Figure 11A, both the via V1 and the via V2 may be destroyed, as shown in Figure 11B, all the vias V1 to V3 may be destroyed, or as shown in Figure 11C, only the vias V2 and V3 may be destroyed. In any of these three cases, the resistance value in the path connecting the terminals T1 and T2 and the resistance value in the path connecting the terminals T1 and T3 are both large, so both the bit B1 and the bit B2 can be set to "1."

[0072] 4A and 4C , in the above embodiment, for example, when the power supply voltage VDD is applied to the wiring 131, the ground voltage VGND is applied to the wiring 111, and the wiring 112 is in a floating state, the via V2 is destroyed, and when the ground voltage VGND is applied to the wiring 131, the power supply voltage VDD is applied to the wiring 111, and the wiring 112 is in a floating state, the via V1 is destroyed, but this is not limited to this. Below, this modification will be described in detail using a specific example.

[0073] 12A to 12C show an example of a data write operation in the memory circuit 10B according to this modification.

[0074] 12A , when the ground voltage VGND is applied to the wiring 131, the power supply voltage VDD is applied to the wiring 111, and the wiring 112 is in a floating state, the write current Iw flows in the order of the wiring 111, the via V2, the wiring 121, the via V1, and the wiring 131. In this case, in this example, the via V2 is destroyed, and the resistance state of the via V2 becomes a high resistance state.

[0075] 12B , when the ground voltage VGND is applied to the wiring 131, the wiring 111 is in a floating state, and the power supply voltage VDD is applied to the wiring 112, the write current Iw flows in the order of the wiring 112, the via V3, the wiring 121, the via V1, and the wiring 131. In this case, in this example, the via V3 is destroyed, and the resistance state of the via V3 becomes a high resistance state.

[0076] 12C , when the power supply voltage VDD is applied to the wiring 131, the ground voltage VGND is applied to the wiring 111, and the wiring 112 is in a floating state, the write current Iw flows in the order of the wiring 131, the via V1, the wiring 121, the via V2, and the wiring 111. In this case, in this example, the via V1 is destroyed, and the resistance state of the via V1 becomes a high resistance state.

[0077] 12A and 12B, when a write current Iw flows from the wiring 111 or 112 in the metal wiring layer ML1 toward the wiring 131 in the metal wiring layer ML3, the via V1 in the via layer VL2 is not destroyed, but the via V2 or the via V3 in the via layer VL1 is destroyed. Also, when a write current Iw flows from the wiring 131 in the metal wiring layer ML3 toward the wiring 111 or 112 in the metal wiring layer ML1, as shown in FIG. 4C, the vias V2 and V3 in the via layer VL1 are not destroyed, but the via V1 in the via layer VL2 is destroyed.

[0078] FIG. 13 shows an example configuration of a write circuit 20B according to this modification. Also shown in FIG. 13 are a memory circuit 10B, switches 11 to 13, and transistors MN14 and MN15. The write circuit 20B includes logical product circuits 74 and 84. The logical product circuit 74 is configured to calculate the logical product of signals SB1 and SB2. The gate of transistor MN49 is supplied with the output signal of NAND circuit 43, the source is supplied with the output signal of logical product circuit 74, and the drain is connected to switch 11. The logical product circuit 84 is configured to calculate the logical product of signal SB1 and the output signal of inverter 53. The gate of transistor MN59 is supplied with the output signal of NAND circuit 52, the source is supplied with the output signal of logical product circuit 84, and the drain is connected to switch 12. The gate of transistor MN69 is supplied with the output signal of logical product circuit 62, the source is supplied with power supply voltage VDD, and the drain is connected to switch 13.

[0079] FIG. 14 shows an example of a write operation according to this modification.

[0080] For example, when signal SB1 is "1" and signal SB2 is "0", write circuit 20B applies ground voltage VGND to terminal T1, applies power supply voltage VDD to terminal T2, and sets terminal T3 in a floating state, as shown in FIG. 14.

[0081] FIG. 15A shows an example of the operation of the write circuit 20B when the signal SB1 is "1" and the signal SB2 is "0".

[0082] When signal SB1 is "1" and signal SB2 is "0," NAND circuit 43 outputs a high-level voltage, turning transistor MN49 on. The ground voltage VGND output from AND circuit 74 is applied to terminal T1 of memory circuit 10B via transistor MN49 and switch 11. NAND circuit 52 outputs a high-level voltage, turning transistor MN59 on. The power supply voltage VDD output from AND circuit 84 is applied to terminal T2 of memory circuit 10B via transistor MN59 and switch 12. AND circuit 62 outputs a low-level voltage, turning transistor MN69 off, and terminal T3 floating. In this way, write circuit 20B applies ground voltage VGND to terminal T1, power supply voltage VDD to terminal T2, and floating terminal T3.

[0083] As a result, the write current Iw flows through the wiring 111, via V2, wiring 121, via V1, and wiring 131 in this order, destroying the via V2 and causing the via V2 to enter a high resistance state. At this time, the resistance value in the path connecting the terminals T1 and T2 is high, and the resistance value in the path connecting the terminals T1 and T3 is low. In this way, the bit B1 becomes "1" and the bit B2 becomes "0."

[0084] For example, when signal SB1 is "0" and signal SB2 is "1", write circuit 20B applies ground voltage VGND to terminal T1, sets terminal T2 to a floating state, and applies power supply voltage VDD to terminal T3, as shown in FIG. 14.

[0085] FIG. 15B shows an example of the operation of the write circuit 20B when the signal SB1 is "0" and the signal SB2 is "1".

[0086] When signal SB1 is "0" and signal SB2 is "1," NAND circuit 43 outputs a high-level voltage, turning transistor MN49 on. The ground voltage VGND output from AND circuit 74 is applied to terminal T1 of memory circuit 10B via transistor MN49 and switch 11. NAND circuit 52 outputs a low-level voltage, turning transistor MN59 off, and terminal T2 floating. AND circuit 62 outputs a high-level voltage, turning transistor MN69 on, and power supply voltage VDD is applied to terminal T3 of memory circuit 10B via transistor MN69 and switch 13. In this way, write circuit 20B applies ground voltage VGND to terminal T1, floats terminal T2, and applies power supply voltage VDD to terminal T3.

[0087] As a result, the write current Iw flows through the wiring 112, via V3, wiring 121, via V1, and wiring 131 in this order, destroying the via V3 and causing the via V3 to enter a high resistance state. At this time, the resistance value in the path connecting the terminals T1 and T2 is small, and the resistance value in the path connecting the terminals T1 and T3 is large. In this way, the bit B1 becomes "0" and the bit B2 becomes "1."

[0088] For example, when signal SB1 is "1" and signal SB2 is "1", write circuit 20B applies power supply voltage VDD to terminal T1, applies ground voltage VGND to terminal T2, and sets terminal T3 in a floating state, as shown in FIG. 14.

[0089] FIG. 15C shows an example of the operation of the write circuit 20B when the signal SB1 is "1" and the signal SB2 is "1".

[0090] When signals SB1 and SB2 are both "1," NAND circuit 43 outputs a high-level voltage, turning on transistor MN49. The power supply voltage VDD output from AND circuit 74 is applied to terminal T1 of memory circuit 10B via transistor MN49 and switch 11. NAND circuit 52 outputs a high-level voltage, turning on transistor MN59. The ground voltage VGND output from AND circuit 84 is applied to terminal T2 of memory circuit 10B via transistor MN59 and switch 12. AND circuit 62 outputs a low-level voltage, turning off transistor MN69, and floating terminal T3. In this way, write circuit 20B applies power supply voltage VDD to terminal T1, applies ground voltage VGND to terminal T2, and floating terminal T3.

[0091] As a result, the write current Iw flows through the wiring 131, via V1, wiring 121, via V1, and wiring 111 in this order, destroying the via V1 and causing the via V1 to change to a high resistance state. At this time, the resistance value of the path connecting the terminals T1 and T2 and the resistance value of the path connecting the terminals T1 and T3 are both large. In this way, both bits B1 and B2 become "1".

[0092] For example, when the signal SB1 is "0" and the signal SB2 is "0", the write circuit 20B puts the terminal T1 in a floating state, applies the ground voltage VGND to the terminal T2, and puts the terminal T3 in a floating state, as shown in Fig. 14. In this case, the write current Iw does not flow, and the resistance states of the vias V1 to V3 are maintained.

[0093] [Modification 3] In the above embodiment, two vias V2 and V3 are provided in the via layer VL1. However, this is not limited to this, and instead, for example, three or more vias may be provided. FIGS. 16 and 17 show an example in which four vias are provided in the via layer VL1. The memory circuit 10 according to this modification has vias V11 to V15 and wirings 211 to 214, 221, and 231. The wiring 231 is provided in the metal wiring layer ML3. The via V11 is provided in the via layer VL2. The wiring 221 is provided in the metal wiring layer ML2. The vias V12 to V15 are provided in the via layer VL1. The wirings 211 to 214 are provided in the metal wiring layer ML1. One end of the via V11 is connected to the wiring 231, and the other end is connected to the wiring 221. One end of the via V12 is connected to the wiring 221, and the other end is connected to the wiring 211. One end of the via V13 is connected to the wiring 221, and the other end is connected to the wiring 212. One end of the via V14 is connected to the wiring 221, and the other end is connected to the wiring 213. One end of the via V15 is connected to the wiring 221, and the other end is connected to the wiring 214. The via V2 is disposed near one end of the wiring 121 in the extension direction, and the via V3 is disposed near the other end of the wiring 121 in the extension direction. The via V1 is provided at a position between the positions of the vias V2 and V3. When viewed from above in the stacking direction, as shown in FIG. 17, the via V11 is provided at a position between the positions of the vias V12 and V14, and is also provided at a position between the positions of the vias V13 and V15. In this example, the vias V12 to V15 are provided at positions symmetrical to one another when viewed from the via V2.

[0094] [Other Modifications] Two or more of these modifications may be combined.

[0095] Although the present technology has been described above by giving embodiments and modifications thereof, the present technology is not limited to these embodiments and can be modified in various ways.

[0096] For example, in the above-described embodiments, the memory circuit 10 is provided in the metal wiring layer ML1, the via layer VL1, the metal wiring layer ML2, the via layer VL2, and the metal wiring layer ML3, but this is not limiting. Instead, for example, as shown in Figure 18, the memory circuit 10 may be provided in the metal wiring layer ML2, the via layer VL2, the metal wiring layer ML3, the via layer VL3, and the metal wiring layer ML4. The metal wiring layer ML2 is the second metal wiring layer from the bottom, the metal wiring layer ML3 is the third metal wiring layer from the bottom, and the metal wiring layer ML4 is the fourth metal wiring layer from the bottom.

[0097] Furthermore, for example, in the above-described embodiment, one memory circuit 10 is provided, but the present invention is not limited to this, and instead, for example, a plurality of memory circuits 10 may be provided, which allows more data to be stored.

[0098] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0099] The present technology can be configured as follows: According to the present technology configured as follows, it is possible to reduce the power consumption while shortening the write time.

[0100] (1) A semiconductor memory device comprising: a first via provided in a path connecting a first connection terminal and a connection node, the first via being capable of irreversibly becoming a high resistance state by passing a current through it; a second via provided in a path connecting the connection node and a second connection terminal, the second via being capable of irreversibly becoming a high resistance state by passing a current through it; a third via provided in a path connecting the connection node and a third connection terminal, the third via being capable of irreversibly becoming a high resistance state by passing a current through it; and a write circuit connected to the first connection terminal, the second connection terminal, and the third connection terminal, the write circuit being capable of bidirectionally passing a write current between the first connection terminal and the second connection terminal, and bidirectionally passing a write current between the first connection terminal and the third connection terminal. (2) The semiconductor memory device according to (1), wherein the first via is capable of becoming a high resistance state when the write current flows in one of a first direction from the first connection terminal to the second connection terminal and a second direction from the second connection terminal to the first connection terminal, and the second via is capable of becoming a high resistance state when the write current flows in the other of the first direction and the second direction. (3) The semiconductor memory device according to (1), wherein the write circuit is capable of putting the first via into a high resistance state by applying a first voltage to the first connection terminal and a second voltage to the second connection terminal, is capable of putting the second via into a high resistance state by applying the second voltage to the first connection terminal and the first voltage to the second connection terminal, and is capable of putting the third via into a high resistance state by applying the second voltage to the first connection terminal and the first voltage to the third connection terminal. (4) The semiconductor memory device according to (3), wherein the second voltage is higher than the first voltage. (5) The semiconductor memory device according to (3), wherein the first voltage is higher than the second voltage. (6) The semiconductor memory device according to any one of (1) to (5), wherein the second via and the third via are provided in a first via layer, and the first via is provided in a second via layer.(7) The semiconductor memory device according to (6), wherein the connection node corresponds to a wiring layer, and the first via layer, the wiring layer, and the second via layer are stacked in this order. (8) The semiconductor memory device according to (6) or (7), wherein, in a plane intersecting a stacking direction of the first via layer and the second via layer, the position of the first via is between the position of the second via and the position of the third via. (9) The semiconductor memory device according to any of (1) to (8), further comprising a read circuit capable of reading a first bit value based on a resistance value between the first connection terminal and the second connection terminal, and capable of reading and detecting a second bit value based on a resistance value between the first connection terminal and the third connection terminal.

[0101] This application claims priority based on Japanese Patent Application No. 2023-148560, filed on September 13, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0102] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a first via provided in a path connecting a first connection terminal and a connection node, the first via being capable of irreversibly becoming a high resistance state by passing a current through it; a second via provided in a path connecting the connection node and a second connection terminal, the second via being capable of irreversibly becoming a high resistance state by passing a current through it; a third via provided in a path connecting the connection node and a third connection terminal, the third via being capable of irreversibly becoming a high resistance state by passing a current through it; and a write circuit connected to the first connection terminal, the second connection terminal, and the third connection terminal, the write circuit being capable of passing a write current in both directions between the first connection terminal and the second connection terminal, and the write circuit being capable of passing a write current in both directions between the first connection terminal and the third connection terminal.

2. The semiconductor memory device described in claim 1, wherein the first via is capable of becoming a high resistance state when the write current flows in one of a first direction from the first connecting terminal to the second connecting terminal and a second direction from the second connecting terminal to the first connecting terminal, and the second via is capable of becoming a high resistance state when the write current flows in the other of the first direction and the second direction.

3. The semiconductor memory device according to claim 1, wherein the write circuit is capable of putting the first via into a high resistance state by applying a first voltage to the first connection terminal and a second voltage to the second connection terminal, is capable of putting the second via into a high resistance state by applying the second voltage to the first connection terminal and the first voltage to the second connection terminal, and is capable of putting the third via into a high resistance state by applying the second voltage to the first connection terminal and the first voltage to the third connection terminal.

4. The semiconductor memory device according to claim 3, wherein the second voltage is higher than the first voltage.

5. The semiconductor memory device according to claim 3, wherein the first voltage is higher than the second voltage.

6. The semiconductor memory device according to claim 1, wherein the second via and the third via are provided in a first via layer, and the first via is provided in a second via layer.

7. The semiconductor memory device according to claim 6, wherein the connection node corresponds to a wiring layer, and the first via layer, the wiring layer, and the second via layer are stacked in this order.

8. The semiconductor memory device according to claim 6, wherein, on a plane intersecting a stacking direction of the first via layer and the second via layer, the position of the first via is between the position of the second via and the position of the third via.

9. The semiconductor memory device according to claim 1, further comprising a read circuit capable of reading out a first bit value based on a resistance value between the first connection terminal and the second connection terminal, and capable of reading and detecting a second bit value based on a resistance value between the first connection terminal and the third connection terminal.

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