Semiconductor device and time measuring method

Abstract

This semiconductor device comprises: a plurality of memory cells, each including a magnetic tunnel junction element; and a determining unit that determines an inversion number, which is the number of memory cells among the plurality of memory cells having a bit value that has been inverted from an initial value over time.

Description

Semiconductor device and time measurement method

[0001] The present disclosure relates to a semiconductor device and a time measurement method.

[0002] For example, Patent Document 1 discloses a technology for providing a backup battery in a semiconductor device equipped with an RTC circuit for providing a time measurement function, to supply power to the RTC circuit and keep it operating even when the main power supply is off.

[0003] Japanese Patent Application Laid-Open No. 2004-96073

[0004] In the technology of Patent Document 1, if the backup battery runs out and the power supply is completely cut off, the time measurement function cannot be maintained.

[0005] One aspect of the present disclosure maintains timing functionality regardless of the presence or absence of power.

[0006] A semiconductor device according to one aspect of the present disclosure includes a plurality of memory cells, each including a magnetic tunnel junction element, and a determination unit that determines an inversion number, which is the number of memory cells among the plurality of memory cells whose bit values ​​have inverted from their initial values ​​over time.

[0007] A time measurement method according to one aspect of the present disclosure includes determining an inversion number, which is the number of memory cells whose bit values ​​have inverted from an initial value over time, from among a plurality of memory cells each including a magnetic tunnel junction element.

[0008] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor device according to an embodiment; FIG. 2 is a diagram showing an example of an initial pattern; FIG. 3 is a diagram showing an example of a process (time measurement method) executed in the semiconductor device; FIG. 4 is a diagram showing an example of a schematic configuration of a semiconductor device according to a modified example; FIG. 5 is a diagram showing an example of a process (time measurement method) executed in the semiconductor device; FIG. 6 is a diagram showing an example of a circuit of a timer unit; FIG. 7 is a diagram showing an example of a circuit of a timer unit;

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0010] The present disclosure will be described in the following order: 1. Embodiment 2. Modification 3. Example of timer unit circuit 4. Application example 5. Summary

[0011] 1 is a diagram showing an example of a schematic configuration of a semiconductor device according to an embodiment. The semiconductor device 1 includes a timer unit 2, a storage unit 4, a control unit 5, a determination unit 6, and a system unit 7.

[0012] The timer unit 2 includes a plurality of memory cells 3. N memory cells 3 are exemplified as the plurality of memory cells 3. To distinguish between the memory cells 3, they are referred to as memory cell 3-1, memory cell 3-2, memory cell 3-N, etc. in the drawings. When no particular distinction is made between them, they are simply referred to as memory cells 3.

[0013] Each of the N memory cells 3 includes an MTJ element 30. The MTJ element 30 is a magnetic tunnel junction element. Examples of the MTJ element 30 include a spin transfer torque (STT) type MTJ element and a spin orbit torque (SOT) type MTJ element. The resistance value of the MTJ element 30 changes between a low resistance value and a high resistance value.

[0014] The memory cell 3 has a bit value of "1" or "0" depending on the resistance value of the MTJ element 30. A bit value is written to the memory cell 3 by setting the resistance value of the MTJ element 30 in the memory cell 3 to either a low resistance value or a high resistance value. The bit value written to the memory cell 3 can be read at any timing. Various known methods may be used for writing and reading.

[0015] A memory cell 3 into which a bit value has been written continues to maintain the same bit value for a certain period of time, but after a longer period of time, the bit value may be reversed from its original value (initial value). This phenomenon does not depend on whether the power supply to the semiconductor device 1 is on or off. In other words, the bit value of the memory cell 3 may be reversed from its initial value over time, regardless of whether the power supply is on or off.

[0016] The number of memory cells 3 whose bit values ​​are inverted from the initial value is also referred to as the inversion number K. The time required for K memory cells 3 out of N memory cells 3 to be inverted is referred to as the timer time T. The timer time T depends on the retention characteristics of the MTJ element 30, and the retention characteristics are stochastically represented by an exponential distribution. The average value (which can also be said to be an expected value) of the timer time T is expressed as the average value μ Ｔ The average value μT is expressed by the following formula (1):

[0017] The value τ in the above formula (1) can also be called the relaxation time or the like, and is determined by the index Δ of the thermal stability of the MTJ element 30. Specifically, τ is expressed as the ratio of Δ to the constant τ ０ Using the above, it is expressed as the following equation (2).

[0018] The number N of memory cells 3 can be designed and the number of inversions K can be set so as to obtain a desired average value μT based on the thermal stability index Δ of the memory cells 3. The specific length of the average value μT is not particularly limited, but may be, for example, one year, two years, or the like, or may be shorter or longer than that.

[0019] The storage unit 4 stores information used in the semiconductor device 1. Examples of the information stored in the storage unit 4 include an initial pattern 41, a determination result 42, and a flag 43.

[0020] The control unit 5 controls the timer unit 2. The control of the timer unit 2 by the control unit 5 includes initialization of the timer unit 2. Specifically, the control unit 5 writes an initial value to each of the N memory cells 3, thereby initializing the bit value of each of the N memory cells 3.

[0021] 1, the control unit 5 initializes the timer unit 2 according to an initial pattern 41 stored in the storage unit 4. The initial pattern 41 describes the initial value of each bit value of the N memory cells 3. This will be described with reference to FIG.

[0022] FIG. 2 is a diagram showing an example of an initial pattern. The initial pattern 41 describes, for each of N memory cells 3, the memory cell 3 and the initial bit value in association with each other. Note that memory cell 3-N-5 in the diagram indicates the N-5th (N minus 5)th memory cell 3. The same applies to memory cells 3-N-4 to 3-N-1. FIG. 2 shows three initial patterns, initial pattern 41A, initial pattern 41B, and initial pattern 41C.

[0023] The initial pattern 41A is a pattern that includes only the initial value "1." In the initial pattern 41A, the initial values ​​of all of the N memory cells 3 are "1."

[0024] The initial pattern 41B is a pattern that includes only the initial value "0." In the initial pattern 41B, the initial values ​​of all of the N memory cells 3 are "0."

[0025] The initial pattern 41C is a pattern that includes a mixture of initial values ​​"1" and "0". In the illustrated initial pattern 41C, "1" and "0" are written alternately. However, the initial values ​​"1" and "0" may be written so as to be mixed in various ways.

[0026] 1 , for example, an initial pattern 41 such as the one described above is prepared in advance and stored in the memory unit 4. The control unit 5 initializes the timer unit 2 so that the bit value of each of the N memory cells 3 becomes the corresponding initial value in the initial pattern 41. Initializing the bit value of each memory cell 3 according to a known pattern enables comparison by the determination unit 6, which will be described later.

[0027] The determination unit 6 determines the number of memory cells 3 whose bit values ​​have been inverted from their initial values ​​over time, that is, the number of inversions K, out of the N memory cells 3 .

[0028] The determination unit 6 reads out the bit value of each of the N memory cells 3. The determination unit 6 counts the number of inversions K based on the result of comparing the read bit value of each of the N memory cells 3 with the corresponding initial value in the initial pattern 41.

[0029] For example, if the initial values ​​of the N memory cells 3 are all "1", the determination unit 6 counts the number of memory cells 3 having a bit value of "0" among the N memory cells 3 as the number of inversions K. Conversely, if the initial values ​​of the N memory cells 3 are all "0", the determination unit 6 counts the number of memory cells 3 having a bit value of "1" among the N memory cells 3 as the number of inversions K.

[0030] The function of the determination unit 6 may be realized by hardware such as a circuit, or by software. In the example shown in FIG. 1 , the determination unit 6 includes a count circuit 60 that counts the number of inversions K. Any circuit configuration capable of counting the number of inversions K may be employed. As an example, the count circuit 60 includes an EXOR circuit or the like that outputs the exclusive OR of the bit value of the read memory cell 3 and the corresponding initial value in the initial pattern 41. The sum of the exclusive ORs of the bit values ​​of the N memory cells 3 is counted as the number of inversions K.

[0031] The determination of the number of inversions K by the determination unit 6 may be a threshold determination. The threshold set for the number of inversions K is referred to as a threshold Kth. The threshold Kth may be set to the same value as the number of inversions K determined by substituting a desired value for the average value μT in the above-mentioned formula (1).

[0032] The determination unit 6 determines whether the number of inversions K is greater than a threshold value Kth (whether K>Kth). The number of inversions K being greater than the threshold value Kth indicates that the timer time T has elapsed since the initialization of the timer unit 2.

[0033] The result of the determination by the determination unit 6 is stored in the storage unit 4 as a determination result 42. The determination result 42 includes information such as the bit value of each of the N memory cells 3 that have been read, the number of inversions K that have been counted, and whether or not the number of inversions K is greater than a threshold value Kth.

[0034] The flag 43 may be updated depending on the determination result 42. The flag 43 indicates whether the inversion number K is greater than the threshold value Kth, i.e., whether the timer time T has elapsed since the initialization of the timer unit 2. The flag 43 is disabled by default (flag 43="Invalid"), indicating that the inversion number K is equal to or less than the inversion number K. When the determination unit 6 determines that the inversion number K is greater than the threshold value Kth, the determination unit 6 enables the flag 43 (flag 43="Valid").

[0035] The system unit 7 controls the control unit 5 and the determination unit 6, thereby controlling the entire semiconductor device 1. For example, the system unit 7 sends an initialization command to the control unit 5. The control unit 5 initializes the timer unit 2 in response to the initialization command from the system unit 7. The system unit 7 also sends a determination command to the determination unit 6. The determination unit 6 determines the number of inversions K in response to the determination command from the system unit 7.

[0036] Furthermore, the system unit 7 acquires the determination result of the determination unit 6. This acquisition may be performed by the determination unit 6 sending the determination result to the system unit 7, or by the system unit 7 referring to the determination result 42 stored in the storage unit 4 or the flag 43.

[0037] The specific configuration of the system unit 7 is not particularly limited as long as it is designed to perform the above-described operations. The design may be hardware design, software design, or a combination of hardware design and software design.

[0038] According to the semiconductor device 1 described above, the determination unit 6 determines the inversion number K, which is the number of memory cells 3 among the N memory cells 3 whose bit values ​​have been inverted from their initial values ​​over time. More specifically, the determination unit 6 determines whether the inversion number K is greater than a threshold value Kth. The fact that the inversion number K is greater than the threshold value Kth means that the timer time T has elapsed since the initialization of the timer unit 2. In other words, a time measurement function is provided.

[0039] In the memory cell 3 including the MTJ element 30, the bit value may be inverted from the initial value over time, even if the power supply to the semiconductor device 1 is completely cut off. Therefore, the semiconductor device 1 can maintain the time measurement function regardless of the presence or absence of power.

[0040] 3 is a diagram showing an example of processing (time measurement method) executed in a semiconductor device. Description of content that overlaps with the above will be omitted as appropriate. The processing of this flowchart is executed when checking whether or not a timer time T has elapsed since the initialization of the timer unit 2 of the semiconductor device 1. The timing of execution of the processing is not particularly limited, and the processing may be executed, for example, when the power supply of the semiconductor device 1 is turned on.

[0041] In step S1, it is determined whether the flag 43 is enabled (flag 43="Valid") or not. This process is executed by, for example, the system unit 7. If the flag 43 is enabled (step S1: Yes), the process of the flowchart ends. As described above, the enabled flag 43 indicates that the timer time T has elapsed since the initialization of the timer unit 2, and therefore the time measurement function is provided. If the flag 43 is not enabled (step S1: No), the process proceeds to step S2.

[0042] In step S2, a judgment command is issued from the system unit 7 to the judgment unit 6.

[0043] In step S3, the bit values ​​are read out. The decision unit 6 reads out the bit values ​​of each of the N memory cells 3.

[0044] In step S4, the number of inversions K is counted. The determination unit 6 counts the number of inversions K based on the result of comparing the bit values ​​of the N memory cells 3 read in the previous step S3 with the corresponding initial values ​​in the initial pattern 41.

[0045] In step S5, it is determined whether the number of inversions K is greater than a threshold value Kth. The determination unit 6 determines whether the number of inversions K counted in the previous step S4 is greater than the threshold value Kth. If the number of inversions K is greater than the threshold value Kth (step S5: Yes), the process proceeds to step S7. If not (step S5: No), the process proceeds to step S6.

[0046] In step S6, the determination result 42 is stored. The determination unit 6 stores the determination result in the storage unit 4 as the determination result 42. As described above, the determination result 42 includes information such as the bit value of each of the N memory cells 3 that have been read, the counted number of inversions K, and whether or not the number of inversions K is greater than the threshold value Kth.

[0047] In step S7, not only is the determination result 42 stored, but also the flag 43 is validated (flag 43="Valid"). This process is executed by the determination unit 6.

[0048] After the process of step S6 or step S7 is completed, the process of the flowchart ends.

[0049] The process of the above flowchart is called at any timing, and the processes of steps S1 to S7 are repeated the number of times the process is called. The determination unit 6 repeatedly reads the bit values ​​of each of the N memory cells 3, counts the number of inversions K, and determines whether the number of inversions K is greater than a threshold value Kth. When the number of inversions K exceeds the threshold value Kth and the flag 43 is activated, it indicates that the timer time T has elapsed since the initialization of the timer unit 2.

[0050] 2. Modification It is possible that an error (inconsistency) occurs such that the number of inversions K increases over time. Such an error can occur, for example, when the bit value of a memory cell 3, whose bit value has inverted from its initial value over time, is inverted again (returns to its initial value) for some reason. The error can reduce the accuracy of time measurement. To address this problem, the bit value of the memory cell 3 may be corrected. This will be described with reference to FIGS. 4 and 5.

[0051] 4 is a diagram showing an example of a schematic configuration of a semiconductor device according to a modified example. The determination result 42 stored in the storage unit 4 includes a determination result 42a and a determination result 42b.

[0052] The determination result 42 a is a determination result (current determination result) obtained by reading the current (latest) bit value by the determination unit 6. For example, the determination result 42 a includes information such as the bit value of each of the N memory cells 3 read this time, the number of inversions K (current number of inversions K), etc.

[0053] The determination result 42b is a determination result (previous determination result) obtained by reading past bit values, more specifically, by reading the previous bit values, by the determination unit 6. For example, the determination result 42b includes information such as the bit values ​​of each of the N memory cells 3 previously read, the number of inversions K (the previous number of inversions K), etc.

[0054] The control unit 5 corrects the bit values ​​of at least some of the N memory cells 3. This correction is also simply called correction of the timer unit 2.

[0055] The control unit 5 corrects the timer unit 2 so that the current reversal number K does not fall below the previous reversal number K. This makes it possible to eliminate (correct) an error in which the reversal number K increases over time.

[0056] For example, the determination unit 6 determines whether the current reversal number K is equal to or greater than the previous reversal number K. If this is not the case, that is, if the current reversal number K is lower than the previous reversal number K, the determination unit 6 sends a correction command to the control unit 5. The control unit 5 corrects the timer unit 2 in response to the correction command from the determination unit 6. The correction command may also be sent to the control unit 5 from the system unit 7.

[0057] The control unit 5 may correct the timer unit 2 by writing a value opposite to the initial value to the memory cell 3 to be corrected. For example, the control unit 5 writes a bit value of "0" to a memory cell 3 whose initial value is "1", or writes a bit value of "1" to a memory cell 3 whose initial value is "0".

[0058] The control unit 5 may correct the timer unit 2 so that the bit values ​​of the N memory cells 3 become the same as the bit values ​​of the memory cells 3 that were previously read. The determination result 42b stored in the storage unit 4 may be referenced. The control unit 5 corrects the timer unit 2 so that the bit values ​​of the N memory cells 3 become the corresponding bit values ​​in the determination result 42b.

[0059] The determination result 42 a may be updated to reflect the correction result of the timer unit 2. Specifically, the determination result 42 a is updated to include information such as the bit value of each of the N memory cells 3 after correction, the number of inversions K, etc. The determination result 42 a may be updated by the control unit 5 or by the determination unit 6.

[0060] As described above, the control unit 5 corrects the timer unit 2, thereby eliminating errors such as an increase in the number of inversions K over time. This makes it possible to suppress a decrease in the accuracy of time measurement that may occur due to errors.

[0061] 5 is a diagram showing an example of processing (time measurement method) executed in a semiconductor device. The processing of steps S1 to S4 is as previously described with reference to FIG. 3. After the processing of step S4 is completed, the processing proceeds to step S11.

[0062] In step S11, it is determined whether the current reversal number K is equal to or greater than the previous reversal number K. The determination unit 6 determines whether the reversal number K counted in the previous step S4 (the current reversal number K) is equal to or greater than the reversal number K (the previous reversal number K) indicated in the determination result 42b stored in the storage unit 4. If the current reversal number K is equal to or greater than the previous reversal number K (step S11: Yes), the process proceeds to step S5. If not, that is, if the current reversal number K is lower than the previous reversal number K (step S11: No), the process proceeds to step S12.

[0063] The processes in steps S5 to S7 are as described above with reference to FIG.

[0064] In step S12, the timer unit 2 is corrected. The determination unit 6 sends a correction command to the control unit 5. The control unit 5 corrects the timer unit 2.

[0065] After step S6, step S7 or step S12 is completed, the process returns to step S2.

[0066] By correcting the timer unit 2 as described above, it is possible to suppress a decrease in the accuracy of time measurement that may occur due to an error such as an increase in the number of inversions K over time.

[0067] 6 to 8 are diagrams showing examples of the timer circuit. The specific circuit operation can be understood by those skilled in the art after learning the circuit configurations shown in the drawings, so detailed explanations will be omitted.

[0068] 6, the timer unit 2 includes an NV-SRAM (nonvolatile SRAM) circuit 8. The illustrated NV-SRAM circuit 8 is provided across two memory cells 3. The two memory cells 3 are exemplified as memory cell 3-1 and memory cell 3-2. The MTJ element 30 of memory cell 3-1 is illustrated as MTJ element 30-1. The MTJ element 30 of memory cell 3-2 is illustrated as MTJ element 30-2.

[0069] The NV-SRAM circuit 8 includes a latch circuit. In this example, the latch circuit is a flip-flop circuit, and its components are shown with reference numerals: a transistor 81, an inverter 82, an inverter 83, and a transistor 84.

[0070] The transistor is assumed to be a field effect transistor (FET). The drain and source of a transistor are also called current terminals. When an element is connected to the current terminal of a transistor, it is simply said to be connected to the transistor.

[0071] The gate of transistor 81 and the gate of transistor 84 are connected to word line WL. Inverter 82 is connected between transistor 81 and transistor 84. Inverter 83 is connected in parallel to inverter 82 and in the opposite direction to inverter 82. The connection point between transistor 81 and inverter 82 is referred to as node N1 and is illustrated. The connection point between inverter 82 and transistor 84 is referred to as node N2 and is illustrated.

[0072] The control line CTRL is a voltage-controllable signal line. A transistor 85 and an MTJ element 30-1 are connected in series between a node N1 and the control line CTRL. A transistor 86 and an MTJ element 30-2 are connected in series between a node N2 and the control line CTRL. A store / restore (write / read) signal SR is supplied to the gates of the transistors 85 and 86.

[0073] Bit values ​​can be written and read by controlling the voltage level of the word line WL, the voltage level of the control line CTRL, the store / restore signal SR, etc. When writing a bit value, a write current (store current) flows through the MTJ elements 30-1 and 30-2 so that their resistance values ​​become the desired resistance values ​​(low resistance value or high resistance value). When reading a bit value, a voltage corresponding to the resistance values ​​of the MTJ elements 30-1 and 30-2 is detected. The specific operation and principles are well known, so a description thereof will be omitted.

[0074] 7, the timer unit 2 includes a NVDFF (nonvolatile flip-flop) circuit 9. The illustrated NVDFF circuit 9 is provided across two memory cells 3, memory cell 3-1 and memory cell 3-2.

[0075] The NVDFF circuit 9 includes a latch circuit. In this example, the latch circuit is a flip-flop circuit, and its components are shown with reference numerals: an inverter 91, a transmission gate 92, a master latch 93, a transmission gate 94, a slave latch 95, an inverter 96, and an inverter 97.

[0076] The master latch 93 includes an inverter 101, an inverter 102, and a transmission gate 103. The inverter 102 and the transmission gate 103 are connected in series, and they are connected in parallel to the inverter 101 in the opposite direction to the inverter 101.

[0077] Slave latch 95 includes inverter 111, inverter 112, transmission gate 113, and transistor 114. Inverter 112 and transmission gate 113 are connected in series, and they are connected in parallel to inverter 111 in the opposite direction to inverter 111. Transistor 114 is connected in parallel to transmission gate 113.

[0078] The slave latch 95 has a storage node N11 and a storage node N12. The storage node N11 is located on the input side of the inverter 111. The storage node N12 is located on the output side of the inverter 111. The input side of the inverter 96 is connected to the storage node N11. The input side of the inverter 97 is connected to the storage node N12.

[0079] The transmission gates 92, 94, 103, and 113 are supplied with the clock signal C or an inverted clock signal CB, which is an inverted signal of the clock signal C.

[0080] A transistor 121 and an MTJ element 30-1 are connected in series between the storage node N11 and the control line CTRL. A transistor 122 and an MTJ element 30-2 are connected in series between the storage node N12 and the control line CTRL. A store / restore signal SR is supplied to the gates of the transistors 121 and 122.

[0081] Bit values ​​can be written and read by controlling the voltage level of the control line CTRL, the clock signal C, the inverted clock signal CB, the store / restore signal SR, etc. When writing a bit value, a write current (store current) flows through the MTJ elements 30-1 and 30-2 so that their resistance values ​​become the desired resistance values ​​(low resistance value or high resistance value). When reading a bit value, a voltage corresponding to the resistance values ​​of the MTJ elements 30-1 and 30-2 is detected. The specific operation and principles are well known, so a description thereof will be omitted.

[0082] For example, the above-described NV-SRAM circuit 8 or NVDFF circuit 9 is provided for two memory cells 3. The timer unit 2 may include a plurality of NV-SRAM circuits 8 or a plurality of NVDFF circuits 9, more specifically, N / 2 NV-SRAM circuits 8 or N / 2 NVDFF circuits 9. In one embodiment, the plurality of NV-SRAM circuits 8 or the plurality of NVDFF circuits 9 may form a shift register.

[0083] 8 shows an example of a shift register. In this example, a plurality of NVDFF circuits 9 are cascade-connected to form a shift register. When reading bit values, the bit values ​​of the memory cells 3 corresponding to each NVDFF circuit 9 are read out in sequence.

[0084] 4. Application Examples The semiconductor device 1 described above may be mounted on and used in an electronic device. Any electronic device can be an application target of the semiconductor device 1. By mounting the semiconductor device 1, a time measurement function is provided, and the time measurement function can be maintained regardless of the presence or absence of a power source.

[0085] The semiconductor device 1 may be incorporated into a semiconductor memory device such as an NVSRAM or an MRAM, or may be mounted together with such a semiconductor memory device in an electronic device. In this case, a part of the memory cell array of the semiconductor memory device may be used as the timer unit 2 of the semiconductor device 1.

[0086] 5. Summary The techniques described above can be specified, for example, as follows. One of the techniques disclosed is a semiconductor device 1. As described with reference to FIGS. 1 to 5 , the semiconductor device 1 includes a plurality of memory cells 3 (N memory cells 3), each including an MTJ element 30 (magnetic tunnel junction element), and a determination unit 6 that determines an inversion number K, which is the number of memory cells 3 among the plurality of memory cells 3, whose bit values ​​have been inverted from their initial values ​​over time. For example, the determination unit 6 determines whether the inversion number K is greater than a threshold value Kth.

[0087] According to the semiconductor device 1, the inversion number K, which is the number of memory cells 3 whose bit values ​​have been inverted from their initial values ​​over time, is determined. The determination of the inversion number K is, for example, a determination of whether or not the inversion number K is greater than a threshold value Kth, which means that the timer time T has elapsed since the initialization of the timer unit 2. In other words, a time measurement function is provided. In the memory cells 3 including the MTJ elements 30, the bit values ​​may be inverted from their initial values ​​over time, even if, for example, the power supply to the semiconductor device 1 is completely cut off. Therefore, the time measurement function can be maintained regardless of the presence or absence of power.

[0088] 1 and 2 , the semiconductor device 1 may include a storage unit 4 that stores an initial pattern 41 that describes the initial value of each bit value of a plurality of memory cells 3, and the determination unit 6 may count the number of inversions K based on a comparison result between the read bit value of each of the plurality of memory cells 3 and the corresponding initial value in the initial pattern 41. The initial pattern 41 may be an initial pattern 41A that includes only an initial value "1", an initial pattern 41B that includes only an initial value "0", or an initial pattern 41B that includes a mixture of initial values ​​"1" and "0". For example, the number of inversions K can be counted in this manner.

[0089] As described with reference to FIG. 1 etc., the determination unit 6 may include a count circuit 60 that counts the number of inversions K. For example, the function of the determination unit 6 realized by such hardware design can count the number of inversions K. Note that, as mentioned above, the function of the determination unit 6 may be designed by software.

[0090] 1 and other figures, the semiconductor device 1 may include a control unit 5 that initializes the bit values ​​of each of the plurality of memory cells 3 according to an initial pattern 41. By initializing the bit values ​​of the plurality of memory cells 3 according to a known pattern, it becomes possible to count the number of inversions K based on the comparison result in the determination unit 6 described above.

[0091] As described with reference to FIGS. 4 and 5 , the control unit 5 may correct the bit values ​​of at least some of the memory cells 3. For example, the determination unit 6 may repeatedly read the bit values ​​of each of the memory cells 3 and count the number of inversions K, and the control unit 5 may correct the bit values ​​of at least some of the memory cells 3 so that the current number of inversions K is not lower than the previous number of inversions K. The control unit 5 may write a value opposite to the initial value to at least some of the memory cells 3. The control unit 5 may correct the bit values ​​of at least some of the memory cells 3 so that the bit values ​​of each of the memory cells 3 are the same as the bit values ​​of each of the memory cells 3 previously read. By performing such a correction, it is possible to deal with errors such as an increase in the number of inversions K over time. It is also possible to suppress a decrease in the accuracy of time measurement that may be caused by an error.

[0092] The time measurement method described with reference to Figures 1 to 5 is also one of the disclosed techniques. The time measurement method includes determining an inversion number K, which is the number of memory cells 3 each including an MTJ element 30, whose bit values ​​have inverted from their initial values ​​over time (steps S3 to S7). For example, the determination may involve determining whether the inversion number K is greater than a threshold value Kth (step S5). As described above, this time measurement method also allows the time measurement function to be maintained regardless of the presence or absence of a power supply.

[0093] 1 to 3, etc., the determination may count the number of inversions K based on the comparison result between each bit value of the read memory cells 3 and the corresponding initial value in the initial pattern 41 that describes the initial value of each bit value of the multiple memory cells 3 (step S4). The initial pattern 41 may be an initial pattern 41A that includes only an initial value "1", an initial pattern 41B that includes only an initial value "0", or an initial pattern 41B that includes a mixture of initial values ​​"1" and "0". For example, the number of inversions K can be counted in this manner.

[0094] 1 and 3, the count circuit 60 may count the number of inversions K (step S4). For example, the number of inversions K can be counted in this manner.

[0095] 1 and 3, the time measurement method may include initializing the bit values ​​of each of the plurality of memory cells 3 according to the initial pattern 41. Initializing the bit values ​​of the plurality of memory cells 3 according to a known pattern makes it possible to count the number of inversions K based on the comparison result obtained by the above-described determination.

[0096] As described with reference to FIGS. 4 and 5 , the time measurement method may include correcting the bit values ​​of at least some of the memory cells 3 (step S12). The determining step involves repeatedly reading the bit values ​​of the memory cells 3 and counting the number of inversions K (step S4, step S5: No, step S4 when the process of the flowchart is next called). The correcting step involves correcting the bit values ​​of at least some of the memory cells 3 so that the current number of inversions K is not lower than the previous number of inversions K (step S11: No, step S12). The correcting step involves writing a value opposite to the initial value to at least some of the memory cells 3 (step S12). The correcting step involves correcting the bit values ​​of at least some of the memory cells 3 so that the bit values ​​of the memory cells 3 are the same as the bit values ​​of the memory cells 3 previously read (step S12). By performing such a correction, it is possible to deal with errors, such as an increase in the number of inversions K over time. This can also prevent a decrease in the accuracy of time measurement that may be caused by an error.

[0097] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0098] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0099] The present technology may also be configured as follows. (1) A semiconductor device comprising: a plurality of memory cells each including a magnetic tunnel junction element; and a determination unit that determines a number of inversions, which is the number of memory cells among the plurality of memory cells whose bit values ​​have inverted from their initial values ​​over time. (2) The semiconductor device according to (1), wherein the determination unit determines whether the number of inversions is greater than a threshold. (3) The semiconductor device according to (1) or (2), further comprising: a storage unit that stores an initial pattern describing an initial value of each of the plurality of memory cells, and the determination unit counts the number of inversions based on a comparison result between the read bit value of each of the plurality of memory cells and the corresponding initial value in the initial pattern. (4) The semiconductor device according to (3), wherein the initial pattern is: a pattern including only an initial value of "1", a pattern including only an initial value of "0", or a pattern including a mixture of initial values ​​of "1" and "0". (5) The semiconductor device according to (3) or (4), wherein the determination unit includes a count circuit that counts the number of inversions. (6) The semiconductor device according to any one of (1) to (5), comprising: a storage unit that stores an initial pattern describing an initial value of a bit value of each of the plurality of memory cells; and a control unit that initializes the bit value of each of the plurality of memory cells according to the initial pattern. (7) The semiconductor device according to any one of (1) to (6), comprising: a control unit that corrects the bit values ​​of at least some of the plurality of memory cells. (8) The semiconductor device according to (7), wherein the determination unit repeatedly reads the bit values ​​of each of the plurality of memory cells and counts the number of inversions, and the control unit corrects the bit values ​​of at least some of the plurality of memory cells so that the number of inversions this time is not less than the number of inversions previously. (9) The semiconductor device according to (7) or (8), wherein the control unit writes a value opposite to the initial value to at least some of the plurality of memory cells.(10) The semiconductor device according to any one of (7) to (9), wherein the control unit corrects bit values ​​of at least some of the memory cells so that the bit values ​​of the memory cells become the same as the bit values ​​of the memory cells previously read. (11) A time measurement method including determining a number of inversions, which is the number of memory cells whose bit values ​​have inverted from their initial values ​​over time, among the plurality of memory cells each including a magnetic tunnel junction element. (12) The time measurement method according to (11), wherein the determining includes determining whether the number of inversions is greater than a threshold. (13) The time measurement method according to (11) or (12), wherein the determining includes counting the number of inversions based on a result of comparing the read bit value of each of the plurality of memory cells with a corresponding initial value in an initial pattern describing the initial value of the bit value of each of the plurality of memory cells. (14) The time measurement method according to (13), wherein the initial pattern is a pattern including only an initial value of "1", a pattern including only an initial value of "0", or a pattern including a mixture of initial values ​​of "1" and "0". (15) The time measurement method according to (13) or (14), wherein in the determining, a counting circuit counts the number of inversions. (16) The time measurement method according to any of (11) to (15), comprising: initializing a bit value of each of the plurality of memory cells according to an initial pattern describing an initial value of the bit value of each of the plurality of memory cells. (17) The time measurement method according to any of (11) to (16), comprising: correcting the bit values ​​of at least some of the plurality of memory cells. (18) The time measurement method according to (17), wherein the determining includes repeatedly reading out the bit values ​​of each of the plurality of memory cells and counting the number of inversions, and the correcting includes correcting the bit values ​​of at least some of the plurality of memory cells so that the number of inversions this time is not less than the number of inversions last time.(19) The time measurement method according to (17) or (18), wherein the correcting includes writing a value opposite to an initial value to at least some of the memory cells among the plurality of memory cells. (20) The time measurement method according to any of (17) to (19), wherein the correcting includes correcting bit values ​​of at least some of the memory cells among the plurality of memory cells so that the bit values ​​of each of the plurality of memory cells become the same as the bit values ​​of each of the plurality of memory cells that were previously read.

[0100] REFERENCE SIGNS LIST 1 semiconductor device 2 timer unit 3 memory cell 3-1 memory cell 3-2 memory cell 30 MTJ element 30-1 MTJ element 30-2 MTJ element 4 storage unit 41 initial pattern 41A initial pattern 41B initial pattern 41C initial pattern 42 determination result 42a determination result 42b determination result 43 flag 5 control unit 6 determination unit 60 count circuit 7 system unit 8 NV-SRAM circuit 81 transistor 82 inverter 83 inverter 84 transistor 85 transistor 86 transistor 9 NVDFF circuit 91 inverter 92 transmission gate 93 master latch 94 transmission gate 95 slave latch 96 inverter 97 inverter 101 inverter 102 inverter 103 transmission gate 111 inverter 112 Inverter 113 Transmission gate 114 Transistor 121 Transistor 122 Transistor C Clock signal CB Inverted clock signal CTRL Control line N1 Node N2 Node N11 Storage node N12 Storage node SR Store / restore signal WL Word line

Claims

1. A semiconductor device comprising: a plurality of memory cells each including a magnetic tunnel junction element; and a determination unit that determines an inversion number, which is the number of memory cells among the plurality of memory cells whose bit values ​​have been inverted from an initial value over time.

2. The semiconductor device according to claim 1, wherein the determination section determines whether or not the number of inversions is greater than a threshold value.

3. The semiconductor device according to claim 1, further comprising a memory unit that stores an initial pattern describing an initial value of each bit value of the plurality of memory cells, and the determination unit counts the number of inversions based on a comparison result between the read bit value of each of the plurality of memory cells and the corresponding initial value in the initial pattern.

4. The semiconductor device according to claim 3, wherein the initial pattern is a pattern including only an initial value of "1", a pattern including only an initial value of "0", or a pattern including a mixture of initial values ​​of "1" and "0".

5. The semiconductor device according to claim 3, wherein the determination section includes a count circuit that counts the number of inversions.

6. The semiconductor device according to claim 1, comprising: a memory unit that stores an initial pattern describing an initial value of each bit value of the plurality of memory cells; and a control unit that initializes the bit value of each bit value of the plurality of memory cells in accordance with the initial pattern.

7. The semiconductor device according to claim 1, further comprising a control unit that corrects bit values ​​of at least some of the plurality of memory cells.

8. The semiconductor device according to claim 7, wherein the determination unit repeatedly reads out the bit values ​​of each of the plurality of memory cells and counts the number of inversions, and the control unit corrects the bit values ​​of at least some of the plurality of memory cells so that the current number of inversions is not lower than the previous number of inversions.

9. The semiconductor device according to claim 7, wherein the control unit writes a value opposite to an initial value into at least some of the plurality of memory cells.

10. The semiconductor device according to claim 7, wherein the control unit corrects the bit values ​​of at least some of the memory cells so that the bit values ​​of each of the memory cells become the same as the bit values ​​of each of the memory cells previously read.

11. A time measurement method comprising: determining an inversion number, which is the number of memory cells whose bit values ​​have been inverted from an initial value over time, among a plurality of memory cells each including a magnetic tunnel junction element.

12. The time measurement method according to claim 11, wherein said determining step determines whether or not said number of inversions is greater than a threshold value.

13. The time measurement method according to claim 11, wherein the determining step counts the number of inversions based on a comparison result between the bit value of each of the plurality of memory cells that has been read and a corresponding initial value in an initial pattern that describes an initial value of each of the bit values ​​of the plurality of memory cells.

14. The time measurement method according to claim 13, wherein the initial pattern is a pattern including only an initial value of "1", a pattern including only an initial value of "0", or a pattern including a mixture of initial values ​​of "1" and "0".

15. The time measurement method according to claim 13, wherein in the determining, a counting circuit counts the number of inversions.

16. The method of claim 11, comprising: initializing a bit value of each of the plurality of memory cells according to an initial pattern describing an initial value of the bit value of each of the plurality of memory cells.

17. The time measurement method according to claim 11, comprising: correcting bit values ​​of at least a portion of the plurality of memory cells.

18. The time measurement method according to claim 17, wherein the determining comprises repeatedly reading out the bit values ​​of each of the plurality of memory cells and counting the number of inversions, and the correcting comprises correcting the bit values ​​of at least some of the plurality of memory cells so that the current number of inversions is not less than the previous number of inversions.

19. The time measurement method according to claim 17, wherein said correcting step includes writing a value opposite to an initial value to at least some of said plurality of memory cells.

20. The time measurement method according to claim 17, wherein the correction comprises correcting bit values ​​of at least some of the memory cells so that the bit values ​​of each of the memory cells become the same as the bit values ​​of each of the memory cells last read.

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