Voltage measuring circuit

Abstract

A voltage measuring circuit (23) comprises a first switched capacitor filter (9) connected to a first battery cell (C2) constituting a battery pack (50), a second switched capacitor filter (10) connected to a second battery cell (C3) constituting the battery pack (50), and a first amplifier (19) shared by the first switched capacitor filter (9) and the second switched capacitor filter (10), wherein: the first switched capacitor filter (9) includes a first switch group (3), a first capacitance (5), and a third switch group (4); the second switched capacitor filter (10) includes a second switch group (6), a second capacitance (8), and a fourth switch group (7); and the first switch group (3) and the second switch group (6) are electrically insulated from the third switch group (4) and the fourth switch group (7) by means of the first capacitance (5) and the second capacitance (8), respectively.

Description

Voltage Measurement Circuit

[0001] The present disclosure relates to a voltage measurement circuit, and more particularly to a voltage measurement circuit used to measure the voltage of a battery cell in a battery pack configured by connecting a plurality of battery cells in series.

[0002] Lithium-ion batteries and lithium-ion capacitors are used in a variety of applications as secondary batteries with high energy density. In particular, in electric vehicles and energy storage systems (ESSs), which require large capacity, lithium-ion batteries are used as assembled batteries consisting of multiple battery cells connected in series or parallel.

[0003] Lithium-ion batteries are prone to deterioration due to over-discharge and risk of heat generation and explosion due to over-charge. Therefore, a battery management system is essential for lithium-ion batteries, measuring the output voltage of each battery cell and controlling charging and discharging to prevent over-discharge and over-charge. Furthermore, the battery management system measures the output voltage of each battery cell and estimates its state of charge (SOC), so highly accurate voltage measurement is required.

[0004] For this reason, a technology has been proposed in the past in which a battery management system is equipped with a voltage measurement circuit such as an analog-to-digital converter that makes it possible to measure the output voltage of each battery cell in a battery pack (see, for example, Patent Documents 1 and 2).

[0005] In the technology of Patent Document 1, each battery cell of a series-connected battery pack is connected to a single analog-to-digital converter via a multiplexer that selects the positive and negative electrodes, and the battery cells are switched and measured in sequence by the single analog-to-digital converter. Hereinafter, this method will be referred to as the multiplexer method. However, the multiplexer method of Patent Document 1 has the problem that the cycle for measuring the voltages of all battery cells is long because the voltages of the series-connected battery cells are measured in sequence by the single analog-to-digital converter.

[0006] On the other hand, the technology of Patent Document 2 uses multiple analog-to-digital converters connected in pairs to each battery cell of a series-connected battery pack for measurement. This method will be referred to as the parallel method hereinafter. The parallel method of Patent Document 2 allows the output voltage of each battery cell of a series-connected battery pack to be measured simultaneously, thereby shortening the cycle for measuring the battery cell voltage.

[0007] Furthermore, efforts are being made to miniaturize electric vehicle motors by increasing their gear ratios and increasing their speed. The current flowing through the lithium-ion battery pack connected to the motor fluctuates rapidly due to the motor's high speed rotation. The output voltage of each battery cell is the sum of the voltage generated by the battery's internal impedance and the current flowing through the battery pack, plus the open circuit voltage (OCV) of the battery cell. Therefore, the rapidly fluctuating current also rapidly fluctuates the output voltage of each battery cell.

[0008] From this perspective, the multiplexer method of Patent Document 1 has the problem of large voltage measurement errors due to differences in measurement times for each battery cell. Therefore, for lithium-ion battery packs connected to high-speed motors, the parallel method of Patent Document 2, which can measure the output voltage of each battery cell simultaneously, is desirable.

[0009] International Publication No. 2019 / 044856 International Publication No. 2016 / 051684

[0010] However, the parallel method of Patent Document 2 requires the same number of analog-to-digital converters as the number of battery cells to be measured, which poses the problem of increased current consumption and mounting area for a semiconductor device equipped with these.

[0011] The issue of current consumption will be explained in more detail. In a typical battery management system, one semiconductor device that performs voltage measurement measures the voltage of each individual cell of a 12- to 24-series battery cell connection. Since a lithium-ion battery cell outputs a voltage of approximately 3.7 V, the total voltage of the 24-series battery cell connection is approximately 90 V. In other words, a semiconductor device that manages a 24-series battery pack supplies power using the same number of battery packs as the number of series it manages as its power source, so the power supply voltage is 90 V.

[0012] On the other hand, the current consumption of one delta-sigma analog-to-digital converter, which is often used in battery management systems, is approximately 0.5 to 1.0 mA, so the power consumption of the semiconductor device is approximately 1 W according to the following formula.

[0013] 0.5mA x 24 pieces x 90V = 1080mW

[0014] For a semiconductor device, the heat loss due to power consumption of 1 W is an amount of heat loss that cannot be tolerated by heat dissipation from the printed circuit board on which the semiconductor device is mounted, and requires special thermal countermeasures such as the installation of a heat sink.

[0015] Therefore, an object of the present disclosure is to provide a voltage measurement circuit that operates faster than the conventional multiplexer method and is superior in current consumption and mounting area to the conventional parallel method.

[0016] In order to solve the above problem, a voltage measurement circuit according to one embodiment of the present disclosure is a voltage measurement circuit used to measure the voltage of a battery cell in an assembled battery formed by connecting a plurality of battery cells in series, and includes: a first switched capacitor filter having an input terminal connected to a first battery cell that constitutes the assembled battery; a second switched capacitor filter having an input terminal connected to the first battery cell or a second battery cell that constitutes the assembled battery; and a first amplifier having an input terminal connected to an output terminal of the first switched capacitor filter and an output terminal of the second switched capacitor filter, the first switched capacitor filter including a first switch group having an input terminal connected to the first battery cell and a first capacitor connected to the output terminal of the first switch group, the second switched capacitor filter including a second switch group having an input terminal connected to the first battery cell or the second battery cell and a second capacitor connected to the output terminal of the second switch group, and the first switch group and the second switch group are electrically insulated from the first amplifier via the first capacitor and the second capacitor, respectively.

[0017] The present disclosure provides a voltage measurement circuit that operates faster than the conventional multiplexer method and is superior in current consumption and mounting area to the conventional parallel method.

[0018] FIG. 1 is a circuit block diagram showing a schematic configuration of a main part of a voltage measurement circuit according to an embodiment. FIG. 2A is a circuit diagram showing a detailed configuration of an amplifier-sharing analog-to-digital converter shown in FIG. 1. FIG. 2B is a timing chart of clock signals shown in FIG. 2A. FIG. 3 is a block diagram showing the overall configuration of a voltage measurement circuit according to an embodiment. FIG. 4 is a circuit block diagram showing a schematic configuration of a main part of a voltage measurement circuit according to a first modified example of an embodiment. FIG. 5 is a circuit block diagram showing a schematic configuration of a main part of a voltage measurement circuit according to a second modified example of an embodiment. FIG. 6 is a circuit diagram of an amplifier-sharing analog-to-digital converter constituting a voltage measurement circuit according to a third modified example of an embodiment. FIG. 7A is a circuit diagram of an amplifier-sharing analog-to-digital converter constituting a voltage measurement circuit according to a fourth modified example of an embodiment. FIG. 7B is a timing chart of the clock signals shown in FIG. 7A. FIG. 8A is a circuit diagram of an amplifier-sharing analog-to-digital converter constituting a voltage measurement circuit according to a fifth modified example of an embodiment. FIG. 8B is an example of a timing chart of the clock signals shown in FIG. 8A. FIG. 8C is another example of a timing chart of the clock signals shown in FIG. 8A.

[0019] Embodiments of the present disclosure will be described in detail below with reference to the drawings. Each of the embodiments described below represents a specific example of the present disclosure. Numerical values, circuits, circuit components, circuit component connection configurations, signals, signal timing, and waveforms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact representation. In each figure, circuit components having substantially the same functions and types are denoted by the same reference numerals, and redundant descriptions are omitted or simplified. Furthermore, "A and B are connected" means that A and B are electrically connected, and includes not only cases where A and B are directly connected, but also cases where A and B are indirectly connected with another circuit element interposed between A and B.

[0020] FIG. 1 is a circuit block diagram showing a schematic configuration of the main parts of a voltage measurement circuit 23 according to an embodiment. This diagram illustrates an amplifier-sharing analog-to-digital converter 21a that measures the voltages of battery cells C2 and C3 that constitute a battery pack 50, and an amplifier-sharing analog-to-digital converter 21b that measures the voltages of battery cells C6 and C7 that constitute the battery pack 50. The voltage measurement circuit 23 is a semiconductor device implemented as a single integrated circuit, and may include not only these two amplifier-sharing analog-to-digital converters 21a and 21b, but also enough amplifier-sharing analog-to-digital converters to measure the voltages of all of the battery cells that constitute the battery pack 50. While FIG. 1 only shows the main parts of the voltage measurement circuit 23, the overall and more detailed configuration of the voltage measurement circuit 23 will be described later using FIG. 3.

[0021] The battery pack 50 is an assembled battery configured by connecting a plurality of battery cells C1 to C7 in series, for example, a 24-series assembled battery. The battery cells C1 to C7 are, for example, lithium-ion battery cells.

[0022] The amplifier-sharing analog-to-digital converter 21 a is a second-order delta-sigma modulator that modulates the voltages of the two battery cells C2 and C3 into pulse density, and includes a first switched capacitor filter 9, a second switched capacitor filter 10, a third switched capacitor filter 11, a fourth switched capacitor filter 12, a fifth switched capacitor filter 13, a sixth switched capacitor filter 14, a seventh switched capacitor filter 15, an eighth switched capacitor filter 16, a first amplifier 19, a second amplifier 20, and a quantizer 17.

[0023] Of these components, the first switched capacitor filter 9, the third switched capacitor filter 11, the fifth switched capacitor filter 13, and the seventh switched capacitor filter 15 are circuit components dedicated to converting the voltage of the battery cell C2 into a digital signal, while the second switched capacitor filter 10, the fourth switched capacitor filter 12, the sixth switched capacitor filter 14, and the eighth switched capacitor filter 16 are circuit components dedicated to converting the voltage of the battery cell C3 into a digital signal, and while the first amplifier 19, the second amplifier 20, and the quantizer 17 are circuit components shared in a time-division manner for converting the voltages of the battery cells C2 and C3 into a digital signal.

[0024] The first switched capacitor filter 9 is a circuit that samples the voltage of the first battery cell C2 (i.e., stores charge in a capacitor) and has a first input terminal 1 connected to both ends of the first battery cell C2. The first switched capacitor filter 9 includes: a first switch group 3 whose input terminal is connected to the first battery cell C2 and turns on / off; a third switch group 4 whose output terminal is connected to the input terminal of the first amplifier 19 and turns on / off; and a first capacitor 5 connected between the output terminal of the first switch group 3 and the input terminal of the third switch group 4. Note that the term "input terminal" refers to both terminals on the input side of each circuit, namely, a terminal connected to a high-potential line, which is a signal line that transmits the voltage of the high-potential terminal of the battery cell, and a terminal connected to a low-potential line, which is a signal line that transmits the voltage of the low-potential terminal of the battery cell. Similarly, the term "output terminal" refers to both terminals on the output side of each circuit, namely, a terminal connected to a high-potential line, which is a signal line that transmits the voltage of the low-potential terminal of the battery cell, and a terminal connected to a low-potential line, which is a signal line that transmits the voltage of the low-potential terminal of the battery cell.

[0025] The first switch group 3 includes two switch elements SW1P that turn on (i.e., connect) the high potential line and the low potential line of the first battery cell C2 during a first period, and two switch elements SW1N that cross and turn on (i.e., connect) the high potential line and the low potential line of the first battery cell C2 during a second period. The first period and the second period will be described in detail using FIG. 2B .

[0026] The third switch group 4 includes a first digital-to-analog converter 40a that performs digital-to-analog conversion using the output of the quantizer 17 as an input and outputs the obtained analog voltage to the input terminal of the third switch group 4, two switch elements SW1N that turn on (i.e., connect) the high potential line and low potential line of the first battery cell C2 during the second period, and two switch elements SW1P that connect the high potential line and low potential line of the first battery cell C2 to a reference voltage during the first period. Note that the third switch group 4 is not an essential component included in the first switched capacitor filter 9 when the output of the quantizer 17 is not fed back, etc.

[0027] In the symbols for the switch elements (such as "SW1P"), the "1" or "2" following the symbol "SW" indicates that the switch is for measuring the first battery cell C2 or the second battery cell C3, respectively, and the "P" or "N" following the symbol indicates that the switch is on (i.e., connected) during the first period or the second period, respectively. The switch element is, for example, a MOSFET.

[0028] The second switched capacitor filter 10 is a circuit that samples the voltage of the second battery cell C3 (i.e., accumulates charge in a capacitor), and has a second input terminal 2 connected to both ends of the second battery cell C3. The second switched capacitor filter 10 includes a second switch group 6 whose input terminal is connected to the second battery cell C3 and which turns on and off, a fourth switch group 7 whose output terminal is connected to the input terminal of the first amplifier 19 and which turns on and off, and a second capacitor 8 connected between the output terminal of the second switch group 6 and the input terminal of the fourth switch group 7.

[0029] The second switch group 6 includes two switch elements SW2N that respectively turn on (i.e., connect) the high potential line and the low potential line of the second battery cell C3 during the second period, and two switch elements SW2P that respectively cross and turn on (i.e., connect) the high potential line and the low potential line of the second battery cell C3 during the first period.

[0030] The fourth switch group 7 includes a second digital-to-analog converter 40b that performs digital-to-analog conversion using the output of the quantizer 17 as an input and outputs the obtained analog voltage to the input terminal of the fourth switch group 7, two switch elements SW2N that turn on (i.e., connect) the high potential line and low potential line of the second battery cell C3 during the second period, and two switch elements SW2P that connect the high potential line and low potential line of the second battery cell C3 to a reference voltage during the first period. Note that the fourth switch group 7 is not an essential component included in the second switched capacitor filter 10 when the output of the quantizer 17 is not fed back or the like.

[0031] The first amplifier 19 is an amplifier shared in a time-sharing manner for integrating the charge stored in the first switched capacitor filter 9 (more precisely, the first capacitor 5) and for integrating the charge stored in the second switched capacitor filter 10 (more precisely, the second capacitor 8).

[0032] The third switched capacitor filter 11 is connected between the input terminal and output terminal of the first amplifier 19, and is a switched capacitor used to integrate the charge accumulated in the first switched capacitor filter 9 (strictly speaking, the first capacitor 5), and includes one capacitor inserted in the high potential line of the first battery cell C2 and two switch elements SW1N that are turned on during the second period, and one capacitor inserted in the low potential line of the first battery cell C2 and two switch elements SW1N that are turned on during the second period.

[0033] The fourth switched capacitor filter 12 is connected between the input terminal and the output terminal of the first amplifier 19, and is a switched capacitor used to integrate the charge accumulated in the second switched capacitor filter 10 (strictly speaking, the second capacitor 8), and includes one capacitor inserted in the high potential line of the second battery cell C3 and two switch elements SW2P that are turned on during the first period, and one capacitor inserted in the low potential line of the second battery cell C3 and two switch elements SW2P that are turned on during the first period.

[0034] The fifth switched capacitor filter 13 is a second-stage circuit that samples the voltage of the first battery cell C2 (i.e., stores charge in a capacitor), and includes one capacitor inserted in the high potential line of the first battery cell C2, two switch elements SW1P that connect both ends of the capacitor to a reference voltage during a first period, and two switch elements SW1N that connect the capacitor so that it is inserted into the high potential line during a second period; one capacitor inserted in the low potential line of the first battery cell C2, two switch elements SW1P that connect both ends of the capacitor to the reference voltage during the first period, and two switch elements SW1N that connect the capacitor so that it is inserted into the low potential line during the second period.

[0035] The sixth switched capacitor filter 14 is a second-stage circuit that samples the voltage of the second battery cell C3 (i.e., stores charge in a capacitor), and includes one capacitor inserted in the high potential line of the second battery cell C3, two switch elements SW2N that connect both ends of the capacitor to a reference voltage during the second period, and two switch elements SW2P that connect the capacitor so that it is inserted into the high potential line during the first period; one capacitor inserted in the low potential line of the second battery cell C3, two switch elements SW2N that connect both ends of the capacitor to the reference voltage during the second period, and two switch elements SW2P that connect the capacitor so that it is inserted into the low potential line during the first period.

[0036] The second amplifier 20 is an amplifier shared in a time-sharing manner for integrating the charge stored in the capacitance of the fifth switched capacitor filter 13 and for integrating the charge stored in the capacitance of the sixth switched capacitor filter 14.

[0037] The seventh switched capacitor filter 15 is connected between the input terminal and output terminal of the second amplifier 20, and is a switched capacitor used to integrate the charge stored in the capacitance of the fifth switched capacitor filter 13. The seventh switched capacitor filter 15 includes one capacitor inserted in the high potential line of the first battery cell C2 and two switch elements SW1N that are turned on during the second period, and one capacitor inserted in the low potential line of the first battery cell C2 and two switch elements SW1N that are turned on during the second period.

[0038] The eighth switched capacitor filter 16 is connected between the input terminal and the output terminal of the second amplifier 20, and is a switched capacitor used to integrate the charge stored in the capacitance of the sixth switched capacitor filter 14. The eighth switched capacitor filter 16 includes one capacitor inserted in the high potential line of the second battery cell C3 and two switch elements SW2P that are turned on during the first period, and one capacitor inserted in the low potential line of the second battery cell C3 and two switch elements SW2P that are turned on during the first period.

[0039] The quantizer 17 is a 1-bit analog-to-digital converter connected to the output terminals of the first amplifier 19 and the second amplifier 20, and is shared in a time-division manner to quantize the voltages of the first battery cell C2 and the second battery cell C3. The quantizer 17 compares the voltages of the high-potential line and the low-potential line of the output terminals of the first amplifier 19 and the second amplifier 20, and outputs the comparison result from the output terminal 18. The quantizer 17 includes capacitors connected to the high-potential line and the low-potential line of the output terminals of the first amplifier 19 and the second amplifier 20, respectively, switch elements SW1N and SW2P connected to the capacitors, and a reset switch element SWRST. In this example, the quantizer 17 is connected to the output terminals of both the first amplifier 19 and the second amplifier 20, but is not limited to this connection configuration. The quantizer 17 may be connected to the output terminal of at least the second amplifier 20 out of the first amplifier 19 and the second amplifier 20.

[0040] In the amplifier sharing analog-to-digital converter 21a configured as described above, the first switch group 3 and the second switch group 6 are arranged in a high-voltage region 51, which is a circuit region that operates by receiving a first power supply voltage, as shown in FIG. 1 , and the subsequent circuits from the third switch group 4 onwards and the subsequent circuits from the fourth switch group 7 onwards are arranged in a low-voltage region 52, which is a circuit region that operates by receiving a second power supply voltage that is lower than the first power supply voltage. Here, the first power supply voltage is, for example, a power supply voltage in which the potential of the low-potential terminal of the first battery cell C2 is grounded for the first switch group 3, and a power supply voltage in which the potential of the low-potential terminal of the second battery cell C3 is grounded for the second switch group 6. Furthermore, the second power supply voltage is, for example, a power supply voltage in which the potential of the low-potential terminal of the battery pack 50 is grounded for the subsequent circuits from the third switch group 4 onwards and the subsequent circuits from the fourth switch group 7 onwards.

[0041] With this type of isolation configuration, an amplifier sharing type level shifter is configured using a common amplifier, while level shifting the output voltage of the first battery cell from the voltage level of the battery pack to the GND level of the integrated circuit, and level shifting the output voltage of the second battery cell from the voltage level of the battery pack to the GND level of the integrated circuit.

[0042] The amplifier-sharing analog-to-digital converter 21b shown in FIG. 1 is a second-order delta-sigma modulator that modulates the voltages of the two battery cells C6 and C7 into pulse densities, and has the same configuration as the amplifier-sharing analog-to-digital converter 21a.

[0043] Fig. 2A is a circuit diagram showing a detailed configuration of the amplifier-sharing analog-to-digital converter 21a shown in Fig. 1. Fig. 2B is a timing chart of the clock signals (Φ1, Φ1D, Φ2, Φ2D) shown in Fig. 2A.

[0044] 2A, an input voltage Input A of 5 V is input to a first input terminal 1, where the potential of the low potential terminal VI_NA of the first battery cell C2 in FIG. 1 is 95 V and the potential of the high potential terminal VI_PA is 100 V, while an input voltage Input B of 5 V is input to a second input terminal 2, where the potential of the low potential terminal VI_NB of the second battery cell C3 in FIG. 1 is 90 V and the potential of the high potential terminal VI_PB is 95 V.

[0045] In addition, in FIG. 2A, the reference voltage and its reference potential are represented by the symbols shown on the right side of FIG. 2A ("VREF" and "VREF_N", respectively).

[0046] 2A also shows clock signals (Φ1, Φ1D, Φ2, Φ2D) adjacent to each switch element and supplied to the switch elements. The timing of the clock signals (Φ1, Φ1D, Φ2, Φ2D) is as shown in FIG. 2B, and the switch elements are turned on during their high periods. The period consisting of the high period of clock signal Φ1 and the high period of its delayed signal, clock signal Φ1D, is the "first period," and the period consisting of the high period of clock signal Φ2 and the high period of its delayed signal, clock signal Φ2D, is the "second period."

[0047] 2A, in the amplifier sharing analog-to-digital converter 21a, the first-stage integrator for measuring the voltage of the first battery cell C2 (i.e., Input A) is denoted as the first integrator 30a, and the second-stage integrator is denoted as the second integrator 31a. On the other hand, the first-stage integrator for measuring the voltage of the second battery cell C3 (i.e., Input B) is denoted as the first integrator 30b, and the second-stage integrator is denoted as the second integrator 31b.

[0048] The first amplifier 19 in the first integrator 30a is also shared by the first integrator 30b. Similarly, the second amplifier 20 in the second integrator 31a is also shared by the second integrator 31b.

[0049] 2A also illustrates additional circuit configurations included in the amplifier-sharing analog-to-digital converter 21a that are not shown in FIG. 1. For example, the two DC shift circuits 32 constituting each of the first integrators 30a and 30b are circuits that convert the voltage of a battery cell that only takes positive voltages (here, 0 to 5 V) into a differential signal (e.g., −2.5 to 2.5 V) by subtracting a fixed voltage (e.g., 2.5 V). The two dither circuits 33 constituting each of the second integrators 31a and 31b are circuits for reducing idle tones that are inherently generated in the delta-sigma modulator according to this embodiment. The two feedforward paths 34 constituting each of the quantizers 17a and 17b are circuits composed of switch elements SW1N and SW2P, which were also shown in FIG. 1, and are CIFF (Cascaded Integrator Feedforward) type feedforward paths.

[0050] As can be seen from FIGS. 2A and 2B, the main operation of the amplifier-sharing type analog-to-digital converter 21a shown in FIG. 2A is as follows.

[0051] To measure the voltage of the first battery cell C2 (i.e., Input A), during a first period (when the clock signal Φ1 or Φ1D is Hi), the voltage of the first battery cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9 (strictly speaking, charge is accumulated in the first capacitor 5), and during a second period (when the clock signal Φ2 or Φ2D is Hi), the difference between the voltage sampled by the first switched capacitor filter 9 and the voltage digital-to-analog converted based on the output of the quantizer 17a is integrated by the first integrator 30a.

[0052] Furthermore, in the next first period (when the clock signal Φ1 or Φ1D is Hi), the value integrated by the first integrator 30a is sampled by the fifth switched capacitor filter 13, and in the next second period (when the clock signal Φ2 or Φ2D is Hi), the voltage sampled by the fifth switched capacitor filter 13 is integrated by the second integrator 31a and quantized by the quantizer 17a.

[0053] On the other hand, to measure the voltage of the second battery cell C3 (i.e., Input B), during the second period (when the clock signal Φ2 or Φ2D is Hi), the voltage of the second battery cell C3 (i.e., Input B) is sampled by the second switched capacitor filter 10 (strictly speaking, charge is accumulated in the second capacitor 8), and during the first period (when the clock signal Φ1 or Φ1D is Hi), the difference between the voltage sampled by the second switched capacitor filter 10 and the voltage digital-to-analog converted based on the output of the quantizer 17b is integrated by the first integrator 30b.

[0054] Furthermore, in the next second period (when the clock signal Φ2 or Φ2D is Hi), the value integrated by the first integrator 30b is sampled by the sixth switched capacitor filter 14, and in the next first period (when the clock signal Φ1 or Φ1D is Hi), the voltage sampled by the sixth switched capacitor filter 14 is integrated by the second integrator 31b and quantized by the quantizer 17b.

[0055] The amplifier sharing type analog-to-digital converter 21b shown in FIG. 1 operates in the same manner as the amplifier sharing type analog-to-digital converter 21a shown in FIG. 2A.

[0056] In this way, in each of the amplifier-sharing analog-to-digital converters 21a and 21b, the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared (i.e., used alternately) in a time-division manner to convert the voltages of the battery cells C2 and C3 into digital signals.

[0057] As a result, in the voltage measurement circuit 23 according to this embodiment, voltage measurements are multiplexed for every two battery cells, allowing for faster operation than the conventional multiplexer method in which voltage measurements of all battery cells are multiplexed. Furthermore, in the voltage measurement circuit 23 according to this embodiment, the first switch group 3 and the second switch group 6 are electrically isolated from the third switch group 4 and the fourth switch group 7 and subsequent circuits via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared for each voltage measurement of two battery cells, resulting in superior current consumption and mounting area compared to the conventional parallel method.

[0058] Generally, the current consumption of a level shifter using a delta-sigma type analog-to-digital converter or a switched capacitor filter type integrator is the sum of the charging / discharging current of the switched capacitor and the current consumption of the amplifier, with the amplifier accounting for the majority of the current consumption. Therefore, by using amplifier sharing according to this embodiment, it is possible to halve the current consumption by sharing an amplifier between two circuits.

[0059] Conventional voltage measurement circuits for parallel-type battery packs use analog-to-digital converters in the same number as the number of battery cells in the battery pack. Therefore, by using an amplifier-sharing type analog-to-digital converter or an amplifier-sharing type level shifter as in this embodiment, the current consumption can be reduced by half, making it unnecessary to take special heat dissipation measures for the semiconductor device.

[0060] Furthermore, a switched capacitor consists of three elements: a switch, a capacitance, and an amplifier. In an amplifier-sharing analog-to-digital converter or an amplifier-sharing level shifter, the amplifiers of the two voltage measurement circuits can be realized with a single common amplifier, which makes it possible to reduce the circuit area.

[0061] Furthermore, analog-to-digital converters used in battery pack voltage measurement circuits are generally operated as oversampling analog-to-digital converters. In the case of the amplifier-sharing analog-to-digital converters 21a and 21b disclosed herein, there is a half-cycle offset (i.e., a half-cycle equal to the combined period of the clock signals Φ1 and Φ2) between the measurement timing of the first battery cell and the second battery cell with respect to the input sampling clock. However, the input sampling clock is very fast compared to the output data rate. When a 256x oversampling delta-sigma analog-to-digital converter is used with an output rate of 10 Ksps (samples per second), the input sampling frequency is 2.56 MHz, and this half-cycle offset is negligible in terms of measurement simultaneity.

[0062] In this way, using the amplifier sharing analog-to-digital converters 21a and 21b, which are the amplifier sharing analog-to-digital converters and amplifier sharing level shifters of the present disclosure, in a voltage measurement circuit for a parallel-type assembled battery is effective in terms of power consumption, circuit area, and functional safety.

[0063] 3 is a block diagram showing the overall configuration of the voltage measurement circuit 23 according to the embodiment. This diagram shows the block configuration of the voltage measurement circuit 23, which comprises a delta-sigma analog-digital converter made up of six amplifier-sharing analog-digital converters 21a to 21f and six decimation filters 22a to 22f, required to measure the voltages of all of the battery cells C1 to C12 that make up the battery pack 50 in parallel.

[0064] Each of the six amplifier sharing type analog-to-digital converters 21a to 21f has the same configuration as the amplifier sharing type analog-to-digital converter 21a shown in FIGS. 1 and 2A.

[0065] The six decimation filters 22a to 22f average the 1-bit high-speed streams output from the amplifier-sharing analog-to-digital converters 21a to 21f, respectively, and output two 16-bit signals indicating the voltages of the two battery cells.

[0066] 4 is a circuit block diagram showing a schematic configuration of the main parts of a voltage measurement circuit 23a according to a first modified example of the embodiment, which shows an amplifier sharing type analog-to-digital converter 21g that measures the voltages of battery cells C2 and C3 that make up the battery pack 50, and an amplifier sharing type analog-to-digital converter 21h that measures the voltages of battery cells C6 and C7.

[0067] The amplifier sharing analog-to-digital converters 21g and 21h according to this modification each constitute a first-order delta-sigma modulator, which differs from the amplifier sharing analog-to-digital converters 21a and 21b according to the embodiment of Fig. 1, which constitute a second-order delta-sigma modulator. Also, the amplifier sharing analog-to-digital converters 21g and 21h according to this modification each comprise 1.5-bit (i.e., outputting three values) quantizers 17c and 17d, which differs from the amplifier sharing analog-to-digital converters 21a and 21b according to the embodiment, which comprise 1-bit quantizers.

[0068] The voltage measurement circuit 23a according to this modified example also has the same characteristics as the voltage measurement circuit 23 according to the embodiment, and therefore can operate at a higher speed than the conventional multiplexer system, and is superior in current consumption and mounting area compared to the conventional parallel system. Furthermore, it is possible to configure a delta-sigma analog-to-digital converter having these characteristics.

[0069] 5 is a circuit block diagram showing a schematic configuration of the main components of a voltage measurement circuit 23b according to a second modification of the embodiment. The difference from the voltage measurement circuit 23 according to the embodiment is that the first input terminal 1 and the second input terminal 2 of each of the amplifier-sharing analog-to-digital converters 21a and 21b according to this modification are both connected to both ends of the same battery cell, and voltage is measured using two redundant switched capacitor filter circuits. This improves the fault tolerance of the voltage measurement circuit 23b.

[0070] In other words, while in the embodiment, voltage measurements were performed on two upper and lower battery cells in a battery pack using a single amplifier-sharing analog-to-digital converter, in this modification, voltage measurements are performed using a single amplifier-sharing analog-to-digital converter connected to one battery cell via two input terminals. In some battery pack voltage measurement circuits, a redundant configuration is required in accordance with the functional safety requirements of ISO 26262. In the amplifier-sharing analog-to-digital converter of this modification, the amplifier is shared and not fully redundant. However, the failure rate is higher for the terminals of the semiconductor device, the switches connected to the terminals, and the capacitors connected via the switches. However, because the failure rate of the amplifier, which could be a common cause of failure, is low, a high safety integrity level (SIL) can be achieved even with this configuration.

[0071] 6 is a circuit diagram of an amplifier-sharing analog-to-digital converter 21 i constituting a voltage measurement circuit according to a third modified example of the embodiment, which shows the circuit configuration of the amplifier-sharing analog-to-digital converter 21 i in which one amplifier is shared in a time-division manner by two integrators, one primary and one secondary.

[0072] The amplifier-sharing analog-to-digital converter 21i according to this modification constitutes a second-order delta-sigma modulator and includes a first integrator 30c having input terminals connected to battery cells constituting the battery pack 50, a second integrator 31c having an input terminal connected to the output terminal of the first integrator 30c, a first amplifier 19 shared by the first integrator 30c and the second integrator 31c, a quantizer 17e having an input terminal connected to the output terminal of the second integrator 31c, and a first digital-to-analog converter 40a that performs digital-to-analog conversion using the output of the quantizer 17e as an input and outputs the obtained analog voltage to the input terminal of the first integrator 30c. The first integrator 30c and the second integrator 31c share the first amplifier 19 in a time-division manner to integrate the input signal.

[0073] The amplifier sharing analog-to-digital converter 21 a according to the embodiment is similar in that the first integrator 30 c includes a first switched capacitor filter 9, the first switched capacitor filter 9 includes a first switch group 3 having input terminals connected to battery cells and turned on and off, a third switch group 4 having output terminals connected to input terminals of the amplifier and turned on and off, and a first capacitor 5 connected between the output terminal of the first switch group 3 and the input terminal of the third switch group 4, the first switch group 3 is electrically insulated from the third switch group 4 via the first capacitor 5, and the first switch group 3 is arranged in a high-voltage region 51, which is a circuit region that operates upon receiving a first power supply voltage, and the third switch group 4 and the first amplifier 19 are arranged in a low-voltage region 52, which is a circuit region that operates upon receiving a second power supply voltage that is lower than the first power supply voltage.

[0074] Therefore, in the amplifier sharing type analog-to-digital converter 21 i of this modified example, the first switch group 3 is electrically isolated from the circuitry following the third switch group 4 via the first capacitance 5 (i.e., it constitutes a level shifter), and the first amplifier 19 is shared by the two integrators, so it is superior in current consumption and mounting area to the conventional parallel system.

[0075] Fig. 7A is a circuit diagram of an amplifier-sharing analog-to-digital converter 21j constituting a voltage measurement circuit according to a fourth modified example of the embodiment, and Fig. 7B is a timing chart of the clock signals shown in Fig. 7A.

[0076] The amplifier sharing analog-to-digital converter 21j according to this modified example has many of the same configurations as the amplifier sharing analog-to-digital converter 21a according to the embodiment shown in FIG. 2A, but differs from the embodiment in that it operates by receiving supply of clock signals of four sets of phases (Φ1 and Φ1D, Φ2 and Φ2D, Φ3 and Φ3D, Φ4 and Φ4D) as compared to the embodiment that operates by receiving supply of clock signals of two sets of phases (Φ1 and Φ1D, Φ2 and Φ2D).

[0077] The amplifier-sharing analog-to-digital converter 21j includes a first integrator 30d, a second integrator 31d, and a quantizer 17f for measuring the voltage of the first battery cell C2 (i.e., Input A), and includes a first integrator 30e, a second integrator 31e, and a quantizer 17g for measuring the voltage of the second battery cell C3 (i.e., Input B).

[0078] The first integrator 30d is composed of a first switched capacitor filter 9a, a third switched capacitor filter 11a, and a first amplifier 19. The first switched capacitor filter 9a includes a first switch group 3, a third switch group 4a, and a first capacitor 5. The third switched capacitor filter 11a is a switched capacitor filter having a reset (short-circuit) function.

[0079] The second integrator 31d is composed of a fifth switched capacitor filter 13a, a seventh switched capacitor filter 15a, and a second amplifier 20. The seventh switched capacitor filter 15a is a switched capacitor filter having a reset (short-circuit) function.

[0080] The first integrator 30e is composed of a second switched capacitor filter 10a and a fourth switched capacitor filter 12a. The second switched capacitor filter 10a includes a second switch group 6, a fourth switch group 7a, and a second capacitor 8. The fourth switched capacitor filter 12a is a switched capacitor filter having a reset (short-circuit) function.

[0081] The second integrator 31e is composed of a sixth switched capacitor filter 14a and an eighth switched capacitor filter 16a. The eighth switched capacitor filter 16a is a switched capacitor filter having a reset (short-circuit) function.

[0082] In measuring the voltage of the first battery cell C2 (i.e., Input A), during a first period (when the clock signal Φ1 or Φ1D is Hi), the voltage of the first battery cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9a (strictly speaking, charge is accumulated in the first capacitor 5), and at the same time, the input / output terminals of the first amplifier 19 are short-circuited and reset by the third switched capacitor filter 11a, and during a second period (when the clock signal Φ2 or Φ2D is Hi), the difference between the voltage sampled by the first switched capacitor filter 9a and the voltage digital-to-analog converted based on the output of the quantizer 17f is integrated by the first integrator 30d.

[0083] Furthermore, during the next first period (when the clock signal Φ1 or Φ1D is Hi), the value integrated by the first integrator 30d is sampled by the fifth switched capacitor filter 13a, and at the same time, the input / output terminals of the second amplifier 20 are short-circuited and reset by the seventh switched capacitor filter 15a, and during the next second period (when the clock signal Φ2 or Φ2D is Hi), the voltage sampled by the fifth switched capacitor filter 13a is integrated by the second integrator 31d and quantized by the quantizer 17f.

[0084] On the other hand, in order to measure the voltage of the second battery cell C3 (i.e., Input B), during a third period (when the clock signal Φ3 or Φ3D is Hi), the voltage of the second battery cell C3 (i.e., Input B) is sampled by the second switched capacitor filter 10a (strictly speaking, charge is accumulated in the second capacitor 8), and at the same time, the input / output terminals of the first amplifier 19 are short-circuited and reset by the fourth switched capacitor filter 12a, and during a fourth period (when the clock signal Φ4 or Φ4D is Hi), the difference between the voltage sampled by the second switched capacitor filter 10a and the voltage digital-to-analog converted based on the output of the quantizer 17g is integrated by the first integrator 30e.

[0085] Furthermore, in the next third period (when the clock signal Φ3 or Φ3D is Hi), the value integrated by the first integrator 30e is sampled by the sixth switched capacitor filter 14a, and at the same time, the input / output terminals of the second amplifier 20 are short-circuited and reset by the eighth switched capacitor filter 16a, and further, in the next fourth period (when the clock signal Φ4 or Φ4D is Hi), the voltage sampled by the sixth switched capacitor filter 14a is integrated by the second integrator 31e and quantized by the quantizer 17g.

[0086] In this way, in the amplifier sharing type analog-to-digital converter 21j according to this modification, the first amplifier 19 and the second amplifier 20 alternate between integration and resetting, thereby suppressing the occurrence of offset.

[0087] Furthermore, in the amplifier sharing type analog-to-digital converter 21j according to this modified example, similarly to the amplifier sharing type analog-to-digital converter 21a according to the embodiment, the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared (i.e., used alternately) in a time-division manner to convert the voltages of the battery cells C2 and C3 into digital signals.

[0088] As a result, the voltage measurement circuit including the amplifier-sharing analog-to-digital converter 21j according to this modification multiplexes voltage measurements for every two battery cells, allowing for faster operation than the conventional multiplexer method in which voltage measurements for all battery cells are multiplexed. Furthermore, the voltage measurement circuit including the amplifier-sharing analog-to-digital converter 21j according to this modification is superior in current consumption and mounting area to the conventional parallel method because the first switch group 3 and the second switch group 6 are electrically isolated from the third switch group 4 and the fourth switch group 7 and subsequent circuits via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared for each voltage measurement of two battery cells.

[0089] Fig. 8A is a circuit diagram of an amplifier-sharing analog-to-digital converter 21k constituting a voltage measurement circuit according to a fifth modified example of the embodiment. Fig. 8B is an example of a timing chart of the clock signal shown in Fig. 8A. Fig. 8C is another example of the timing chart of the clock signal shown in Fig. 8A.

[0090] The amplifier-sharing analog-to-digital converter 21k according to this modification includes a first integrator 30f and a quantizer 17h for measuring the voltage of the first battery cell C2 (i.e., Input A), and a first integrator 30g and a quantizer 17i for measuring the voltage of the second battery cell C3 (i.e., Input B).

[0091] The amplifier sharing analog-to-digital converter 21k according to this modification is similar to the amplifier sharing analog-to-digital converter 21j according to the fourth modification shown in FIG. 7A in that it operates by receiving supply of clock signals of four sets of phases. However, it differs from the amplifier sharing analog-to-digital converter 21j according to the fourth modification, which is a second-order delta-sigma modulator, in that it constitutes a first-order delta-sigma modulator.

[0092] The timing of the clock signals shown in FIG. 8B is the same as the timing according to the fourth modified example shown in FIG. 7B.

[0093] 8C is unique to this modification. As shown in the figure, clock signals Φ1 and Φ1D also serve as clock signals Φ3 and Φ3D (i.e., they are the same).

[0094] Therefore, according to the timing of FIG. 8C , unlike the timing of FIG. 8B , the following processes occur simultaneously: (1) during a first period (when the clock signal Φ1 or Φ1D is Hi), the voltage of the first battery cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9a (to be precise, charge is accumulated in the first capacitor 5), and at the same time, the input / output terminals of the first amplifier 19 are short-circuited and reset; and (2) during a third period (when the clock signal Φ3 or Φ3D is Hi), the voltage of the second battery cell C3 (i.e., Input B) is sampled by the second switched capacitor filter 10a (to be precise, charge is accumulated in the second capacitor 8), and at the same time, the input / output terminals of the first amplifier 19 are short-circuited and reset.

[0095] Thus, according to the timing of FIG. 8C, integration and resetting in the first amplifier 19 and the second amplifier 20 are performed by clock signals with substantially three sets of phases, which speeds up analog-to-digital conversion, unlike the timing of FIG. 8B, in which integration and resetting in the first amplifier 19 and the second amplifier 20 are performed by clock signals with four sets of phases.

[0096] Furthermore, in the amplifier-sharing analog-to-digital converter 21k according to this modification, as in the amplifier-sharing analog-to-digital converter 21j according to the fourth modification, the first amplifier 19 and the quantizer 17 are shared (i.e., used alternately) in a time-division manner to convert the voltages of the battery cells C2 and C3 into digital form.

[0097] As a result, the voltage measurement circuit including the amplifier-sharing analog-to-digital converter 21k according to this modification multiplexes voltage measurements for every two battery cells, allowing for faster operation than the conventional multiplexer method in which voltage measurements for all battery cells are multiplexed. Furthermore, the voltage measurement circuit including the amplifier-sharing analog-to-digital converter 21k according to this modification is superior in current consumption and mounting area to the conventional parallel method because the first switch group 3 and the second switch group 6 are electrically isolated from the third switch group 4 and the fourth switch group 7 and subsequent circuits via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19 and quantizer 17 are shared for each voltage measurement of two battery cells.

[0098] As described above, the voltage measurement circuit 23 according to this embodiment is a voltage measurement circuit used to measure the voltage of a battery cell in an assembled battery 50 configured by connecting a plurality of battery cells C1 to C3 in series, and includes a first switched capacitor filter 9 having an input terminal connected to a first battery cell C2 that configures the assembled battery 50, a second switched capacitor filter 10 having an input terminal connected to the first battery cell C2 or a second battery cell C3 that configures the assembled battery 50, and an input terminal connected to the output terminal of the first switched capacitor filter 9 and the output terminal of the second switched capacitor filter 10. The first switched capacitor filter 9 includes a first switch group 3 having an input terminal connected to the first battery cell C2 and a first capacitor 5 connected to the output terminal of the first switch group 3, and the second switched capacitor filter 10 includes a second switch group 6 having an input terminal connected to the first battery cell C2 or the second battery cell C3 and a second capacitor 8 connected to the output terminal of the second switch group 6, and the first switch group 3 and the second switch group 6 are electrically insulated from the first amplifier 19 via the first capacitor 5 and the second capacitor 8, respectively.

[0099] This multiplexes voltage measurements for every two battery cells, enabling faster operation than the conventional multiplexer method in which voltage measurements for all battery cells are multiplexed. Furthermore, in the voltage measurement circuit 23 according to this embodiment, the first switch group 3 and the second switch group 6 are electrically isolated from the first amplifier 19 and subsequent circuits via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19 is shared for each voltage measurement of two battery cells, resulting in superior current consumption and mounting area compared to the conventional parallel method.

[0100] In other words, according to the voltage measurement circuit 23 of this embodiment, in a parallel-type semiconductor device in which measurements are performed using a plurality of analog-digital converters connected in pairs to each of the battery cells of a series-connected battery pack, by configuring an amplifier-sharing analog-digital converter, it is possible to reduce the current consumption and area of ​​the plurality of analog-digital converters and provide a battery pack voltage measurement circuit that can measure the battery cell voltages of the battery pack at approximately the same time.

[0101] Here, the first switched capacitor filter 9 may further include a third group of switches 4 connected between the first capacitor 5 and the input terminal of the first amplifier 19, and the second switched capacitor filter 10 may further include a fourth group of switches 7 connected between the second capacitor 8 and the input terminal of the first amplifier 19.

[0102] Furthermore, the first switch group 3 and the second switch group 6 may be arranged in a high-voltage region 51, which is a circuit region that operates upon receiving a first power supply voltage, and the third switch group 4, the fourth switch group 7 and the first amplifier 19 may be arranged in a low-voltage region 52, which is a circuit region that operates upon receiving a second power supply voltage that is lower than the first power supply voltage. This forms an amplifier-sharing level shifter, making it possible to suppress current consumption and heat loss.

[0103] Furthermore, the voltage measurement circuit 23 may further include a third switched capacitor filter 11 and a fourth switched capacitor filter 12 connected between the input terminal and the output terminal of the first amplifier 19. This enables integration by the first amplifier 19.

[0104] The voltage measurement circuit 23 may further include a quantizer 17 connected after the first amplifier 19, and the voltage measurement circuit 23 and other components may constitute an analog-to-digital converter that converts the voltage of the first battery cell C2 into a digital value, or that converts the voltage of the first battery cell C2 and the voltage of the second battery cell C3 into digital values ​​in a time-division manner. This realizes an analog-to-digital converter that operates at high speed and is superior to conventional analog-to-digital converters in terms of current consumption and mounting area.

[0105] Furthermore, the third switch group 4 may include a first digital-to-analog converter 40a that receives the output of the quantizer 17 as its input, performs digital-to-analog conversion, and outputs the resulting analog voltage to the input terminal of the third switch group 4, the fourth switch group 7 may include a second digital-to-analog converter 40b that receives the output of the quantizer 17 as its input, and outputs the resulting analog voltage to the input terminal of the fourth switch group 7, and the voltage measurement circuit 23 and the like may form a delta-sigma analog-to-digital converter. This achieves a delta-sigma analog-to-digital converter that operates at high speed and is superior to conventional ones in terms of current consumption and mounting area.

[0106] Furthermore, the path between the first amplifier 19 and the quantizer 17 may further include a fifth switched capacitor filter 13 and a sixth switched capacitor filter 14, the input terminals of which are connected to the output terminal of the first amplifier 19, a second amplifier 20, the input terminals of which are connected to the output terminal of the fifth switched capacitor filter 13 and the output terminal of the sixth switched capacitor filter 14, and a seventh switched capacitor filter 15 and an eighth switched capacitor filter 16, which are connected between the input terminal and the output terminal of the second amplifier 20, so that the voltage measurement circuit 23 constitutes a second-order or higher delta-sigma analog-to-digital converter. This realizes a second-order or higher delta-sigma analog-to-digital converter that operates at high speed and is superior to conventional ones in terms of current consumption and mounting area.

[0107] Furthermore, the input terminal of the second switched capacitor filter 10 may be connected to the second battery cell C3. This allows voltage measurement to be performed by two redundant switched capacitor filter circuits, thereby realizing a voltage measurement circuit that satisfies a high level of safety.

[0108] Furthermore, a voltage measurement circuit used to measure the voltages of battery cells in an assembled battery 50 formed by connecting multiple battery cells C1 to C3 in series may include: a first integrator 30c having an input terminal connected to a battery cell that constitutes the assembled battery 50; a second integrator 31c having an input terminal connected to the output terminal of the first integrator 30c; a first amplifier 19 shared by the first integrator 30c and the second integrator 31c; a quantizer 17e having an input terminal connected to the output terminal of at least the second integrator 31c of the first integrator 30c and the second integrator 31c; and a first digital-analog converter 40a that performs digital-to-analog conversion using the output of the quantizer 17e as an input and outputs the obtained analog voltage to the input terminal of the first integrator 30c, wherein the first integrator 30c and the second integrator 31c share the first amplifier 19 in a time-division manner to integrate the input signal, and the voltage measurement circuit may constitute a second-order or higher delta-sigma analog-to-digital converter.

[0109] As a result, the first amplifier 19 is shared by the two integrators, and a voltage measuring circuit superior in current consumption and mounting area to the conventional parallel type is realized.

[0110] Here, the first integrator 30c includes a first switched capacitor filter 9, and the first switched capacitor filter 9 includes a first switch group 3 whose input terminals are connected to the battery cells and which switches on and off, and a first capacitor 5 connected to the output terminal of the first switch group 3, and the first switch group 3 may be electrically isolated from the first amplifier 19 via the first capacitor 5. In this way, the first switch group 3 is electrically isolated from the circuits subsequent to the first amplifier 19 via the first capacitor 5, and a voltage measurement circuit with reduced current consumption is realized.

[0111] The first switched capacitor filter 9 may further include a third switch group 4 connected between the first capacitor 5 and the input terminal of the first amplifier 19 .

[0112] Furthermore, the first switch group 3 may be arranged in a high-voltage region 51, which is a circuit region that operates upon receiving a first power supply voltage, and the third switch group 4 and the first amplifier may be arranged in a low-voltage region 52, which is a circuit region that operates upon receiving a second power supply voltage that is lower than the first power supply voltage. This forms an amplifier-sharing level shifter, making it possible to suppress current consumption and heat loss.

[0113] While the voltage measurement circuit according to the present disclosure has been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications that would occur to a person skilled in the art to the present embodiments and modifications, and other forms constructed by combining some of the components in the embodiments and modifications, are also included within the scope of the present disclosure.

[0114] For example, in the above embodiments, the amplifier sharing analog-digital converter is applied to a delta-sigma analog-digital converter, but application examples of the amplifier sharing analog-digital converter are not limited to this, and the amplifier sharing analog-digital converter may also be applied to a cyclic or successive approximation type analog-digital converter.

[0115] The voltage measurement circuit according to the present disclosure can be used as a voltage measurement circuit used to measure the voltage of a battery cell in a battery pack formed by connecting multiple battery cells in series, and in particular as a voltage measurement circuit that operates faster than conventional multiplexer methods and is superior in current consumption and mounting area to conventional parallel methods.

[0116] REFERENCE SIGNS LIST 1 First input terminal 2 Second input terminal 3 First switch group 4, 4a Third switch group 5 First capacitance 6 Second switch group 7, 7a Fourth switch group 8 Second capacitance 9, 9a First switched capacitor filter 10, 10a Second switched capacitor filter 11, 11a Third switched capacitor filter 12, 12a Fourth switched capacitor filter 13, 13a Fifth switched capacitor filter 14, 14a Sixth switched capacitor filter 15, 15a Seventh switched capacitor filter 16, 16a Eighth switched capacitor filter 17, 17a to 17i Quantizer 18 Output terminal 19 First amplifier 20 Second amplifier 21a to 21k Amplifier sharing type analog-to-digital converter 22a to 22f Decimation filter 23, 23a, 23b Voltage measurement circuit 30a to 30g: First integrator 31a to 31e: Second integrator 32: DC shift circuit 33: Dither circuit 34: Feed-forward path 40a: First digital-to-analog converter 40b: Second digital-to-analog converter 50: Assembled battery 51: High-voltage region 52: Low-voltage region C1 to C12: Battery cells

Claims

1. A voltage measurement circuit used to measure the voltage of a battery cell in an assembled battery formed by connecting a plurality of battery cells in series, comprising: a first switched capacitor filter having an input terminal connected to a first battery cell constituting the assembled battery; a second switched capacitor filter having an input terminal connected to the first battery cell or a second battery cell constituting the assembled battery; and a first amplifier having an input terminal connected to an output terminal of the first switched capacitor filter and an output terminal of the second switched capacitor filter, the first switched capacitor filter including a first switch group having an input terminal connected to the first battery cell and a first capacitance connected to the output terminal of the first switch group, the second switched capacitor filter including a second switch group having an input terminal connected to the first battery cell or the second battery cell and a second capacitance connected to the output terminal of the second switch group, the first switch group and the second switch group being electrically insulated from the first amplifier via the first capacitance and the second capacitance, respectively.

2. The voltage measurement circuit according to claim 1, wherein the first switched capacitor filter further includes a third group of switches connected between the first capacitance and the input terminal of the first amplifier, and the second switched capacitor filter further includes a fourth group of switches connected between the second capacitance and the input terminal of the first amplifier.

3. The voltage measurement circuit according to claim 2, wherein the first group of switches and the second group of switches are arranged in a high voltage area, and the third group of switches, the fourth group of switches and the first amplifier are arranged in a low voltage area which is a circuit area that operates by receiving a power supply voltage lower than that of the high voltage area.

4. The voltage measurement circuit according to claim 2 or 3, further comprising a third switched capacitor filter and a fourth switched capacitor filter connected between the input terminal and the output terminal of the first amplifier.

5. The voltage measurement circuit according to claim 4, further comprising a quantizer connected downstream of the first amplifier, wherein the voltage measurement circuit constitutes an analog-to-digital converter that converts the voltage of the first battery cell into a digital value, or that converts the voltage of the first battery cell and the voltage of the second battery cell into digital values ​​in a time-division manner.

6. The voltage measurement circuit according to claim 5, wherein the third group of switches includes a first digital-to-analog converter that takes the output of the quantizer as an input, performs digital-to-analog conversion, and outputs the obtained analog voltage to an input terminal of the third group of switches; the fourth group of switches includes a second digital-to-analog converter that takes the output of the quantizer as an input, and outputs the obtained analog voltage to an input terminal of the fourth group of switches; and the voltage measurement circuit constitutes a delta-sigma analog-to-digital converter.

7. The voltage measurement circuit according to claim 5, further comprising, in a path between the first amplifier and the quantizer, a fifth switched capacitor filter and a sixth switched capacitor filter, the input terminals of which are connected to the output terminal of the first amplifier, a second amplifier, the input terminals of which are connected to the output terminal of the fifth switched capacitor filter and the output terminal of the sixth switched capacitor filter, and a seventh switched capacitor filter and an eighth switched capacitor filter connected between the input terminal and the output terminal of the second amplifier, and the voltage measurement circuit constitutes a second-order or higher delta-sigma analog-digital converter.

8. The voltage measurement circuit according to any one of claims 1 to 7, wherein an input terminal of the second switched capacitor filter is connected to the second battery cell.

9. A voltage measurement circuit used to measure the voltage of a battery cell in an assembled battery formed by connecting a plurality of battery cells in series, comprising: a first integrator having an input terminal connected to a battery cell constituting the assembled battery; a second integrator having an input terminal connected to an output terminal of the first integrator; a first amplifier shared by the first integrator and the second integrator; a quantizer having an input terminal connected to an output terminal of at least the second integrator of the first integrator and the second integrator; and a first digital-to-analog converter which performs digital-to-analog conversion using an output of the quantizer as an input and outputs the obtained analog voltage to an input terminal of the first integrator, wherein the first integrator and the second integrator share the first amplifier in a time-division manner to integrate an input signal; the first integrator includes a first switched capacitor filter; and the first switched capacitor filter includes a first switch group having an input terminal connected to the battery cell and a first capacitance connected to the output terminal of the first switch group; the first switch group is electrically isolated from the first amplifier via the first capacitance.

10. The voltage measurement circuit of claim 1, wherein said first switched capacitor filter further includes a third group of switches connected between said first capacitance and an input terminal of said first amplifier.

11. The voltage measurement circuit according to claim 10, wherein the first group of switches is arranged in a high voltage area, and the third group of switches and the first amplifier are arranged in a low voltage area, which is a circuit area that operates by receiving a power supply voltage lower than that of the high voltage area.

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