Local tile based content adaptive backlight

Abstract

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a local tile based content adaptive backlight. A processor determines a cutoff value for each of a plurality of tiles of a frame (506) based on a local histogram for each of the plurality of tiles (504). The processor applies a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles (518). The processor adjusts the cutoff value for each of the plurality of tiles based on a backlight value (506) for a global histogram for the frame (508). The processor calculates a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles (520). The processor outputs an indication of the calculated LUT for each of the plurality of tiles.

Description

LOCAL TILE BASED CONTENT ADAPTIVE BACKLIGHTCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of Indian Patent Application Serial No. 202341061287, entitled “LOCAL TILE BASED CONTENT ADAPTIVE BACKLIGHT” and filed on September 12, 2023, which is expressly incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to processing systems, and more particularly, to one or more techniques for display processing.INTRODUCTION

[0003] Computing devices often perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor may be configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a CPU, a GPU, and / or a display processor.

[0004] Current techniques for content adaptive backlight may not address “washed-out images.” There is a need for improved content adaptive backlight techniques.BRIEF SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for display processing are provided. The apparatus includes a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: determine a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles; apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles; adjust the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame; calculate a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles; and output an indication of the calculated LUT for each of the plurality of tiles.

[0007] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for display processing are provided. The apparatus includes a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area; divide each of a plurality of local histograms for the frame into a plurality of slabs; assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs; calculate a global lookup table (LUT) map for the frame based on the first slope and the slope assigned to each of the plurality of slabs; and output an indication of the global LUT map for the frame.

[0008] To the accomplishment of the foregoing and related ends, the one or more aspects include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative,however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.

[0010] FIG. 2 illustrates an example graphics processor (e.g., a graphics processing unit (GPU)) in accordance with one or more techniques of this disclosure.

[0011] FIG. 3 illustrates an example display framework including a display processor and a display in accordance with one or more techniques of this disclosure.

[0012] FIG. 4 is a diagram illustrating an example of an image, tiles, and a local histogram collection in accordance with one or more techniques of this disclosure.

[0013] FIG. 5 is a diagram illustrating a first example of a process for mitigating detail loss in an image using local lookup table (LUT) maps.

[0014] FIG. 6 is a diagram illustrating an example of calculating a cutoff value in accordance with one or more techniques of this disclosure.

[0015] FIG. 7 is a diagram illustrating an example of adjusting gains in accordance with one or more techniques of this disclosure.

[0016] FIG. 8 is a diagram illustrating an example of spatial filtering in accordance with one or more techniques of this disclosure.

[0017] FIG. 9 is a diagram illustrating a second example of a process for mitigating detail loss for an image using a hybrid approach.

[0018] FIG. 10 is a diagram illustrating an example of a global histogram, a local histogram, and a region of interest in the global histogram and the local histogram in accordance with one or more techniques of this disclosure.

[0019] FIG. 11 is a diagram illustrating an example of finding a knee point in accordance with one or more techniques of this disclosure.

[0020] FIG. 12 is a diagram illustrating an example of initial piecewise linear global LUT map construction in accordance with one or more techniques of this disclosure.

[0021] FIG. 13 is a diagram illustrating an example of finding additional slopes for a global LUT map in accordance with one or more techniques of this disclosure.

[0022] FIG. 14 is a diagram illustrating an example piecewise linear global LUT map in accordance with one or more techniques of this disclosure.

[0023] FIG. 15 is a diagram illustrating examples of adjusting a piecewise linear global LUT map in accordance with one or more techniques of this disclosure.

[0024] FIG. 16 is a call flow diagram illustrating example communications between a central processing unit (CPU) and a display processing unit (DPU) in accordance with one or more techniques of this disclosure.

[0025] FIG. 17 is a call flow diagram illustrating example communications between a CPU and a DPU in accordance with one or more techniques of this disclosure.

[0026] FIG. 18 is a flowchart of an example method of display processing in accordance with one or more techniques of this disclosure.

[0027] FIG. 19 is a flowchart of an example method of display processing in accordance with one or more techniques of this disclosure.

[0028] FIG. 20 is a flowchart of an example method of display processing in accordance with one or more techniques of this disclosure.

[0029] FIG. 21 is a flowchart of an example method of display processing in accordance with one or more techniques of this disclosure.DETAILED DESCRIPTION

[0030] Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the variousaspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0031] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

[0032] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0033] By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs,subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0034] The term application may refer to software. As described herein, one or more techniques may refer to an application (e.g., software) being configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or subcomponents of a single component.

[0035] In one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

[0036] As used herein, instances of the term “content” may refer to “graphical content,” an “image,” etc., regardless of whether the terms are used as an adjective, noun, or other parts of speech. In some examples, the term “graphical content,” as used herein, may refer to a content produced by one or more processes of a graphics processingpipeline. In further examples, the term “graphical content,” as used herein, may refer to a content produced by a processing unit configured to perform graphics processing. In still further examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

[0037] Certain types of displays (e.g., liquid crystal displays (LCDs)) may utilize a backlight in order to display content. In some cases, the backlight of a display may be set at a maximum level (or a relatively high level) while the display displays graphical content, and hence the display consumes a maximum level of power (or a relatively high amount of power) when the backlight is set to the maximum level. In other cases, the backlight of the display may be set to a level that is less than the maximum level (or less than the relatively high level) while the display displays graphical content in order to conserve power. For instance, a mobile computing device that includes an LCD may have a limited amount of battery power, and the backlight may be set to the level that is less than the maximum level (or less than the relatively high level) in order to conserve battery power and prolong an amount of time a user can use the mobile computing device. In a specific example, the LCD may be set to the level that is less than the maximum level (or less than the relatively high level) when a battery level of the mobile computing device falls below a threshold percentage (e.g., below 50%, below 25%, below 10%, etc.). However, setting the backlight to the level that is less than the maximum level (or less than the relatively high level) may degrade picture quality. For instance, certain details in an image may not be visible when the backlight is set at the level that is less than the maximum level (or less than the relatively high level).

[0038] Some techniques (e.g., content adaptive backlight (CABL)) compensate for backlight level reduction by “boosting” (i.e., increasing) pixel values according to a reduced backlight level to minimize impact on an overall visual impression of an image. A pixel value may refer to a value that is associated with a displayed color of the pixel. However, pixel value boosting may be limited by an intensity range (i.e., a fixed bitdepth) and may compress a dynamic range (i.e., dynamic range compression) for certain pixels in an image, and hence may sacrifice details and contrast (i.e., washout) in regions of the image that include the certain pixels. Dynamic range compression may refer to a difference between pixel values being decreased. The sacrificed detailsand contrast may be particularly noticeable for darker images, where a lower backlight level may be calculated for greater power savings.

[0039] Various technologies pertaining to local tile based content adaptive backlighting are described herein. In one example, an apparatus (e.g., a CPU) determines a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. The apparatus applies a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. The apparatus adjusts the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. The apparatus calculates a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. The apparatus outputs an indication of the calculated LUT for each of the plurality of tiles. Vis-a-vis calculating a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles, the apparatus may preserve detail s / contrast in the frame and may prevent “washing out” in the frame, particularly when a backlight level is set to less than a maximum level. In comparison to some techniques for backlight compensation (e.g., CABL), the techniques described herein may provide room to reduce backlight levels to relatively low levels, and hence may reduce power consumption of a device with no impact (or minimal impact) on image quality.

[0040] In another example, an apparatus (e.g., a CPU) calculates a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. The apparatus divides each of a plurality of local histograms for the frame into a plurality of slabs. The apparatus assigns a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. The apparatus calculates a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. The apparatus outputs an indication of the global LUT map for the frame. Vis-a-vis calculating a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs, the apparatus may preserve detail s / contrast in the frame and may prevent “washing out” in the frame, particularly when a backlight level is set to less than a maximum level. In comparison to some techniques for backlight compensation (e.g., CABL), the techniques described herein may provide room to reduce backlight levels torelatively low levels, and hence may reduce power consumption of a device with no impact (or minimal impact) on image quality. Furthermore, the above-described technologies may be reverse compatible, that is, the apparatus may receive a target backlight value and the apparatus may regenerate the global LUT map based on the target backlight value.

[0041] The examples describe herein may refer to a use and functionality of a graphics processing unit (GPU). As used herein, a GPU can be any type of graphics processor, and a graphics processor can be any type of processor that is designed or configured to process graphics content. For example, a graphics processor or GPU can be a specialized electronic circuit that is designed for processing graphics content. As an additional example, a graphics processor or GPU can be a general purpose processor that is configured to process graphics content.

[0042] FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include a number of components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). Display(s) 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays, which may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first display and the second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this may be referred to as split-rendering.

[0043] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing using a graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a processor, which may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before the frames are displayed by the one or more displays 131. While the processor in the example content generation system 100 is configured as a display processor 127, it should be understood that the display processor 127 is one example of the processor and that other types of processors, controllers, etc., may be used as substitute for the display processor 127. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0044] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to external memory, such as the system memory 124. The processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the internal memory 121 over the bus or via a different connection.

[0045] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive encoded or decoded graphical content, e.g., from the system memory 124 and / or thecommunication interface 126, in the form of encoded pixel data. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0046] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, a magnetic data media or an optical storage media, or any other type of memory. The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non- transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0047] The processing unit 120 may be a CPU, a GPU, a GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In further examples, the processing unit 120 may be present on a graphics card that is installed in a port of the motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0048] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may beintegrated into a motherboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 123, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0049] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, and / or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and / or transmitting function described herein with respect to the device 104.

[0050] Referring again to FIG. 1, in certain aspects, the processing unit 120 may include a LUT generator 198 configured to determine a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles; apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles; adjust the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame; calculate a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles; and output an indication of the calculatedLUT for each of the plurality of tiles. In certain aspects, the LUT generator 198 is configured to calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area; divide each of a plurality of local histograms for the frame into a plurality of slabs; assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs; calculate a global lookup table (LUT) map for the frame based on the first slope and the slope assigned to each of the plurality of slabs; and output an indication of the global LUT map for the frame. Although the following description may be focused on display processing, the concepts described herein may be applicable to other similar processing techniques. Furthermore, although the following description may be focused on liquid crystal displays (LCDs), the concepts described herein may be applicable to other types of displays that use a backlight.

[0051] A device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device such as a portable video game device or a personal digital assistant (PDA), a wearable computing device such as a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU) but in other embodiments, may be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.

[0052] GPUs can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shadingprogram, or constant data, which can regulate how a graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit or bits that indicate which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and / or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a GPU.

[0053] Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and / or in what mode the processing unit functions. In order to do so, GPUs can use context registers and programming data. In some aspects, a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

[0054] FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, GPU 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, L2 cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that GPU 200 includes processing units 220-238, GPU 200 can include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units can be used by GPUs according to the present disclosure. GPU 200 also includes command buffer 250, context register packets 260, and context states 261.

[0055] As shown in FIG. 2, a GPU can utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and / or draw call data packets, e.g., draw call packets 212. The CP 210 can then send the context register packets 260 or draw call packets 212 through separate paths to the processing units or blocks in the GPU. Further, the command buffer 250 canalternate different states of context registers and draw calls. For example, a command buffer can simultaneously store the following information: context register of context N, draw call(s) of context N, context register of context N+l, and draw call(s) of context N+l.

[0056] GPUs can render images in a variety of different ways. In some instances, GPUs can render an image using direct rendering and / or tiled rendering. In tiled rendering GPUs, an image can be divided or separated into different sections or tiles. After the division of the image, each section or tile can be rendered separately. Tiled rendering GPUs can divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects of tiled rendering, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream can be constructed where visible primitives or draw calls can be identified. A rendering pass may be performed after the binning pass. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time (i.e., without a binning pass). Additionally, some types of GPUs can allow for both tiled rendering and direct rendering (e.g., flex rendering).

[0057] In some aspects, GPUs can apply the drawing or rendering process to different bins or tiles. For instance, a GPU can render to one bin, and perform all the draws for the primitives or pixels in the bin. During the process of rendering to a bin, the render targets can be located in GPU internal memory (GMEM). In some instances, after rendering to one bin, the content of the render targets can be moved to a system memory and the GMEM can be freed for rendering the next bin. Additionally, a GPU can render to another bin, and perform the draws for the primitives or pixels in that bin. Therefore, in some aspects, there might be a small number of bins, e.g., four bins, that cover all of the draws in one surface. Further, GPUs can cycle through all of the draws in one bin, but perform the draws for the draw calls that are visible, i.e., draw calls that include visible geometry. In some aspects, a visibility stream can be generated, e.g., in a binning pass, to determine the visibility information of each primitive in an image or scene. For instance, this visibility stream can identify whether a certain primitive is visible or not. In some aspects, this information can be used to remove primitives that are not visible so that the non-visible primitives are notrendered, e.g., in the rendering pass. Also, at least some of the primitives that are identified as visible can be rendered in the rendering pass.

[0058] In some aspects of tiled rendering, there can be multiple processing phases or passes. For instance, the rendering can be performed in two passes, e.g., a binning, a visibility or bin-visibility pass and a rendering or bin-rendering pass. During a visibility pass, a GPU can input a rendering workload, record the positions of the primitives or triangles, and then determine which primitives or triangles fall into which bin or area. In some aspects of a visibility pass, GPUs can also identify or mark the visibility of each primitive or triangle in a visibility stream. During a rendering pass, a GPU can input the visibility stream and process one bin or area at a time. In some aspects, the visibility stream can be analyzed to determine which primitives, or vertices of primitives, are visible or not visible. As such, the primitives, or vertices of primitives, that are visible may be processed. By doing so, GPUs can reduce the unnecessary workload of processing or rendering primitives or triangles that are not visible.

[0059] In some aspects, during a visibility pass, certain types of primitive geometry, e.g., position-only geometry, may be processed. Additionally, depending on the position or location of the primitives or triangles, the primitives may be sorted into different bins or areas. In some instances, sorting primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, GPUs may determine or write visibility information of each primitive in each bin or area, e.g., in a system memory. This visibility information can be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin can be rendered separately. In these instances, the visibility stream can be fetched from memory and used to remove primitives which are not visible for that bin.

[0060] Some aspects of GPUs or GPU architectures can provide a number of different options for rendering, e.g., software rendering and hardware rendering. In software rendering, a driver or CPU can replicate an entire frame geometry by processing each view one time. Additionally, some different states may be changed depending on the view. As such, in software rendering, the software can replicate the entire workload by changing some states that may be utilized to render for each viewpoint in an image. In certain aspects, as GPUs may be submitting the same workload multiple times for each viewpoint in an image, there may be an increased amount of overhead. In hardware rendering, the hardware or GPU may be responsible for replicating orprocessing the geometry for each viewpoint in an image. Accordingly, the hardware can manage the replication or processing of the primitives or triangles for each viewpoint in an image.

[0061] FIG. 3 is a block diagram 300 that illustrates an example display framework including the processing unit 120, the system memory 124, the display processor 127, and the display(s) 131, as may be identified in connection with the device 104.

[0062] A GPU may be included in devices that provide content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphical data for display on a computing device (e.g., the device 104), which may be a computer workstation, a mobile phone, a smartphone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, and the like. Operations of the GPU 310 may be controlled based on one or more graphics processing commands provided by a CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the concurrently executed multiple applications may utilize the GPU 310 simultaneously. Processing techniques may be performed via the processing unit 120 output a frame over physical or wireless communication channels.

[0063] The system memory 124, which may be executed by the processing unit 120, may include a user space 320 and a kernel space 325. The user space 320 (sometimes referred to as an “application space”) may include software application(s) and / or application framework(s). For example, software application(s) may include operating systems, media applications, graphical applications, workspace applications, etc. Application framework(s) may include frameworks used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. The kernel space 325 may further include a display driver 330. The display driver 330 may be configured to control the display processor 127. For example, the display driver 330 may cause the display processor 127 to compose a frame and transmit the data for the frame to a display.

[0064] The display processor 127 includes a display control block 335 and a display interface 340. The display processor 127 may be configured to manipulate functions of the display(s) 131 (e.g., based on an input received from the display driver 330). The display control block 335 may be further configured to output image frames to thedisplay(s) 131 via the display interface 340. In some examples, the display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of the system memory 124 by the processing unit 120.

[0065] The display interface 340 may be configured to cause the display(s) 131 to display image frames. The display interface 340 may output image data to the display(s) 131 according to an interface protocol, such as, for example, the MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display(s) 131, may be configured in accordance with MIPI DSI standards. The MIPI DSI standard supports a video mode and a command mode. In examples where the display(s) 131 is / are operating in video mode, the display processor 127 may continuously refresh the graphical content of the display(s) 131. For example, the entire graphical content may be refreshed per refresh cycle (e.g., line-by-line). In examples where the display(s) 131 is / are operating in command mode, the display processor 127 may write the graphical content of a frame to a buffer 350.

[0066] In some such examples, the display processor 127 may not continuously refresh the graphical content of the display(s) 131. Instead, the display processor 127 may use a vertical synchronization (Vsync) pulse to coordinate rendering and consuming of graphical content at the buffer 350. For example, when a Vsync pulse is generated, the display processor 127 may output new graphical content to the buffer 350. Thus, generation of the Vsync pulse may indicate that current graphical content has been rendered at the buffer 350.

[0067] Frames are displayed at the display(s) 131 based on a display controller 345, a display client 355, and the buffer 350. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display(s) 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0068] The display client 355 may be associated with a touch panel that senses interactions between a user and the display(s) 131. As the user interacts with the display(s) 131, one or more sensors in the touch panel may output signals to the display controller 345 that indicate which of the one or more sensors have sensor activity, a duration ofthe sensor activity, an applied pressure to the one or more sensor, etc. The display controller 345 may use the sensor outputs to determine a manner in which the user has interacted with the display(s) 131. The display(s) 131 may be further associated with / include other devices, such as a camera, a microphone, and / or a speaker, that operate in connection with the display client 355.

[0069] Some processing techniques of the device 104 may be performed over three stages (e.g., stage 1 : a rendering stage; stage 2: a composition stage; and stage 3: a display / transfer stage). However, other processing techniques may combine the composition stage and the display / transfer stage into a single stage, such that the processing technique may be executed based on two total stages (e.g., stage 1 : the rendering stage; and stage 2: the composition / display / transfer stage). During the rendering stage, the GPU 310 may process a content buffer based on execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stage(s), pixel elements may be assembled to form a frame that is transferred to a physical display panel / subsystem (e.g., the displays 131) that displays the frame.

[0070] Instructions executed by a CPU (e.g., software instructions) or a display processor may cause the CPU or the display processor to search for and / or generate a composition strategy for composing a frame based on a dynamic priority and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, may include a plurality of layers. Also, composition of the frame may be based on combining the plurality of layers into the frame (e.g., based on a frame buffer). After the plurality of layers are combined into the frame, the frame may be provided to the display panel for display thereon. The process of combining each of the plurality of layers into the frame may be referred to as composition, frame composition, a composition procedure, a composition process, or the like.

[0071] A frame composition procedure or composition strategy may correspond to a technique for composing different layers of the plurality of layers into a single frame. The plurality of layers may be stored in doubled data rate (DDR) memory. Each layer of the plurality of layers may further correspond to a separate buffer. A composer or hardware composer (HWC) associated with a block or function may determine an input of each layer / buffer and perform the frame composition procedure to generatean output indicative of a composed frame. That is, the input may be the layers and the output may be a frame composition procedure for composing the frame to be displayed on the display panel.

[0072] Some aspects of display processing may utilize different types of mask layers, e.g., a shape mask layer. A mask layer is a layer that may represent a portion of a display or display panel. For instance, an area of a mask layer may correspond to an area of a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of a display area. Also, for certain portions of a display area, the content of different mask layers may overlap with one another. Accordingly, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0073] In order to compensate for backlight reduction, pixel values may be boosted according to a new backlight level so that there is minimal impact on an overall visual impression. The pixel value boosting may cause compressed dynamic range on certain pixels, sacrificing details and contrast at certain regions. In one aspect described herein, a device may determine a cutoff for each tile using the brightest x% of pixels in the local histogram, where x may be user configurable. The device may then calculate individual gamma shaped LUTs for each tile depending on the cutoff. A gamma shaped LUT may refer to a LUT having a shape associated with a function y = xr, where 0 < T < 1. The device may use a spatial filter for the smoothening of LUTs such that spatial discontinuities across different tiles may be countered. Spatial discontinuities may refer to a visual difference seen at a boundary of two adjacent tiles. The filter may be designed in such a way that the filter preserves details in brighter tiles. The device may then calculate a backlight for the whole frame based on the global histogram and adjust the local LUTs to correspond to the calculated backlight. In another aspect, a device may calculate a piecewise linear global LUT map based on a shape of image histograms (both global and local). The device may calculate an initial slope of the LUT using the global histogram and the device may use the local histogram to calculate histogram area densities that may appear insignificant in a global histogram for the subsequent slopes in the LUT. A higherslope in the LUT may correspond to a higher area density. The device may calculate a backlight for the whole frame based on an initial shape of the LUT. The process may be reverse compatible, i.e., the process may take a target backlight and compute (regenerate) the LUT map such that the LUT map is compatible with a histogram.

[0074] FIG. 4 is a diagram 400 illustrating an example 402 of an image 404, tiles 406, and a local histogram collection 408 in accordance with one or more techniques of this disclosure. A liquid crystal display (LCD) may refer to a display device that utilizes light-modulating properties of liquid crystals combined with polarizers in order to display graphical content. The liquid crystals may not emit light directly; instead, the LCD may utilize a backlight to produce the graphical content. LCDs may be utilized as displays for different types of devices (e.g., desktop computer monitors and mobile computing devices such as laptop computing devices, tablet computing devices, smartphones, etc.).

[0075] In some cases, the backlight of an LCD may be set at a maximum level (or a relatively high level) while the LCD displays graphical content, and hence the LCD may consume a maximum level of power (or a relatively high amount of power) when the backlight is set to the maximum level. In other cases, the backlight of the LCD may be set to a level that is less than the maximum level (or less than the relatively high level) while the LCD displays graphical content in order to conserve power. For instance, a mobile computing device that includes an LCD may have a limited amount of battery power, and the backlight may be set to the level that is less than the maximum level (or less than the relatively high level) in order to conserve battery power and prolong an amount of time a user can use the mobile computing device. In a specific example, the LCD may be set to the level that is less than the maximum level (or less than the relatively high level) when a battery level of the mobile computing device falls below a threshold percentage (e.g., below 50%, below 25%, below 10%, etc.). However, setting the backlight to the level that is less than the maximum level (or less than the relatively high level) may degrade picture quality. For instance, certain details in an image may not be visible when the backlight is set at the level that is less than the maximum level (or less than the relatively high level).

[0076] In order to address the aforementioned degraded picture quality issue, some techniques (e.g., content adaptive backlight (CABL)) may compensate for backlight level reduction by “boosting” (i.e., increasing) pixel values according to a reducedbacklight level to minimize impact on an overall visual impression of an image. A pixel may refer to a smallest addressable element in a display device. However, pixel value boosting may be limited by an intensity range (i.e., a fixed bit-depth) and may compress a dynamic range for certain pixels in an image, and hence may sacrifice details and contrast (i.e., washout) in regions of the image that include the certain pixels. The sacrificed details and contrast may be particularly noticeable for darker images, where a lower backlight level may be calculated for greater power savings. With more particularity, a CABL process (i.e., performed via a CABL algorithm) may generate a LUT that may saturate pixel ranges in bright regions of the image. A CABL algorithm may refer to a power saving algorithm that reduces a backlight in order to save power based on content of an image while causing minimal impact to a perceived picture quality. Saturated pixel mappings may cause bright regions in an image to lose detail and contrast. Techniques presented herein may make use of local histograms to generate multiple local lookup tables (LUTs) or a global LUT for compensating for a reduced backlight level while preserving details and contrast. In comparison to some techniques for backlight compensation (e.g., CABL), the techniques described herein may provide room to reduce backlight levels to relatively low levels, and hence may reduce power consumption of a device with no impact (or minimal impact) on image quality.

[0077] The image 404 may include a house 410 including a door 412 and a window 414. The image 404 may include a first tree 416 and a second tree 418. In an example, a device (e.g., the device 104) may generate the image 404 (e.g., render the image 404) and present the image 404 on an LCD display (e.g., the display(s) 131). However, if a backlight level of the LCD display is set to a level that is less than a maximum level (or less than a relatively high level), certain details in the image 404 may not be visible (or may be otherwise difficult to perceive) when presented on the LCD display, which may affect user experience. For instance, the window 414 may not be visible when the backlight level of the LCD display is set to the level that is less than the maximum level (or less than the relatively high level).

[0078] FIG. 5 is a diagram 500 illustrating a first example 502 of a process for mitigating detail loss in an image using local lookup table (LUT) maps when a device is operating at a reduced backlight level. The process may utilize local histogram information to generate local LUT maps (as opposed to a global LUT map) for a framefor image boosting in order to avoid saturation of pixels and to preserve detail s / contrast in the frame. A frame may refer to an image (e.g., an image in a sequence of images) that is displayed on a display panel. A LUT map may also be referred to as a color map or a LUT. A LUT may refer to a table of cross-references linking index numbers (i.e., input pixel values) to output values (i.e., output pixel values). A LUT may be utilize to determine colors and intensity values with which a particular frame will be displayed. A local LUT (i.e., a local LUT map, a local color map) may be a LUT for a portion of a frame (e.g., a tile of a frame), where the portion of the frame is less than an entirety of the frame. A global LUT (i.e., a global LUT map, a global color map) may be a LUT for the entirety of a frame.

[0079] A device (e.g., the device 104) may compute a local histogram collection 504 for a frame. For instance, referring jointly now to FIGs. 4 and 5, the device may divide the image 404 into tiles 406. In an example, the tiles 406 may be rectangular or square. A tile may refer to a defined portion of an image. In an example, the device may divide the image 404 into 4 x 10 tiles, 3 x 12 tiles, etc. In one aspect, a number of tiles in the tiles 406 may be fixed. In another aspect, the device may determine the number of tiles in the tiles 406 based on segmentation criteria, such as characteristics of a display (e.g., the display(s)) of the device, processing capabilities of the device, etc.) and / or a heuristic. Segmentation criteria may be based on a tradeoff between an improvement in picture quality versus hardware cost. For example, a first device may include a first processor with a first clock speed and a first amount of memory and a second device may include a second processor with a second clock speed and a second amount of memory. In the example, the first clock speed may be greater than the second clock speed and the first amount of memory may be greater than the second amount of memory. In the example, the first device may determine a first number of tiles based on the first clock speed and / or the first amount of memory and the second device may determine a second number of tiles based on the second clock speed and / or the second amount of memory. In the example, the first number of tiles may be greater than the second number of tiles. In an example, the tiles 406 may include a first tile 420 and a second tile 422. As depicted in FIG. 4, the second tile 422 may include the first tree 416.

[0080] The device may compute a local histogram collection 408 for the image 404, where each local histogram in the local histogram collection 408 corresponds to a differenttile in the tiles 406. A histogram may refer to a data structure that stores a number of pixels for each tonal value (e.g., each pixel value) in an image (or a portion of an image). When a histogram stores a number of pixels for each pixel value in an entirety of an image, the histogram may be referred to as a global histogram. When a histogram stores a number of pixels for each pixel value for a portion of an image (e.g., for a tile in the tiles 406), the histogram may be referred to as a local histogram. When displayed on a display, a histogram plots the number of tonal values (e.g., each pixel value). In an example, when displayed on a display, a histogram may include a plurality of bars along an x-axis, where each of the plurality of bars corresponds to a different pixel value, and where a height of each of the plurality of bars (along a y- axis) corresponds to a number of pixels. A pixel value that occurs relatively frequently in an image (or a portion of an image) may correspond to a relatively high bar and a pixel value that occurs relatively infrequently (or not at all) may have a relatively low bar (or no bar at all). In an example, the local histogram collection 408 may include a first local histogram 424 and a second local histogram 426, as well as other local histograms (not depicted in FIG. 4) for remaining tiles in the tiles 406. As depicted in FIG. 4, the first local histogram 424 and the second local histogram 426 have bars of different heights due to the first tree 416 being present in the second tile 422 of the image 404 and not being present in the first tile 420. In an example, the local histogram collection 408 may be or include the local histogram collection 504.

[0081] At 506, the device may calculate cutoff values and initial tile gains for each of the tiles 406. Pixel values that are above the cutoff values may suffer contrast loss. The device may calculate the cutoff values in accordance with a CABL procedure. FIG. 6 is a diagram 600 illustrating an example 602 of calculating a cutoff value in accordance with one or more techniques of this disclosure. Referring jointly now to FIGs. 4-6, the device may generate a local image histogram 604 for a tile in an input image 606. In an example, the input image 606 may be the image 404 and the tile may be the first tile 420 or the second tile 422. In an example, the local image histogram 604 may be the first local histogram 424 or the second local histogram 426.

[0082] The device may calculate a cutoffbin 608 (i.e., a bar corresponding to a pixel intensity value in the local image histogram 604, which may also be referred to as ''cutoffBin") based on a pixel distortion value 610 (i.e., a pixel distortion setting). In an example, the pixel distortion value may range from 1% - 25%, such as 5% - 20%, 10% - 15%,or 12% to 14%. In a specific example, the pixel distortion value may be 10%. The device may calculate the cutoff bin 608 as a histogram bin (i.e., a bar) where a number of pixels to the right of the histogram bin is equal to the pixel distortion value 610. For instance, when the pixel distortion value 610 is 10%, the device may calculate the cutoff bin 608 as a bin where a number of pixels to the right of the bin is equal to 10% of a total number of pixels in an image. In an example, the cutoff bin 608 may be approximately “75.”

[0083] The device may calculate a cutoff value 612 (which may also be referred to as “ cutoff') for the local image histogram 604 for the tile based on the cutoff bin 608. In an example, the device may calculate the cutoff value 612 according to equation (I) below.(I) cutoff = CentroicKregion to the right of cutoff Bin)

[0084] In equation (I), “Centroid" may refer to an arithmetic mean of the region to the right of “ cutoff Bin." In an example, the device may compute the cutoff value 612 to be 92.

[0085] Referring back to FIGs. 4 and 5, the device may calculate initial tile gains for each of the tiles 406 based on cutoff values for each of the tiles. In an example, the device may calculate the initial tile gains according to relationship (II) below. i(II) Gaini ocCUtoffi

[0086] In relationship (II), a gain value (Gaint) for an zth tile (e.g., the first tile 420) may be inversely proportional to a cutoff value (cutoff) for the zth tile, where i is a nonnegative integer. A gain value may refer to an amplification value that is applied to a pixel value. Stated differently, the gain value may be analogous to a slope of a (boosting) LUT map. As will be described in greater detail below, the gain value for each of the tiles 406 may be utilized to generate different local LUT maps for the tiles, which may each be used to boost respective pixels in the tiles 406.

[0087] Referring back to FIG. 4, the device may generate a global histogram collection 508. The global histogram collection 508 may include global histograms for frames. In an example, the global histogram collection 508 may include a global histogram for the image 404, as well as global histograms for previous presented images (e.g., previousframes). At 510, the device may calculate a backlight value based on statistics for the global histogram collection 508. A backlight value may refer to a level at which a backlight is set (e.g., 100% of maximum brightness, 50% of maximum brightness, 25% of maximum brightness, etc.). In an example, the device may calculate the backlight value based on a 256-bin histogram of a value channel (V-channel) of a frame and based on a brightness parameter, where the brightness parameter dictates a percentage of brightest pixels in a frame that may be distorted / saturated in order to conserve power. The V-channel may be from an hue, saturation, and value (HSV) color model. The V-channel may be defined as a maximum of red (R), green (G), and blue (B) from an RGB color model. At 512, the device may calculate a frame similarity based on the global histogram collection 508. At 514, the device may apply temporal filtering to the calculated backlight value based on the calculated frame similarity in order to generate a final backlight value 516. The temporal filtering may be configured to generate the final backlight value 516 such that flickering on a display panel is reduced. The global histogram collection 508 and the final backlight value 516 may correspond to a CABL process. Additionally, 510, 512, and 514 may correspond to the CABL process.

[0088] At 518, the device may apply spatial filtering and perform additional processing on the initial tile gains, where the additional processing may be based on the final backlight value 516. Applying the spatial filtering and performing the additional processing may collectively be referred to as “adjusting gains.” FIG. 7 is a diagram 700 illustrating an example 702 of adjusting gains in accordance with one or more techniques of this disclosure.

[0089] FIG. 7 illustrates a plot that depicts initial gains 704 for the image 404. The plot includes a first axis (0, 1, 2, 3, etc.) that corresponds to an x-axis of the image 404, a second axis (0.0, 0.5, 1.0, 1.5, etc.) that corresponds to a y-axis of the image 404, and a third axis that corresponds to the gain values (e.g., initial gain values) for the image 404 calculated at 506. In an example, “0” on the first axis and “0.0” on the second axis may collectively correspond to the first tile 420. The initial gains 704 may be represented as “Gij.” Target gains 706 also depicted in the plot. The target gains 706 may correspond to the final backlight value 516. The target gains 706 may be represented as “GT.”

[0090] Referring jointly now to FIGs. 5 and 7, the device may apply spatial filtering (i.e., a smoothening spatial filter) to the initial gains 704 for the image 404 in order to remove or mitigate discontinuities (i.e., spatial inconsistencies) from tile to tile in the tiles 406. With more particularity, the spatial filtering may retain lower gains in the initial gains 704 and may reduce higher gains in the initial gains 704 to reduce a difference (i.e., a delta) between the initial gains 704 and the target gains 706. Applying the spatial filtering to the initial gains 704 may generate filtered gains 708. The spatial filtering may reduce discontinuities between tiles and may preserve information in the brightest tiles in the tiles 406. The filtered gains 708 may be represented as “Gi ” The device may apply the spatial filtering according to equation (III) below.(Ill) Gtj = SpatialFilter Gij')

[0091] FIG. 8 is a diagram 800 illustrating an example 802 of spatial filtering in accordance with one or more techniques of this disclosure. The spatial filtering may be implemented in a spatial filtering block. The diagram 800 depicts a plot of initial gains 804. The plot of the initial gains 804 may correspond to the initial gains 704. In the plot of the initial gains 704, the x-axis may correspond to tile indices for the image 404 and the y-axis may correspond to gain values. In an example, a zero tile index may correspond to the first tile 420 and a first tile index may correspond to the second tile 422. The plot of the initial gains 804 includes a first initial gain value 806 for the first tile 420 and a second initial gain value 808 for the second tile 422. In an example, the first initial gain value 806 may be relatively high (e.g., “10”) and the second gain value may be relatively low (e.g., “2”).

[0092] The diagram 800 also depicts a plot of filtered gains 810 after the initial gains 804 have undergone spatial filtering. The plot of the filtered gains 810 may correspond to the filtered gains 708. The plot of the filtered gains 810 includes a first filtered gain value 812 corresponding to the first initial gain value 806 for the first tile 420 and a second filtered gain value 814 corresponding to the second initial gain value 808 for the second tile 422. As the first initial gain value 806 was relatively high (e.g., “10”), the first filtered gain value 812 may be “5.” As the second initial gain value 808 was relatively low (e.g., 2”), the second filtered gain value 814 may “2,” that is, the spatial filtering may not reduce a gain value. With more particularity, higher vain values maybe reduced if a slope cone of a neighbor tile of a tile dictates a lower gain for the tile. A slope may be dynamically dependent on image content (e.g., content of the image 404). In an example, the device may compute the slope according to equation (IV) below.

[0093] Referring back to FIG. 7, the device may mean shift the filtered gains 708 to generate mean shifted gains 710. The mean shift may push a mean of the filtered gains 708 towards the target gains 706. The mean shifted gains 710 may be represented as “Gij" .” The device may perform the mean shift according to equations (V)-(VII) below.(VII) Gtj = Gtj + Delta

[0094] The device may clip the mean shifted gains 710 to generate clipped gains 712 such that no gain value is greater than a target gain such that no tile appears brighter than an input value. The clipped gains 712 may be represented as “Gij' ' ' .” In an example, the device may clip the mean shifted gains 710 according to equation (VIII) below.

[0095] Referring back to FIG. 5, at 520, the device may generate local LUT maps based on the clipped gains 712, where each local LUT map in the local maps corresponds to a tile in the tiles 406. In an example, a first local LUT map may correspond to the first tile 420 and a second local LUT map may correspond to the second tile 422. At 522, the device may perform pixel mapping (i.e., pixel boosting) based on the local LUT maps. The local LUT maps may avoid washing out pixels and may preserve details in the image 404 at lower backlight levels. By using a different LUT map for each tile in the tiles 406, a bright tile that would be washed out under a CABL process maynow have a lower gain value and hence may retain its detail s / contrast. After performing the pixel mapping, the device may present the image 404 on a display panel (e.g., the display(s) 131).

[0096] FIG. 9 is a diagram 900 illustrating a second example 902 of a process for mitigating detail loss in an image via a hybrid approach that utilizes local LUT maps and a global LUT map. FIG. 10 is a diagram 1000 illustrating an example 1002 of a global histogram 1004, a local histogram 1006, and a region of interest 1008 in the global histogram and in the local histogram in accordance with one or more techniques of this disclosure. In an example, the global histogram 1004 may be for the image 404 and the local histogram 1006 may be for the second tile 422 of the image 404. In an example, the region of interest 1008 may correspond to the first tree 416 in the second tile 422. As the global histogram 1004 is for an entirety of the image 404 and the local histogram is for the second tile 422, heights of bars in the region of interest 1008 for the local histogram 1006 and the global histogram 1004 may vary. For instance, pixels corresponding to the first tree 416 may make up a relatively large amount of the second tile 422, whereas the pixels corresponding to the first tree 416 may make up a relatively small amount of the entirety of the image 404. Stated differently, the region of interest 1008 may be insignificant in the global histogram 1004, whereas the region of interest 1008 may be significant in the local histogram 1006. The hybrid approach described herein may leverage both local histograms and global histograms in order to mitigate detail loss in an image when a device is operating at a reduced backlight level. The hybrid approach may preserve high intensity regions of a histogram and hence may have a high possibility of preserving details in an image. The hybrid approach may predict a backlight level based on a shape of a histogram, and hence predicted backlights for images with similar histograms may be similar. This may help to assign consistent backlights to similar frames. The hybrid approach may also employ tuning parameters which may provide freedom to users to tune LUT maps (and predicted backlights) for different image quality settings and power savings. The hybrid approach may generate a piece-wise linear LUT map, which may preserve details in an image.

[0097] Referring back to FIG. 9, a device may obtain / compute a global histogram collection 904 for an image (e.g., the image 404). In an example, the global histogram collection 904 may include the global histogram 1004. At 906, the device may calculate a kneepoint based on the global histogram 1004. A knee point may refer to a point (1) at which a histogram intensity (i.e., a slope) of a histogram decreases to or beyond a threshold slope and / or (2) which encompasses (i.e., covers) a threshold percentage (e.g., 50%) of a total area of the histogram. The knee point may include an x- coordinate (xknee) and a y-coordinate (yknee). If the histogram does not have a decreasing slope (i.e., a decreasing trend), the knee point may be a point that encompasses the threshold percentage (e.g., 50%) of the total area of the histogram. The knee point may be calculated based on the global histogram 1004 in order to preserve grey-levels in the image 404.

[0098] FIG. 11 is a diagram 1100 illustrating an example 1102 of finding a knee point in accordance with one or more techniques of this disclosure. The example 1102 may correspond to 906 in FIG. 9. A device may generate / obtain a global histogram 1104 for an image (e.g., the image 404). The device may identify / compute xk e 1108 based on a threshold slope and a threshold percentage of an area of the global histogram 1104. The slope at xk e 1108 may be referred to as a knee slope 1109. The device may generate a cumulative histogram 1106 (e.g., a cumulative global histogram) based on the global histogram 1104. A cumulative histogram (e.g., a cumulative global histogram) may refer to a mapping that counts a cumulative number of observations (e.g., pixel counts) in all bins (e.g., pixel values) up to a specified bin (e.g., a maximum pixel value, such as 255). The cumulative histogram 1106 may be a cumulative sum of the global histogram 1104 normalized such that a maximum value is 255 (e.g., the maximum pixel value). The device may identify / compute yknee 1110 based on xk e 1108 according to equation (IX) below.(IX) yknee = CumulativeH istogram(xknee)

[0099] FIG. 12 is a diagram 1200 illustrating an example 1202 of initial piecewise linear global LUT map construction in accordance with one or more techniques of this disclosure. A piecewise linear global LUT map may refer to a global LUT that includes different pieces, where a line within each piece is linear. Lines between pieces may or may not be linear. After identifying / computing Xknee 1108 and yknee 1110, the device may construct an initial part 1206 of a piecewise linear global LUTmap by drawing a line from (0,0) to a knee point 1204, where the knee point 1204 is defined by Xknee 1108 andywe 1110.

[0100] Referring back to FIG. 9, at 907, the device may calculate a knee area density based on the knee point (e.g., the knee point 1204). For instance, referring to FIG. 11, the device may calculate a knee area density 1111 (i.e., a knee point area density) as the average number of pixels in a bin till a knee point A knee area density (i.e., a knee point area density) may be an area of a global histogram to the left of xknee divided by Xknee.

[0101] The device may compute remaining parts of the global LUT map based on a local histogram collection 908. The device may generate the local histogram collection 908 in a manner similar to that described above in FIG. 5. For instance, the device may divide the image 404 into the tiles 406 and the device may compute a local histogram for each of the tiles 406. In an example, the local histogram collection 908 may be or include the local histogram collection 408 or the local histogram collection 504. At 910, the device may divide each local histogram in the local histogram collection 908 into slabs.

[0102] FIG. 13 is a diagram 1300 illustrating an example 1302 of finding additional slopes for a global LUT map in accordance with one or more techniques of this disclosure. The example 1302 may correspond to 910 in FIG. 9. FIG. 13 depicts a local histogram 1304. In an example, the local histogram 1304 may be for the first tile 420. The device may divide the local histogram 1304 into slabs (not illustrated in FIG. 13), where the slabs include a slab 1306 with a slab width 1308. The slab 1306 may have a histogram area 1310, where the histogram area 1310 may refer to a total area of the local histogram 1304 within the slab 1306. A slab may refer to a division of a histogram that encompasses a subset of pixel values in the histogram. In one aspect, a number of slabs in the slabs may be fixed. In another aspect, the device may dynamically determine the number of slabs in the slabs based on criteria, such as characteristics of a display (e.g., the display(s)) of the device, processing capabilities of the device, etc. In one aspect, the slabs may have varying widths. For example, a first slab may encompass pixel values ranging from 0 to 50 and a second slab may encompass pixel values ranging from 50 to 75. In another aspect, the slabs may have a fixed width (e.g., 50).

[0103] Referring jointly now to FIGs. 9 and 13, at 912, the device may calculate a slab area density of the slabs based on widths of the slabs and a histogram area associated with each of the slabs. For instance, the device may calculate an area density 1312 for the slab 1306 based on the slab width 1308 and the histogram area 1310 according to equation (X) below. Stated differently, an area density of a slab may be an average number of pixels in a bin inside the slab.

[0104] At 912, the device may also calculate an area ratio of the slabs based on the area density for the slabs and the knee area density (e.g., the knee area density 1111). For instance, referring to FIG. 13, the device may calculate an area ratio 1314 for the slab 1306 based on the area density 1312 and the knee area density 1111 according to equation (XI) below. An area ratio for a slab may refer to a relative area density of the slab with respect to a knee point area density.

[0105] At 914, the device may calculate a relative slope for each of the slabs based on the area ratios (e.g., the area ratio 1314) and the knee slope (e.g., the knee slope 1109). For instance, for the slab 1306, the device may calculate a slope 1316 according to equation (XII) below.(XII) Slope slab) = Knee Slope * minimum(max. area ratio, 1)

[0106] In equation (XII), “max. area ratio” may refer to a maximum area ratio amongst the area ratios calculated for the slabs. A slope may refer to a slope of line associated with the slab forming the piecewise linear LUT map.

[0107] At 916, the device may generate a piecewise linear global LUT map based on the relative slops calculated at 914 and based on the initial part 1206 of the piecewise linear global LUT map 1402.

[0108] FIG. 14 is a diagram 1400 illustrating an example piecewise linear global LUT map 1402 in accordance with one or more techniques of this disclosure. The piecewiselinear global LUT map 1402 may include the initial part 1206 as described above with respect to FIG. 12. The piecewise linear global LUT map 1402 may also include a first piece 1403 corresponding to the slab 1306, where the first piece 1403 has the slope 1316. For instance, the device may connect a line with the slope 1316 from an ending point of the initial part 1206 (e.g., the knee point 1204) to an ending point of the slab 1306. The device may repeat a similar procedure for other slabs to generate the piecewise linear global LUT map 1402.

[0109] Referring to FIG. 9, at 918, the device may adjust the piecewise linear global LUT map. FIG. 15 is a diagram 1500 illustrating examples 1502 of adjusting a piecewise linear global LUT map (e.g., the piecewise linear global LUT map 1402) in accordance with one or more techniques of this disclosure. In a first example 1504, the device may normalize (e.g., based on a normalization value) the piecewise linear global LUT map 1402 such that a maximum value (e.g., a pixel count) of the piecewise linear global LUT map 1402 is the maximum bit depth (e.g. 255 in 8-bit format). In a second example, the device may assign a slope of “1” to a piece of the piecewise linear global LUT map 1402 if a slope of the piece is less than “1.”

[0110] Referring back to FIG. 9, at 920, the device may calculate a backlight value based on the calculated knee point. Calculating the backlight value may include aspects described above in connection with 510 of FIG. 5. At 922, the device may perform temporal filtering on the calculated backlight value to obtain a final filtered backlight value 924. The temporal filtering may include aspects described above in connection with 514 of FIG. 5. The final filtered backlight value 924 may be or include the final backlight value 516. After performing the pixel mapping, the device may display the image (e.g., image 404) on a display panel (e.g., the display(s) 131).[OHl] At 926, the device may regenerate the (adjusted) piecewise linear global LUT map based on the final filtered backlight value 924. At 928, the device may perform pixel mapping based on the regenerated piecewise linear global LUT map.

[0112] FIG. 16 is a call flow diagram 1600 illustrating example communications between a CPU 1602 and a DPU 1604 in accordance with one or more techniques of this disclosure. In an example, the CPU 1602 and the DPU 1604 may be included in the device 104. The call flow diagram 1600 may correspond to the first example 502.

[0113] At 1606, the CPU 1602 may segment a frame into a plurality of tiles based on segmentation criteria. At 1608, the CPU 1602 may determine a cutoff value for eachof the plurality of tiles of the frame based on a local histogram for each of the plurality of tiles. At 1610, the CPU 1602 may apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. At 1612, the CPU 1602 may calculate a backlight value for the global histogram for the frame based on a CABL algorithm. At 1614, the CPU 1602 may adjust the cutoff value for each of the plurality of tiles based on the backlight value for a global histogram for the frame. At 1616, the CPU 1602 may calculate a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. At 1618, the CPU 1602 may adjust a pixel value associated with the frame based on the calculated LUT. At 1620, the CPU 1602 may output (e.g., to the DPU 1604) an indication of the calculated LUT for each of the plurality of tiles.

[0114] FIG. 17 is a call flow diagram 1700 illustrating example communications between a CPU 1702 and a DPU 1704 in accordance with one or more techniques of this disclosure. In an example, the CPU 1702 and the DPU 1704 may be included in the device 104. The call flow diagram 1700 may correspond to the second example 902.

[0115] At 1706, the CPU 1702 may segment a frame into a plurality of tiles based on segmentation criteria. At 1708, the CPU 1702 may calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. At 1710, the CPU 1702 may divide each of a plurality of local histograms for the frame into a plurality of slabs. At 1712, the CPU 1702 may assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. At 1714, the CPU 1702 may calculate a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. At 1715, the CPU 1702 may calculate a backlight value based on the knee point and the global LUT map. At 1718, the CPU 1702 may receive a backlight value. At 1720, the CPU 1702 may modify the global LUT map based on the backlight value, where adjusting the pixel value includes adjusting the pixel value based on the modified global LUT map. At 1722, the CPU 1702 may adjust a pixel value associated with the frame based on the global LUT map. At 1724, the CPU 1702 may output (e.g., to the DPU 1704) an indication of the global LUT map for the frame.

[0116] FIG. 18 is a flowchart 1800 of an example method display processing in accordance with one or more techniques of this disclosure. The method may be performed by anapparatus, such as an apparatus for display processing, the device 104, a GPU, a CPU, a display processing unit (DPU) or other display processor, DPU driver software executed by a CPU, wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-17. In an example, the method may be associated with removing or mitigating “washed out” images caused by reduced backlight levels. The method may correspond to the first example 502. In an example, the method may be performed by the LUT generator 198.

[0117] At 1802, the apparatus (e.g., a CPU) determines a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. For example, FIG. 16 at 1608 shows that the CPU 1602 may determine a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. In an example, determining the cutoff value may be associated with equations (I) and relationship (II) above. In another example, determining the cutoff value may correspond to 506 in FIG. 5. In a further example, determining the cutoff value may correspond to the example 602. For instance, the cutoff value may be or include the cutoff value 612. In an example, the plurality of tiles may be or include the tiles 406. In another example, the frame may be or include the image 404 or the input image 606. In a further example, the cutoff value may be associated with the initial gains 704 or the initial gains 804. In an example, the local histogram for each of the plurality of tiles may be the local histogram collection 408 (e.g., the first local histogram 424, the second local histogram 426, etc.) or the local histogram collection 504. In an example, 1802 may be performed by the LUT generator 198.

[0118] At 1804, the apparatus (e.g., a CPU) applies a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. For example, FIG. 16 at 1610 shows that the CPU 1602 may apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. In an example, applying the spatial filter may correspond to 518 in FIG. 5. In an example, applying the spatial filter may be associated with equation (III) above. In another example, applying the spatial filter may be associated with the filtered gains 708 or the filtered gains 810. In an example, 1804 may be performed by the LUT generator 198.

[0119] At 1806, the apparatus (e.g., a CPU) adjusts the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. For example,FIG. 16 at 1614 shows that the CPU 1602 may adjust the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. In an example, adjusting the cutoff value may correspond to 518 in FIG. 5. In an example, the global histogram may be a global histogram in the global histogram collection 508. In an example, the global histogram may be the global histogram 1004. In an example, the global histogram may be for the image 404. In an example, the backlight value may be the final backlight value 516. In an example, adjusting the cutoff value may be associated with the mean shifted gains 710 and / or the clipped gains 712. In an example, the backlight value may be associated with target gains 706. In an example, 1806 may be performed by the LUT generator 198.

[0120] At 1808, the apparatus (e.g., a CPU) calculates a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. For example, FIG. 16 at 1614 shows that the CPU 1602 may calculate a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. In an example, calculating the LUT for each of the plurality of tiles may correspond to 520 in FIG. 5. In an example, 1808 may be performed by the LUT generator 198.

[0121] At 1810, the apparatus (e.g., a CPU) outputs an indication of the calculated LUT for each of the plurality of tiles. For example, FIG. 16 at 1620 shows that the CPU 1602 may output (e.g., to the DPU 1604) an indication of the calculated LUT for each of the plurality of tiles. In an example, 1810 may be performed by the LUT generator 198.

[0122] FIG. 19 is a flowchart 1900 of an example method display processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, such as an apparatus for display processing, the device 104, a GPU, a CPU, a display processing unit (DPU) or other display processor, DPU driver software executed by a CPU, wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-17. In an example, the method may be associated with removing or mitigating “washed out” images caused by reduced backlight levels. The method may correspond to the first example 502. In an example, the method may be performed by the LUT generator 198.

[0123] At 1904, the apparatus (e.g., a CPU) determines a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. For example, FIG. 16 at 1608 shows that the CPU 1602 may determine a cutoff value foreach of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. In an example, determining the cutoff value may be associated with equations (I) and relationship (II) above. In another example, determining the cutoff value may correspond to 506 in FIG. 5. In a further example, determining the cutoff value may correspond to the example 602. For instance, the cutoff value may be or include the cutoff value 612. In an example, the plurality of tiles may be or include the tiles 406. In another example, the frame may be or include the image 404 or the input image 606. In a further example, the cutoff value may be associated with the initial gains 704 or the initial gains 804. In an example, the local histogram for each of the plurality of tiles may be the local histogram collection 408 (e.g., the first local histogram 424, the second local histogram 426, etc.) or the local histogram collection 504. In an example, 1904 may be performed by the LUT generator 198.

[0124] At 1906, the apparatus (e.g., a CPU) applies a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. For example, FIG. 16 at 1610 shows that the CPU 1602 may apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. In an example, applying the spatial filter may correspond to 518 in FIG. 5. In an example, applying the spatial filter may be associated with equation (III) above. In another example, applying the spatial filter may be associated with the filtered gains 708 or the filtered gains 810. In an example, 1906 may be performed by the LUT generator 198.

[0125] At 1910, the apparatus (e.g., a CPU) adjusts the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. For example, FIG. 16 at 1614 shows that the CPU 1602 may adjust the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. In an example, adjusting the cutoff value may correspond to 518 in FIG. 5. In an example, the global histogram may be a global histogram in the global histogram collection 508. In an example, the global histogram may be the global histogram 1004. In an example, the global histogram may be for the image 404. In an example, the backlight value may be the final backlight value 516. In an example, adjusting the cutoff value may be associated with the mean shifted gains 710 and / or the clipped gains 712. In an example, the backlight value may be associated with target gains 706. In an example, 1910 may be performed by the LUT generator 198.

[0126] At 1912, the apparatus (e.g., a CPU) calculates a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. For example, FIG. 16 at 1614 shows that the CPU 1602 may calculate a LUT for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. In an example, calculating the LUT for each of the plurality of tiles may correspond to 520 in FIG. 5. In an example, 1912 may be performed by the LUT generator 198.

[0127] At 1914, the apparatus (e.g., a CPU) outputs an indication of the calculated LUT for each of the plurality of tiles. For example, FIG. 16 at 1620 shows that the CPU 1602 may output (e.g., to the DPU 1604) an indication of the calculated LUT for each of the plurality of tiles. In an example, 1914 may be performed by the LUT generator 198.

[0128] In one aspect, determining the cutoff value for each of the plurality of tiles of the frame based on the local histogram for each of the plurality of tiles may include: calculating a first cutoff value for a first tile based on a threshold percentage of pixels associated with a first local histogram for the first tile. In an example, the aforementioned aspect may correspond to equation (I) above. In an example, the first cuff value may be the cutoff value 612 and the first tile may be the first tile 420. In an example, the first local histogram may be the first local histogram 424. In an example, the threshold percentage of pixels may be associated with the pixel distortion value 610.

[0129] In one aspect, each LUT for each of the plurality of tiles may be associated with a dynamic range compression that is different from other dynamic range compressions associated with other LUTs for other tiles of the plurality of tiles. For example, each LUT calculated at 1616 for each of the plurality of tiles may be associated with a dynamic range compression that is different from other dynamic range compressions associated with other LUTs for other tiles of the plurality of tiles. In an example, a LUT corresponding to the first tile 420 may have a different dynamic range compression than a dynamic range compression of a LUT corresponding to the second tile 422.

[0130] In one aspect, adjusting the cutoff value for each of the plurality of tiles based on the backlight value for the global histogram for the frame may include: performing a mean shift based on the backlight value. For example, performing the mean shift based on the backlight value may correspond to the mean shifted gains 710.

[0131] In one aspect, at 1908, the apparatus (e.g., a CPU) may calculate the backlight value for the global histogram for the frame based on a CABL algorithm. For example, FIG. 16 at 1612 shows that the CPU 1602 may calculate the backlight value for the global histogram for the frame based on a CABL algorithm. In an example, the aforementioned aspect may correspond to 510, 512, and / or 514 in FIG. 5. In an example, 1908 may be performed by the LUT generator 198.

[0132] In one aspect, the cutoff values for each of the plurality of tiles may be associated with a gain value. For example, the aforementioned aspect may correspond to FIG. 7.

[0133] In one aspect, at 1902, the apparatus (e.g., a CPU) may segment the frame into the plurality of tiles based on segmentation criteria. For example, FIG. 16 at 1606 shows that the CPU 1602 may segment the frame into the plurality of tiles based on segmentation criteria. In an example, 1902 may be performed by the LUT generator 198.

[0134] In one aspect, a first tile and a second tile in the plurality of tiles may respectively be associated with a first gain value and a second gain value that is greater than the first gain value, where applying the spatial filter to the cutoff value for each of the plurality of tiles may include: reducing the second gain value based on the first gain value. For example, the first tile may be the first tile 420 and the second tile may be the second tile 422. In an example, the aforementioned aspect may correspond to the example 802.

[0135] In one aspect, outputting the indication of the calculated LUT for each of the plurality of tiles may include: storing the indication of the calculated LUT for each of the plurality of tiles in at least one of a memory, a buffer, or a cache; or transmitting the indication of the calculated LUT for each of the plurality of tiles. For example, outputting the indication at 1620 may include storing the indication of the calculated LUT for each of the plurality of tiles in at least one of a memory, a buffer, or a cache. In another example, outputting the indication at 1620 may include transmitting (e.g., to the DPU 1604) the indication of the calculated LUT for each of the plurality of tiles.

[0136] In one aspect, at 1916, the apparatus (e.g., a CPU) may adjust a pixel value associated with the frame based on the calculated LUT. For example, FIG. 16 at 1618 shows that the CPU 1602 may adjust a pixel value associated with the frame based on thecalculated LUT. In an example, the aforementioned aspect may correspond to 522 in FIG. 5. In an example, 1916 may be performed by the LUT generator 198.

[0137] FIG. 20 is a flowchart 2000 of an example method display processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, such as an apparatus for display processing, the device 104, a GPU, a CPU, a display processing unit (DPU) or other display processor, DPU driver software executed by a CPU, wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-17. The method may correspond to the second example 902. In an example, the method may be performed by the LUT generator 198.

[0138] At 2002, the apparatus (e.g., a CPU) calculates a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. For example, FIG. 17 at 1708 shows that the CPU 1702 may calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. In an example, calculating the knee point may correspond to 906 in FIG. 9. In an example, calculating the knee point may correspond to the example 1102 and / or the example 1202. In an example, the global histogram may be the global histogram 1004 or the global histogram 1104. In an example, the frame may be the image 404. In an example, the cumulative global histogram may be the cumulative histogram 1106. In an example, calculating the knee point may be associated with equation (IX) above. In an example, 2002 may be performed by the LUT generator 198.

[0139] At 2004, the apparatus (e.g., a CPU) divides each of a plurality of local histograms for the frame into a plurality of slabs. For example, FIG. 17 at 1710 shows that the CPU 1702 may divide each of a plurality of local histograms for the frame into a plurality of slabs. In an example, the plurality of local histograms may be the local histogram collection 408 or the local histogram collection 908. In an example, dividing each of the plurality of local histograms may correspond to 910 in FIG. 9. In an example, the plurality of local histograms may include the local histogram 1006 or the local histogram 1304. In an example, the plurality of slabs may include the slab 1306. In an example, 2004 may be performed by the LUT generator 198.

[0140] At 2006, the apparatus (e.g., a CPU) assigns a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. For example, FIG. 17 at 1712 shows that the CPU 1702 may assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. In an example, assigning the slope to each of the slabs may correspond to 914 in FIG. 9. In an example, the area may be associated with the histogram area 1310. In an example, a slope may be the slope 1316. In an example, 2006 may be performed by the LUT generator 198.

[0141] At 2008, the apparatus (e.g., a CPU) calculates a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. For example, FIG. 17 at 1714 shows that the CPU 1702 may calculate a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. For example, the global LUT map may be the piecewise linear global LUT map 1402. In an example, the calculating the global LUT map may correspond to 916 in FIG. 9. In an example, 2008 may be performed by the LUT generator 198.

[0142] At 2010, the apparatus (e.g., a CPU) outputs an indication of the global LUT map for the frame. For example, FIG. 17 at 1724 shows that the CPU 1702 may output an indication of the global LUT map for the frame. In an example, 2010 may be performed by the LUT generator 198.

[0143] FIG. 21 is a flowchart 2100 of an example method display processing in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus, such as an apparatus for display processing, the device 104, a GPU, a CPU, a display processing unit (DPU) or other display processor, DPU driver software executed by a CPU, wireless communication device, and the like, as used in connection with the aspects of FIGs. 1-17. The method may correspond to the second example 902. In an example, the method may be performed by the LUT generator 198.

[0144] At 2102, the apparatus (e.g., a CPU) calculates a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. For example, FIG. 17 at 1708 shows that the CPU 1702 may calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. In anexample, calculating the knee point may correspond to 906 in FIG. 9. In an example, calculating the knee point may correspond to the example 1102 and / or the example 1202. In an example, the global histogram may be the global histogram 1004 or the global histogram 1104. In an example, the frame may be the image 404. In an example, the cumulative global histogram may be the cumulative histogram 1106. In an example, calculating the knee point may be associated with equation (IX) above. In an example, 2102 may be performed by the LUT generator 198.

[0145] At 2104, the apparatus (e.g., a CPU) divides each of a plurality of local histograms for the frame into a plurality of slabs. For example, FIG. 17 at 1710 shows that the CPU 1702 may divide each of a plurality of local histograms for the frame into a plurality of slabs. In an example, the plurality of local histograms may be the local histogram collection 408 or the local histogram collection 908. In an example, dividing each of the plurality of local histograms may correspond to 910 in FIG. 9. In an example, the plurality of local histograms may include the local histogram 1006 or the local histogram 1304. In an example, the plurality of slabs may include the slab 1306. In an example, 2104 may be performed by the LUT generator 198.

[0146] At 2106, the apparatus (e.g., a CPU) assigns a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. For example, FIG. 17 at 1712 shows that the CPU 1702 may assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. In an example, assigning the slope to each of the slabs may correspond to 914 in FIG. 9. In an example, the area may be associated with the histogram area 1310. In an example, a slope may be the slope 1316. In an example, 2106 may be performed by the LUT generator 198.

[0147] At 2108 the apparatus (e.g., a CPU) calculates a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. For example, FIG. 17 at 1714 shows that the CPU 1702 may calculate a global LUT map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. For example, the global LUT map may be the piecewise linear global LUT map 1402. In an example, the calculating the global LUT map may correspond to 916 in FIG. 9. In an example, 2108 may be performed by the LUT generator 198.

[0148] At 2110, the apparatus (e.g., a CPU) outputs an indication of the global LUT map for the frame. For example, FIG. 17 at 1724 shows that the CPU 1702 may output anindication of the global LUT map for the frame. In an example, 2110 may be performed by the LUT generator 198

[0149] In one aspect, outputting the indication of the global LUT map for the frame may include: storing the indication of the global LUT map for the frame in at least one of a memory, a buffer, or a cache; or transmitting the indication of the global LUT map. For example, outputting the indication of the global LUT map at 1724 may include storing the indication of the global LUT map for the frame in at least one of a memory, a buffer, or a cache. In another example, outputting the indication of the global LUT map at 1724 may include transmitting (e.g., to the DPU 1704) the indication of the global LUT map.

[0150] In one aspect, calculating the knee point of the global histogram for the frame may include: computing the cumulative global histogram based on the global histogram. For example, calculating the knee point at 1708 may include computing the cumulative histogram 1106 based on the global histogram 1104.

[0151] In one aspect, calculating the knee point of the global histogram for the frame may include: identifying an x-coordinate of the knee point based on (1) at least one of the change in the first slope of the cumulative global histogram or the threshold area and (2) a threshold slope. For example, the x-coordinate of the knee point may be xkme 1108.

[0152] In one aspect, calculating the knee point of the global histogram for the frame may include: identifying a y-coordinate of the knee point based on the x-coordinate of the knee point and the cumulative global histogram. In an example, the y-coordinate of the knee point may be y / .-nee 1110. In an example, the y-coordinate may be identified according to equation (IX) above.

[0153] In one aspect, calculating the global LUT map for the frame may include assigning an initial line from an origin to a point defined by the x-coordinate of the knee point and the y-coordinate of the knee point. For example, the initial line may correspond to the initial part 1206.

[0154] In one aspect, assigning the slope to each of the plurality of slabs may include: computing an area density for each of the plurality of slabs based on an area of each of the plurality of slabs and a width of each of the plurality of slabs. For example, the area density may be the area density 1312 and the width may be the slab width 1308. In an example, the aforementioned aspect may correspond to 912 in FIG. 9. In anexample, an area of a slab may correspond to the histogram area 1310. In an example, the area density may be computed according to equation (X) above.

[0155] In one aspect, assigning the slope to each of the plurality of slabs may include: computing a knee point area density based on a global area of the global histogram extending until the knee point and a global width of the global histogram until the knee point. For example, the knee point area density may be the knee area density 1111. In an example, the aforementioned aspect may correspond to 907 in FIG. 9.

[0156] In one aspect, assigning the slope to each of the plurality of slabs may include: computing an area ratio for each of a plurality of tiles corresponding to the plurality of slabs based on the area density for each of the plurality of slabs and the knee point area density. In an example, the area ratio may be the area ratio 1314. In an example, the aforementioned aspect may correspond to 912 in FIG. 9. In an example, the area ratio may be computed according to equation (XI) above.

[0157] In one aspect, assigning the slope to each of the plurality of slabs further may include: assigning the slope to each of the plurality of slabs based on a knee point slope associated with the knee point, a maximum area ratio from amongst the area ratio for each of the plurality of tiles, and a predefined slope. In an example, the aforementioned aspect may correspond to 912 and 914 in FIG. 9. In an example, the knee point slope may be the knee slope 1109. In an example, the aforementioned aspect may correspond to equation (XII) above.

[0158] In one aspect, calculating the global LUT map for the frame may further include: computing a plurality of lines based on the slope assigned to each of the plurality of slabs. In an example, the aforementioned aspect may correspond to 914 and 916 in FIG. 9. In another example, FIG. 14 shows that a device may compute a plurality of lines of the piecewise linear global LUT map 1402.

[0159] In one aspect, calculating the global LUT map for the frame may further include: combining each line in the plurality of lines with at least one other line in the plurality of lines. In an example, the aforementioned aspect may correspond to 914 and 916 in FIG. 9. In another example, FIG. 14 shows that a device may combining each line in the plurality of lines with at least one other line in the plurality of lines.

[0160] In one aspect, calculating the global LUT map for the frame may further include: combining the initial line with a first line in the plurality of lines, where the global LUT map may include the line and the plurality of lines. For example, the initial linemay be a line associated with the initial part 1206 and first line may be a line associated with the first piece 1403 of the piecewise linear global LUT map 1402.

[0161] In one aspect, calculating the global LUT map for the frame may further include: normalizing the global LUT map based on a normalization value. For example, the first example 1504 shows that calculating the global LUT map for the frame may further include: normalizing the global LUT map based on a normalization value. In an example, the aforementioned aspect may correspond to 918 in FIG. 9.

[0162] In one aspect, calculating the global LUT map for the frame may further include: determining that a second slope of a second line in the plurality of lines is less than the predefined slope. For example, the aforementioned aspect may correspond to the second example 1506 of FIG. 15. In an example, the aforementioned aspect may correspond to 918 in FIG. 9.

[0163] In one aspect, calculating the global LUT map for the frame may further include: adjusting, based on the determination, the second slope of the second line to be equal to the predefined slope. For example, the aforementioned aspect may correspond to the second example 1506 of FIG. 15. In an example, the aforementioned aspect may correspond to 918 in FIG. 9.

[0164] In one aspect, the global LUT map may include a piecewise linear global LUT map. For example, the global LUT map may be the piecewise linear global LUT map 1402.

[0165] In one aspect, each of the plurality of slabs may correspond to a tile in a plurality of tiles of the frame. For example, the slab 1306 may correspond to a tile in the tiles 406 (e.g., the first tile 420, the second tile 422).

[0166] In one aspect, at 2118, the apparatus (e.g., a CPU) may adjust a pixel value associated with the frame based on the global LUT map. For example, FIG. 17 at 1722 shows that the CPU 1702 may adjust a pixel value associated with the frame based on the global LUT map. In an example, the aforementioned aspect may correspond to 928 in FIG. 9. In an example, 2118 may be performed by the LUT generator 198.

[0167] In one aspect, at 2112, the apparatus (e.g., a CPU) may calculate a backlight value based on the knee point and the global LUT map, where adjusting the pixel value may include adjusting the pixel value based on the calculated backlight value. In an example, FIG. 17 at 1715 shows that the CPU 1702 may calculate a backlight value based on the knee point and the global LUT map, where adjusting the pixel value at 1722 may include adjusting the pixel value based on the calculated backlight value.In an example, the aforementioned aspect may correspond to 920 and 922 in FIG. 9. For instance, the backlight value may be the final filtered backlight value 924. In an example, 2112 may be performed by the LUT generator 198.

[0168] In one aspect, at 2114, the apparatus (e.g., a CPU) may receive a backlight value. For example, FIG. 17 at 1718 shows that the CPU 1702 may receive a backlight value. In an example, the backlight value may be the final filtered backlight value 924. In an example, 2114 may be performed by the LUT generator 198.

[0169] In one aspect, at 2116, the apparatus (e.g., a CPU) may modify the global LUT map based on the backlight value, where adjusting the pixel value may include adjusting the pixel value based on the modified global LUT map. For example, FIG. 17 at 1720 shows that the CPU 1702 may modify the global LUT map based on the backlight value, where adjusting the pixel value at 1722 may include adjusting the pixel value based on the modified global LUT map. In an example, the aforementioned aspect may correspond to 926 in FIG. 9. In an example, 2116 may be performed by the LUT generator 198.

[0170] In configurations, a method or an apparatus for display processing is provided. The apparatus may be a DPU, a display processor, or some other processor that may perform display processing. In aspects, the apparatus may be the display processor 127 within the device 104, or may be some other hardware within the device 104 or another device, such as the processing unit 120. The apparatus may include means for determining a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles. The apparatus may further include means for applying a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles. The apparatus may further include means for adjusting the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame. The apparatus may further include means for calculating a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles. The apparatus may further include means for outputting an indication of the calculated LUT for each of the plurality of tiles. The apparatus may further include means for calculating the backlight value for the global histogram for the frame based on a content adaptive backlight (CABL) algorithm. The apparatus may further include means for segmenting the frame into the plurality of tiles based on segmentationcriteria. The apparatus may further include means for adjusting a pixel value associated with the frame based on the calculated LUT.

[0171] In configurations, a method or an apparatus for display processing is provided. The apparatus may be a DPU, a display processor, or some other processor that may perform display processing. In aspects, the apparatus may be the display processor 127 within the device 104, or may be some other hardware within the device 104 or another device, such as the processing unit 120. The apparatus may include means for calculating a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area. The apparatus may further include means for dividing each of a plurality of local histograms for the frame into a plurality of slabs. The apparatus may further include means for assigning a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs. The apparatus may further include means for calculating a global lookup table (LUT) map for the frame based on the first slope and the slope assigned to each of the plurality of slabs. The apparatus may further include means for outputting an indication of the global LUT map for the frame. The apparatus may further include means for adjusting a pixel value associated with the frame based on the global LUT map. The apparatus may further include means for calculating a backlight value based on the knee point and the global LUT map, where adjusting the pixel value includes adjusting the pixel value based on the calculated backlight value. The apparatus may further include means for receiving a backlight value. The apparatus may further include means for modifying the global LUT map based on the backlight value, where adjusting the pixel value includes adjusting the pixel value based on the modified global LUT map.

[0172] It is understood that the specific order or hierarchy of blocks / steps in the processes, flowcharts, and / or call flow diagrams disclosed herein is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of the blocks / steps in the processes, flowcharts, and / or call flow diagrams may be rearranged. Further, some blocks / steps may be combined and / or omitted. Other blocks / steps may also be added. The accompanying method claims present elements of the various blocks / steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0173] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, where reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0174] Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like may not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.” Unless stated otherwise, the phrase “a processor” may refer to “any of one or more processors” (e.g., one processor of one or more processors, a number (greater than one) of processors in the one or more processors, or all of the one or more processors) and the phrase “a memory” may refer to “any of one or more memories” (e.g., one memory of one or more memories, anumber (greater than one) of memories in the one or more memories, or all of the one or more memories).

[0175] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0176] Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to: (1) tangible computer-readable storage media, which is non-transitory; or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compact disc-read only memory (CD-ROM), or other optical disk storage, magnetic disk storage, or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0177] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or moreprocessors as described above, in conjunction with suitable software and / or firmware. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0178] The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

[0179] Aspect l is a method of display processing, including: determining a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles; applying a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles; adjusting the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame; calculating a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles; and outputting an indication of the calculated LUT for each of the plurality of tiles.

[0180] Aspect 2 may be combined with aspect 1, wherein determining the cutoff value for each of the plurality of tiles of the frame based on the local histogram for each of the plurality of tiles includes: calculating a first cutoff value for a first tile based on a threshold percentage of pixels associated with a first local histogram for the first tile.

[0181] Aspect 3 may be combined with any of aspects 1-2, wherein each LUT for each of the plurality of tiles is associated with a dynamic range compression that is different from other dynamic range compressions associated with other LUTs for other tiles of the plurality of tiles.

[0182] Aspect 4 may be combined with any of aspects 1-3, wherein adjusting the cutoff value for each of the plurality of tiles based on the backlight value for the global histogram for the frame includes: performing a mean shift based on the backlight value.

[0183] Aspect 5 may be combined with any of aspects 1-4, further including: calculating the backlight value for the global histogram for the frame based on a content adaptive backlight (CABL) algorithm.

[0184] Aspect 6 may be combined with any of aspects 1-5, wherein the cutoff values for each of the plurality of tiles is associated with a gain value.

[0185] Aspect 7 may be combined with any of aspects 1-6, further including: segmenting the frame into the plurality of tiles based on segmentation criteria.

[0186] Aspect 8 may be combined with any of aspects 1-7, wherein a first tile and a second tile in the plurality of tiles are respectively associated with a first gain value and a second gain value that is greater than the first gain value, wherein applying the spatial filter to the cutoff value for each of the plurality of tiles includes: reducing the second gain value based on the first gain value.

[0187] Aspect 9 may be combined with any of aspects 1-8, wherein outputting the indication of the calculated LUT for each of the plurality of tiles includes: storing the indication of the calculated LUT for each of the plurality of tiles in at least one of a memory, a buffer, or a cache; or transmitting the indication of the calculated LUT for each of the plurality of tiles.

[0188] Aspect 10 may be combined with any of aspects 1-9, further including: adjusting a pixel value associated with the frame based on the calculated LUT.

[0189] Aspect 11 is an apparatus for display processing comprising a processor coupled to a memory and, based on information stored in the memory, the processor is configured to implement a method as in any of aspects 1-10.

[0190] Aspect 12 may be combined with aspect 11 and comprises that the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein the processor is configured to obtain the frame via at least one of the transceiver or the antenna.

[0191] Aspect 13 is an apparatus for display processing comprising means for implementing a method as in any of aspects 1-10.

[0192] Aspect 14 is a computer-readable medium (e.g., a non-transitory computer readable- medium) storing computer executable code, the computer executable code, when executed by a processor, causes the processor to implement a method as in any of aspects 1-10.

[0193] Aspect 15 is a method of display processing, including: calculating a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area; dividing each of a plurality of local histograms for the frame into a plurality of slabs; assigning a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs; calculating a global lookup table (LUT) map for the frame based on the first slope and the slope assignedto each of the plurality of slabs; and outputting an indication of the global LUT map for the frame.

[0194] Aspect 16 may be combined with aspect 15, wherein outputting the indication of the global LUT map for the frame includes: storing the indication of the global LUT map for the frame in at least one of a memory, a buffer, or a cache; or transmitting the indication of the global LUT map.

[0195] Aspect 17 may be combined with any of aspects 15-16, wherein calculating the knee point of the global histogram for the frame includes: computing the cumulative global histogram based on the global histogram; identifying an x-coordinate of the knee point based on (1) at least one of the change in the first slope of the cumulative global histogram or the threshold area and (2) a threshold slope; identifying a y-coordinate of the knee point based on the x-coordinate of the knee point and the cumulative global histogram.

[0196] Aspect 18 may be combined with aspect 17, wherein calculating the global LUT map for the frame includes assigning an initial line from an origin to a point defined by the x-coordinate of the knee point and the y-coordinate of the knee point.

[0197] Aspect 19 may be combined with aspect 18, wherein assigning the slope to each of the plurality of slabs includes: computing an area density for each of the plurality of slabs based on an area of each of the plurality of slabs and a width of each of the plurality of slabs; computing a knee point area density based on a global area of the global histogram extending until the knee point and a global width of the global histogram until the knee point; and computing an area ratio for each of a plurality of tiles corresponding to the plurality of slabs based on the area density for each of the plurality of slabs and the knee point area density.

[0198] Aspect 20 may be combined with aspect 19, wherein assigning the slope to each of the plurality of slabs further includes: assigning the slope to each of the plurality of slabs based on a knee point slope associated with the knee point, a maximum area ratio from amongst the area ratio for each of the plurality of tiles, and a predefined slope.

[0199] Aspect 21 may be combined with aspect 20, wherein calculating the global LUT map for the frame further includes: computing a plurality of lines based on the slope assigned to each of the plurality of slabs; combining each line in the plurality of lines with at least one other line in the plurality of lines; and combining the initial line witha first line in the plurality of lines, wherein the global LUT map includes the line and the plurality of lines.

[0200] Aspect 22 may be combined with aspect 21, wherein calculating the global LUT map for the frame further includes: normalizing the global LUT map based on a normalization value.

[0201] Aspect 23 may be combined with any of aspects 21-22, wherein calculating the global LUT map for the frame further includes: determining that a second slope of a second line in the plurality of lines is less than the predefined slope; and adjusting, based on the determination, the second slope of the second line to be equal to the predefined slope.

[0202] Aspect 24 may be combined with any of aspects 15-23, wherein the global LUT map includes a piecewise linear global LUT map.

[0203] Aspect 25 may be combined with any of aspects 15-24, wherein each of the plurality of slabs corresponds to a tile in a plurality of tiles of the frame.

[0204] Aspect 26 may be combined with any of aspects 15-25, further including: adjusting a pixel value associated with the frame based on the global LUT map.

[0205] Aspect 27 may be combined with aspect 26, further including: calculating a backlight value based on the knee point and the global LUT map, wherein adjusting the pixel value includes adjusting the pixel value based on the calculated backlight value.

[0206] Aspect 28 may be combined with any of aspects 26-27, further including: receiving a backlight value; and modifying the global LUT map based on the backlight value, wherein adjusting the pixel value includes adjusting the pixel value based on the modified global LUT map.

[0207] Aspect 29 is an apparatus for display processing comprising a processor coupled to a memory and, based on information stored in the memory, the processor is configured to implement a method as in any of aspects 15-28.

[0208] Aspect 30 may be combined with aspect 29 and comprises that the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein the processor is configured to obtain the frame via at least one of the transceiver or the antenna.

[0209] Aspect 31 is an apparatus for display processing comprising means for implementing a method as in any of aspects 15-28.

[0210] Aspect 32 is a computer-readable medium (e.g., a non-transitory computer readable- medium) storing computer executable code, the computer executable code, when executed by a processor, causes the processor to implement a method as in any of aspects 15-28.

[0211] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. An apparatus for display processing, comprising: a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: determine a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles; apply a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles; adjust the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame; calculate a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles; and output an indication of the calculated LUT for each of the plurality of tiles.

2. The apparatus of claim 1, wherein to determine the cutoff value for each of the plurality of tiles of the frame based on the local histogram for each of the plurality of tiles, the processor is configured to: calculate a first cutoff value for a first tile based on a threshold percentage of pixels associated with a first local histogram for the first tile.

3. The apparatus of claim 1, wherein each LUT for each of the plurality of tiles is associated with a dynamic range compression that is different from other dynamic range compressions associated with other LUTs for other tiles of the plurality of tiles.

4. The apparatus of claim 1, wherein to adjust the cutoff value for each of the plurality of tiles based on the backlight value for the global histogram for the frame, the processor is configured to: perform a mean shift based on the backlight value.

5. The apparatus of claim 1, wherein the processor is further configured to:calculate the backlight value for the global histogram for the frame based on a content adaptive backlight (CABL) algorithm.

6. The apparatus of claim 1, wherein the cutoff values for each of the plurality of tiles is associated with a gain value.

7. The apparatus of claim 1, wherein the processor is further configured to: segment the frame into the plurality of tiles based on segmentation criteria.

8. The apparatus of claim 1, wherein a first tile and a second tile in the plurality of tiles are respectively associated with a first gain value and a second gain value that is greater than the first gain value, wherein to apply the spatial filter to the cutoff value for each of the plurality of tiles, the processor is configured to: reduce the second gain value based on the first gain value.

9. The apparatus of claim 1, wherein to output the indication of the calculated LUT for each of the plurality of tiles, the processor is configured to: store the indication of the calculated LUT for each of the plurality of tiles in at least one of the memory, a buffer, or a cache; or transmit the indication of the calculated LUT for each of the plurality of tiles.

10. The apparatus of claim 1, wherein the processor is further configured to: adjust a pixel value associated with the frame based on the calculated LUT.

11. The apparatus of claim 1, wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein the processor is further configured to receive the frame via at least one of the transceiver or the antenna.

12. An apparatus for display processing, comprising: a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to:calculate a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area; divide each of a plurality of local histograms for the frame into a plurality of slabs; assign a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs; calculate a global lookup table (LUT) map for the frame based on the first slope and the slope assigned to each of the plurality of slabs; and output an indication of the global LUT map for the frame.

13. The apparatus of claim 12, wherein to output the indication of the global LUT map for the frame, the processor is configured to: store the indication of the global LUT map for the frame in at least one of the memory, a buffer, or a cache; or transmit the indication of the global LUT map.

14. The apparatus of claim 12, wherein to calculate the knee point of the global histogram for the frame, the processor is configured to: compute the cumulative global histogram based on the global histogram; identify an x-coordinate of the knee point based on (1) at least one of the change in the first slope of the cumulative global histogram or the threshold area and (2) a threshold slope; and identify a y-coordinate of the knee point based on the x-coordinate of the knee point and the cumulative global histogram.

15. The apparatus of claim 14, wherein to calculate the global LUT map for the frame, the processor is configured to assign an initial line from an origin to a point defined by the x-coordinate of the knee point and the y-coordinate of the knee point.

16. The apparatus of claim 15, wherein to assign the slope to each of the plurality of slabs, the processor is configured to:compute an area density for each of the plurality of slabs based on an area of each of the plurality of slabs and a width of each of the plurality of slabs; compute a knee point area density based on a global area of the global histogram extending until the knee point and a global width of the global histogram until the knee point; and compute an area ratio for each of a plurality of tiles corresponding to the plurality of slabs based on the area density for each of the plurality of slabs and the knee point area density.

17. The apparatus of claim 16, wherein to assign the slope to each of the plurality of slabs, the processor is further configured to: assign the slope to each of the plurality of slabs based on a knee point slope associated with the knee point, a maximum area ratio from amongst the area ratio for each of the plurality of tiles, and a predefined slope.

18. The apparatus of claim 17, wherein to calculate the global LUT map for the frame, the processor is further configured to: compute a plurality of lines based on the slope assigned to each of the plurality of slabs; combine each line in the plurality of lines with at least one other line in the plurality of lines; and combine the initial line with a first line in the plurality of lines, wherein the global LUT map comprises the line and the plurality of lines.

19. The apparatus of claim 18, wherein to calculate the global LUT map for the frame, the processor is configured to: normalize the global LUT map based on a normalization value.

20. The apparatus of claim 18, wherein to calculate the global LUT map for the frame, the processor is configured to: determine that a second slope of a second line in the plurality of lines is less than the predefined slope; andadjust, based on the determination, the second slope of the second line to be equal to the predefined slope.

21. The apparatus of claim 12, wherein the global LUT map comprises a piecewise linear global LUT map.

22. The apparatus of claim 12, wherein each of the plurality of slabs corresponds to a tile in a plurality of tiles of the frame.

23. The apparatus of claim 12, wherein the processor is further configured to: adjust a pixel value associated with the frame based on the global LUT map.

24. The apparatus of claim 23, wherein the processor is further configured to: calculate a backlight value based on the knee point and the global LUT map, wherein to adjust the pixel value, the processor is configured to adjust the pixel value based on the calculated backlight value.

25. The apparatus of claim 23, wherein the processor is further configured to: receive a backlight value; and modify the global LUT map based on the backlight value, wherein to adjust the pixel value, the processor is configured to adjust the pixel value based on the modified global LUT map.

26. The apparatus of claim 12, wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor, wherein the processor is further configured to receive the frame via at least one of the transceiver or the antenna.

27. A method of display processing, comprising: determining a cutoff value for each of a plurality of tiles of a frame based on a local histogram for each of the plurality of tiles; applying a spatial filter to the cutoff value for each of the plurality of tiles to remove or mitigate spatial discontinuities across the plurality of tiles;adjusting the cutoff value for each of the plurality of tiles based on a backlight value for a global histogram for the frame; calculating a lookup table (LUT) for each of the plurality of tiles based on the adjusted cutoff value for each of the plurality of tiles; and outputting an indication of the calculated LUT for each of the plurality of tiles.

28. The method of claim 27, wherein determining the cutoff value for each of the plurality of tiles of the frame based on the local histogram for each of the plurality of tiles comprises: calculating a first cutoff value for a first tile based on a threshold percentage of pixels associated with a first local histogram for the first tile.

29. The method of claim 27, wherein each LUT for each of the plurality of tiles is associated with a dynamic range compression that is different from other dynamic range compressions associated with other LUTs for other tiles of the plurality of tiles.

30. A method of display processing, comprising: calculating a knee point of a global histogram for a frame based on at least one of a change in a first slope of a cumulative global histogram corresponding to the global histogram or a threshold area; dividing each of a plurality of local histograms for the frame into a plurality of slabs; assigning a slope to each of the plurality of slabs based on (1) the knee point and (2) an area corresponding to each of the plurality of slabs; calculating a global lookup table (LUT) map for the frame based on the first slope and the slope assigned to each of the plurality of slabs; and outputting an indication of the global LUT map for the frame.

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