Sense amplification circuit and control method therefor, and storage apparatus and electronic device

Abstract

The present application relates to the technical field of storage. Provided are a sense amplification circuit and a control method therefor, and a storage apparatus and an electronic device, which can amplify a voltage difference ΔV generated after a storage unit performs charge sharing on a bitline, thereby reducing the likelihood of stored data being mistakenly read from the storage unit. The sense amplification circuit comprises a sense amplifier, a pre-amplification circuit, a first switch circuit, a second switch circuit and an amplification input node, wherein the sense amplifier comprises a first input end, a second input end, a first output end and a second output end; the amplification input node is connected to a bitline by means of the pre-amplification circuit; the pre-amplification circuit can amplify a voltage difference generated on the bitline and output the amplified voltage difference to the amplification input node; the first switch circuit can control the connection and disconnection between the first input end and the amplification input node and the connection and disconnection between the second input end and the amplification input node; and the second switch circuit can control the connection and disconnection between the first input end and the first output end and the connection and disconnection between the second input end and the second output end.

Description

Sensitive amplifier circuit and control method thereof, storage device, and electronic device Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a sensitive amplifier circuit and a control method thereof, a storage device, and an electronic device. Background Art

[0002] A sense amplifier (SA) is a crucial component of a memory device. Its primary function is to sense and amplify small signals on the bitline (BL) to enable reading of data stored in the memory cell. The small signal on the bitline is the voltage difference ΔV generated by the memory cell sharing charge with the bitline (BL). If this voltage difference ΔV is greater than the voltage offset of the SA, the data stored in the memory cell is correctly read. If this voltage difference ΔV is less than the voltage offset of the SA, the data stored in the memory cell is incorrectly read.

[0003] As technology advances, the storage density of memory devices continues to increase, while the operating voltage decreases. Consequently, the voltage difference ΔV generated by charge sharing between the memory cell and the bit line (BL) also decreases. This increases the probability of erroneous reading of the stored data in the memory cell, which in turn reduces the success rate of the SA sensing amplification.

[0004] Summary of the Invention

[0005] The present application provides a sensitive amplifier circuit and a control method thereof, a storage device, and an electronic device, which can amplify the voltage difference ΔV generated on the bit line after charge sharing.

[0006] The present application provides a sensitive amplifier circuit, which includes a sensitive amplifier, a pre-amplifier circuit, a first switching circuit, a second switching circuit, and an amplifying input node. The sensitive amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The amplifying input node is connected to a bit line via a pre-amplifier circuit, which is capable of amplifying the voltage difference generated on the bit line and outputting it to the amplifying input node. The amplifying input node is also connected to a first input terminal and a second input terminal via a first switching circuit. The first switching circuit is capable of controlling the on / off connection between the first input terminal and the amplifying input node, as well as the on / off connection between the second input terminal and the amplifying input node. The second switching circuit is connected to the first input terminal, the second input terminal, the first output terminal, and the second output terminal. The second switching circuit is capable of controlling the on / off connection between the first input terminal and the first output terminal, as well as the on / off connection between the second input terminal and the second output terminal.

[0007] With the aforementioned sensitive amplifier circuit, the pre-amplifier circuit can control the voltage of the amplifier input node to be pulled to a first voltage and a second voltage before and after amplifying the voltage difference generated on the bit line. The voltage difference between the second voltage and the first voltage is equivalent to the amplified voltage difference, thereby amplifying the voltage difference on the bit line. Furthermore, the first and second voltages of the amplified input node are input to the first and second input terminals of the sense amplifier through different paths in a time-sharing manner via a first switching circuit. Under the control of a second switching circuit, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal. The sense amplifier performs a sensing operation based on the voltage difference between the first and second input terminals (i.e., the voltage difference between the second voltage and the first voltage), thereby completing the amplification and reading of stored data. In other words, with the sensitive amplifier circuit of the present application, the pre-amplifier circuit amplifies the voltage difference generated on the bit line, enabling the amplified voltage difference to be greater than the voltage deviation of the sense amplifier, thereby reducing the probability of erroneous reading of stored data and improving the sensing and amplification success rate of the sense amplifier.

[0008] In addition, for edge dummy bitlines, the sensitive amplifier circuit provided in the embodiments of the present application is used. By amplifying the precharge voltage on the bitline through the pre-amplifier circuit and using it as a reference voltage for the sensitive amplifier, there is no need for the bitline at the other end as a reference. In other words, the sensitive amplifier circuit can be used on a single end, thus eliminating the problem of reduced storage density due to edge dummy bitlines.

[0009] In some possible implementations, the pre-amplification circuit includes: a first transistor, a second transistor, an amplification unit, a switch control terminal, a pre-charge control terminal, a common voltage terminal, and a pre-amplification control terminal. The gate of the first transistor is connected to the switch control terminal, the first electrode of the first transistor is connected to the bit line, and the second electrode of the first transistor is connected to the amplification input node. The gate of the second transistor is connected to the pre-charge control terminal, the first electrode of the second transistor is connected to the common voltage terminal, and the second electrode of the second transistor is connected to the amplification input node. The amplification unit is connected to the bit line, the amplification input node, and the pre-amplification control terminal. Under the control of the pre-amplification control terminal, the amplification unit can adjust the voltage of the amplification input node according to the voltage on the bit line to amplify the voltage difference generated on the bit line.

[0010] In some possible implementations, the amplification unit includes a first switching transistor, a first amplifying transistor, and a first voltage terminal. The gate of the first switching transistor is connected to the pre-amplification control terminal, the first electrode of the first switching transistor is connected to the first voltage terminal, and the second electrode of the first switching transistor is connected to the first electrode of the first amplifying transistor. The gate of the first amplifying transistor is connected to a bit line, and the second electrode of the first amplifying transistor is connected to an amplification input node.

[0011] In some possible implementations, the first switch transistor and the first amplifying transistor are both PMOS transistors.

[0012] In some possible implementations, the first switch transistor and the first amplifying transistor are both NMOS transistors.

[0013] In some possible implementations, the amplifier unit further includes a second switching transistor, a second amplifier transistor, a second voltage terminal, and an inverting pre-amplification control terminal. The gate of the second switching transistor is connected to the inverting pre-amplification control terminal, the first electrode of the second switching transistor is connected to the second voltage terminal, and the second electrode of the second switching transistor is connected to the first electrode of the second amplifier transistor. The gate of the second amplifier transistor is connected to a bit line, and the second electrode of the second amplifier transistor is connected to an amplifier input node. The first switching transistor and the first amplifier transistor are both PMOS transistors. The second switching transistor and the second amplifier transistor are both NMOS transistors.

[0014] In some possible implementations, the pre-amplifier circuit further includes an adjustment input terminal. The pre-amplifier circuit is further configured to, before a voltage difference is generated on the bit line, adaptively adjust the pulse width of a pulse signal inputted to the pre-amplifier control terminal under the control of the adjustment input terminal to control the voltage of the amplifier input node to not exceed a set voltage, thereby ensuring that the operating region of the first amplifier transistor is located in a region with high amplification efficiency.

[0015] In some possible implementations, the pre-amplification circuit further includes a comparator, a NAND gate, an inverter, and a first reference voltage terminal. The first input of the comparator is connected to the first reference voltage terminal, the second input of the comparator is connected to the amplifier input node, and the output of the comparator is connected to the first input of the NAND gate. The voltage at the first reference voltage terminal is a set voltage. The second input of the NAND gate is connected to the adjustment input terminal, and the output of the NAND gate is connected to the pre-amplification control terminal. The input of the inverter is connected to the adjustment input terminal, and the output of the inverter is connected to the pre-charge control terminal.

[0016] In some possible implementations, the pre-amplification circuit further includes a first inverter, a second inverter, and a NAND gate. The input of the first inverter is connected to the amplifier input node, and the output of the first inverter is connected to the first input of the NAND gate; wherein the flip point of the first inverter is set to a set voltage. The second input of the NAND gate is connected to the amplifier input node, and the output of the NAND gate is connected to the pre-amplification control terminal. The input of the second inverter is connected to the amplifier input node, and the output of the second inverter is connected to the pre-charge control terminal.

[0017] In some possible implementations, the first switch circuit includes: a first switch connected between the amplifying input node and the first input terminal, and a second switch connected between the amplifying input node and the second input terminal.

[0018] In some possible implementations, the second switch circuit includes: a third switch and a fourth switch. The third switch is connected between the second input terminal and the second output terminal. The fourth switch is connected between the first input terminal and the first output terminal.

[0019] In some possible implementations, the sense amplifier further includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first power supply terminal, and a second power supply terminal. The first electrode of the first P-type transistor and the first electrode of the second P-type transistor are both connected to the first power supply terminal; the gate of the first P-type transistor is connected to the first input terminal, and the second electrode of the first P-type transistor is connected to the second output terminal. The gate of the second P-type transistor is connected to the second input terminal, and the second electrode of the second P-type transistor is connected to the first output terminal. The first electrode of the first N-type transistor and the first electrode of the second N-type transistor are both connected to the second power supply terminal. The gate of the first N-type transistor is connected to the first input terminal, and the second electrode of the first N-type transistor is connected to the second output terminal; the gate of the second N-type transistor is connected to the second input terminal, and the second electrode of the second N-type transistor is connected to the first output terminal.

[0020] The present application also provides a control method for a sensitive amplifier circuit as provided in any of the aforementioned possible implementations, the control method comprising: controlling the pre-amplifier circuit to precharge the bit line to a reference voltage and resetting the voltage of the amplifier input node. Controlling the pre-amplifier circuit to adjust the voltage of the amplifier input node to a first voltage based on the reference voltage on the bit line, and inputting the first voltage to the first input terminal under the control of a first switch circuit. Controlling the pre-amplifier circuit to reset the voltage of the amplifier input node. Controlling the pre-amplifier circuit to amplify the voltage difference generated on the bit line to adjust the voltage of the amplifier input node to a second voltage; and controlling the first switch circuit to input the second voltage to the second input terminal. Controlling the second switch circuit to connect the first input terminal to the first output terminal and the second input terminal to the second output terminal, thereby starting the operation of the sensitive amplifier.

[0021] The present application also provides a storage device, which includes at least one storage array and a sensitive amplifier circuit provided in any of the possible implementation methods described above, wherein a plurality of storage cells are provided in the storage array; the sensitive amplifier circuit is connected to the plurality of storage cells via bit lines.

[0022] The present application also provides an electronic device, which includes a controller and a storage device provided in any of the possible implementation methods described above, wherein the controller is electrically connected to the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic diagram of a sensitive amplifier circuit provided in an embodiment of the present application;

[0024] FIG2 is a schematic diagram showing the connection between a sense amplifier (SA) and a memory array (MAT) in a memory device provided in the related art of this application;

[0025] FIG3 is a circuit diagram of a sense amplifier (SA) provided in the related art of this application;

[0026] FIG4 is a circuit diagram of a pre-amplifier circuit in a sensitive amplifier circuit provided in an embodiment of the present application;

[0027] FIG5 is a circuit diagram of a pre-amplifier circuit in a sensitive amplifier circuit according to an embodiment of the present application;

[0028] FIG6 is a circuit diagram of a pre-amplifier circuit in a sensitive amplifier circuit provided in an embodiment of the present application;

[0029] FIG7 is a circuit diagram of a pre-amplifier circuit in a sensitive amplifier circuit according to an embodiment of the present application;

[0030] FIG8 is an operation waveform diagram of the pre-amplifier circuit in FIG7 ;

[0031] FIG9 is a circuit diagram of a pre-amplifier circuit in a sensitive amplifier circuit according to an embodiment of the present application;

[0032] FIG10 is a schematic diagram of a sensitive amplifier provided in an embodiment of the present application;

[0033] FIG11 is a circuit connection diagram of a sensitive amplifier circuit provided in an embodiment of the present application;

[0034] FIG12 is a flow chart of a control method for a sensitive amplifier circuit according to an embodiment of the present application;

[0035] FIG13 is an operating waveform diagram of a sensitive amplifier circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0038] An embodiment of the present application provides an electronic device, which may be any electronic product provided with a storage device, such as consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0039] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0040] Of course, in addition to including a storage device, the electronic device may also be provided with other devices as needed. For example, based on actual needs, the electronic device may be provided with a controller (or control circuit) connected to the storage device to control the storage device through the controller.

[0041] The electronic device provided in the embodiment of the present application adopts a novel storage device, which adopts a sensitive amplifier circuit with a novel structure. The sensitive amplifier circuit is connected to the storage unit in the storage device through a bit line. The use of the sensitive amplifier circuit with the novel structure can reduce the probability of erroneous reading of the data stored in the storage unit, and can also improve the storage density of the storage device.

[0042] The present application does not limit the configuration of the above-mentioned storage device. For example, the storage device may be a ferroelectric random access memory (FERAM), a dynamic random access memory (DRAM), or the like.

[0043] The novel sensitive amplifier circuit provided in the embodiments of the present application is additionally provided with a pre-amplifier circuit and a switch circuit on the basis of a conventional sense amplifier (SA). Therefore, when reading the stored data in the memory cell, the voltage difference ΔV generated on the bit line is amplified by the pre-amplifier circuit and the switch circuit and written into the sense amplifier (SA). The amplified voltage difference ΔV can be made greater than the voltage offset of the sense amplifier (SA), thereby reducing the probability of the stored data being erroneously read and improving the sensing amplification success rate of the sense amplifier (SA).

[0044] The novel sensitive amplifier circuit provided in the embodiments of the present application is described in detail below.

[0045] Schematically, as shown in FIG1 , an embodiment of the present application provides a sensitive amplifier circuit, which includes: a sensitive amplifier SA, a pre-amplifier circuit 100, a first switch circuit 201, a second switch circuit 202, and an amplifier input node SAIN. The sensitive amplifier SA includes a first input terminal GB, a second input terminal GT, a first output terminal DB, and a second output terminal DT.

[0046] As shown in FIG1 , the amplified input node SAIN is connected to the bit line BL via a pre-amplifier circuit 100. The bit line BL is then connected to a memory cell in a memory array (not shown in FIG1 ). When reading data stored in a memory cell, the reference voltage precharged to the bit line BL is first pulled to a first voltage via the pre-amplifier circuit 100. Then, when the memory cell and the bit line BL share charge, the resulting voltage difference ΔV is amplified by the pre-amplifier circuit 100, pulling the voltage of the amplified input node SAIN to a second voltage. In this case, the voltage difference between the second voltage and the first voltage corresponds to the amplified voltage difference ΔV.

[0047] Continuing with FIG1 , the amplifier input node SAIN is further connected to the first input terminal GB and the second input terminal GT via a first switch circuit 201. The first switch circuit 201 controls the connection between the first input terminal GB and the amplifier input node SAIN, as well as the connection between the second input terminal GT and the amplifier input node SAIN. A second switch circuit 202 is connected to the first input terminal GB, the second input terminal GT, the first output terminal DB, and the second output terminal DT. The second switch circuit 202 controls the connection between the first input terminal GB and the first output terminal DB, as well as the connection between the second input terminal GT and the second output terminal DT.

[0048] In this case, before and after amplifying the voltage difference ΔV, under the control of the first switch circuit 201, the two voltages generated at the amplified input node SAIN (i.e., the aforementioned first voltage and second voltage, i.e., the amplified voltage difference ΔV) can be input to the first input terminal GB and the second input terminal GT through different paths in a time-sharing manner. Furthermore, under the control of the second switch circuit 202, the first input terminal GB is connected to the first output terminal DB, and the second input terminal GT is connected to the second output terminal DT. In this way, the sense amplifier SA begins operating based on the voltage difference between the first input terminal GB and the second input terminal GT (i.e., the voltage difference between the second voltage and the first voltage), performing a sensing operation.

[0049] That is, using the sense amplifier circuit provided in the embodiments of the present application, the pre-amplifier circuit 100 controls the voltage of the amplifier input node SAIN to be pulled to a first voltage and a second voltage, respectively, before and after amplifying the voltage difference ΔV generated on the bit line BL. The voltage difference between the second voltage and the first voltage is equivalent to the amplified voltage difference ΔV, thereby amplifying the voltage difference ΔV on the bit line BL. Furthermore, the first and second voltages of the amplifier input node SAIN are input to the first input terminal GB and the second input terminal GT of the sense amplifier SA through different paths in a time-sharing manner via the first switch circuit 201. Under the control of the second switch circuit 202, the first input terminal GB is connected to the first output terminal DB, and the second input terminal GT is connected to the second output terminal DT, thereby completing the amplification and reading of the stored data through the sense amplifier SA.

[0050] In summary, by using the sensitive amplifier circuit provided in the embodiment of the present application, the voltage difference ΔV generated on the bit line BL is amplified by the pre-amplifier circuit 100, so that the amplified voltage difference ΔV is greater than the voltage offset of the sense amplifier (SA), thereby reducing the probability of stored data being erroneously read, thereby improving the sensing amplification success rate of the sense amplifier (SA).

[0051] In addition, using the sensitive amplifier circuit provided in the embodiment of the present application, the pre-charge voltage on the bit line BL is amplified by the pre-amplifier circuit 100 and used as the reference voltage for the sense amplifier SA. The bit line at the other end does not need to be used as a reference. That is, the sensitive amplifier circuit can be used in a single-ended manner, thereby avoiding the problem of reduced storage density caused by edge dummy bitlines.

[0052] The following briefly describes the configuration of the edge dummy bitline.

[0053] Figure 2 is a schematic diagram of the connection between a sense amplifier (SA) and a memory array (MAT) in a FERAM / DRAM provided in the related art of the present application. Figure 3 is a schematic diagram of the circuit connection of a sense amplifier (SA) provided in the related art of the present application.

[0054] As shown in Figure 2, in some FERAM / DRAMs, the memory array (MAT) employs an open bitline layout. The bitlines BL in odd and even rows of the memory array (MAT) are connected to sense amplifiers (SA) from either side. Furthermore, in two adjacent memory arrays, the bitlines BL in odd rows of one memory array (MAT2) and the bitlines BL in even rows of the other memory array (MAT3) are connected to the same sense amplifier (SA). In this case, as shown in Figure 3, when reading stored data, after the bitline BLL on one side of the sense amplifier (SA) is selected, the bitline BLR on the other side of the sense amplifier (SA) serves as a reference, and the corresponding stored data is read by comparing the two sides. This means that the open bitline layout results in the memory arrays (MAT1 and MATN) on both sides having no reference bitlines BL to use.

[0055] Because existing sense amplifiers (SAs) must use the bit line BLR as a reference when reading data stored on the bit line BLL, the bit lines BL' in the memory arrays on both sides (MAT1 and MATN) have no reference bit lines to use. These bit lines BL' are then abandoned and referred to as edge dummy bit lines. The memory cells connected to these edge dummy bit lines cannot be properly read or written, resulting in memory cell redundancy and a reduction in the unit storage density of FERAM / DRAM.

[0056] In contrast, the novel sensitive amplifier circuit provided by the embodiment of the present application can not only meet the requirement that the left and right bit lines (BLL and BLR) can share a sense amplifier (SA), but also can use the sense amplifier (SA) on a single end. In this way, the use of the sensitive amplifier circuit of the present application can not only meet the requirement that the two bit lines in the middle area of ​​the memory array (MAT1 and MATN) share a sense amplifier (SA), thereby saving area; at the same time, the edge bit line BL' can use the sense amplifier (SA) on a single end, without the need for the bit line at the other end as a reference, thereby avoiding the disadvantage of the memory cell connected to the edge dummy bit line (edge ​​dummy bitline) in the prior art being unable to read and write normally, further improving the storage density of the memory device.

[0057] The present application does not limit the specific circuit structures of the first switch circuit 201, the second switch circuit 202, the pre-amplifier circuit 100, and the sense amplifier SA in the above-mentioned sense amplifier circuit, and they can be configured as needed in practice.

[0058] Schematically, as shown in FIG1 , in some possible implementations, the first switch circuit 201 may include a first switch K1 and a second switch K2. The first switch K1 is connected to the path between the amplifier input node SAIN and the first input terminal GB, and the first switch K2 can control the connection between the amplifier input node SAIN and the first input terminal GB. The second switch K2 is connected to the path between the amplifier input node SAIN and the second input terminal GT, and the second switch K2 can control the connection between the amplifier input node SAIN and the second input terminal GT.

[0059] Schematically, as shown in FIG1 , in some possible implementations, the second switch circuit 202 may include a third switch K3 and a fourth switch K4. The third switch K3 is connected to the path between the second input terminal GT and the second output terminal DT, and the third switch K3 can control the connection between the second input terminal GT and the second output terminal DT. The fourth switch K4 is connected to the path between the first input terminal GB and the first output terminal DB, and the fourth switch K4 can control the connection between the first input terminal GB and the first output terminal DB.

[0060] The first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 may be PMOS transistors, NMOS transistors or CMOS transmission gates, and this application does not impose any restrictions thereto. In practice, the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 may be configured as needed.

[0061] For example, in some possible implementations, as shown in FIG1 , the first switch K1 and the second switch K2 can both be NMOS transistors. In this case, the gate of the first switch K1 is connected to the first control terminal IC0, the source (or drain) is connected to the amplifier input node SAIN, and the drain (or source) is connected to the first input terminal GB. The gate of the second switch K2 is connected to the second control terminal IC1, the source (or drain) is connected to the amplifier input node SAIN, and the drain (or source) is connected to the second input terminal GT. The following embodiments are described using this example.

[0062] For another example, in some possible implementations, as shown in FIG1 , the third switch K3 and the fourth switch K4 can both be NMOS transistors. In this case, the gate of the third switch K3 is connected to the third control terminal ISO, the source (or drain) is connected to the second input terminal GT, and the drain (or source) is connected to the second output terminal DT. The gate of the fourth switch K4 is connected to the third control terminal ISO, the source (or drain) is connected to the first input terminal GB, and the drain (or source) is connected to the first output terminal DB. The following embodiments are all described using this example.

[0063] It should be noted that the source and drain of all MOS transistors involved in the embodiments of this application can have a symmetrical structure, that is, the source and drain can be not clearly distinguished, and the connection method of the source and drain can be interchanged accordingly. In this application, one of the source and drain can be represented as the first electrode, and the other can be represented as the second electrode.

[0064] For the configuration of the above-mentioned pre-amplifier circuit 100:

[0065] As shown in FIG4 , in some possible implementations, the pre-amplifier circuit 100 may include: a first transistor M1, a second transistor M2, an amplifier unit 101, a switch control terminal SWITCH, a precharge control terminal PCH, a common voltage terminal COM, and a pre-amplifier control terminal PRESA. The amplifier unit 101 is connected to a bit line BL, an amplifier input node SAIN, and the pre-amplifier control terminal PRESA.

[0066] The gate of the first transistor M1 is connected to the switch control terminal SWITCH, the source (or drain) of the first transistor M1 is connected to the bit line, and the drain (or source) of the first transistor M1 is connected to the amplification input node SAIN.

[0067] The gate of the second transistor M2 is connected to the precharge control terminal PCH, the source (or drain) of the second transistor M2 is connected to the common voltage terminal COM, and the drain (or source) of the second transistor M2 is connected to the amplification input node SAIN.

[0068] In this case, under the control of the precharge control terminal PCH and the switch control terminal SWITCH, the second transistor M2 and the first transistor M1 are turned on, and the bit line BL can be precharged through the common voltage terminal COM via the amplified input node SAIN.

[0069] The first transistor M1 and the second transistor M2 can be NMOS transistors or PMOS transistors, which is not limited in this application and can be set as needed. FIG4 is only a schematic illustration of the example in which the first transistor M1 and the second transistor M2 are both NMOS transistors.

[0070] In the above pre-amplifier circuit 100 , the amplifier unit 101 can adjust the voltage of the amplification input node SAIN according to the voltage on the bit line BL under the control of the pre-amplifier control terminal PRESA, thereby amplifying the voltage difference ΔV generated on the bit line BL.

[0071] The present application does not limit the specific circuit of the amplifier unit 101 , as long as it can amplify the voltage difference ΔV generated on the bit line BL, and can be configured as needed.

[0072] Circuit structure of amplifier unit 101

[0073] As shown in Figure 4, in some possible implementations, the amplifying unit 101 may include a first switching transistor PREMOS1, a first amplifying transistor PREMOS2, and a first voltage terminal VPA. The first switching transistor PREMOS1 and the first amplifying transistor PREMOS2 may both be PMOS transistors.

[0074] The gate of the first switching transistor PREMOS1 is connected to the pre-amplification control terminal PRESA, the source (or drain) of the first switching transistor PREMOS1 is connected to the first voltage terminal VPA, and the drain (or source) of the first switching transistor PREMOS1 is connected to the source (or drain) of the first amplification transistor PREMOS2; the gate of the first amplification transistor PREMOS2 is connected to the bit line BL, and the drain (or source) of the first amplification transistor PREMOS2 is connected to the amplification input node SAIN.

[0075] In this circuit structure 1, a pulse signal inputted from the pre-amplification control terminal PRESA controls the first switching transistor PREMOS1 to turn on, connecting the first voltage terminal VPA to the source of the first amplifier transistor PREMOS2. In this case, the voltage on the bit line BL directly determines the voltage at the amplifier input node SAIN. Consequently, when reading data from a memory cell, the voltage difference ΔV generated on the bit line BL is amplified by the first amplifier transistor PREMOS2. At this point, the voltage at the amplifier input node SAIN is adjusted from the first voltage to a second voltage. The voltage difference between the second voltage and the first voltage corresponds to the amplified voltage difference ΔV.

[0076] Circuit structure 2 of amplifier unit 101

[0077] 5 , in some possible implementations, the amplifying unit 101 may include a first switching transistor PREMOS1, a first amplifying transistor PREMOS2, and a first voltage terminal VPA. The first switching transistor PREMOS1 and the first amplifying transistor PREMOS2 may both be NMOS transistors.

[0078] The gate of the first switching transistor PREMOS1 is connected to the pre-amplification control terminal PRESA, the source (or drain) of the first switching transistor is connected to the first voltage terminal VPA, and the drain (or source) of the first switching transistor PREMOS1 is connected to the source (or drain) of the first amplification transistor PREMOS2; the gate of the first amplification transistor PREMOS2 is connected to the bit line BL, and the drain (or source) of the first amplification transistor PREMOS2 is connected to the amplification input node SAIN.

[0079] The principle of amplifying the voltage difference ΔV in the second circuit structure is similar to that of the first circuit structure, and will not be described in detail here.

[0080] Circuit structure of amplifier unit 101

[0081] As shown in FIG6 , in some possible implementations, the amplifier unit 101 may include a first switching transistor PREMOS1, a first amplifying transistor PREMOS2, a second switching transistor PREMOS1′, a second amplifying transistor PREMOS2′, a first voltage terminal VPA, and a second voltage terminal VGPA. The first switching transistor PREMOS1 and the first amplifying transistor PREMOS2 may be PMOS transistors, and the second switching transistor PREMOS1′ and the second amplifying transistor PREMOS2′ may be NMOS transistors.

[0082] The gate of the first switching transistor PREMOS1 is connected to the pre-amplification control terminal PRESA, the source (or drain) of the first switching transistor is connected to the first voltage terminal VPA, and the drain (or source) of the first switching transistor PREMOS1 is connected to the source (or drain) of the first amplification transistor PREMOS2; the gate of the first amplification transistor PREMOS2 is connected to the bit line BL, and the drain (or source) of the first amplification transistor PREMOS2 is connected to the amplification input node SAIN.

[0083] The gate of the second switching transistor PREMOS1' is connected to the inverting pre-amplification control terminal PRESA_N, the source (or drain) of the second switching transistor PREMOS1' is connected to the second voltage terminal GVPA, and the drain (or source) of the second switching transistor PREMOS1' is connected to the source (or drain) of the second amplifier transistor PREMOS2'; the gate of the second amplifier transistor PREMOS2' is connected to the bit line BL, and the drain (or source) of the second amplifier transistor PREMOS2' is connected to the amplifier input node SAIN.

[0084] The first amplifying transistor PREMOS2 and the second amplifying transistor PREMOS2' can be a combination of an NMOS transistor and a PMOS transistor to form an inverter. The signals of the pre-amplifying control terminal PRESA and the inverting pre-amplifying control terminal PRESA_N can be inverted signals of each other.

[0085] The amplification principle of the three pairs of voltage differences ΔV in this circuit structure is similar to that of the aforementioned circuit structure 1 and will not be repeated here.

[0086] It should be noted that, according to actual needs, the MOS transistors (PREMOS1, PREMOS2, PREMOS1', PREMOS2') in the aforementioned amplification unit 101 can be N-type MOS transistors or P-type MOS transistors. This application does not impose any restrictions on this, and it can be set according to actual needs.

[0087] In addition, as shown in the amplifier unit 101 shown in Figures 4, 5, and 6, before a voltage difference ΔV is generated on the bit line BL, the bit line BL is precharged to a reference voltage by turning on the first transistor M1 and the second transistor M2. Under the control of this reference voltage, the first amplifier transistor PREMOS2 pulls the amplifier input node SAIN to a first voltage. This first voltage is used as a reference voltage for the sense amplifier SA to amplify and read the stored data. In actual operation, it is necessary to ensure that the first voltage of the amplifier input node SAIN is adjusted by the first amplifier transistor PREMOS2 under the control of this reference voltage and does not exceed a specified voltage to ensure that the operating region of the first amplifier transistor PREMOS2 is located in a region with high amplification efficiency. However, due to process corners and process variations during the manufacturing process of the first amplifier transistor PREMOS2, there is a risk that the first voltage may exceed the specified voltage.

[0088] On this basis, by controlling the pulse width of the pulse signal input to the pre-amplification control terminal PRESA, the duration of the connection between the source of the first amplifier transistor PREMOS2 and the first voltage terminal VPA is controlled, thereby indirectly controlling the amplifier input node SAIN. In other words, by controlling the pulse width of the pulse signal input to the pre-amplification control terminal PRESA, the first voltage of the amplifier input node SAIN can be controlled to not exceed a specified voltage.

[0089] Based on this, with reference to Figures 7 and 8, an embodiment of the present application further provides a novel pre-amplifier circuit 100. The pre-amplifier circuit 100 may be based on the pre-amplifier circuits illustrated in Figures 4, 5, and 6 above, and further includes an adaptive pulse width modulation unit 102. The adaptive pulse width modulation unit 102 can adaptively adjust the pulse width of the pulse signal input to the pre-amplifier control terminal PRESA when precharging the bit line BL before a voltage difference ΔV is generated on the bit line BL, so as to control the first voltage of the amplifier input node SAIN not to exceed a specified voltage.

[0090] The present application does not limit the specific circuit structure of the adaptive pulse width modulation unit 102, as long as it can meet the requirements of adaptively adjusting the pulse width of the pulse signal input by the pre-amplification control terminal PRESA. In practice, it can be configured as needed. Two different circuit structures are provided below for the adaptive pulse width modulation unit 102.

[0091] Circuit structure of adaptive pulse width modulation unit 102

[0092] As shown in FIG7 , in some possible implementations, the adaptive pulse width modulation unit 102 may include a comparator, a NAND gate, an inverter, a first reference voltage terminal Vref, and an adjustment input terminal IN. The first input terminal of the comparator is connected to the first reference voltage terminal Vref1, the second input terminal of the comparator is connected to the amplification input node SAIN, and the output terminal (FEEDBACK) of the comparator is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the adjustment input terminal IN, and the output terminal of the NAND gate is connected to the pre-amplification control terminal PRESA. The input terminal of the inverter is connected to the adjustment input terminal IN, and the output terminal of the inverter is connected to the pre-charge control terminal PCH. The amplification input node SAIN in FIG7 is correspondingly connected to the sense amplifier SA (see FIG1 ).

[0093] The voltage of the first reference voltage terminal Vref1 is a set voltage. The set voltage is related to the working condition of the sense amplifier SA. The set voltage should ensure that the sense amplifier SA can operate at a stable working point.

[0094] FIG. 8 is an operation waveform diagram of the adaptive pulse width modulation unit 102 in FIG. 7 .

[0095] The working principle of the adaptive pulse width modulation unit 102 may be as follows.

[0096] Schematically, referring to Figures 7 and 8 , when the signal at the adjustment input terminal IN is pulled up, since the initial state of the comparator's output terminal (FEEDBACK) is 1, the output terminal of the NAND gate outputs a low-level pulse signal to the pre-amplification control terminal PRESA. Simultaneously, the first amplifier transistor PREMOS2 turns on, and the first voltage terminal VPA begins charging the amplifier input node SAIN. When the voltage at the amplifier input node SAIN exceeds the set voltage of the first reference voltage terminal Vref, the comparator outputs a 0 to the input terminal of the NAND gate. At this point, the output signal of the NAND gate pulls high, and the pulse received by the pre-amplification control terminal PRESA ends. Finally, when the signal at the adjustment input terminal IN pulls low, the pre-charge signal at the pre-charge control terminal PCH is turned on via the inverter, pre-charging the amplifier input node SAIN back to 0.

[0097] Circuit structure 2 of the adaptive pulse width modulation unit 102

[0098] As shown in FIG9 , in some possible implementations, the adaptive pulse width modulation unit 102 may include a first inverter A1, a second inverter A2, and a NAND gate. The input of the first inverter A1 is connected to the amplifier input node SAIN, and the output of the first inverter A1 is connected to the first input of the NAND gate. The second input of the NAND gate is connected to the amplifier input node SAIN, and the output of the NAND gate is connected to the pre-amplification control terminal PRESA. The input of the second inverter A2 is connected to the amplifier input node SAIN, and the output of the second inverter A2 is connected to the pre-charge control terminal PCH. In FIG9 , the amplifier input node SAIN is correspondingly connected to the sense amplifier SA (see FIG1 ).

[0099] The flip point (flip voltage) of the first inverter is related to the working condition of the sense amplifier SA. The setting voltage of the flip point should ensure that the sense amplifier SA can operate at a stable working point.

[0100] The pulse width modulation process of the adaptive pulse width modulation unit 102 in FIG9 is similar to that in FIG8 . For details, please refer to the corresponding description in FIG8 , which will not be repeated here.

[0101] It should be noted here that the pre-amplifier circuit 100 in Figures 7 and 9 is only illustrated by taking the amplifying unit 101 shown in Figure 4 as an example, and this application does not impose any restrictions on this. When the pre-amplifier circuit 100 adopts the amplifying unit 101 shown in Figures 5 and 6, the above-mentioned two adaptive pulse width adjustment units 102 can also be adopted. This application does not impose any restrictions on this, and in practice it can be set as needed.

[0102] In addition, the present application does not limit the specific circuit structure of the sense amplifier SA.

[0103] Schematically, referring to FIG. 1 , in some possible implementations, the core circuit of the sense amplifier SA includes four MOS transistors (a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2), as well as a first power supply terminal SAP and a second power supply terminal SAN. The source (or drain) of the first PMOS transistor P1 and the source (or drain) of the second PMOS transistor P2 are both connected to the first power supply terminal SAP. The gate of the first PMOS transistor P1 is connected to the first input terminal GB, and the drain (or source) of the first PMOS transistor P1 is connected to the second output terminal DT. The gate of the second PMOS transistor P2 is connected to the second input terminal GT, and the drain (or source) of the second PMOS transistor P2 is connected to the first output terminal DB. The source (or drain) of the first NMOS transistor N1 and the source (or drain) of the second NMOS transistor N2 are both connected to the second power supply terminal SAN. The gate of the first NMOS transistor N1 is connected to the first input terminal GB, and the drain (or source) of the first NMOS transistor N1 is connected to the second output terminal DT. The gate of the second NMOS transistor N2 is connected to the second input terminal GT, and the drain (or source) of the second NMOS transistor N2 is connected to the first output terminal DB.

[0104] Of course, the sensitive amplifier SA can be provided with other MOS tubes based on the four MOS tubes (P1, P2, N1, N2) of the core circuit according to actual functional requirements.

[0105] Schematically, as shown in FIG10 , to reduce the voltage offset of the sense amplifier SA, in some possible implementations, the sense amplifier SA can, in addition to the four MOS transistors (P1, P2, N1, N2) of the core circuit, further include: a third NMOS transistor N3, a fourth NMOS transistor N4, and a fourth control terminal OC. The third NMOS transistor N3 has a gate connected to the fourth control terminal OC, a source (or drain) connected to the first input terminal GB, and a drain (or source) connected to the second output terminal DT. The fourth NMOS transistor N4 has a gate connected to the fourth control terminal OC, a source (or drain) connected to the second input terminal GT, and a drain (or source) connected to the first output terminal DB.

[0106] In addition, for the sensitive amplifier circuit provided in an embodiment of the present application, as shown in FIG11 , when the left and right bit lines (BLL and BLR) share one sensitive amplifier (SA), the amplification input node SAIN is connected to the left bit line BLL through a pre-amplification circuit 100 on the left, and the amplification input node SAIN can be connected to the right bit line BLR through another pre-amplification circuit 100 on the right.

[0107] Of course, in some embodiments, in order to reduce the occupied area of ​​the sensitive amplifier circuit in the storage device, as shown in FIG11 , it is not necessary to separately set the first switch circuit 201 and the second switch circuit 202 for the left and right bit lines (BLL and BLR), that is, the left and right bit lines (BLL and BLR) can share the first switch circuit 201 and the second switch circuit 202.

[0108] Similarly, in practice, different sensitive amplifier circuits can be configured in the storage device to share some transistors as needed to simplify the circuit and reduce the area occupied by the sensitive amplifier circuit. For example, referring to FIG11 , in some possible implementations, different sensitive amplifier circuits can be configured to share a first switching transistor PREMOS1.

[0109] Figure 12 is a flow chart of a control method for a sensitive amplifier circuit according to an embodiment of the present application. Figure 13 is an operation waveform diagram of a sensitive amplifier circuit according to an embodiment of the present application.

[0110] Schematically, an embodiment of the present application provides a control method for a sensitive amplifier circuit. Referring to Figures 12 and 13, the control method may include a first stage T0, a second stage T1, a third stage T2, a fourth stage T3, and a fifth stage T4.

[0111] The control methods for each stage can be as follows:

[0112] The first stage T0: referring to FIG. 1 , the pre-amplifier circuit 100 is controlled to precharge the bit line BL to a reference voltage and reset the voltage of the amplifier input node SAIN.

[0113] Schematically, referring to FIG. 1 and FIG. 12 , the first stage T0 may include: inputting a high level to the switch control terminal SWITCH and the precharge control terminal PCH, turning on the first transistor M1 and the second transistor M2, and precharging the bit line BL to the reference voltage VREF via the common voltage terminal COM. Next, turning off the first transistor M1 and keeping the second transistor M2 on, precharging the voltage of the amplifier input node SAIN to 0 via the common voltage terminal COM (i.e., resetting the amplifier input node SAIN).

[0114] Second stage T1: Referring to FIG. 1 , the pre-amplifier circuit 100 is controlled to adjust the voltage of the amplifier input node SAIN to the first voltage V1 according to the reference voltage VREF on the bit line BL, and inputs the first voltage V1 to the first input terminal GB under the control of the first switch circuit 201 .

[0115] Schematically, referring to Figures 1 and 12 , the second phase T1 may include: low-level inputs to the switch control terminal SWITCH and the precharge control terminal PCH, turning off the first transistor M1 and the second transistor M2. A low-level pulse signal is input to the pre-amplification control terminal PRESA, turning on the first switching transistor PREMOS1. In this case, the reference voltage VREF on the bit line BL controls the first amplifier transistor PREMOS2 to enter the linear region, precharging the amplifier input node SAIN to the first voltage V1. Simultaneously, under the control of the first control terminal IC0, the first switch K1 opens, and the first voltage V1 of the amplifier input node SAIN is input to the first input terminal GB.

[0116] The third stage T2: referring to FIG. 1 , the pre-amplifier circuit 100 is controlled to reset the voltage of the amplified input node SAIN.

[0117] 1 and 12 , the third stage T2 may include: inputting a high level to the pre-charge control terminal PCH, turning on the second transistor M2 again, and pre-charging the voltage of the amplifying input node SAIN to 0 V again through the common voltage terminal COM (i.e., resetting the amplifying input node SAIN again).

[0118] Fourth stage T3: Referring to FIG. 1 , the pre-amplifier circuit 100 is controlled to amplify the voltage difference ΔV generated on the bit line BL, and the voltage of the amplified input node SAIN is adjusted to the second voltage V2; and the first switch circuit 201 is controlled to input the second voltage V2 to the second input terminal GT.

[0119] Schematically, referring to Figures 1 and 12 , the fourth stage T3 may include: opening a selected memory cell via the word line WL, performing charge sharing with the bit line BL, generating a voltage difference ΔV on the bit line BL, and then the voltage on the bit line BL becomes VREF ± ΔV. A low-level pulse signal is input to the pre-amplification control terminal PRESA, turning on the first switching transistor PREMOS1. In this case, the voltage on the bit line BL (VREF ± ΔV) controls the first amplifier transistor PREMOS2 to enter the linear region, precharging the amplifier input node SAIN to the second voltage V2. Simultaneously, under the control of the second control terminal IC1, the second switch K2 is opened, and the second voltage V2 on the amplifier input node SAIN is input to the second input terminal GT.

[0120] In order to ensure that the voltage difference ΔV generated on the bit line BL can be accurately amplified to the first input terminal GB and the second input terminal GT, in some possible implementation methods, the pulse width (second pulse width) of the low-level pulse signal input to the pre-amplification control terminal PRESA in the fourth stage T3 can be set to be the same as the pulse width (first pulse width) of the low-level pulse signal input to the pre-amplification control terminal PRESA in the second stage T1, that is, the second pulse width is the same as the first pulse width.

[0121] As mentioned above, the first pulse width can be adjusted by providing an adaptive pulse width adjustment unit 102 in the pre-amplifier circuit 100 , and the second pulse width can be ensured to be the same as the first pulse width by using other circuits.

[0122] Fifth stage T4: referring to FIG. 1 , the second switch circuit 202 is controlled to output the first voltage V1 of the first input terminal GB to the first output terminal DB, and to input the second voltage V2 of the second input terminal GT to the second output terminal DT.

[0123] Schematically, referring to FIG. 1 and FIG. 12 , the fifth stage T4 may include: pulling down the voltage of the second power supply terminal SAN (e.g., from 1V to 0V), maintaining the first power supply terminal SAP at 1V. A high level is input to the third control terminal ISO, turning on the third switch K3 (NMOS transistor) and the fourth switch K4 (NMOS transistor), connecting the first input terminal GB to the first output terminal DB, and connecting the second input terminal GT to the second output terminal DT. The sense amplifier SA begins operating to perform a sensing operation.

[0124] Of course, in other possible implementations, the first power supply terminal SAP and the second power supply terminal SAN are maintained at the reference voltage VREF before the fifth stage T4. In the fifth stage T4, the voltage of the second power supply terminal SAN can be pulled down from VREF to 0v; and the first power supply terminal SAP can be pulled up from VREF to 1v.

[0125] After the fifth stage T4, the sixth stage T5 may be included, and subsequent write operations or write-back operations may be performed through the sixth stage T5, which can be performed as needed, and this application does not impose any restrictions on this.

[0126] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A sensitive amplifier circuit, characterized in that: It includes a sensitive amplifier, a pre-amplification circuit, a first switch circuit, a second switch circuit, and an amplification input node; The amplification input node is connected to a bit line through the pre-amplification circuit; The pre-amplification circuit is configured to: amplify the voltage difference generated on the bit line and output it to the amplification input node; The sensitive amplifier comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal; The amplifying input node is also connected to the first input terminal and the second input terminal through the first switching circuit; the first switching circuit is configured to: control the connection and disconnection between the first input terminal and the amplifying input node and the connection and disconnection between the second input terminal and the amplifying input node; The second switch circuit is connected to the first input terminal, the second input terminal, the first output terminal, and the second output terminal; the second switch circuit is configured to control the on-off between the first input terminal and the first output terminal and the on-off between the second input terminal and the second output terminal.

2. The sensitive amplifier circuit according to claim 1, characterized in that: The pre-amplification circuit comprises: a first transistor, a second transistor, an amplification unit, a switch control terminal, a pre-charging control terminal, a common voltage terminal, and a pre-amplification control terminal; The gate of the first transistor is connected to the switch control terminal, the first electrode of the first transistor is connected to the bit line, and the second electrode of the first transistor is connected to the amplification input node; The gate of the second transistor is connected to the precharge control terminal, the first electrode of the second transistor is connected to the common voltage terminal, and the second electrode of the second transistor is connected to the amplification input node; The amplification unit is connected to the bit line, the amplification input node, and the pre-amplification control terminal; the amplification unit is configured to: under the control of the pre-amplification control terminal, adjust the voltage of the amplification input node according to the voltage on the bit line to amplify the voltage difference generated on the bit line.

3. The sensitive amplifier circuit according to claim 2, characterized in that: The amplifying unit includes a first switch transistor, a first amplifying transistor, and a first voltage terminal; The gate of the first switch transistor is connected to the pre-amplification control terminal, the first electrode of the first switch transistor is connected to the first voltage terminal, and the second electrode of the first switch transistor is connected to the first electrode of the first amplification transistor; A gate electrode of the first amplifying transistor is connected to the bit line, and a second electrode of the first amplifying transistor is connected to the amplifying input node.

4. The sensitive amplifier circuit according to claim 3, characterized in that: The first switch transistor and the first amplifying transistor are both PMOS transistors; Alternatively, both the first switch transistor and the first amplifying transistor are NMOS transistors.

5. The sensitive amplifier circuit according to claim 3, characterized in that: The amplification unit further includes a second switch transistor, a second amplification transistor, a second voltage terminal, and an inverting pre-amplification control terminal; The gate of the second switch transistor is connected to the inverting pre-amplification control terminal, the first electrode of the second switch transistor is connected to the second voltage terminal, and the second electrode of the second switch transistor is connected to the first electrode of the second amplification transistor; The gate of the second amplifying transistor is connected to the bit line, and the second electrode of the second amplifying transistor is connected to the amplifying input node; The first switch transistor and the first amplifying transistor are both PMOS transistors; The second switch transistor and the second amplifying transistor are both NMOS transistors.

6. The sensitive amplifier circuit according to any one of claims 2 to 5, characterized in that: The pre-amplification circuit also includes an adjustment input terminal; The pre-amplifier circuit is also configured to: before generating the voltage difference on the bit line, under the control of the adjustment input terminal, adaptively adjust the pulse width of the pulse signal input by the pre-amplifier control terminal to control the voltage of the amplification input node not to exceed the set voltage.

7. The sensitive amplifier circuit according to claim 6, characterized in that: The pre-amplification circuit also includes a comparator, a NAND gate, an inverter, and a first reference voltage terminal; The first input terminal of the comparator is connected to the first reference voltage terminal, the second input terminal of the comparator is connected to the amplification input node, and the output terminal of the comparator is connected to the first input terminal of the NAND gate; wherein the voltage of the first reference voltage terminal is the set voltage; The second input terminal of the NAND gate is connected to the adjustment input terminal, and the output terminal of the NAND gate is connected to the pre-amplification control terminal; The input end of the inverter is connected to the regulating input end, and the output end of the inverter is connected to the pre-charge control end.

8. The sensitive amplifier circuit according to claim 6, characterized in that: The pre-amplification circuit also includes a first inverter, a second inverter, and a NAND gate; The input end of the first inverter is connected to the amplification input node, and the output end of the first inverter is connected to the first input end of the NAND gate; wherein the flip point of the first inverter is set to the set voltage; The second input terminal of the NAND gate is connected to the amplification input node, and the output terminal of the NAND gate is connected to the pre-amplification control terminal; An input terminal of the second inverter is connected to the amplification input node, and an output terminal of the second inverter is connected to the precharge control terminal.

9. The sensitive amplifier circuit according to any one of claims 1 to 8, characterized in that: The first switch circuit includes: a first switch and a second switch; The first switch is connected between the amplification input node and the first input terminal; The second switch is connected between the amplifying input node and the second input terminal.

10. The sensitive amplifier circuit according to any one of claims 1 to 9, characterized in that: The second switch circuit includes: a third switch and a fourth switch; The third switch is connected between the second input terminal and the second output terminal; The fourth switch is connected between the first input terminal and the first output terminal.

11. The sensitive amplifier circuit according to claims 1-10, characterized in that: The sensitive amplifier further includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first power supply terminal, and a second power supply terminal; The first electrode of the first P-type transistor and the first electrode of the second P-type transistor are both connected to the first power supply terminal; the gate of the first P-type transistor is connected to the first input terminal, and the second electrode of the first P-type transistor is connected to the second output terminal; the gate of the second P-type transistor is connected to the second input terminal, and the second electrode of the second P-type transistor is connected to the first output terminal; The first electrode of the first N-type transistor and the first electrode of the second N-type transistor are both connected to the second power supply terminal; the gate of the first N-type transistor is connected to the first input terminal, and the second electrode of the first N-type transistor is connected to the second output terminal; the gate of the second N-type transistor is connected to the second input terminal, and the second electrode of the second N-type transistor is connected to the first output terminal.

12. A control method for a sensitive amplifier circuit according to any one of claims 1 to 11, characterized in that: include: Controlling the pre-amplification circuit to precharge the bit line to a reference voltage and reset the voltage of the amplification input node; Controlling the pre-amplification circuit to adjust the voltage of the amplification input node to a first voltage according to the reference voltage on the bit line, and inputting the first voltage to the first input terminal under the control of the first switch circuit; Controlling the pre-amplification circuit to reset the voltage of the amplification input node; Controlling the pre-amplification circuit to amplify the voltage difference generated on the bit line to adjust the voltage of the amplification input node to a second voltage; and controlling the first switch circuit to input the second voltage to the second input terminal; The second switch circuit is controlled to connect the first input terminal with the first output terminal, and the second input terminal with the second output terminal, and the sense amplifier starts to work.

13. A storage device, characterized in that: It comprises at least one storage array and the sensitive amplifier circuit according to any one of claims 1 to 11, wherein the storage array is provided with a plurality of storage units; The sensitive amplifier circuit is connected to the plurality of storage cells through the bit lines.

14. An electronic device, characterized in that: The invention comprises a controller and the storage device as claimed in claim 13, wherein the controller is electrically connected to the storage device.

Images