Method, apparatus, and system for calculating function on the basis of integration of memory and computation

Abstract

The present disclosure is applicable to the technical field of artificial intelligence, and provides a method, apparatus, and system for calculating a function on the basis of integration of memory and computation, a device, and a storage medium. The method comprises: for a first power term in a first Taylor expansion in a first function to be calculated, on the basis of a coefficient value of a first coefficient corresponding to the first power term, adjusting a first conductance value of a variable resistor on a word line in a semiconductor memory device which corresponds to the first power term; on the basis of the numerical value of the first power term, inputting a pulse voltage to the word line passing through the variable resistor in the semiconductor memory device, and obtaining a first current outputted by a bit line; performing analog-to-digital conversion on the first current, and obtaining a first current value corresponding to the first current; and, on the basis of the first current value, determining a first calculation result of said first function.

Description

Method, device, and system for implementing function computing based on storage and computing integration Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to a method, device, and system for implementing function computing based on storage and computing integration. Background Art

[0002] With the rapid development of deep neural networks, the number of parameters and computational complexity has increased exponentially. In order to ensure that the computing power requirements of advanced neural network algorithms can be met and thus successfully complete artificial intelligence computing tasks, high energy and hardware overhead is required.

[0003] In related technologies, the Graphics Processing Unit (GPU), widely used to accelerate AI algorithms, is a computing system based on the von Neumann architecture. This architecture is characterized by the separation of storage and computation. When performing a computation, the computing unit must first access memory and then write the results back to memory after the computation is complete. Because deep neural networks contain a large number of parameters, the computing unit must perform a large number of memory access operations, resulting in significant memory access time and power consumption.

[0004] In neural networks, the Softmax function is a generalization of logistic regression, so it can be used for multi-classification tasks and is one of the most commonly used classification functions. However, at present, the Softmax function cannot be processed energy-efficiently in the von Neumann architecture.

[0005] Summary of the Invention

[0006] In view of the above problems, the present disclosure provides a method for implementing function computing based on storage and computing integration.

[0007] According to a first aspect of the present disclosure, a method for implementing function calculation based on storage and calculation integration is provided, comprising: for a first power term in a first Taylor expansion in a first function to be calculated, adjusting a first conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term; inputting a pulse voltage to the word line through the variable resistor in the semiconductor memory device according to the value of the first power term to obtain a first current output by the bit line; performing analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current; and determining a first calculation result of the first function to be calculated based on the first current value.

[0008] According to an embodiment of the present disclosure, a first conductance value of a variable resistor on a word line corresponding to a first power term in a semiconductor memory device is adjusted according to a coefficient value of a first coefficient corresponding to the first power term, including: determining the variable resistor on the word line corresponding to the first power term according to an exponent value of the first power term of a first Taylor expansion; and adjusting the first conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device according to the coefficient value of the first coefficient.

[0009] According to an embodiment of the present disclosure, a pulse voltage is input to a word line through a variable resistor in a semiconductor memory device according to the value of the first power term to obtain a first current output by the bit line, including: determining a word line corresponding to the first power term from multiple word lines according to the exponent value of the first power term of a first Taylor expansion; inputting a pulse voltage corresponding to the coefficient value of the first coefficient to the word line corresponding to the first power term according to the value of the first power term; for each bit line, summing up the currents on multiple word lines associated with the bit line to obtain the first current output by the bit line.

[0010] According to an embodiment of the present disclosure, a method for realizing function calculation based on storage and calculation integration also includes: for a first power term in a first Taylor expansion in a first function to be calculated, adjusting a second conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to the value of the first power term; inputting a pulse voltage to a word line through a variable resistor in a semiconductor memory device according to the coefficient value of a first coefficient corresponding to the first power term to obtain a second current output by a bit line; performing analog-to-digital conversion on the first current to obtain a second current value corresponding to the first current; and determining a second calculation result of the first function to be calculated based on the second current value.

[0011] According to an embodiment of the present disclosure, the second conductance value of the variable resistor on the word line corresponding to the first power term in the semiconductor memory device is adjusted according to the value of the first power term, including: determining the variable resistor on the word line corresponding to the first power term according to the exponent value of the first power term of the first Taylor expansion; and adjusting the second conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device according to the value of the first power term of the first Taylor expansion.

[0012] According to an embodiment of the present disclosure, the first function to be calculated includes multiple first Taylor expansions; based on the second current value, determining the second calculation result of the first function to be calculated includes: summing the multiple second current values ​​to obtain the second calculation result.

[0013] According to an embodiment of the present disclosure, a method for realizing function calculation based on storage and calculation integration also includes: determining each second power term in the Maclaurin expansion of the second function to be calculated based on a second calculation result; for each second power term, adjusting the third conductance value of the variable resistor on the word line corresponding to the second power term in the semiconductor memory device according to the value of the second power term; inputting a pulse voltage to the word line in the semiconductor memory device according to the coefficient value of the second coefficient corresponding to the second power term to obtain a third current output by the bit line; performing analog-to-digital conversion on the third current to obtain a third current value corresponding to the third current; and determining the third calculation result based on the third current value and the first calculation result.

[0014] According to an embodiment of the present disclosure, the method for realizing function calculation based on storage and calculation integration also includes: determining each third power term in the second Taylor expansion of the third function to be calculated based on the third calculation result; for each third power term, adjusting the fourth conductance value of the variable resistor on the word line corresponding to the third power term in the semiconductor memory device according to the coefficient value of the third coefficient corresponding to the third power term; inputting a pulse voltage to the word line in the semiconductor memory device according to the numerical value of the third power term to obtain a fourth current output by the bit line; performing analog-to-digital conversion on the fourth current to obtain a fourth current value corresponding to the fourth current; and determining the fourth calculation result of the third function to be calculated based on the fourth current value.

[0015] A second aspect of the present disclosure provides a device for implementing function computing based on storage and computing integration, including:

[0016] a first adjustment module, configured to adjust a first conductance value of a variable resistor on a word line corresponding to the first power term in the semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term;

[0017] A first input module is configured to input a pulse voltage to a word line through a variable resistor in the semiconductor memory device according to a value of the first power term, so as to obtain a first current output by a bit line;

[0018] a first conversion module, configured to perform analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current;

[0019] The first determining module is configured to determine a first calculation result of a first to-be-calculated function based on the first current value.

[0020] A third aspect of the present disclosure provides a system for implementing function computing based on storage and computing integration, including:

[0021] A semiconductor memory device includes a word line and a bit line, wherein a variable resistor is provided on the word line; the semiconductor memory device is configured to receive a pulse voltage on the bit line and obtain a first current output by the bit line via the variable resistor on the word line, wherein a first conductance value of the variable resistor is obtained by adjusting a coefficient value of a first coefficient corresponding to a first power term; and a voltage value of the pulse voltage is determined based on the value of the first power term.

[0022] an analog-to-digital converter, configured to receive a first current sent by the semiconductor memory device, perform analog-to-digital conversion on the first current, and obtain a first current value corresponding to the first current;

[0023] The calculator is configured to receive a first current value sent by the analog-to-digital converter, and determine a first calculation result of a first function to be calculated based on the first current value.

[0024] The fourth aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors execute the above-mentioned method for implementing function calculation based on integrated storage and computing.

[0025] The fifth aspect of the present disclosure also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to execute the above-mentioned method for implementing function calculation based on storage and computing integration.

[0026] The sixth aspect of the present disclosure also provides a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned method for implementing function calculation based on storage and computing integration.

[0027] According to an embodiment of the present disclosure, a natural exponential operation is implemented using a resistive random access memory (RRAM). Since the polynomial coefficients of the Taylor expansion are constants, the conductance value of the variable resistor in the semiconductor memory device is set according to the coefficient value of the first coefficient corresponding to the first power term, thereby achieving reuse of fixed constants. Moreover, due to the multi-bit storage characteristics of the resistive random access memory, the advantage of using in-memory calculations to perform highly parallel matrix-vector multiplication is achieved while avoiding the operation of determining the voltage value of the pulse voltage input on the word line through multiple accesses, thereby reducing the number of times the memory needs to be accessed. At the same time, the problem of low computational efficiency caused by the need to read and calculate multiple times from the memory space when performing calculations using common computer architectures is also reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] FIG1 schematically illustrates an application scenario of a method, apparatus, device, medium, and program product for implementing function computing based on storage-computing integration according to an embodiment of the present disclosure;

[0030] FIG2 schematically shows a flow chart of a method for implementing function computing based on storage-computing integration according to an embodiment of the present disclosure;

[0031] FIG3 schematically shows a structural diagram of a system for implementing function computing based on storage and computing integration according to an embodiment of the present disclosure;

[0032] FIG4 schematically shows a flow chart of a method for implementing Softmax function calculation based on storage and computing integration according to an embodiment of the present disclosure;

[0033] FIG5 schematically shows a flow chart of a method for implementing function computing based on storage-computing integration according to another embodiment of the present disclosure;

[0034] FIG6 schematically shows a structural diagram of a system for implementing function computing based on storage and computing integration according to another embodiment of the present disclosure;

[0035] FIG7 schematically shows a structural block diagram of an apparatus for implementing function computing based on storage and computing integration according to an embodiment of the present disclosure; and

[0036] FIG8 schematically shows a block diagram of an electronic device suitable for implementing function computing based on storage and computing integration according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0038] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0039] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0040] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0041] In the technical solution disclosed herein, the user information involved (including but not limited to user personal information, user image information, user device information, such as location information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of relevant data comply with the relevant laws, regulations and standards of relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0042] In the technical solution of the embodiment of the present disclosure, the user's authorization or consent is obtained before obtaining or collecting the user's personal information.

[0043] In the process of implementing the present disclosure, it was found that the calculation of the Softmax function requires the implementation of three operators: natural exponent, natural exponent summation, and division. The core calculation is the calculation of the natural exponent. The conventional calculation method is to expand the natural exponent into a Taylor expansion, calculate the expansion terms one by one through a digital multiplier, and then accumulate the expansion terms through a digital adder to obtain the result. Since the polynomial coefficients of the Taylor expansion are fixed constants, they should be reused. However, in the von Neumann architecture, these constants cannot be effectively reused in the process of calculation according to the above calculation method, and the use of conventional digital circuits to calculate the natural exponential operation requires huge hardware area overhead.

[0044] An embodiment of the present disclosure provides a method for implementing function calculation based on integrated storage and calculation, including: for a first power term in a first Taylor expansion in a first function to be calculated, adjusting a first conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term; inputting a pulse voltage to the word line through the variable resistor in the semiconductor memory device according to the value of the first power term to obtain a first current output by the bit line; performing analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current; and determining a first calculation result of the first function to be calculated based on the first current value.

[0045] FIG1 schematically shows an application scenario diagram of the method, apparatus, device, medium, and program product for implementing function computing based on storage-computing integration according to an embodiment of the present disclosure.

[0046] As shown in Figure 1, an application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 is a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables.

[0047] The user may use at least one of the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications may be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (only as examples).

[0048] The first terminal device 101 , the second terminal device 102 , and the third terminal device 103 may be various electronic devices having display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, and the like.

[0049] The server 105 may be a server that provides various services, such as a background management server (for example only) that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103. The background management server may analyze and process received user requests and other data, and feed back processing results (e.g., web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0050] It should be noted that the method for implementing function computing based on storage and computing integration provided by the embodiment of the present disclosure can generally be executed by the server 105. Accordingly, the device for implementing function computing based on storage and computing integration provided by the embodiment of the present disclosure can generally be set in the server 105. The method for implementing function computing based on storage and computing integration provided by the embodiment of the present disclosure can also be executed by a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105. Accordingly, the device for implementing function computing based on storage and computing integration provided by the embodiment of the present disclosure can also be set in a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105.

[0051] It should be understood that the number of terminal devices, networks, and servers in Figure 1 is merely illustrative and any number of terminal devices, networks, and servers may be provided as required.

[0052] Based on the scenario described in FIG1 , the following will describe in detail the method for implementing function computing based on storage and computing integration in the disclosed embodiment through FIG2 to FIG4 .

[0053] FIG2 schematically shows a flow chart of a method for implementing function computing based on storage-computing integration according to an embodiment of the present disclosure.

[0054] As shown in FIG2 , the method 200 for implementing function computing based on storage-computing integration in this embodiment includes operations S210 to S240 .

[0055] In operation S210, for a first power term in a first Taylor expansion in a first function to be calculated, a first conductance value of a variable resistor on a word line corresponding to the first power term in the semiconductor memory device is adjusted according to a coefficient value of a first coefficient corresponding to the first power term.

[0056] According to an embodiment of the present disclosure, a semiconductor memory device may include N word lines and one or more bit lines, wherein each word line may include a variable resistor. The number of terms in the first Taylor expansion may be determined based on the number of word lines of the semiconductor memory device. The N word lines correspond one-to-one to the N terms in the first function to be calculated from the front to the back. The first conductance value of the variable resistor is set to the coefficient value of the first coefficient corresponding to the first power term corresponding to the variable resistor. The first coefficient of the first function to be calculated may be the coefficient value of each term in the first function to be calculated, wherein the first coefficient corresponds one-to-one to the first power term.

[0057] According to embodiments of the present disclosure, semiconductor memory devices can utilize resistive random access memory (RRAM). RRAM is a type of non-volatile memory, where metal oxide is sandwiched between electrodes on either side. This allows for low power consumption and high-speed rewriting. By applying a pulse voltage to the metal oxide film, a large resistance difference is generated to store "0" and "1." Furthermore, because RRAM can achieve multi-bit storage by adjusting its resistance state, it facilitates the storage of multi-bit data using less hardware.

[0058] In operation S220, a pulse voltage is input to a word line through a variable resistor in the semiconductor memory device according to a value of the first power term, so as to obtain a first current output by a bit line.

[0059] According to an embodiment of the present disclosure, the pulse voltage is determined according to the value of the first power term. After the pulse voltage is input to each word line, a current is generated through the variable resistor on each word line, and the current converges on the bit line to obtain a first current.

[0060] In operation S230 , analog-to-digital conversion is performed on the first current to obtain a first current value corresponding to the first current.

[0061] According to an embodiment of the present disclosure, analog-to-digital conversion is performed on the first current, and the current signal is converted into a digital signal to obtain a first current value.

[0062] In operation S240 , a first calculation result of a first to-be-calculated function is determined based on the first current value.

[0063] According to embodiments of the present disclosure, based on Kirchhoff's and Ohm's laws, the first current converging on the bit line can represent the value of the polynomial being calculated on that bit line. Therefore, the value of the target power term in the first function to be calculated can be derived based on the value of the first current. After inputting a pulse voltage, the first current can be directly generated on the bit line, eliminating the need for manual summation. This avoids the time and power consumption overhead associated with multiple memory accesses in the von Neumann architecture, enabling in-memory computation by performing computations in-situ in the memory.

[0064] FIG3 schematically shows a structural diagram of a semiconductor memory device for implementing function computing based on storage and computing integration according to an embodiment of the present disclosure.

[0065] As shown in FIG3 , the semiconductor memory device for implementing function calculation based on storage and calculation integration in this embodiment includes a word line 310 , a bit line 320 and a variable resistor 330 .

[0066] According to an embodiment of the present disclosure, the semiconductor memory device shown in FIG3 can be used to calculate Connect the 4 word lines with The four first power terms in the Taylor expansion of are in one-to-one correspondence. According to the values ​​of the first power terms, the first conductance values ​​of the variable resistors on the four word lines are set to 1, 1, And according to the coefficient value of the first coefficient corresponding to the first power term, the word line of the semiconductor memory device through the variable resistor is input with a size of x0 0 、x0 1 、x0 2 、x0 3 Since the current value = voltage value * conductivity value, the current values ​​on the four word lines are 1, x0, and The size of the bit line is The current value can be determined according to the current value value.

[0067] According to an embodiment of the present disclosure, a natural exponential operation is implemented using a variable resistive memory. Since the polynomial coefficients of the Taylor expansion are constants, the conductance value of the variable resistor in the semiconductor memory device is set according to the coefficient value of the first coefficient corresponding to the first power term, thereby achieving reuse of fixed constants. Moreover, due to the multi-bit storage characteristics of the variable resistive memory, the advantage of using in-memory calculations to perform high-parallel matrix-vector multiplication is achieved, while avoiding the operation of determining the voltage value of the pulse voltage input on the word line through multiple accesses, thereby reducing the number of times the memory needs to be accessed. At the same time, it also reduces the problem of low computational efficiency caused by the need to read and calculate multiple times from the memory space when performing calculations using common computer architectures.

[0068] According to an embodiment of the present disclosure, a first conductance value of a variable resistor on a word line corresponding to a first power term in a semiconductor memory device is adjusted according to a coefficient value of a first coefficient corresponding to the first power term, including: determining the variable resistor on the word line corresponding to the first power term according to an exponent value of the first power term of a first Taylor expansion; and adjusting the first conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device according to the coefficient value of the first coefficient.

[0069] According to an embodiment of the present disclosure, the first function to be calculated can be a function e x The first N terms of the Taylor expansion, the first power term is x in ascending order of exponent 0 、x 1 、x 2 ,…,x N-2 、x N-1 First, the correspondence between the variable resistor on the word line and each term in the first Taylor expansion is determined, that is, the term of order n corresponds to the (n+1)th word line, and then the conductance value of the variable resistor corresponding to the term is adjusted according to the coefficient value of each term.

[0070] According to an embodiment of the present disclosure, a pulse voltage is input to a word line through a variable resistor in a semiconductor memory device according to the value of the first power term to obtain a first current output by the bit line, including: determining a word line corresponding to the first power term from multiple word lines according to the exponent value of the first power term of a first Taylor expansion; inputting a pulse voltage corresponding to the coefficient value of the first coefficient to the word line corresponding to the first power term according to the value of the first power term; for each bit line, summing up the currents on multiple word lines associated with the bit line to obtain the first current output by the bit line.

[0071] According to the embodiments of the present disclosure, since the correspondence between each variable resistor on a word line and each first-order power term is already determined, a pulse voltage corresponding to each power term is input to the word line corresponding to that term to obtain the current output by that word line. The currents on all word lines associated with a bit line are summed on that bit line to obtain the first current of the bit line.

[0072] According to an embodiment of the present disclosure, a method for realizing function calculation based on storage and calculation integration also includes: for a first power term in a first Taylor expansion in a first function to be calculated, adjusting a second conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to the value of the first power term; inputting a pulse voltage to a word line through a variable resistor in a semiconductor memory device according to the coefficient value of a first coefficient corresponding to the first power term to obtain a second current output by a bit line; performing analog-to-digital conversion on the first current to obtain a second current value corresponding to the first current; and determining a second calculation result of the first function to be calculated based on the second current value.

[0073] According to an embodiment of the present disclosure, the second conductance value of the variable resistor on the word line corresponding to the first power term in the semiconductor memory device is adjusted according to the value of the first power term, including: determining the variable resistor on the word line corresponding to the first power term according to the exponent value of the first power term of the first Taylor expansion; and adjusting the second conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device according to the value of the first power term of the first Taylor expansion.

[0074] According to an embodiment of the present disclosure, the first function to be calculated can be a function e x The first N terms of the Taylor expansion, the first power term is x in ascending order of exponent 0 、x 1 、x 2 ,…,x N-2 、x N-1First, the correspondence between the variable resistor on the word line and each term in the first Taylor expansion is determined, that is, the term of order n corresponds to the (n+1)th word line. Then, the conductance value of the variable resistor corresponding to the term is adjusted according to the exponential value of each term and the value of the independent variable.

[0075] According to an embodiment of the present disclosure, the first function to be calculated includes multiple first Taylor expansions; based on the second current value, determining the second calculation result of the first function to be calculated includes: summing the multiple second current values ​​to obtain the second calculation result.

[0076] According to an embodiment of the present disclosure, when a semiconductor memory device is provided with multiple bit lines, after obtaining multiple second currents of each bit line and performing analog-to-digital conversion to obtain second current values, the multiple second current values ​​are summed to obtain a second calculation result representing the sum of function values ​​of multiple Taylor expansions in the first function to be calculated calculated on the semiconductor memory device.

[0077] According to an embodiment of the present disclosure, since the conductance value of the variable resistor on the word line is set to the power term of the term of the first function to be calculated corresponding to the variable resistor, the pulse voltage of the word line is determined according to the coefficient value of the first coefficient, and therefore the magnitude of the current generated on the word line is the result of this term.

[0078] For example, in the first function to be calculated, take e x In the case of the first N terms of the Taylor expansion, when x=x0, the second current value of the corresponding bit line obtained by analog-to-digital conversion is In a semiconductor memory device with three bit lines, and x is x0, x1, and x2 respectively, the second current values ​​of the three bit lines are summed to obtain Therefore, semiconductor memory devices can be used to calculate The value of , where d is the number of bit lines of the semiconductor memory device.

[0079] According to an embodiment of the present disclosure, the operation of the Softmax function is formula (1):

[0080] The function is obtained by the first current value After the second calculation result, the division operation is realized by formula (2):

[0081] in, So the division operation can be converted to the calculation

[0082] FIG4 schematically shows a flowchart of a method for implementing function computing based on storage-computing integration according to an embodiment of the present disclosure.

[0083] As shown in FIG4 , the method 400 for implementing function computing based on storage-computing integration in this embodiment includes operations S410 to S450 .

[0084] In operation S410 , each second power term in a Maclaurin expansion of a second function to be calculated is determined based on the second calculation result.

[0085] According to an embodiment of the present disclosure, the base of the second power term of the second function to be calculated may be numerically equal to the second calculation result.

[0086] In operation S420 , for each second power term, a third conductance value of a variable resistor on a word line corresponding to the second power term in the semiconductor memory device is adjusted according to a value of the second power term.

[0087] According to an embodiment of the present disclosure, a semiconductor memory device may include M word lines and one bit line, wherein each word line may include a variable resistor. The number of terms in the second function to be calculated is determined based on the number of word lines in the semiconductor memory device. The M word lines then correspond one-to-one to the M terms in the second function to be calculated, from front to back. The third conductance value of the variable resistor is set to the value of the second power term of the term in the second function to be calculated corresponding to the variable resistor.

[0088] In operation S430, a pulse voltage is input to a word line in the semiconductor memory device according to a coefficient value of a second coefficient corresponding to the second power term, so as to obtain a third current outputted from a bit line.

[0089] According to an embodiment of the present disclosure, the second coefficient of the second function to be calculated can be the coefficient value of each term in the second function to be calculated, where the second coefficient corresponds to the second power term. The pulse voltage on each word line is determined based on the coefficient value of the second coefficient. After the pulse voltage is input to each word line, a current is generated through the variable resistor on each word line. The currents on multiple word lines associated with the bit line are summed to obtain a third current for the bit line.

[0090] In operation S440 , analog-to-digital conversion is performed on the third current to obtain a third current value corresponding to the third current.

[0091] According to an embodiment of the present disclosure, analog-to-digital conversion is performed on the third current, and the current signal is converted into a digital signal to obtain the third current value.

[0092] In operation S450 , a third calculation result is determined based on the third current value and the first calculation result.

[0093] According to an embodiment of the present disclosure, a third calculation result is obtained by performing a subtraction between the first calculation result and the third current value, wherein the subtraction can be implemented using a current differential amplifier.

[0094] According to an embodiment of the present disclosure, a semiconductor memory device is used to calculate the value of the natural logarithm whose base is the second calculation result. By using the properties of the logarithmic function, the division is converted into subtraction for calculation, thereby avoiding operations such as shifting and accumulation required when performing division operations in commonly used computer architectures, thereby improving calculation efficiency.

[0095] According to an embodiment of the present disclosure, the second function to be calculated can be the first M terms of the Maclaurin expansion of ln(1+a), where (1+a) can be numerically equal to the first calculation result. Then the second power term is (1+a) in ascending order of exponents. 1 、(1+a) 2 ,…,(1+a) M-1 、(1+a) M First, based on the exponents of the second-order terms, the corresponding relationship between the variable resistor on the word line and the second-order terms in the Maclaurin expansion is determined, that is, the m-th second-order term corresponds to the variable resistor on the m-th word line. Then, based on the value of the power term of each term, the third conductance value of the variable resistor corresponding to the term is adjusted.

[0096] For example, one of the second functions to be calculated is 1 / 3(1+a) 3 , the second calculation result is p, then the conductance value of the variable resistor on the word line corresponding to this item is set to p 3 , the pulse voltage input to the word line is 1 / 3, and the current generated on the word line is 1 / 3 (p 3 ), which is the same as the result of this calculation. The third current value obtained on the bit line is Use x=x i The third calculation result can be obtained by subtracting the first calculation result on the corresponding bit line from the third current value.

[0097] According to an exemplary embodiment of the present disclosure, a method for realizing Softmax function calculation based on storage and calculation integration can also be provided. On the basis of operations S410 to S450 as shown in Figure 4, it can also include: determining each third power term in the second Taylor expansion of the third function to be calculated based on the third calculation result; for each third power term, adjusting the fourth conductance value of the variable resistor on the word line corresponding to the third power term in the semiconductor memory device according to the coefficient value of the third coefficient corresponding to the third power term; inputting a pulse voltage to the word line in the semiconductor memory device according to the numerical value of the third power term to obtain a fourth current output by the bit line; performing analog-to-digital conversion on the fourth current to obtain a fourth current value corresponding to the fourth current; and determining the fourth calculation result of the third function to be calculated based on the fourth current value.

[0098] According to an embodiment of the present disclosure, after obtaining a third calculation result through the first calculation result and the third current value, the calculation of the Softmax function can be completed through formula (3):

[0099] FIG5 schematically shows a flowchart of a method for implementing Softmax function calculation based on storage and computing integration according to an embodiment of the present disclosure.

[0100] As shown in FIG5 , the method 500 for implementing Softmax function calculation based on storage and computing integration in this embodiment includes operations S510 to S550 .

[0101] In operation S510 , each third power term in a second Taylor expansion of a third function to be calculated is determined based on the third calculation result.

[0102] According to an embodiment of the present disclosure, the base of the third power term of the third function to be calculated may be numerically equal to the third calculation result.

[0103] In operation S520 , for each third power term, a fourth conductance value of a variable resistor on a word line corresponding to the third power term in the semiconductor memory device is adjusted according to a coefficient value of a third coefficient corresponding to the third power term.

[0104] According to an embodiment of the present disclosure, the third coefficient of the third function to be calculated may be the coefficient value of each term in the third function to be calculated, wherein the third coefficient corresponds one-to-one with the third power term. The semiconductor memory device may include P word lines and one bit line, wherein each word line may include a variable resistor. The number of terms in the third function to be calculated may be determined based on the number of word lines in the semiconductor memory device. The P word lines then correspond one-to-one with the P terms in the third function to be calculated. The conductance value of the variable resistor is set as the coefficient value of the third coefficient.

[0105] In operation S530, a pulse voltage is input to a word line in the semiconductor memory device according to the value of the third power term to obtain a fourth current output from the bit line.

[0106] According to an embodiment of the present disclosure, a pulse voltage on each word line is determined based on the value of the third power term of the term of the third function to be calculated corresponding to the variable resistor. After the pulse voltage is input to each word line, a current is generated through the variable resistor on each word line. The currents on multiple word lines associated with a bit line are summed to obtain a fourth current for the bit line.

[0107] In operation S540 , analog-to-digital conversion is performed on the fourth current to obtain a fourth current value corresponding to the fourth current.

[0108] According to an embodiment of the present disclosure, analog-to-digital conversion is performed on the fourth current, and the current signal is converted into a digital signal to obtain the fourth current value.

[0109] In operation S550 , a fourth calculation result of the third to-be-calculated function is determined based on the fourth current value.

[0110] According to an embodiment of the present disclosure, the fourth calculation result of the third to-be-calculated function may be numerically equal to the magnitude of the fourth current value.

[0111] According to an embodiment of the present disclosure, a semiconductor memory device is used to calculate a value using a natural constant as the base and a third calculation result as the exponent. The result of the Softmax function is obtained by using the inverse relationship between the logarithmic function and the power function. Furthermore, because the coefficient of the Taylor expansion of the natural exponential is set to the fourth conductance value of the variable resistor, the calculation result can be obtained by simply changing the voltage value of the pulse voltage on the word line, thus achieving constant reuse.

[0112] According to an embodiment of the present disclosure, the fourth calculation result of the third function to be calculated can be calculated using the system for realizing function calculation based on storage and calculation integration shown in FIG3. According to an embodiment of the present disclosure, the third function to be calculated can take e b The first P terms of the Taylor expansion, where b can be numerically equal to the second calculation result. Then the third parameter is b in ascending order of exponents. 0 、b 1 ,…,b P-2 、b P-1 First, the corresponding relationship between the variable resistor on the word line and each term in the Taylor expansion is determined, and then the conductance value of the variable resistor corresponding to the term is adjusted according to the coefficient value of each term.

[0113] For example, one of the third functions to be calculated is 1 / 6(b 3 ), then the pulse voltage of the word line input corresponding to this item is b 3 , the conductance of the variable resistor on the word line is set to 1 / 6, and the current generated on the word line is 1 / 6 (b 3 ), which is the same as the result of this calculation. The third current value obtained on the bit line is Thus we get softmax(x i ) results.

[0114] FIG6 schematically shows a structural diagram of a system for implementing function computing based on storage-computing integration according to another embodiment of the present disclosure.

[0115] As shown in FIG6 , the system for implementing function calculation based on storage and calculation integration in this embodiment includes a semiconductor memory device 610 , an analog-to-digital converter 620 , and a calculator 630 .

[0116] A semiconductor memory device includes a word line 611 and a bit line 612, wherein a variable resistor 613 is provided on the word line. The semiconductor memory device is configured to receive a pulse voltage on the bit line and obtain a first current output by the bit line via the variable resistor on the word line, wherein a first conductance value of the variable resistor is obtained by adjusting the value of a first power term; and a voltage value of the pulse voltage is determined by a coefficient value of a first coefficient corresponding to the first power term.

[0117] an analog-to-digital converter, configured to receive a first current sent by the semiconductor memory device, perform analog-to-digital conversion on the first current, and obtain a first current value corresponding to the first current;

[0118] The calculator is configured to receive a first current value sent by the analog-to-digital converter, and determine a first calculation result of a first function to be calculated based on the first current value.

[0119] According to an embodiment of the present disclosure, a pulse voltage is input to a word line, generating a current through a resistor on the word line that converges on a bit line. An analog-to-digital converter can convert the current signal into a digital signal. The calculator can be an accumulation tree.

[0120] For example, when calculating Softmax(x2), according to the setting method of the pulse voltage of the word line and the conductance value of the variable resistor in Figure 6, the currents on the four bit lines are converted into digital form respectively, and the sum is obtained by the calculator to obtain the second calculation result, that is, According to the setting method of the pulse voltage of the word line and the conductance value of the variable resistor in FIG3 , the current on the bit line is converted into analog to digital to obtain the first calculation result, that is, the value of x2.

[0121] Set the second calculation result to m, and calculate ln(softmax(x2)) by calculating x2-lnm. When calculating lnm, expand it according to the Maclaurin formula of lnm, that is, calculate When five word lines are used to calculate the McLaughlin formula results, the pulse voltages are set to The conductance values ​​of the variable resistors set on the five word lines are set to (m-1), (m-1) 2 、(m-1) 3 、(m-1) 4 、(m-1) 5 The current obtained on the bit line is converted to digital form, and the current value is the value of lnm. The first calculation result is subtracted from the third current value to calculate x2-lnm to obtain the third calculation result.

[0122] Set the third calculation result to n, and the calculation of Softmax(x2) is converted into the calculation That is e nThe pulse voltage can be set to 1, n, n respectively according to the pulse voltage setting method of each word line in Figure 3. 2 、n 3 The conductance values ​​of the variable resistors on the four word lines are set to 1, 1, The current obtained on the bit line is converted into digital form, and the fourth calculation result representing the magnitude of the current value is e n The value of , thereby realizing the calculation of Softmax(x2).

[0123] Based on the above-mentioned method and system for implementing function computing based on storage and computing integration, the present disclosure also provides a device for implementing function computing based on storage and computing integration. The device will be described in detail below with reference to FIG8 .

[0124] FIG7 schematically shows a structural block diagram of a device for implementing function computing based on storage and computing integration according to an embodiment of the present disclosure.

[0125] As shown in FIG. 7 , the apparatus 700 for implementing function computing based on storage and computing integration in this embodiment includes a first adjustment module 710 , a first input module 720 , a first conversion module 730 and a first determination module 740 .

[0126] The first adjustment module 710 is configured to adjust, for a first power term in a first Taylor expansion of a first to-be-calculated function, a first conductance value of a variable resistor on a word line corresponding to the first power term in the semiconductor memory device based on a coefficient value of a first coefficient corresponding to the first power term. In one embodiment, the first adjustment module 710 may be configured to perform operation S210 described above, and further description thereof will not be repeated herein.

[0127] The first input module 720 is used to input a pulse voltage to the word line of the semiconductor memory device through the variable resistor according to the value of the first power term to obtain a first current output by the bit line. In one embodiment, the first input module 720 can be used to perform the operation S220 described above, which will not be repeated here.

[0128] The first conversion module 730 is configured to perform analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current. In one embodiment, the first conversion module 730 may be configured to perform the operation S230 described above, which will not be described in detail herein.

[0129] The first determining module 740 is configured to determine a first calculation result of the first to-be-calculated function based on the first current value. In one embodiment, the first determining module 740 may be configured to execute the operation S240 described above, which will not be described in detail herein.

[0130] According to an embodiment of the present disclosure, the first adjustment module 710 includes a first determining unit and a first adjusting unit.

[0131] The first determining unit is configured to determine, according to an exponent value of a first power term of a first Taylor expansion, a variable resistor on a word line corresponding to the first power term.

[0132] The first adjusting unit is configured to adjust a first conductance value of a variable resistor corresponding to a first power term in the semiconductor memory device according to a coefficient value of the first coefficient.

[0133] According to an embodiment of the present disclosure, the first input module 720 includes a second determining unit, an input unit, and a summarizing unit.

[0134] The second determining unit is configured to determine a word line corresponding to the first power term from a plurality of word lines according to an exponent value of the first power term of the first Taylor expansion.

[0135] The input unit is used to input a pulse voltage corresponding to the coefficient value of the first coefficient to the word line corresponding to the first power term according to the value of the first power term.

[0136] The summing unit is configured to sum up, for each bit line, currents on a plurality of word lines associated with the bit line to obtain a first current output by the bit line.

[0137] According to an embodiment of the present disclosure, the device 700 for implementing function computing based on storage and computing integration also includes a second adjustment module, a second input module, a second conversion module and a second determination module.

[0138] The second adjustment module is used to adjust the second conductance value of the variable resistor on the word line corresponding to the first power term in the semiconductor memory device according to the value of the first power term in the first Taylor expansion of the first function to be calculated.

[0139] The second input module is used to input a pulse voltage to the word line through the variable resistor in the semiconductor memory device according to the coefficient value of the first coefficient corresponding to the first power term to obtain a second current output by the bit line.

[0140] The second conversion module performs analog-to-digital conversion on the first current to obtain a second current value corresponding to the first current.

[0141] The second determining module is configured to determine a second calculation result of the first to-be-calculated function based on the second current value.

[0142] According to an embodiment of the present disclosure, the second adjustment module includes a third determining unit and a second adjustment unit.

[0143] The third determining unit is configured to determine the variable resistance on the word line corresponding to the first power term according to the exponent value of the first power term of the first Taylor expansion.

[0144] The second adjusting unit adjusts a second conductance value of a variable resistor corresponding to the first power term in the semiconductor memory device according to a value of the first power term of the first Taylor expansion.

[0145] According to an embodiment of the present disclosure, the second determining module includes a summing unit.

[0146] The summing unit is configured to sum the multiple second current values ​​to obtain a second calculation result.

[0147] According to an embodiment of the present disclosure, the device 700 for implementing function computing based on storage and computing integration also includes a third determination module, a third adjustment module, a third input module, a third conversion module and a fourth determination module.

[0148] The third determining module is configured to determine each second power term in the Maclaurin expansion of the second function to be calculated based on the second calculation result.

[0149] The third adjustment module is configured to adjust, for each second power term, a third conductance value of a variable resistor on a word line corresponding to the second power term in the semiconductor memory device according to the value of the second power term.

[0150] The third input module is used to input a pulse voltage to the word line in the semiconductor memory device according to the coefficient value of the second coefficient corresponding to the second power term to obtain a third current output by the bit line.

[0151] The third conversion module is configured to perform analog-to-digital conversion on the third current to obtain a third current value corresponding to the third current.

[0152] The fourth determining module is configured to determine a third calculation result based on the third current value and the first calculation result.

[0153] According to an embodiment of the present disclosure, the device 700 for implementing function computing based on storage and computing integration further includes a fifth determination module, a fourth adjustment module, a fourth input module, a fourth conversion module and a sixth determination module.

[0154] The fifth determining module is configured to determine each third power term in the second Taylor expansion of the third function to be calculated based on the third calculation result.

[0155] The fourth adjustment module is configured to adjust, for each third power term, a fourth conductance value of a variable resistor on a word line corresponding to the third power term in the semiconductor memory device according to a coefficient value of a third coefficient corresponding to the third power term.

[0156] The fourth input module is used to input a pulse voltage to the word line in the semiconductor memory device according to the value of the third power term to obtain a fourth current output by the bit line.

[0157] The fourth conversion module is configured to perform analog-to-digital conversion on the fourth current to obtain a fourth current value corresponding to the fourth current.

[0158] The sixth determining module is configured to determine a fourth calculation result of the third to-be-calculated function based on the fourth current value.

[0159] According to an embodiment of the present disclosure, any multiple modules among the first adjustment module 710, the first input module 720, the first conversion module 730 and the first determination module 740 can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the first adjustment module 710, the first input module 720, the first conversion module 730 and the first determination module 740 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware such as any other reasonable way of integrating or packaging the circuit, or can be implemented in any one of the three implementation methods of software, hardware and firmware, or in an appropriate combination of any of them. Alternatively, at least one of the first adjustment module 710 , the first input module 720 , the first conversion module 730 and the first determination module 740 may be at least partially implemented as a computer program module, which may perform corresponding functions when executed.

[0160] FIG8 schematically shows a block diagram of an electronic device suitable for implementing a method of function computing based on storage and computing integration according to an embodiment of the present disclosure.

[0161] As shown in Figure 8, the electronic device 800 according to an embodiment of the present disclosure includes a processor 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage part 808 into a random access memory (RAM) 803. The processor 801 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a dedicated microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 801 may also include an onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for executing different actions of the method flow according to an embodiment of the present disclosure.

[0162] Various programs and data required for the operation of the electronic device 800 are stored in the RAM 803. The processor 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. The processor 801 executes the various operations of the method flow according to the embodiment of the present disclosure by executing the programs in the ROM 802 and / or the RAM 803. It should be noted that the programs may also be stored in one or more memories other than the ROM 802 and the RAM 803. The processor 801 may also execute the various operations of the method flow according to the embodiment of the present disclosure by executing the programs stored in the one or more memories.

[0163] According to an embodiment of the present disclosure, the electronic device 800 may further include an input / output (I / O) interface 805, which is also connected to the bus 804. The electronic device 800 may further include one or more of the following components connected to the I / O interface 805: an input portion 806 including a keyboard, a mouse, etc.; an output portion 807 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage portion 808 including a hard disk; and a communication portion 809 including a network interface card such as a LAN card or a modem. The communication portion 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed in the drive 810 as needed, so that a computer program read therefrom can be installed into the storage portion 808 as needed.

[0164] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, and when executed, implements the method according to the embodiments of the present disclosure.

[0165] According to an embodiment of the present disclosure, a computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, it may include but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present disclosure, a computer-readable storage medium may include the ROM 802 and / or RAM 803 described above and / or one or more memories other than ROM 802 and RAM 803.

[0166] The embodiments of the present disclosure also include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the method provided by the embodiments of the present disclosure.

[0167] The computer program executes the above functions defined in the system / device of the embodiment of the present disclosure when the computer program is executed by the processor 801. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0168] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 809, and / or installed from a removable medium 811. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0169] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 809, and / or installed from a removable medium 811. When the computer program is executed by the processor 801, the above-described functions defined in the system of the embodiment of the present disclosure are performed. According to the embodiment of the present disclosure, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0170] According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0171] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0172] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0173] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for implementing function computing based on storage and computing integration, comprising: For the first power term in the first Taylor expansion of the first function to be calculated, adjusting a first conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term; According to the value of the first power term, a pulse voltage is input to the word line through the variable resistor in the semiconductor memory device to obtain a first current output by the bit line; Performing analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current; Based on the first current value, a first calculation result of the first function to be calculated is determined.

2. The method according to claim 1, wherein: The method of adjusting a first conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term comprises: determining the variable resistance on the word line corresponding to the first power term according to the exponent value of the first power term of the first Taylor expansion; According to the coefficient value of the first coefficient, a first conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device is adjusted.

3. The method according to claim 1, wherein: The step of inputting a pulse voltage to a word line through the variable resistor in the semiconductor memory device according to the value of the first power term to obtain a first current output by a bit line comprises: According to the exponential value of the first power term of the first Taylor expansion, determining the word line corresponding to the first power term from a plurality of word lines; According to the value of the first power term, inputting a pulse voltage corresponding to the coefficient value of the first coefficient to the word line corresponding to the first power term; For each of the bit lines, currents on a plurality of the word lines associated with the bit line are summed up to obtain the first current output by the bit line.

4. The method according to claim 1, further comprising: For each first power term in the first Taylor expansion of the first function to be calculated, According to the value of the first power term, adjusting a second conductance value of a variable resistor on a word line corresponding to the first power term in the semiconductor memory device; According to the coefficient value of the first coefficient corresponding to the first power term, A pulse voltage is input through the word line of the variable resistor to obtain a second current output by the bit line; Performing analog-to-digital conversion on the first current to obtain a second current value corresponding to the first current; Based on the second current value, a second calculation result of the first function to be calculated is determined.

5. The method according to claim 4, wherein: The method of adjusting the second conductance value of the variable resistor on the word line corresponding to the first power term in the semiconductor memory device according to the value of the first power term comprises: determining the variable resistance on the word line corresponding to the first power term according to the exponent value of the first power term of the first Taylor expansion; According to the value of the first power term of the first Taylor expansion, a second conductance value of the variable resistor corresponding to the first power term in the semiconductor memory device is adjusted.

6. The method according to claim 4, wherein: The first function to be calculated includes a plurality of first Taylor expansions; The determining, based on the second current value, a second calculation result of the first function to be calculated includes: The second calculation result is obtained by summing up a plurality of the second current values.

7. The method according to claim 1, further comprising: Based on the second calculation result, determine each second power term in the Maclaurin expansion of the second function to be calculated; For each of the second power terms, adjusting a third conductance value of a variable resistor on a word line corresponding to the second power term in the semiconductor memory device according to a value of the second power term; According to the coefficient value of the second coefficient corresponding to the second power term, a pulse voltage is input to the word line in the semiconductor memory device to obtain a third current output by the bit line; Performing analog-to-digital conversion on the third current to obtain a third current value corresponding to the third current; Based on the third current value and the first calculation result, a third calculation result is determined.

8. The method according to claim 1, further comprising: Based on the third calculation result, determine each third power term in the second Taylor expansion of the third function to be calculated; For each of the third power terms, adjusting a fourth conductance value of a variable resistor on a word line corresponding to the third power term in the semiconductor memory device according to a coefficient value of a third coefficient corresponding to the third power term; According to the value of the third power term, a pulse voltage is input to the word line in the semiconductor memory device to obtain a fourth current output by the bit line; Performing analog-to-digital conversion on the fourth current to obtain a fourth current value corresponding to the fourth current; Based on the fourth current value, a fourth calculation result of the third function to be calculated is determined.

9. A device for implementing function computing based on storage and computing integration, comprising: A first adjustment module, configured to adjust a first conductance value of a variable resistor on a word line corresponding to the first power term in a semiconductor memory device according to a coefficient value of a first coefficient corresponding to the first power term; A first input module, used for inputting a pulse voltage to a word line through the variable resistor in the semiconductor memory device according to the value of the first power term, so as to obtain a first current output by a bit line; A first conversion module, configured to perform analog-to-digital conversion on the first current to obtain a first current value corresponding to the first current; The first determining module is used to determine a first calculation result of the first to-be-calculated function based on the first current value.

10. A system for implementing function computing based on storage and computing integration, comprising: A semiconductor memory device comprises a word line and a bit line, wherein a variable resistor is arranged on the word line; The semiconductor memory device is used to receive a pulse voltage on the bit line, and obtain a first current output by the bit line through a variable resistor on the word line, wherein a first conductance value of the variable resistor is obtained by adjusting a coefficient value of a first coefficient corresponding to a first power term; and a voltage value of the pulse voltage is determined according to a value of the first power term; an analog-to-digital converter, configured to receive the first current sent by the semiconductor memory device, perform analog-to-digital conversion on the first current, and obtain a first current value corresponding to the first current; A calculator is used to receive the first current value sent by the analog-to-digital converter, and determine a first calculation result of the first function to be calculated based on the first current value.

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