FPGA-based data plane state programmable system and switch

Abstract

The present invention provides an FPGA-based data plane state programmable system, comprising a multi-stage match action table pipeline. The pipeline comprises a plurality of ordered match action table modules, configured to implement different data plane processing forwarding algorithms on the basis of read configuration instructions combined with a flow state matching table and a conditional branch matching table. The match action table modules each comprise: a key value extraction module, configured to construct a key value to be matched; a flow state query module, configured to obtain, by matching of said key value, information of flow address to which a packet pertains, and read corresponding flow state information; a packet header vector emission queue, configured to use a flow state address in the flow state information as an identifier to dynamically schedule, on the basis of the flow state address and a dependency relationship, packet header vectors for out-of-order emission; an action module, configured to determine a data plane processing forwarding algorithm on the basis of the configuration instruction for processing, and update the flow state information and table state information; and a packet header vector reordering cache module, configured to store executed packet header vectors, and submit disordered packet header vectors in order.

Description

A data plane state programmable system and switch based on FPGA

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023112236476, entitled “A Data Plane State Programmable System and Switch Based on FPGA,” filed on September 21, 2023, which is hereby incorporated by reference. Technical Field

[0003] This invention applies to the fields of FPGA and network packet processing, and more particularly to an FPGA-based data plane state programmable system and switch. This system implements data plane state programmability based on FPGA hardware, supports the deployment of user-defined packet processing algorithms on the data plane, and maintains constant state query time. Background Art

[0004] With the rapid development of the internet, network traffic is growing exponentially, posing significant challenges to switching equipment performance. Current switching equipment architectures are primarily categorized into three types: those based on dedicated network interface card chips, those based on general-purpose processors, and those based on FPGAs. In recent years, as network scale has continued to expand, general-purpose processors have struggled to support the line-rate packet forwarding demands of high-speed networks. FPGAs, offering a compromise between general-purpose processors and dedicated chips, are widely used in high-speed networks due to their programmability and high performance.

[0005] In traditional network equipment, routers, switches, and other network devices use data plane and control plane algorithms to process packets. Users can configure control plane functions and protocols, but the underlying algorithms are only modified by the operator. In software-defined networking (SDN), users can deploy their own custom algorithms within network devices. Forwarding devices with a programmable data plane offer user-programmable functionality, employing a "match-action" paradigm. Users can define protocol field processing methods and forwarding behaviors through the programmable data plane.

[0006] The data plane in traditional SDN is a stateless data plane, whose network status information is completely managed by the controller, and the data plane is only responsible for forwarding functions.

[0007] The related patent application, "Packet Programmable State Set (Publication No.: CN111771358A)," proposes a network device containing a state set memory. The state set retains the flow state information of data packets passing through the network device. The network device interacts with the state set to control the processing performed on the flow of these data packets. This patented method implements data packet processing and state set management functions based on a general-purpose computer processor, resulting in significant packet processing latency. A related published paper, "Open Packet Processor," proposes a hardware-implementable extended state machine model for deploying a state data plane in hardware. The problem with this approach is that it fails to consider the consistency of flow state information.

[0008] Summary of the Invention

[0009] The purpose of the present invention is to overcome the defects of the prior art and propose a data plane state programmable system and switch based on FPGA.

[0010] A data plane state programmable system based on FPGA, the system comprising a matching action table pipeline with multiple stages;

[0011] The multi-stage matching action table pipeline includes multiple ordered matching action table modules, each matching action table module is used to implement different data plane processing and forwarding algorithms based on the read configuration instructions, combined with the flow state matching table and the conditional branch matching table; wherein the matching action table module includes:

[0012] A key value extraction module is used to extract fields from the packet header vector, global state and / or table state information according to the issued instructions to form a key value to be matched;

[0013] The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address;

[0014] The packet header vector transmission queue is used to dynamically schedule packet header vectors for out-of-order transmission based on the flow state address in the flow state information and the dependency relationship;

[0015] An action module, configured to determine a customized data plane processing and forwarding algorithm through a conditional branch matching table according to the read configuration instructions, process the flow state information corresponding to the out-of-order transmitted packet header vectors, and update the flow state information and table state information; and

[0016] The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

[0017] Preferably, the output of each matching action table module can serve as the input of a subsequent matching action table module.

[0018] Preferably, the flow state matching table is a ternary content addressable memory matching table, a hash matching table or a longest prefix matching table.

[0019] Preferably, the packet header vector transmission queue includes:

[0020] The scoreboard is used to record the read and write operations of the flow state, and use this to determine whether the flow state of the packet header vector entering the packet header vector transmit queue depends on the write-back results of other packet header vectors to be executed;

[0021] The packet header vector transmit queue is used to cache the input packet header vector into the free table entry;

[0022] The selection logic is used to select a packet header vector with the longest time for which flow state information is ready from the packet header vector transmission queue in each clock cycle and transmit it to the action module, while the packet header vectors for which flow state information is not ready continue to wait.

[0023] Preferably, the configuration instruction adopts a very long instruction word structure, and encapsulates multiple instructions with no data dependency into one very long instruction word.

[0024] Preferably, the action module includes a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule, wherein:

[0025] The conditional branch judgment submodule is used to select fields from the packet header vector and status information according to the configuration instructions, input them into several arithmetic logic units that are executed in parallel and support very long instruction words for calculating comparison results, and determine the corresponding specific data plane processing and forwarding algorithm in the conditional branch matching table based on the comparison results;

[0026] The status update submodule is used to update the status information according to the configuration instructions;

[0027] The packet header vector action submodule is used to modify the packet header vector.

[0028] On the other hand, the present invention provides a switch including the above-mentioned FPGA-based data plane state programmable system.

[0029] Compared with the prior art, the advantages of the present invention are:

[0030] 1. The state data plane in this application allows network applications to store some network state information on the data plane. The state data plane adopts the "match-state-action" paradigm. The overall design of the module highlights programmability. It can implement user-defined algorithms by issuing configuration instructions. At the same time, it supports the deployment of some dynamic network applications and can select appropriate data packet forwarding strategies in real time based on the state information in the data plane.

[0031] 2. Compared with the stateless data plane of traditional SDN, the stateful data plane allows network applications to store some network state information on the data plane, reducing the interaction between the data plane and the control plane, while enabling more dynamic network functions;

[0032] 3. Flexibility: Ability to quickly change data plane functions and enable rapid deployment of new protocols;

[0033] 4. High performance: Allows parallel processing of packet header vectors at the flow level, enabling line-speed processing and flow state consistency assurance;

[0034] 5. Dynamically schedule packet header vectors based on flow state addresses and dependencies, significantly improving packet processing speed while ensuring state consistency;

[0035] 6. Based on FPGA deployment, it has the advantages of low latency and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a general framework diagram of a data plane state programmable system based on FPGA of the present invention;

[0037] FIG2 is a diagram of the architecture of a matching action module in FIG1 ;

[0038] FIG3 is a diagram of the packet header vector transmission queue architecture in FIG2 ;

[0039] FIG4 is a diagram of the conditional branch judgment submodule architecture;

[0040] FIG5 is a flow chart of a state programmable data plane;

[0041] FIG6 is a diagram of the arithmetic logic unit architecture. DETAILED DESCRIPTION

[0042] In response to the need for state-based packet processing and programmable flexibility in FPGA programmable switching chips, the present invention proposes an FPGA-based system that supports data plane state programmability. As shown in Figure 1, the system includes a multi-stage matching action table pipeline; the multi-stage matching action table pipeline includes multiple ordered matching action table modules, each of which is used to implement different data plane processing and forwarding algorithms based on read configuration instructions, combined with flow state matching tables and conditional branch matching tables. As shown in Figure 2, it includes:

[0043] A key value extraction module is used to extract fields from the packet header vector, global state and / or table state information according to the issued instructions to form a key value to be matched;

[0044] The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address;

[0045] The packet header vector transmission queue is used to dynamically schedule packet header vectors for out-of-order transmission based on the flow state address in the flow state information and the dependency relationship;

[0046] An action module, configured to determine a customized data plane processing and forwarding algorithm through a conditional branch matching table according to the read configuration instructions, process the flow state information corresponding to the out-of-order transmitted packet header vectors, and update the flow state information and table state information; and

[0047] The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

[0048] The programmable key value extraction module implements the following steps: Based on the issued instructions, it extracts fields from the packet header vector, global state, and table state to form the key value to be matched. This module supports key value extraction of up to 256 bits.

[0049] The implementation steps of the matching table are as follows: the matching table can be configured as a ternary content addressable memory (TCAM) matching table, a hash matching table or a longest prefix matching table. According to the input key value, the address information of the flow to which the packet belongs can be matched, and the corresponding flow status information can be read using this address.

[0050] The implementation steps of the flow state storage are: reading the flow state information in the storage module according to the input address information.

[0051] The implementation steps for the packet header vector transmit queue are as follows: using the flow state address as an identifier, and based on the dependency relationships between the flow states to which the packet header vectors belong, adjacent packet header vectors belonging to the same flow ID are scheduled in the transmit queue, blocking packet header vectors with flow state dependencies. The transmit queue caches incoming packet header vectors in its idle entries. Each clock cycle, a packet header vector with the longest data readiness time is selected and transmitted to the pipeline, while packet header vectors with unready flow state information continue to wait in the transmit queue. After the flow state is updated, it is broadcast to all entries in the transmit queue. The entries in the transmit queue then determine whether the flow state they are waiting for is ready based on the broadcasted flow state. Packet header vectors for the same flow are transmitted in order based on the updated flow state information, while different flows are transmitted out of order. This is shown in Figure 3.

[0052] The action module consists of a conditional branch judgment submodule, a state update submodule and a header vector action submodule.

[0053] The implementation steps of the conditional branch judgment submodule are as follows: Based on the issued instruction, fields are selected from the packet header vector and status information, and input into several parallel execution arithmetic logic units that support very long instruction words for calculating comparison results. The comparator can execute R-type and I-type instructions and output the comparison judgment result as the basis for conditional branch judgment. This result can be spliced ​​with the flow state value to form a key value for querying the ternary content addressable memory (TCAM) table. This is input into the ternary content addressable memory (TCAM) conditional branch matching table to query the corresponding conditional branch instruction block address and determine the specific processing method for the packet with the current state value. Figure 4 is the structural framework diagram of the conditional branch judgment submodule.

[0054] The state update submodule and the packet header vector action submodule implement the following steps: based on the very long instruction word read from the instruction storage module, the current packet header vector and the state information modification and update instruction are determined. The arithmetic logic unit modifies the packet header vector and updates the state value according to the instruction.

[0055] The aforementioned VLIW (Very Long Instruction Word) is a computer instruction set architecture (ISE) that features highly parallel instructions. Multiple unrelated instructions are bundled into a single VLIW. Processors that support VLIWs are constructed from multiple independent functional components. This structure simplifies hardware design and provides strong data processing capabilities.

[0056] The implementation steps of the reorder buffer are as follows: the reorder buffer stores the packet header vectors completed by the pipeline, writes them to the corresponding address of the queue according to the ROB ID, and submits the out-of-order packet header vectors in order.

[0057] FIG5 is a flow chart of a state-programmable data plane.

[0058] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0059] Example 1

[0060] Embodiment 1 of the present invention proposes a data plane status programmable system based on FPGA. A specific description is given using the implementation of counting TCP retransmission packets and a weighted round-robin algorithm as an example. If other custom algorithms need to be implemented, they can be designed according to this principle.

[0061] Calculate the number of TCP retransmitted packets. This algorithm works by determining whether a packet is a retransmitted packet based on the seq number in the TCP packet and the latest valid seq number of the corresponding flow. If the seq number of the currently received packet is the same as or less than the seq number of the latest packet in the corresponding flow recorded by the module, the received packet is considered a retransmitted packet. The flow state variable Num is used to record the number of retransmitted packets for a flow.

[0062] The implementation method of the algorithm in this application is to sequentially configure the corresponding instructions and table entries of the data plane state programmable module components: programmable key value extraction module, matching table, state storage module, programmable condition judgment module, and state update module. First, the programmable key value extraction module will issue an instruction to extract the five-tuple (source IP address, destination IP address, source port number, destination port number, protocol number) from the packet header vector to form the Key to be matched. The flow matching table and the flow state storage module together constitute the flow state matching table shown below. The flow matching table matches the key value to obtain the flow state address, which is used to read the flow state information (R0, R1) from the storage module, which are: the cumulative number of retransmitted packets of the flow to which the data packet belongs, flow i .Num; serial number flow i .Seq, as shown in Table 1 below.

[0063] Table 1 Calculation of TCP retransmission packet count-flow state matching table

[0064] Table 2 Calculation of TCP retransmission packet number - conditional branch matching table

[0065] The state update and action arithmetic logic unit executes the corresponding instructions for updating state information and modifying packet header vectors according to the very long instruction word read from the instruction storage module. In the current application of calculating the number of TCP retransmitted packets, the seq sequence number of the flow to which it belongs is updated according to the result of the conditional branch judgment. i .Seq) or the number of retransmitted packets (flow i .Num) increases by 1.

[0066] Example 2

[0067] Embodiment 2 of the present invention proposes a data plane state programmable system based on FPGA to implement a weighted round-robin scheduling algorithm.

[0068] Weighted round-robin scheduling is a load balancing algorithm that works by round-robin based on the weights of the available paths at the current node. Arriving packets select the path corresponding to the current weight. After selecting that path, the current weight is decremented by 1. This process continues until the weight of the currently selected path reaches 0, returns to its initial value, and then jumps to the next available path. This process repeats until the weight of the currently selected path reaches 0, returns to its initial value, and then jumps to the next available path.

[0069] The following uses the application of eight optional path weights as an example to illustrate the application of the data plane state programmable module, explaining the corresponding instruction configuration and matching action table entries of each data plane state programmable module. The data plane table state storage module sends information such as the current node optional path set: {path[0], path[1], ..., path[7]}, and the initial weight value of each path of the current node: {init[0], init[1], ..., init[7]}. Each packet header vector that enters the matching action table can obtain the above table state information.

[0070] The programmable key value extraction module extracts the optional path set of the table state information and the corresponding field of the packet header vector according to the issued instructions, and generates the optional path subset mask of the data packet at the current node as the input query key value of the flow state matching table.

[0071] In the flow state matching table shown in Table 3 below, the variables {w0, w1, ..., w7} represent the current weights of the eight possible paths for the flow, and the variables {nxt_w0, nxt_w1, ..., nxt_w7} represent the next hop path number of the current path. The index value ranges from 0 to 7, representing the current possible path number for the flow. This matching table indicates flow state information such as the path number and path weight of the current flow.

[0072] Table 3 Weighted Round Robin Scheduling-Flow State Matching Table

[0073] In the conditional branch judgment module, the state can be used as a matching domain or as an input to the arithmetic logic unit. The module judges whether the current weight value has enough surplus according to the issued instruction. If the current weight value is greater than 1, it continues to select the current path, otherwise it jumps to the next optional path: (the corresponding state update operation index = nxt_w index The key value generated by the module enters the TCAM conditional branch matching table shown in Table 4 below, matches the corresponding conditional branch, obtains the instruction block address of the corresponding conditional branch, and reads the very long instruction word from the instruction storage module according to the address.

[0074] Table 4 Weighted Round Robin Scheduling - Conditional Branch Matching Table

[0075] The status update and action module executes the corresponding update status information and modification packet header vector operations according to the super long instruction word read out by the bear instruction storage module. In the current weighted polling scheduling application, the module will update the weight value (W i ) and index, and modify the corresponding indication path field in the packet header vector.

[0076] The conditional branch judgment module, state update, and action module are composed of several parallel basic arithmetic logic units (ALUs). The overall ALU architecture is shown in Figure 6. Its inputs are two 32-bit operands, oprand0 and oprand1, and a 32-bit instruction. Its output is a 32-bit result. The ALU supports 32-bit, 16-bit, and 8-bit bit-width operations and comparisons. The variable suffixes B3, B2, B1, B0, H1, H0, and W in Figure 6 represent 8-bit, 16-bit, and 32-bit inputs, respectively, and their relative positions within the 32-bit input width. The ALU supports selection of relative input and output data addresses (e.g., result.B3 = oprand0.B0 + oprand1.B2; instructions allow selection of input data addresses and specification of output data addresses), offering high programmability and flexibility.

[0077] It should be noted that the above two embodiments are only for illustrating how to implement the system in combination with specific data forwarding algorithms, and are not limited to the above algorithms.

[0078] Example 3

[0079] An embodiment of the present invention provides a switch having the system of embodiment 1 or embodiment 2.

[0080] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is merely a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A data plane state programmable system based on FPGA, characterized in that: The system includes a matching action table pipeline having multiple stages; The multi-level matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module is used to implement different data plane processing forwarding algorithms according to the read configuration instructions, combined with the flow state matching table and the conditional branch matching table; wherein the matching action table module includes: A key value extraction module is used to extract fields from the packet header vector, the global state and / or the table state information according to the issued instructions to form a key value to be matched; The flow state query module is used to match the flow address information of the packet from the flow state matching table according to the key value to be matched, and read the corresponding flow state information based on this address; The packet header vector transmission queue is used to dynamically schedule the packet header vector for out-of-order transmission based on the flow state address and dependency relationship in the flow state information, using the flow state address in the flow state information as an identifier; An action module, configured to determine a custom data plane processing forwarding algorithm through a conditional branch matching table according to the read configuration instruction, process the flow state information corresponding to the packet header vector transmitted out of order, and update the flow state information and table state information; and The packet header vector reordering cache module is used to store the executed packet header vectors and submit the disordered packet header vectors in order.

2. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The output of each matching action table module can be used as the input of the subsequent matching action table module.

3. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The flow state matching table is a ternary content addressable memory matching table, a hash matching table or a longest prefix matching table.

4. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The packet header vector transmission queue includes: The scoreboard is used to record the read and write operations of the flow state, and to determine whether the flow state of the packet header vector entering the packet header vector transmission queue depends on the write-back results of other packet header vectors to be executed; The packet header vector transmission queue is used to cache the input packet header vector into the free table entry; The selection logic is used to select a packet header vector with the longest time for which flow state information is ready from the packet header vector transmission queue in each clock cycle and transmit it to the action module, while the packet header vector for which flow state information is not ready continues to wait.

5. The FPGA-based data plane state programmable system according to claim 1, characterized in that: The configuration instruction adopts a very long instruction word structure to encapsulate multiple instructions with no data dependency into one very long instruction word.

6. The FPGA-based data plane state programmable system according to claim 5, characterized in that: The action module includes a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule, wherein: The conditional branch judgment submodule is used to select fields from the packet header vector and the status information according to the configuration instruction, input them into several arithmetic logic units for calculating the comparison results that are executed in parallel and support very long instruction words, and determine the corresponding specific data plane processing forwarding algorithm in the conditional branch matching table according to the comparison result; The status update submodule is used to update the status information according to the configuration instructions; The packet header vector action submodule is used to modify the packet header vector.

7. A switch, characterized in that: A data plane state programmable system based on FPGA comprising any one of claims 1-6.

Images