Hybrid passivated back contact cell and post-texturing method for removing undercut residual mask layer

Abstract

The present disclosure relates to the technical field of hybrid passivated back contact cell preparation, and in particular to a post-texturing method for removing an undercut residual mask layer and a hybrid passivated back contact cell prepared by the method. The method comprises: S101, providing a double-side polished and cleaned silicon wafer; S102, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S103, forming a second semiconductor opening region on the back side; S104, first, performing texturing by means of an alkali solution, forming a textured surface on the front side of the silicon wafer, and forming an edge undercut region on the side edge of the second semiconductor opening region; then performing cleaning by means of an ultrasonic process, and performing cleaning by means of a cleaning solution; S105, forming a passivation layer on the front side; S106, forming a second semiconductor layer on the back side; and S107, forming an anti-reflection layer on the front side. The present disclosure significantly improves the passivation effect, simplifies the process flow, improves the reliability of products, and prolongs the minority carrier lifetime of batteries, thereby improving the cell conversion efficiency.

Description

Post-texturing method for combined passivation of back contact cell and removal of side-etching residual mask layer

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2023111984395 filed with the Chinese Patent Office on September 18, 2023, entitled “Combined passivation back contact cell and post-texturing method for removing side-etching residual mask layer”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure belongs to the technical field of preparation of combined passivation back contact cells, and particularly relates to a post-texturing method for removing a side-etching residual mask layer and a combined passivation back contact cell prepared by the method. Background Art

[0004] The structure of the back-contact heterojunction solar cell is generally a front-side texturing and back-side polishing structure. The silicon wafer of this structure is generally formed by first texturing on both sides and then protecting one side and then polishing, or first polishing on both sides and then protecting one side and then texturing. The preparation process is very complicated, and after forming the second semiconductor opening, too strong alkaline solution cannot be used for cleaning, which can easily cause side corrosion or damage to the first semiconductor layer.

[0005] In order to solve the technical problems of the above-mentioned complex preparation process, a post-texturing method has been proposed in the art. However, post-texturing also has the following new technical problems:

[0006] ① The first semiconductor layer is an amorphous / microcrystalline layer, which has poor acid and alkali resistance and needs to be processed through a strong alkaline solution for post-texturing. Although the first semiconductor layer is protected by a mask layer, there are defects such as dust particles and contact damage during the preparation of the mask layer. After passing through the strong alkaline solution, the defective area is quickly etched and enlarged, resulting in a large number of defects in the first semiconductor layer under the mask layer, which in turn affects the passivation of the silicon wafer surface.

[0007] ② During texturing, the bulk silicon in the second semiconductor opening area is generally etched away by 2-6μm. However, the mask layer is essentially unreactive with the alkali solution, resulting in a large amount of side erosion at the edge of the second semiconductor opening area (as shown in Figure 4c). The mask layer in the side erosion area is suspended. The mask layer in the side erosion area blocks the deposition of the second semiconductor layer, preventing the side erosion area from being passivated, significantly reducing the minority carrier lifetime of the battery and, in turn, reducing battery efficiency.

[0008] Summary of the Invention

[0009] The purpose of the present invention is to overcome the defect of the prior art that the post-texturing method will reduce the battery conversion efficiency, and to provide a post-texturing method for a combined passivation back contact battery and a removal of the side-etched residual mask layer. The combined passivation back contact battery obtained by the post-texturing method significantly improves the passivation effect, simplifies the process flow, improves the reliability of the product, greatly improves the electrical efficiency loss caused by carrier transmission, and increases the minority carrier life of the battery, thereby improving the battery conversion efficiency.

[0010] In order to achieve the above objectives, in a first aspect, the present disclosure provides a post-texturing method for removing a side-etching residual mask layer of a combined passivated back contact cell, comprising the following steps:

[0011] S101, providing double-sided polished and cleaned silicon wafers;

[0012] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer, and the mask layer is inorganic silicon;

[0013] S103, performing a first etching opening on the first semiconductor layer on the back surface obtained in S102 to form second semiconductor opening regions distributed at intervals, and the width of the second semiconductor opening regions is Wp1;

[0014] S104, first performing texturing with an alkaline solution to form a textured surface on the front side of the silicon wafer, and simultaneously forming a textured surface on the inner bottom surface of the second semiconductor opening region, and simultaneously forming an edge undercut region at the side edge of the second semiconductor opening region, wherein the mask layer in the edge undercut region extends and protrudes into the second semiconductor opening region, and the maximum width of the edge undercut region is Wp2, and satisfies: Wp2 / (Wp1+2×Wp2)=(1-25):1000;

[0015] Afterwards, the mask layer is cleaned by ultrasonic cleaning to remove part of the mask layer in the edge undercut area and retain the mask layer outside the edge undercut area; and then the mask layer is cleaned by cleaning solution;

[0016] S105, forming a passivation layer on the front surface obtained in S104;

[0017] S106, forming a second semiconductor layer on the back surface obtained in S105, wherein the second semiconductor layer includes an intrinsic silicon crystal layer and a second doped silicon crystal layer;

[0018] S107, forming an anti-reflection layer on the front surface obtained in S106.

[0019] In some preferred embodiments of the present disclosure, Wp1 = 0.4-0.6 mm, and Wp2 = 1-5 μm.

[0020] Preferably, the thickness of the mask layer is D1, where D1 = 30-110 nm.

[0021] In some preferred embodiments of the present disclosure, the mask layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide and organic protective ink.

[0022] In some preferred embodiments of the present disclosure, the conditions of the ultrasonic process include: a frequency of 20-80 kHz, a power of 100-2000 W, and a time of 30-120 s.

[0023] Preferably, the cleaning liquid used in the ultrasonic cleaning process is water or a mixed solution.

[0024] Preferably, the mass concentration of the solute in the mixed solution is 0-5wt%, and the solute is selected from at least one of ammonia water, sodium hydroxide, potassium hydroxide, and hydrogen peroxide.

[0025] In some preferred embodiments of the present disclosure, in S104, the texturing conditions include: a mass concentration of alkali in the alkaline solution of 0.5-5 wt%, a temperature of the alkaline solution of 65-85°C, and a treatment time of 5-15 minutes. The alkaline solution also includes a texturing additive, and the mass concentration of the texturing additive is 0.05-0.5 wt%.

[0026] In some preferred embodiments of the present disclosure, in S105 , the passivation layer is an intrinsic amorphous layer or an amorphous silicon oxide layer.

[0027] In some preferred embodiments of the present disclosure, S105 further includes a step of forming an N-type doped silicon layer after forming the passivation layer.

[0028] In some preferred embodiments of the present disclosure, the thickness of the tunneling oxide layer in the first semiconductor layer is 1.5-2.5 nm, and the thickness of the first doped polycrystalline layer is 50-200 nm; the thickness of the intrinsic silicon crystal layer in the second semiconductor layer is 5-15 nm, and the thickness of the second doped silicon crystal layer is 5-20 nm.

[0029] In some preferred embodiments of the present disclosure, the post-texturing method further comprises:

[0030] S108, performing a second etching opening on the back surface obtained in S107 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, with a transition region formed between the first semiconductor opening region and the second semiconductor opening region, and the transition region having a width Wg; then removing the mask layer corresponding to the first semiconductor opening region by acid etching to expose the first semiconductor layer;

[0031] S109, depositing a conductive film layer on the back surface obtained in S108;

[0032] S110, performing a third etching opening on the portion of the conductive film layer located in the transition region Wg on the back side obtained in S109, to form an insulating groove with an insulating layer width of Wi;

[0033] S111 , forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back side obtained in S110 .

[0034] In a second aspect, the present disclosure provides a combined passivation back contact cell, which is prepared by the post-texturing method described in the first aspect. Beneficial effects:

[0035] The present disclosure adopts the above-mentioned technical scheme, especially in the post-texturing method of the combined passivation structure, texturing is performed after the second semiconductor opening area is formed, thereby simplifying the process flow, and the residual mask layer in the edge side etch area with a certain structure generated by the texturing in the post-texturing method is removed by ultrasonic cleaning. On the one hand, it removes the residual mask layer in the edge side etch area, thereby avoiding the problem that the residual mask layer in the edge side etch area affects the bottom passivation, improving the passivation effect, and cooperating with the combined passivation structure, greatly improving the electrical efficiency loss caused by the transmission of carriers in the isolation area, thereby improving the battery efficiency; and there is no need to etch all the mask layers cleanly, reducing the time for removing the mask layer, and further simplifying the process flow; on the second hand, it retains the mask layer in the area outside the opening area, especially retaining the mask layer in the corresponding area of ​​the insulating groove to form protection, thereby avoiding the possibility of leakage current and improving the reliability of the product. The edge erosion area formed by texturing has the structure described above. Part of the mask layer in the edge erosion area is in a moderately suspended state. During ultrasonic cleaning, the microbubbles in the cleaning liquid can maintain vibration under the action of the sound waves, thereby vibrating, breaking, and peeling off the suspended mask layer in the edge erosion area. However, the mask layer in the non-edge erosion area has good adhesion to the silicon wafer and is therefore not peeled off. Under the same conditions, if the width of the edge erosion area is not appropriate, the ultrasonic cleaning liquid will not be able to fully fill the edge erosion area, and effective vibration will not be achieved, resulting in the inability to effectively remove the protruding portion of the mask layer in the edge erosion area through the ultrasonic process.

[0036] Furthermore, the present invention eliminates the need for specialized front-side texturing and back-side polishing silicon wafers. Texturing can be performed only after the second semiconductor opening is formed, significantly simplifying the battery manufacturing process and improving process stability, making it more suitable for large-scale production. Specifically, the first doped polycrystalline layer in the combined passivation structure employed in the present invention replaces the conventional amorphous / microcrystalline layer, significantly enhancing acid and alkali resistance and enabling texturing after the first semiconductor layer is deposited (i.e., post-texturing).

[0037] Furthermore, the present invention forms the anti-reflection layer on the front side after forming the second semiconductor layer on the back side, thus avoiding the adverse effects of the anti-reflection layer's bypass plating on the passivation interface between the second semiconductor layer and the silicon wafer. In the prior art, the anti-reflection layer is typically formed immediately after the passivation layer, and then the second semiconductor layer is formed. Forming the anti-reflection layer before the second semiconductor layer can lead to bypass plating, resulting in a very thin anti-reflection layer also being plated on the back side, thereby affecting the passivation effect on the interface between the silicon wafer on the back side of the cell and the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0039] FIG1 shows an N-type single crystal silicon wafer after polishing and cleaning provided in Example 1 of the present disclosure;

[0040] FIG2 a is a schematic structural diagram of forming a tunneling oxide layer and an intrinsic polycrystalline layer on the back side of a silicon wafer in accordance with Embodiment 1 of the present disclosure;

[0041] FIG2 b is a schematic structural diagram of forming an N-type doped polycrystalline layer and a phosphosilicate glass layer on the back side of a silicon wafer using a high-temperature diffusion technique according to Example 1 of the present disclosure;

[0042] FIG2c is a schematic structural diagram of the removal of the phosphosilicate glass layer on the back side of the silicon wafer according to Example 1 of the present disclosure;

[0043] FIG2 d is a schematic diagram of the structure of forming a mask layer on the back of a silicon wafer using chemical vapor deposition technology in Example 1 of the present disclosure, and a schematic diagram of the structure of directly forming a tunneling oxide layer, an N-type doped polycrystalline layer and a mask layer on the back of a silicon wafer using a polycrystalline deposition device in Example 2;

[0044] FIG3 is a schematic structural diagram of forming a second semiconductor opening region on the back side of a silicon wafer using a laser process according to an embodiment of the present disclosure;

[0045] FIG4a is a schematic structural diagram of forming a pyramid texture surface on the front side of a silicon wafer, forming a pyramid texture surface at the bottom of a second semiconductor opening region on the back side of the silicon wafer, and forming an edge undercut region on the edge thereof by texturing in Example 1 of the present disclosure;

[0046] FIG4 b is a schematic structural diagram of removing residual silicon nitride in the edge undercut region caused by texturing by ultrasonic cleaning in Example 1 of the present disclosure;

[0047] FIG4 c is a SEM image magnified 24,000 times of the edge undercut region formed at the edge of the second semiconductor opening region on the back side of the silicon wafer in Example 1 of the present disclosure;

[0048] FIG4 d is a SEM image magnified 24,000 times in Example 1 of the present disclosure after ultrasonic cleaning of silicon nitride at the edge of the second semiconductor opening region on the back side of the silicon wafer;

[0049] FIG5 is a schematic structural diagram of forming a passivation layer on the front side of a silicon wafer using PECVD technology in Example 1 of the present disclosure;

[0050] FIG6 is a schematic structural diagram of forming an intrinsic amorphous layer and a P-type doped amorphous layer on the back side of a silicon wafer using PECVD technology in Example 1 of the present disclosure;

[0051] FIG7 is a schematic structural diagram of forming an anti-reflection layer on the front side of a silicon wafer using PECVD technology in Example 1 of the present disclosure;

[0052] FIG8 a is a schematic structural diagram of forming an N-type first semiconductor opening region spaced apart from a P-type second semiconductor opening region in a polished area on the back side of a silicon wafer using laser technology according to the first embodiment of the present disclosure;

[0053] FIG8 b is a structural diagram of removing the surface mask layer of the N-type first semiconductor opening region according to the first embodiment of the present disclosure;

[0054] FIG9 is a schematic structural diagram of forming a conductive film layer on the back side of a silicon wafer using physical vapor deposition technology in Example 1 of the present disclosure;

[0055] FIG10 is a schematic structural diagram of forming an insulating trench between an N-type first semiconductor opening region and a P-type second semiconductor opening region on the back side of a silicon wafer using laser technology in accordance with the first embodiment of the present disclosure;

[0056] FIG11 is a schematic structural diagram of metal electrodes arranged alternately formed on an N-type first semiconductor opening region and a P-type second semiconductor opening region on the back side of a silicon wafer using printed silver paste in Example 1 of the present disclosure.

[0057] Explanation of the reference numerals: 10, silicon wafer, 11, tunneling oxide layer, 12, N-type doped polycrystalline layer, 12a, intrinsic polycrystalline layer, 12b, phosphosilicate glass layer, 13, mask layer, 14i, passivation layer, 14n, N-type doped silicon layer, 15i, intrinsic amorphous layer, 15p, P-type doped amorphous layer, 16, anti-reflection layer, 17, conductive film layer, 18n, first electrode, 18p, second electrode. DETAILED DESCRIPTION

[0058] In this disclosure, unless otherwise specified, directional words such as "up, down, left, right" are generally understood in combination with the directions shown in the drawings and actual applications, and "inside and outside" refer to the inside and outside of the outline of the component.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0060] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0061] In this disclosure, the area close to the silicon wafer is referred to as the inner area, and the area away from the silicon wafer is referred to as the outer area. In this disclosure, width refers to the dimension in a direction parallel to the silicon wafer (such as the direction in the figure), and thickness refers to the dimension in a direction perpendicular to the silicon wafer.

[0062] In a first aspect, the present disclosure provides a post-texturing method for removing a residual mask layer of a combined passivated back contact cell, comprising the following steps:

[0063] S101, providing double-sided polished and cleaned silicon wafers;

[0064] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer, and the mask layer is inorganic silicon;

[0065] S103, performing a first etching opening on the first semiconductor layer on the back surface obtained in S102 to form second semiconductor opening regions distributed at intervals, and the width of the second semiconductor opening regions is Wp1;

[0066] S104, first performing texturing with an alkaline solution to form a textured surface on the front side of the silicon wafer, and simultaneously forming a textured surface on the inner bottom surface of the second semiconductor opening region, and simultaneously forming an edge undercut region at the side edge of the second semiconductor opening region, wherein the mask layer in the edge undercut region extends and protrudes into the second semiconductor opening region, and the maximum width of the edge undercut region is Wp2, and satisfies: Wp2 / (Wp1+2×Wp2)=(1-25):1000;

[0067] After that, the wafer is cleaned with an ultrasonic process to remove part of the mask layer in the edge undercut area, while retaining the mask layer outside the edge undercut area. The wafer is then cleaned with a cleaning solution to remove organic matter, metal ions, and oxide layers on the surface of the wafer.

[0068] S105, forming a passivation layer on the front surface obtained in S104;

[0069] S106, forming a second semiconductor layer on the back surface obtained in S105, wherein the second semiconductor layer includes an intrinsic silicon crystal layer and a second doped silicon crystal layer;

[0070] S107, forming an anti-reflection layer on the front surface obtained in S106.

[0071] The double-side polishing conditions in S101 can be performed according to conventional techniques. For example, an alkaline solution having a temperature of 70-90° C. and a mass concentration of alkali of 3%-8% can be used. The alkali can be, for example, potassium hydroxide or sodium hydroxide. The silicon wafer can be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0072] In the present disclosure, conventional operations such as cleaning may be performed after the double-sided polishing in S101. For example, SC1 cleaning solution, SC2 solution, HF solution, etc. may be used for cleaning, and the concentration of each solution is determined according to the prior art and actual needs.

[0073] The process of forming the first semiconductor layer in S102 can be carried out according to the methods in the prior art, such as using LPCVD to grow the tunnel oxide layer and the intrinsic polycrystalline layer and then diffusing them. Alternatively, the tunnel oxide layer and the first doped polycrystalline layer can be directly deposited using a plasma deposition device. Specifically, for example, the tunnel oxide layer can be formed using low-pressure chemical vapor deposition (LPCVD) technology. The conditions for forming the tunnel oxide layer include: introducing oxygen, a process pressure of 100-100,000 Pa, an oxidation temperature of 550-700°C, an oxidation time of 5-60 minutes, and evacuating and purging after oxidation. For example, the formation of the first doped polycrystalline layer may include: first using low-pressure chemical vapor deposition (LPCVD) technology to deposit an undoped intrinsic polycrystalline layer on the surface of the tunnel oxide layer on the back side; then performing phosphorus diffusion, keeping the back side of the silicon wafer exposed during the phosphorus diffusion process to form a phosphosilicate glass layer; and then removing the phosphosilicate glass layer. Wherein, the deposition of the intrinsic polycrystalline layer can adopt LPCVD technology, and the conditions for depositing the intrinsic polycrystalline layer include: introducing silane, a process pressure of 10-100Pa, a deposition temperature of 550-700℃, a deposition time of 5-80min, and an intrinsic polycrystalline layer thickness of 50-200nm. Wherein, the phosphorus diffusion process may include, for example, introducing oxygen, small nitrogen carrying phosphorus oxychloride (i.e., nitrogen containing phosphorus oxychloride, wherein the mass proportion of phosphorus oxychloride in the small nitrogen can be 1%-20%), large nitrogen (i.e., pure nitrogen) and other process gases, the process pressure is 50-10000Pa, the diffusion temperature is 700-925℃, the diffusion time is 10-120min, and the effective doping concentration of phosphorus after diffusion can be 1e19-4e20cm -3 After the diffusion, the intrinsic polycrystalline layer is transformed into a first doped polycrystalline layer, and a phosphosilicate glass layer is formed on the surface of the first doped polycrystalline layer. The removal of the phosphosilicate glass layer can be performed by, for example, treating with hydrofluoric acid.

[0074] The mask layer can be formed by those skilled in the art according to methods in the prior art, for example, plasma chemical vapor deposition (PECVD) technology can be used.

[0075] The type of the mask layer can be any type as long as it can withstand the high temperature alkaline texturing solution. In some preferred embodiments of the present disclosure, the mask layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide and organic protective ink.

[0076] In S103, the first etching opening method can adopt any etching method in the prior art, for example, a laser process can be adopted, the laser can be a green light or ultraviolet laser, and the laser pulse width is less than 100ns; the laser directly etches away the mask layer or the mask layer and the first semiconductor layer.

[0077] In S104, the dimensions of Wp1 and Wp2 only need to satisfy the aforementioned proportional relationship. In some preferred embodiments of the present disclosure, Wp1 = 0.4-0.6 mm, and Wp2 = 1-5 μm. This preferred solution can more effectively remove the portion of the mask layer within the edge undercut region, thereby improving the passivation effect and the battery conversion efficiency.

[0078] Preferably, the thickness of the mask layer is D1, where D1 = 30-110 nm.

[0079] The textured surface obtained in S104 is a pyramid textured surface. It can be understood that there are edge undercut regions on both sides of the second semiconductor opening region.

[0080] In some preferred embodiments of the present disclosure, the conditions of the ultrasonic process include: a frequency of 20-80 kHz, a power of 100-2000 W, and a time of 30-120 s.

[0081] More preferably, the ultrasonic process conditions include: a frequency of 20-40 kHz, a power of 200-1000 W, and a duration of 30-100 seconds. This preferred solution can more fully vibrate the edge erosion area, effectively removing the portion of the mask layer within the edge erosion area, and preventing the second semiconductor layer from being unable to be deposited in the portion of the mask layer within the edge erosion area, thereby affecting the passivation of the portion of the mask layer within the edge erosion area. This is more conducive to improving the passivation effect and increasing the battery conversion efficiency.

[0082] Preferably, the cleaning liquid used in the ultrasonic cleaning process is water or a mixed solution.

[0083] The mixed solution can be an aqueous solution of a weak acid or a weak base. The mass concentration of the solute in the mixed solution is 0.1-5wt%, and the solute is selected from at least one of ammonia water, sodium hydroxide, potassium hydroxide, and hydrogen peroxide.

[0084] The cleaning performed by the cleaning solution disclosed herein is conventional cleaning in the art, and those skilled in the art can select a cleaning solution as needed. For example, the cleaning solution includes SC1 solution, SC2 solution, HF solution, etc. SC1 solution and SC2 solution are corresponding standard cleaning solutions. SC1 solution is composed of a mixture of ammonia water, hydrogen peroxide, and water in a volume ratio of 1:2:50. SC2 solution is composed of a mixture of hydrochloric acid, hydrogen peroxide, and water in a volume ratio of 1:1:50. The mass concentration of HF in the HF solution is 0.5-5wt%.

[0085] In some preferred embodiments of the present disclosure, in S104, the texturing conditions include: the mass concentration of the alkali in the alkaline solution is 0.5-5wt%, the temperature of the alkaline solution is 65-85°C, and the processing time is 5-15 minutes. This preferred solution can obtain the edge erosion area under the aforementioned structure, which is more compatible with the ultrasonic process, thereby efficiently removing part of the mask layer in the edge erosion area, which is more conducive to improving the passivation effect and improving the battery conversion efficiency. The alkali in the texturing can be, for example, sodium hydroxide and / or potassium hydroxide.

[0086] The alkaline solution may also include conventional additives such as texturing additives, which are commercially available. Preferably, the mass concentration of the texturing additives is 0.05-0.5 wt%.

[0087] Preferably, in S104, Wp2 / (Wp1+2×Wp2)=(1-8): 1000. This preferred solution is more conducive to improving the passivation effect of the battery, thereby further improving the conversion efficiency of the battery.

[0088] In S104 , after the ultrasonic cleaning process, the cleaning process using a cleaning solution is conventional cleaning, which is the same as the cleaning in S101 .

[0089] In some preferred embodiments of the present disclosure, in S105 , the passivation layer is at least one of an intrinsic amorphous layer and an amorphous silicon oxide layer.

[0090] Preferably, the passivation layer is an amorphous silicon layer and has a thickness of 5-10 nm.

[0091] In some preferred embodiments of the present disclosure, S105 further includes a step of forming an N-type doped silicon layer after forming the passivation layer.

[0092] In some preferred embodiments of the present disclosure, the thickness of the tunnel oxide layer in the first semiconductor layer is 1.5-2.5 nm, and the thickness of the first doped polycrystalline layer is 50-200 nm.

[0093] Preferably, the thickness of the intrinsic silicon crystal layer in the second semiconductor layer is 5-15 nm, and the thickness of the second doped silicon crystal layer is 5-20 nm.

[0094] The intrinsic silicon crystal layer may be an intrinsic amorphous layer or an intrinsic microcrystalline layer, and the second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer.

[0095] The effective doping concentrations of the first doped polycrystalline layer and the second doped silicon crystal layer can adopt the corresponding ranges in the prior art in this field, such as the concentration ranges in the applicant's early patents on the combined passivation structure, which will not be repeated here.

[0096] One of the first doped polycrystalline layer and the second doped silicon crystal layer is N-type, and the other is P-type.

[0097] The second semiconductor layer can be formed by depositing according to any corresponding method in the prior art, as long as the desired type of layer and its thickness and doping concentration are obtained. For example, PECVD technology can be used.

[0098] The type, thickness, and formation method of the anti-reflection layer described in S107 can all be performed according to conventional techniques. For example, the anti-reflection layer can be at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the thickness of the anti-reflection layer can be 80-160 nm. Preferably, the anti-reflection layer is a composite layer of silicon nitride and silicon oxide, with a thickness ratio of silicon nitride to silicon oxide of 1:1-2. The anti-reflection layer can be formed using, for example, PECVD technology.

[0099] In some preferred embodiments of the present disclosure, the post-texturing method also includes: S108, performing a second etching opening on the back side obtained in S107 to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region, and forming a transition region between the first semiconductor opening region and the second semiconductor opening, and the width of the transition region is Wg; then removing the corresponding mask layer in the first semiconductor opening region by acid corrosion to expose the first semiconductor layer.

[0100] The second etched opening can be formed using laser technology, for example. Preferably, the laser used to form the second etched opening is a green or ultraviolet laser with a pulse width of less than 100 ns. The laser directly etches away a portion of the mask layer and the second semiconductor layer to form a first semiconductor opening region with a width of Wn and a width of Wg for the transition region. Preferably, Wn is 0.1-0.3 mm, and Wg is 0.1-0.3 mm.

[0101] Other conventional layers such as a conductive film layer can also be formed in the post-texturing method disclosed herein.

[0102] In some preferred embodiments of the present disclosure, the post-texturing method further includes: S109, depositing a conductive film layer on the back surface obtained in S108. The conductive film layer can be formed, for example, using physical vapor deposition technology or activated reactive plasma technology. The type and thickness of the conductive film layer can be selected within the corresponding ranges in the prior art and are not limited in this disclosure. For example, the thickness can be 50-130 nm.

[0103] In some preferred embodiments of the present disclosure, the post-texturing method further includes: S110, performing a third etching opening on the portion of the conductive film layer located in the transition region Wg on the back obtained in S109 to form an insulating groove with an insulating layer width Wi. Wi can be, for example, 0.03-0.1 mm.

[0104] The third etched opening can be formed, for example, using laser technology, or by etching after printing or spraying a protective layer. Preferably, the laser used to form the third etched opening is an ultraviolet laser with a pulse width of less than 10ns, and the laser directly etches away a portion of the mask layer, the second semiconductor layer, and the conductive film layer in the insulating trench region.

[0105] In some preferred embodiments of the present disclosure, the post-texturing method further includes: S111, forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back surface obtained in S110. The metal electrodes can be formed, for example, by silver paste printing, or by electroplating copper grid metal or PVD metal film coating instead of metal electrodes.

[0106] In a second aspect, the present disclosure provides a combined passivation back contact cell, which is prepared by the post-texturing method described in the first aspect. The combined passivation back contact cell disclosed in the present disclosure has high product reliability and high cell conversion efficiency.

[0107] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0108] Example 1

[0109] A post-texturing method for removing a side-etching residual mask layer of a combined passivated back contact cell comprises the following steps:

[0110] S101, as shown in FIG1 , providing an N-type single crystal silicon wafer 10 after double-sided polishing and cleaning;

[0111] The silicon wafer 10 was polished with a potassium hydroxide solution having a temperature of 80° C. and a mass concentration of 5%, and then the surface of the silicon wafer 10 was cleaned with an SC1 cleaning solution (which consists of a mixture of ammonia water, hydrogen peroxide, and water in a volume ratio of 1:2:50). The silicon wafer was a Czochralski single crystal silicon wafer.

[0112] S102, as shown in FIG2a, FIG2b, FIG2c, and FIG2d, a first semiconductor layer and a mask layer 13 are sequentially formed on the back side of the silicon wafer 10, wherein the first semiconductor layer includes a tunneling oxide layer 11 and an N-type doped polycrystalline layer 12;

[0113] S102a. As shown in FIG2a , a tunneling oxide layer 11 and an intrinsic polycrystalline layer 12a are formed on the back side of the silicon wafer 10 by using low-pressure chemical vapor deposition (LPCVD) technology. LPCVD is used for depositing the tunneling oxide layer 11, and the process includes: introducing oxygen, a process pressure of 70,000 Pa, an oxidation temperature of 610° C., an oxidation time of 20 min, and a thickness of the tunneling oxide layer 11 of 2 nm. After the tunneling silicon oxide 11 is formed, the gas is evacuated and washed, and then the intrinsic polycrystalline layer 12a is deposited. LPCVD is used for depositing the intrinsic polycrystalline layer 12a, and the process includes: introducing silane, a process pressure of 80 Pa, a deposition temperature of 610° C., a deposition time of 60 min, and a thickness of the intrinsic polycrystalline layer 12a of 60 nm.

[0114] S102b, as shown in FIG2b, the silicon wafer 10 is placed in a diffusion furnace for diffusion gettering, and oxygen, small nitrogen carrying phosphorus oxychloride (the mass proportion of phosphorus oxychloride in the small nitrogen is 10%), and large nitrogen are introduced. The volume flow ratio of oxygen, small nitrogen carrying phosphorus oxychloride, and large nitrogen is 2:1:1. The process pressure is 80 Pa, the diffusion temperature is 880°C, and the diffusion time is 60 minutes. After diffusion, the intrinsic polycrystalline layer 12a is transformed into an N-type doped polycrystalline layer 12, and a phosphorus silicon glass layer 12b is formed on the surface of the N-type doped polycrystalline layer 12. The effective doping concentration of the N-type doped polycrystalline layer 12 is 2e20cm -3 .

[0115] S102c, as shown in FIG2c, the silicon wafer 10 is treated with hydrofluoric acid (HF) to remove the phosphosilicate glass layer 12b on the surface of the silicon wafer.

[0116] S102d, as shown in FIG2d, a mask layer 13 is formed on the back side of the silicon wafer 10 by plasma chemical vapor deposition (PECVD) technology. The mask layer 13 is silicon nitride, and the thickness D1 of the mask layer 13 is 100 nm.

[0117] S103. As shown in FIG3 , a first etching opening is performed on the back side of silicon wafer 10 to form a P-type second semiconductor opening region with a width Wp1. The first etching opening is performed using a laser process, wherein the laser is a green or ultraviolet laser with a pulse width of 10 ps. The laser directly etches away the mask layer 13 and a portion of the first semiconductor layer within the first etching opening region. The width Wp1 is 0.5 mm.

[0118] S104. As shown in FIG4a, texturing is performed using an alkaline solution. The texturing conditions include: a mass concentration of 2 wt% of the alkali in the alkaline solution, a mass concentration of 0.2 wt% of the texturing additive (commercially available), a temperature of 70°C, and a treatment time of 12 minutes. A pyramid texture is formed on the front surface of the silicon wafer 10, and a pyramid texture and an edge erosion region Wp2 are formed on the bottom and side surfaces of the second semiconductor opening region, respectively. The maximum width of the edge erosion region Wp2 is 2 μm. FIG4c is a SEM image of the edge erosion region Wp2 at a magnification of 24,000 times. Wp = Wp1 + 2 × Wp2, Wp2 / (Wp1 ​​+ 2 × Wp2) = 4:1000.

[0119] As shown in Figure 4b, ultrasonic cleaning was performed at a frequency of 40 kHz, a power of 500 W, and a duration of 50 seconds, thereby removing the mask layer 13 from the edge undercut region Wp2, while retaining the mask layer 13 outside the edge undercut region. Figure 4d shows a 24,000x magnification SEM image after removing the mask layer 13 from the edge undercut region Wp2.

[0120] The silicon wafer is then cleaned with a cleaning solution, SC1 solution (a mixture of ammonia, hydrogen peroxide, and water in a volume ratio of 1:2:50), to remove organic matter, metal ions, and oxide layers on the surface of the silicon wafer.

[0121] S105. As shown in FIG5 , a passivation layer 14i and an N-type doped silicon layer 14n are formed on the front surface of the silicon wafer 10 by using PECVD technology. The passivation layer 14i is intrinsic amorphous silicon with a thickness of 5 nm, and the N-type doped silicon layer 14n is an N-type doped microcrystalline silicon layer with a thickness of 8 nm.

[0122] S106. As shown in FIG6 , a second semiconductor layer is formed on the back of the silicon wafer 10 using PECVD technology: an intrinsic amorphous layer 15i and a P-type doped amorphous layer 15p. The thickness of the intrinsic amorphous layer 15i is 6 nm, and the thickness of the P-type doped amorphous layer 15p is 6 nm. The effective doping concentration of the P-type doped amorphous layer 15p is 1e20 cm -3 .

[0123] S107, as shown in FIG7, using PECVD technology to form an anti-reflection layer 16 on the front surface of the silicon wafer 10, wherein the anti-reflection layer 16 is a composite layer of silicon nitride and silicon oxide, and the thickness of the anti-reflection layer 16 is 150 nm, and the thickness ratio of silicon nitride to silicon oxide is 1:2;

[0124] S108. As shown in FIG8a, a laser technique is used to form an N-type first semiconductor opening region with a width Wn spaced apart from a P-type second semiconductor opening region on the polished area on the back side of the silicon wafer 10. A transition region with a width Wg is formed between the first semiconductor opening region and the second semiconductor opening region. Wg is the width of the transition region.

[0125] The laser is a green or ultraviolet laser with a pulse width of 10 ps. The laser directly etches away part of the mask layer 13, the intrinsic amorphous layer 15i, and the P-type doped amorphous layer 15p to form an N-type first semiconductor opening region Wn, where Wn is 0.2 mm and Wg is 0.15 mm.

[0126] As shown in FIG. 8 b , the mask layer 13 on the inner surface of the N-type first semiconductor opening region Wn is removed by etching with hydrofluoric acid.

[0127] S109 , as shown in FIG9 , forming a conductive film layer 17 on the back side of the silicon wafer 10 by using physical vapor deposition technology; the conductive film layer 17 is indium tin oxide (ITO) with a thickness of 50 nm.

[0128] S110. As shown in FIG10 , an insulating trench having a width Wi is formed between the N-type first semiconductor opening region Wn and the P-type second semiconductor opening region Wp on the back side of the silicon wafer 10 using laser technology. The insulating layer has a width Wi. The laser is an ultraviolet laser with a pulse width of 5 ps. The laser directly etches away portions of the mask layer 13, the intrinsic amorphous layer 15i, the P-type doped amorphous layer 15p, and the conductive film layer 17 in the insulating trench Wi region. Wi is 0.03 mm.

[0129] S111 , as shown in FIG11 , using printing technology, first electrodes 18 n and second electrodes 18 p are formed in an alternate arrangement in the N-type opening region Wn and the P-type opening region Wp on the back side of the silicon wafer 10 .

[0130] Example 2

[0131] The method of Example 1 is referred to, except that the texturing in S104 is such that Wp2 / (Wp1+2×Wp2)=1:100, Wp2=5μm; the texturing process parameters are changed accordingly: the mass concentration of the alkali in the alkaline solution is 5wt%, the mass solubility of the texturing additive (same as Example 1) is 0.5wt%, the temperature of the solution is 85℃, and the processing time is 15min.

[0132] Example 3

[0133] The method of Example 1 is referred to, except that the ultrasonic cleaning parameters are changed in S104: the power is 100 W, and the time is 60 s. The ultrasonic power is too low, so that the mask layer 13 in the edge undercut area Wp2 is not completely removed.

[0134] Example 4

[0135] The method of Example 1 was referred to, except that the key parameters of ultrasonic cleaning were changed in S104: the power was 2000 W and the time was 60 s. The ultrasonic power was too high, causing damage to the first semiconductor layer.

[0136] Comparative Example 1

[0137] The method of Example 1 is referred to, except that the ultrasonic cleaning in S104 is not performed.

[0138] Comparative Example 2

[0139] The method of Example 1 is followed, except that after texturing in S104, ultrasonic cleaning is not performed, but S105 is performed directly, and then all mask layers are removed, followed by subsequent steps such as S106. The method for removing all mask layers is to etch with a 10% hydrofluoric acid solution for 10 minutes.

[0140] Comparative Example 3

[0141] The method of Example 1 is referred to, except that a conventional texturing method is used, that is, the silicon wafer is first textured on the front side and then polished on the back side, as follows:

[0142] S1, double-sided polishing of silicon wafer;

[0143] S2, coating the back of the silicon wafer with a first mask layer for protection, wherein the first mask layer is silicon nitride;

[0144] S3, cleaning the silicon wafer to form a pyramid texture surface on the opposite side of the first mask layer (i.e., the front side), and then removing the first mask layer to form a silicon wafer with a textured front side and polished back side;

[0145] S4, coating the first semiconductor layer and the mask layer in sequence on the back side of the silicon wafer;

[0146] S5, performing the first etching opening on the back side of the silicon wafer to form a second semiconductor opening region;

[0147] S6, cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area;

[0148] S7, forming a passivation layer, an N-type doped silicon layer and an anti-reflection layer in sequence on the front side of the silicon wafer, and forming a second semiconductor layer on the back side;

[0149] Then, steps S108 to S111 of Example 1 are performed.

[0150] Test Case

[0151] The combined passivated back contact cells prepared in the above embodiments and comparative examples were respectively used to collect different preparation process index parameters, and IV tests were performed on the prepared back contact cells. The process index parameters, such as process cycle, production yield and conversion efficiency, were extracted and compared based on 10,000 pieces. The results are shown in Table 1 below.

[0152] Table 1

[0153] It can be seen from the results in Table 1 above that the combined passivation back contact battery produced by the present disclosure using the post-texturing method of removing the residual mask layer after side etching can greatly shorten the process cycle, improve the production yield, thereby improving product reliability and improving the battery conversion efficiency. The comparative examples that are not within the scope of the present disclosure cannot simultaneously take into account the comprehensive effects of short process cycle, low leakage current and high battery conversion efficiency. Specifically, according to Example 1 and Comparative Example 1 of the present disclosure, it can be seen that the solution of adding ultrasonic cleaning to remove part of the mask layer in the edge side etching area after texturing of the present disclosure is more conducive to improving the passivation effect of the battery, thereby helping to improve the conversion efficiency of the battery. According to Example 1 and Comparative Example 2 of the present disclosure, it can be seen that the solution of retaining the mask layer outside the edge side etching area after texturing of the present disclosure is more conducive to reducing leakage current, thereby helping to improve the conversion efficiency of the battery. According to Example 1 and Comparative Example 3 of the present disclosure, it can be seen that the solution of the present disclosure is more conducive to shortening the process cycle.

[0154] Furthermore, according to Example 1 and Example 2 of the present disclosure, it can be seen that the use of the preferred texturing parameter scheme of the present disclosure is more conducive to improving the passivation effect of the battery, thereby further improving the conversion efficiency of the battery.

[0155] Furthermore, according to Examples 1 and 3-4 of the present disclosure, it can be seen that the use of the preferred ultrasonic cleaning process of the present disclosure is more conducive to improving the passivation effect of the battery, reducing leakage current, and further improving the battery conversion efficiency.

[0156] The preferred embodiments of the present disclosure are described in detail above, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0157] The present disclosure provides a combined passivation back contact battery and a post-texturing method for removing the side-etched residual mask layer. The combined passivation back contact battery produced by the post-texturing method significantly improves the passivation effect, simplifies the process flow, improves product reliability, greatly improves the electrical efficiency loss caused by carrier transmission, and increases the minority carrier life of the battery, thereby improving the battery conversion efficiency.

Claims

1. A post-texturing method for removing the residual mask layer of the side etching of a combined passivation back contact cell, comprising the following steps: S101, providing double-sided polished and cleaned silicon wafers; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer, and the mask layer is inorganic silicon; S103, performing a first etching opening on the first semiconductor layer on the back surface obtained in S102 to form second semiconductor opening regions distributed at intervals and having a width of Wp1; It is characterized by further comprising: S104, firstly, texturing is performed by using an alkaline solution to form a textured surface on the front side of the silicon wafer, and at the same time, a textured surface is formed on the inner bottom surface of the second semiconductor opening area, and at the same time, an edge side etching area is formed on the side edge of the second semiconductor opening area, and the mask layer in the edge side etching area extends and protrudes into the second semiconductor opening area, and the maximum width of the edge side etching area is Wp2, and satisfies: Wp2 / (Wp1+2×Wp2)=(1-25):1000; Afterwards, the device is cleaned by an ultrasonic process to remove part of the mask layer in the edge undercut region and retain the mask layer outside the edge undercut region; and then, the device is cleaned by a cleaning solution; S105, forming a passivation layer on the front surface obtained in S104; S106, forming a second semiconductor layer on the back surface obtained in S105, wherein the second semiconductor layer includes an intrinsic silicon crystal layer and a second doped silicon crystal layer; S107, forming an anti-reflection layer on the front surface obtained in S106.

2. The post-texturing method according to claim 1, characterized in that: Wp1=0.4-0.6mm, Wp2=1-5μm.

3. The post-texturing method according to claim 1, characterized in that: The mask layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide and organic protective ink; And / or, the thickness of the mask layer is D1, D1=30-110 nm.

4. The post-texturing method according to claim 1, characterized in that: The conditions of the ultrasonic process include: frequency of 20-80kHz, power of 100-2000W, and time of 30-120s.

5. The post-texturing method according to claim 1, characterized in that: The cleaning liquid used in the ultrasonic cleaning process is water or a mixed solution, the mass concentration of the solute in the mixed solution is 0-5wt%, and the solute is selected from at least one of ammonia water, sodium hydroxide, potassium hydroxide, and hydrogen peroxide.

6. The post-texturing method according to claim 1, characterized in that: In S104, the texturing conditions include: the mass concentration of the alkali in the alkali solution is 0.5-5wt%, the temperature of the alkali solution is 65-85°C, and the treatment time is 5-15min.

7. The post-texturing method according to claim 1, characterized in that: In S105, the passivation layer is an intrinsic amorphous layer or an amorphous silicon oxide layer; And / or, S105 further includes a step of forming an N-type doped silicon layer after forming the passivation layer.

8. The post-texturing method according to claim 1, characterized in that: The thickness of the tunnel oxide layer in the first semiconductor layer is 1.5-2.5 nm, and the thickness of the first doped polycrystalline layer is 50-200 nm; the thickness of the intrinsic silicon crystal layer in the second semiconductor layer is 5-15 nm, and the thickness of the second doped silicon crystal layer is 5-20 nm.

9. The post-texturing method according to claim 1, characterized in that: The post-texturing method also includes: S108, performing a second etching opening on the back surface obtained in S107 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and forming a transition region between the first semiconductor opening region and the second semiconductor opening region, and the width of the transition region is Wg; then removing the corresponding mask layer in the first semiconductor opening region by acid etching to expose the first semiconductor layer; S109, depositing a conductive film layer on the back surface obtained in S108; S110, performing a third etching opening on the portion of the conductive film layer located in the transition region Wg on the back side obtained in S109 to form an insulating groove with an insulating layer width of Wi; S111 , forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back side obtained in S110 .

10. A combined passivation back contact cell, characterized in that: It is prepared by the post-texturing method as described in any one of claims 1 to 9.

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