Device management system, computer system, and data transmission method

Abstract

Disclosed are a device management system, a computer system, and a data transmission method, which relate to the field of computers. The computer system comprises a device management system and a plurality of processing systems, wherein a management controller of the device management system is connected to the plurality of processing systems by means of interface chips; and the interface chips of the device management system is used for receiving data sent by the plurality of processing systems or sending data to the plurality of processing systems, such that data convergence and distribution are implemented for the plurality of processing systems. In this way, compared with a solution of separately providing a corresponding device management system for each processing system, only one device management system is required to perform communication management on a plurality of independent processing systems, thereby simplifying the topology structure of an overall architecture for managing a plurality of processing systems.

Description

Equipment management system, computer system and data transmission method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 19, 2023, with application number 202311221717.4 and application name “Equipment Management System, Computer System and Data Transmission Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computers, and in particular to a device management system, a computer system, and a data transmission method. Background Art

[0003] As processor performance improves, a single or small number of processors can now independently handle most types of business. Therefore, a single computing node or server in a data center can be divided into multiple processing systems, each used to independently handle business.

[0004] Typically, a device management system connects to one processing system. When a computing node or server in a data center contains multiple processing systems, a corresponding device management system is required for each processing system, enabling point-to-point management communication between each device management system and the processing system. Consequently, device management systems that manage and communicate with multiple processing systems present a complex topology.

[0005] Summary of the Invention

[0006] The present application provides a device management system, a computer system, and a data transmission method, thereby reducing the topological complexity of the overall architecture for managing a multi-processing system.

[0007] In a first aspect, the present application provides a device management system, comprising a management controller and an interface chip. The management controller is connected to the interface chip via a first bus, and the interface chip is configured to connect to multiple processing systems via a second bus. The interface chip is configured to receive data from the multiple processing systems and forward the data from the multiple processing systems to the management controller. The management controller is configured to process the data from the multiple processing systems.

[0008] Based on this device management system, the device management system uses an interface chip to aggregate data sent from multiple processing systems and forwards this data to a management controller, enabling a single management controller to communicate with and manage multiple processing systems. This simplifies the topology of the overall hardware architecture for managing multiple processing systems, compared to having a separate device management system for each processing system, and reduces hardware costs.

[0009] In one possible embodiment, the device management system further includes registers, which are connected to the management controller and the interface chip via a first bus. When forwarding data to the management controller, the interface chip is specifically configured to store data sent by a first processing system among the multiple processing systems into a first register corresponding to the first processing system, so that the management controller can read the data sent by the first processing system from the first register and process the data sent by the first processing system. In this way, the device management system uses different registers to store data sent by different processing systems, and the management controller can distinguish data sent by different processing systems from different registers, thereby supporting communication between a single management controller and multiple processing systems.

[0010] In a possible embodiment, the device management system also includes a memory, and the memory is connected to the management controller and the interface chip respectively through the first bus. When forwarding data to the management controller, the interface chip is specifically used to store the data sent by the first processing system among the multiple processing systems into the address space corresponding to the first processing system in the memory, so that the management controller reads the data sent by the first processing system from the address space corresponding to the first processing system in the memory, and processes the data sent by the first processing system. In this way, the device management system divides the address space in the memory, and stores data sent by different processing systems in different address spaces. The management controller can distinguish the data sent by different processing systems based on the address space, thereby supporting communication between one management controller and multiple processing systems. Optionally, the interface chip of the device management system includes multiple bus interfaces, and the interface chip can be connected to a processing system respectively through each bus interface. In this way, the device management system can connect to the buses of multiple processing systems through multiple bus interfaces, thereby communicating with multiple processing systems.

[0011] Optionally, because the first and second buses may be of different types, the interface chip may also have a data format conversion function. Specifically, the interface chip is configured to convert data sent by the processing systems from the data format of the second bus to the data format of the first bus, and then transmit the data from multiple processing systems to the management controller via the first bus. This allows the interface chip to transmit data from multiple processing systems to the management controller via a single first bus, simplifying the management controller's circuit complexity.

[0012] In one possible implementation, the device management system and multiple processing systems communicate based on the Intelligent Platform Management Interface (IPMI) protocol, and the above data includes keyboard controller style (KCS) data, system management interface chip (SMIC) data and / or block transfer BT (BT) data.

[0013] In a possible implementation, when the data includes block-transmitted data, the interface chip includes a block-transmitted channel connected to the management controller via a first bus. The block-transmitted channel is used to send and receive the block-transmitted data.

[0014] As a possible implementation, the multiple processing systems include a first processing system, the first processing system also includes a second interface chip, the second interface chip is connected to the processor via a third bus, and the second interface chip is connected to the first interface chip via a second bus. The data of the first processing system includes block transmission data, and the block transmission data includes a reset request, BT control information, BT interrupt mask information, BT data, and BT data. The third bus is used to transmit the block transmission data to the second interface chip via an address latch signal line, a write enable signal line, and an address / data signal line. The second interface chip is specifically used to parse the data transmitted by the address / data signal line based on the address latch signal of the address latch signal line and the write enable signal of the write enable signal line, obtain the reset request, BT control information, BT interrupt mask information, and BT data, generate an identity identifier of the BT data, and send the reset request, BT control information, BT interrupt mask information, BT data, and the identity identifier of the BT data to the second bus, where the identity identifier is used to indicate the first processing system.

[0015] Optionally, the interface chip further includes a control interface, and the interface chip is connected to the management controller via the control interface.

[0016] When the data is in the memory or register, an interrupt signal is output through the control interface to instruct the management controller to read the data from the memory or register and process the data. In this way, the communication efficiency between the device management system and the processing system is improved.

[0017] Optionally, the management controller uses a polling method to sequentially read the data of each processing system in the memory or register in each polling cycle. This reduces the number of interfaces between the management controller and the interface chip, further simplifies the topology, and reduces hardware costs.

[0018] In one possible embodiment, the first bus is a local bus, a serial peripheral interface (SPI) bus, or a universal serial bus (USB). In this way, compared to the management controller providing only one low pin count bus (LPC) interface, the interface can aggregate and transmit inter-board signals such as keyboard controller style data, system management interface chip data, and block transmission data through multiple signal lines of the low pin count bus, and transmit them to the management controller through the first bus, thereby reducing the number of pins and cables between the device management system and the processing system, simplifying the topology of the overall architecture, and reducing hardware costs.

[0019] In one possible implementation, the management controller is further configured to send data to the interface chip. The interface chip is further configured to receive data sent by the management controller and distribute the data sent by the management controller to multiple processing systems. This allows the device management system to send data to multiple processing systems, enabling data transmission and reception between the device management system and multiple processing systems, thereby improving communication flexibility.

[0020] In a second aspect, the present application provides a computer system. The computer system includes a device management system and multiple processing systems. The device management system includes a management controller and a first interface chip. The multiple processing systems include a first processing system. The first processing system includes a processor. The management controller is connected to the first interface chip via a first bus. The first interface chip is used to connect to the first processing system via a second bus. The processor of the first processing system is used to generate data and send data to the first interface chip of the device management system. The first interface chip of the device management system is used to receive data and send data to the management controller. The management controller is used to process data from the multiple processing systems.

[0021] In a possible implementation, the processor is one of a central processing unit (CPU), a graphics processing unit (GPU), and a neural-network processing unit (NPU).

[0022] In one possible embodiment, the multiple processing systems include a first processing system, the first processing system also includes a second interface chip, the second interface chip is connected to the processor via a third bus, and the second interface chip is connected to the first interface chip via the second bus. The data of the first processing system includes block transmission data, and the block transmission data includes a reset request, BT control information, BT interrupt mask information, BT data, and BT data. The third bus is used to transmit the block transmission data to the second interface chip via the address latch signal line, the write enable signal line, and the address / data signal line. The second interface chip is specifically used to parse the data transmitted by the address / data signal line based on the address latch signal of the address latch signal line and the write enable signal of the write enable signal line, obtain the reset request, BT control information, BT interrupt mask information, and BT data, generate an identity identifier of the BT data, and send the reset request, BT control information, BT interrupt mask information, BT data, and the identity identifier of the BT data to the second bus, where the identity identifier is used to indicate the first processing system.

[0023] In a possible implementation, the second bus is specifically used to transmit a reset request, BT control information, BT interrupt mask information, BT data and an identity of the BT data to the first interface chip through an address latch signal line, a write enable signal line and an address / data signal line.

[0024] In one possible implementation, because the second bus and the third bus may be of different types, the second interface chip may also have a data format conversion function. The second interface chip of the processing system is specifically configured to convert data from the data format of the third bus to the data format of the second bus, and then transmit the data to the device management system via the second bus.

[0025] In a possible implementation, the third bus is a local bus, a serial peripheral interface bus, or a universal serial bus.

[0026] In one possible implementation, in addition to the processing system sending data to the device management system, the device management system can also send data to the processing system. For example, the device management system sending data to the first processing system involves the management controller sending data to the first interface chip of the device management system. The first interface chip forwards the data to the second interface chip of the first processing system, which then forwards the data to the processor.

[0027] Optionally, the management controller stores the data whose recipient is the first processing system into a first register corresponding to the first processing system or an address space corresponding to the first processing system in a memory, so that the first interface chip of the device management system forwards the data in the first register or the address space corresponding to the first processing system to the second interface chip of the first processing system.

[0028] In one possible implementation, the second interface chip of the first processing system further includes a control interface, and the second interface chip is connected to the processor of the first processing system via the control interface. The second interface chip is further configured to output an interrupt signal via the control interface when sending data to the processor. The interrupt signal is configured to trigger the processor to process the data.

[0029] In a third aspect, the present application provides a data transmission method for a computer system described in any embodiment of the second aspect. The computer system includes a device management system and multiple processing systems, the device management system includes a management controller and a first interface chip, the multiple processing systems include a first processing system, the first processing system includes a processor, and the first interface chip is used to connect to the first processing system through a second bus. The data transmission method includes: first, the processor of the first processing system generates data and sends the data to the first interface chip. Then, the first interface chip receives the data from the first processing system and sends the data to the management controller. Finally, the management controller processes the data of the first processing system. The processing system that sends data to the device management system can be one or more of the multiple processing systems, and the management controller can read and process the data of the multiple processing systems.

[0030] In one possible implementation, the device management system further includes a register, which is connected to the management controller and the interface chip via a first bus. When forwarding data to the management controller, the interface chip is specifically configured to store data sent by a first processing system among the multiple processing systems into a first register corresponding to the first processing system, so that the management controller reads the data sent by the first processing system from the first register and processes the data sent by the first processing system.

[0031] In one possible embodiment, the device management system further includes a memory, which is connected to the management controller and the interface chip via a first bus. When forwarding data to the management controller, the interface chip is specifically configured to store data sent by a first processing system among the multiple processing systems into an address space in the memory corresponding to the first processing system, so that the management controller reads the data sent by the first processing system from the address space in the memory corresponding to the first processing system and processes the data sent by the first processing system.

[0032] In one possible implementation, the first processing system further includes a second interface chip, which is connected to the first interface chip via a second bus. The second interface chip is connected to the processor via a third bus. The processor generates data and sends the data to the first interface chip via the second interface chip.

[0033] Optionally, before sending data to the first interface chip, the second interface chip adds an identity identifier to the data, where the identity identifier is used to indicate the processing system that sends the data.

[0034] In a possible implementation, in addition to sending data to the device management system, the processing system may also receive data sent by the device management system. The specific steps may refer to the relevant description of the second aspect above and will not be repeated here.

[0035] In a possible implementation, when the second interface chip of the first processing system sends data to the processor of the first processing system, the second interface chip sends an interrupt signal to the processor, wherein the interrupt signal is used to trigger the processor to process data.

[0036] Regarding the technical principles and beneficial effects of the second and third aspects, please refer to the relevant description of the first aspect mentioned above and will not be repeated here.

[0037] In a fourth aspect, a readable storage medium is provided. The readable storage medium includes a computer program or instructions that, when executed on a computer, causes the computer to execute the data transmission method described in any possible implementation of the third aspect.

[0038] In a fifth aspect, a computer program product is provided, which includes a computer program or instructions, and when the computer program or instructions are executed on a computer, the computer executes the data transmission method described in any possible implementation of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic diagram of the architecture of a traditional server's processing chip and BMC;

[0040] FIG2a is a schematic diagram of the architecture of a computer system provided by the present application;

[0041] FIG2b is a schematic diagram of the architecture of another computer system provided by the present application;

[0042] FIG3 is a schematic diagram of a data center scenario provided by this application;

[0043] FIG4 is a schematic diagram of a server scenario provided by this application;

[0044] FIG5 is a flow chart of a data transmission method provided by the present application;

[0045] FIG6 is a schematic diagram showing the working principle of an interface chip provided by the present application;

[0046] FIG7 is a schematic diagram of the structure of a computing device provided in this application. DETAILED DESCRIPTION

[0047] The device management system, computer system, and data transmission method provided in the embodiments of the present application can be applied to communication scenarios in which a device management system manages multiple processing systems. The following is a brief introduction to the technologies that may be involved in this application.

[0048] (1) Baseboard Management Controller

[0049] The baseboard management controller (BMC) is a dedicated controller used to monitor and manage servers. Its main functions include device information management, server status monitoring and management, remote server control and management, and maintenance management. The BMC is an independent system that operates independently of other system hardware (such as the CPU and memory). However, the BMC can communicate with the basic input and output system (BIOS) and operating system (OS), and thus with the systems managed by the BMC, to perform platform management.

[0050] (2) Network management

[0051] Network management can be divided into two management modes: out-of-band management and in-band management.

[0052] In-band management refers to the transmission of network management and control information and user network service information over the same logical channel. Out-of-band management refers to the transmission of network management and control information and user network service information over separate logical channels. For example, a baseboard management controller managing a server's CPU is considered out-of-band management. The baseboard management controller is an out-of-band system, while the server's CPU is an in-band system.

[0053] (3) Bus

[0054] A bus is a public communication trunk line for transmitting data between various functional components of a computer. It is a transmission bundle composed of wires.

[0055] According to the type of data transmitted by the computer, the computer bus can be divided into data bus, address bus and control bus, etc.

[0056] Computer buses can be categorized as parallel or serial buses based on the method of information transmission. Parallel buses require n signal lines to transmit n bits of data in parallel. Serial buses transmit data bit by bit on a single line, while parallel buses require n signal lines to transmit data in parallel.

[0057] For example, the reduced pin bus, local bus, and peripheral component interconnect (PCI) bus are parallel buses. Also, the bidirectional two-wire synchronous serial inter-integrated circuit (I2C) bus, peripheral component interconnect express (PCIe) bus, serial peripheral interface bus, and universal serial bus are serial buses.

[0058] The following describes a traditional one-to-one communication method between a device management system and a processing system, using a device management system including a BMC and a processing system including a server processor as an example. The processor can be a CPU, GPU, NPU, or southbridge chip (platform controller hub).

[0059] As shown in Figure 1, the server's processor and BMC are usually connected through an LPC interface to transmit BT data between the processor and the BMC. A BMC usually provides one LPC interface, including a clock signal interface, a request input signal interface, a frame valid signal interface, an address / data multiplexing signal interface, a reset signal interface, etc., to connect to the processor through clock signal lines, request input signal lines, frame valid signal lines, address / data multiplexing signal lines, reset signal lines, etc. Therefore, in a computing node composed of multiple independent processors, a BMC that matches the number of processors is required. Each independent processor requires multiple signal lines to connect to the BMC. For each additional processor, the server needs to add multiple connector pins (pins) and multiple signal lines. In addition, in order to ensure signal interaction and level type matching between the power domains of the processor and the BMC, multiple isolation devices need to be added to the processor and the BMC.

[0060] Among them, the device management system can be regarded as an out-of-band management system, and the processing system can be regarded as an in-band system.

[0061] It can be seen that the communication architecture between the existing equipment management system and the processing system has the problems of complex topology and high hardware cost.

[0062] This application provides a device management system, particularly a device management system that forwards data from multiple processing systems via an interface chip. The device management system includes an interface chip and a management controller, which is connected to the first interface chip via a first bus. The interface chip is configured to receive data from the multiple processing systems via a second bus and transmit the data to the management controller. The management controller is configured to process the data from the multiple processing systems.

[0063] This application provides a computer system, particularly a computer system that forwards data between a device management system and multiple processing systems via an interface chip. The computer system includes a device management system and multiple processing systems. The device management system includes a first interface chip and a management controller, which is connected to the first interface chip via a first bus. The multiple processing systems include a first processing system, which includes a processor, which is connected to the first interface chip of the device management system via a second bus.

[0064] Taking the first processing system among multiple processing systems as an example, the processor of the first processing system is used to generate data and send the data to the first interface chip of the device management system. The first interface chip of the device management system is used to receive data from the multiple processing systems and forward the data from the multiple processing systems to the management controller, which processes the data from the multiple processing systems.

[0065] Based on the aforementioned device management system and computer system, the device management system uses an interface chip to aggregate data sent from multiple processing systems and forwards this data to a management controller, enabling a single management controller to communicate with multiple processing systems and thus manage the devices of multiple processing systems. This simplifies the overall hardware architecture topology of the device management system for managing multiple processing systems, compared to setting up a separate device management system for each processing system, and reduces hardware costs.

[0066] The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0067] FIG2 a is a schematic diagram of the architecture of a computer system provided in this application. As shown in FIG2 a , the computer system 200 may include a device management system 210 and multiple processing systems. The device management system 210 and the multiple processing systems are connected via a bus 220 .

[0068] The device management system 210 may include a management controller 211 and an interface chip 212. The management controller 211 and the interface chip 212 are connected via a bus 213. The interface chip 212 may be considered a first interface chip, and the bus 213 may be considered a first bus.

[0069] Optionally, the management controller 211 may be a baseboard management controller (BMC). The following describes the computer system 200 and the data transmission method, etc., by taking the management controller 211 as an example.

[0070] Optionally, each device management system 210 is connected to a processing system via a bus 220 , that is, the number of processing systems in the computer system 200 is the same as the number of buses 220 .

[0071] As a possible implementation, the types of logic devices that can be used by the interface chip 212 include: field programmable gate array (FPGA), complex programmable logic device (CPLD), microcontroller unit (MCU), etc.

[0072] As a possible implementation manner, the device management system 210 further includes a register.

[0073] Alternatively, the register interface chip 212 includes multiple registers as a logic device. The multiple registers are registers corresponding to different offset addresses, and the offset addresses correspond to the processing systems one-to-one, and are used to store data sent to the management controller 211 or data received from the management controller 211.

[0074] In another possible implementation, the device management system 210 may use a memory instead of a register.

[0075] Optionally, different address spaces in the memory correspond one-to-one to the processing systems, and are used to store data sent to the management controller 211 or data received from the management controller 211 .

[0076] The present application does not limit the configuration mode of the memory. For example, the memory is a memory belonging to the interface chip 212 , or the memory is an external memory connected to the interface chip 212 .

[0077] Optionally, the bus 213 may be a local bus, an SPI bus, a PCIe bus, a USB bus, or other types of buses.

[0078] The embodiment of the present application does not limit the number of processing systems included in the computer system 200. FIG2 a only shows the processing system 230 and the processing system 240 as examples.

[0079] Processing system 230 includes a processor 231 and an interface chip 232. Processor 231 and interface chip 232 are connected via bus 233, and interface chip 232 is connected to interface chip 212 via bus 220. Processing system 230 can be considered a first processing system, interface chip 232 can be considered a second interface chip, bus 233 can be considered a third bus, and bus 220 can be considered a second bus.

[0080] Processing system 240 includes a processor 241 and an interface chip 242. Processor 241 and interface chip 242 are connected via bus 243, and interface chip 242 is connected to interface chip 212 via bus 220. Because processing system 240 and processing system 230 have the same structure and operating principle, the following description will only use processing system 230 as an example, and processing systems other than processing system 230 will not be described in detail.

[0081] In another possible embodiment, as shown in FIG2b , when processors 231 and 241 have data conversion functions, processing systems 230 and 240 may not include an interface chip. Processors 241 and 241 are connected to interface chip 212 via bus 220, and processors 231 and 241 transmit generated data to bus 220 in accordance with the data format of bus 220. Bus 220 may be a local bus, SPI bus, PCIe bus, USB bus, or other type of bus.

[0082] As a possible implementation, the types of logic devices that can be used by the interface chip 232 include: field programmable gate array (FPGA), complex programmable logic device (CPLD), microcontroller unit (MCU), etc.

[0083] Optionally, the bus 233 may be a local bus, an SPI bus, a PCIe bus, a USB bus, or other types of buses.

[0084] Alternatively, bus 220 may be a serial bus such as an I2C bus or a Hisport bus. The Hisport bus is a high-speed asynchronous serial interface that uses time-division multiplexing to transmit data in frames. Different frames send different data (e.g., data from different processing systems), enabling the transmission of different types of low-speed signals within a single data channel. For example, processing system 230, which includes a CPU in a server, is connected to the bus 220 via a connector on the substrate to which processing system 230 belongs and a connector on the substrate to which device management system 210 belongs, respectively.

[0085] In some possible embodiments, the processing system 230 may include multiple processors, and the multiple processors belong to the same processing system.

[0086] The internal structure and connection relationship of the processing systems other than the processing system 230 included in the computer system 200, such as the processing system 240, can be referred to as the processing system 230, and will not be repeated here.

[0087] It is worth noting that Figures 2a and 2b are merely schematic diagrams provided herein and should not be construed as limiting the present application. The computer system 200 may also include other components or modules not shown in Figures 2a and 2b. For example, the management controller 211 and the interface chip 212 may be provided with hardware modules or software modules to implement the logical functions of the management controller 211 and the interface chip 212. The specific architecture of these modules is shown in Figure 6 and will not be further described here.

[0088] Because the processing system can be considered the master in a master-slave communication architecture, and the device management system can be considered the slave in a master-slave communication architecture, the application scenarios of the computer system 200 provided in this application are not limited to an architecture with a single device management system and multiple processing systems. It can also be applied to an architecture with a single slave and multiple masters performing master-slave communication. The structure and connection relationship between the device management system 210 and the out-of-band system 230 included in the computer system 200 is merely an example provided in this application.

[0089] The above-mentioned computer system 200 provided in this application can be applied to communication scenarios between a device management system and multiple processing systems, such as scenarios in which computing nodes in a data center communicate with a device management system, and scenarios in which a processing system composed of multiple processors in a server is divided into multiple processing systems, and multiple processing systems communicate with a device management system, etc.

[0090] For example, in a computing node of a data center, taking the processing system as an in-band system and the device management system as an out-of-band management system as an example, as shown in FIG3 , each computing node includes multiple (8 as an example in FIG3 ) independent in-band systems 310, and each in-band system 310 includes multiple CPUs (2 as an example in FIG3 ). Each in-band system 310 exchanges data with the out-of-band management system 320, thereby realizing communication management of multiple in-band systems 310 by one out-of-band management system 320. Optionally, the computing node may further include a network card module 330, a switching module 340, a sensor module 350, and a heat dissipation control module 360, etc. The network card module 330 is respectively connected to the in-band system 310, the sensor module 350 and the heat dissipation control module 360 ​​are respectively connected to the out-of-band management system 320, and the switching module 340 is used to communicate with other computing nodes, which will not be repeated here.

[0091] For another example, as shown in FIG4 , taking the processing system as an in-band system and the device management system as an out-of-band management system, in an in-band system comprising a server with four CPUs, the server is constructed from two identical dual-CPU modules stacked together, each of which is divided into an independent in-band system 410. Each in-band system 410 exchanges data with an out-of-band management system 420 via interface chip 212 and interface chip 232, enabling communication management of multiple in-band systems 410 by a single out-of-band management system 420.

[0092] The above briefly describes the architecture of the computer system 200 in conjunction with Figures 2a, 2b, 3 and 4. The following describes the data interaction method of the computer system 200 in conjunction with Figure 5 using the communication scenario of the processing system and the device management system.

[0093] As shown in Figure 5, the device management system 210 includes a management controller 211. The management controller 211 can manage the devices of the server substrate. The processing system 230 is a processing system in the server substrate. The processor 231 can be a CPU, GPU, NPU or other type of processor.

[0094] The data between the device management system 210 and the processing system 230, that is, the data between the management controller 211 and the processor 231, includes BT data. In order to integrate the BT data between the management controller 211 and the processor 231, a BT module 214 can be set in the management controller 211, and a BT module 234 can be set in the processor 231. The BT module 214 is connected to the interface chip 212 through the bus 213, and the BT module 234 is connected to the interface chip 232 through the bus 233.

[0095] Optionally, the BT module 214 and the BT module 234 may include a BT control register, a first buffer register, a second buffer register, and a BT interrupt register. The BT control register is used to receive a reset signal, the BT interrupt register is used to receive an interrupt signal, the first buffer register serves as a data channel for first data, and the second buffer register serves as a data channel for second data. The first data is data sent by the processor 231 to the management controller 211, and the second data is data sent by the management controller 211 to the processor 231.

[0096] The following describes a data transmission method applied to the computer system 200. The data transmission method may include the following steps 510 to 580.

[0097] Step 510 : The processor 231 sends first data to the interface chip 232 .

[0098] As a possible example, the processor 231 inputs the first data into the BT module 234 , and the BT module 234 sends the first data to the interface chip 232 through the bus 233 , so that the interface chip 232 receives the first data.

[0099] Optionally, the first data may be BT data and control information generated by an operating system (OS) and a basic input output system (BIOS) of the processor 231, and stored by the processor 231 in the BT module 234. The control information may be a reset request, BT control information, BT interrupt mask information, etc.

[0100] Step 520 : The interface chip 232 sends the first data to the interface chip 212 .

[0101] As a possible example, after processing the first data, the interface chip 232 sends the first data to the interface chip 212 through the bus 220 .

[0102] As one possible implementation, the processing of the first data by interface chip 232 includes data conversion and data identification. Data conversion is used to convert the first data from a data format consistent with bus 233 to a data format consistent with bus 220. Data identification is used to add an identifier to the first data that indicates the sender of the first data. The specific steps of the data conversion and data identification are described in detail in FIG. 6 and are not further elaborated here.

[0103] Step 530 : The interface chip 212 sends first data to the management controller 211 .

[0104] As a possible example, the interface chip 212 sends the first data to the management controller 211 , that is, the interface chip 212 stores the first data in a first register corresponding to the processing system 230 .

[0105] As a possible implementation, the interface chip 212 stores the first data in the address space corresponding to the processing system 230 according to the mapping relationship between the processing system and the address space. For example, the memory includes address space 1 to address space 3, where address space 1 is the address space corresponding to the processing system 230, address space 2 is the address space corresponding to the processing system 240, and address space 3 is the address space corresponding to the processing system n.

[0106] Optionally, the mapping relationship between the processing system and the address space is preset when configuring the computer system 200. Taking the multiple registers of the interface chip 212 as an example, registers indicated by different offset addresses correspond to different processing systems. For example, the mapping relationship includes the corresponding relationship between the identity of the processing system 230 and the offset address A.

[0107] For example, the interface chip 212 searches for the offset address A in the mapping relationship according to the identity carried by the first data, and stores the first data into the register indicated by the offset address A.

[0108] In order to improve the communication efficiency and performance between the interface chip 212 and the management controller 211 , after step 530 , the interface chip 212 may further send an interrupt signal to the management controller 211 to trigger the management controller 211 to execute step 540 .

[0109] Step 540: The management controller 211 processes the first data.

[0110] As a possible example, the management controller 211 obtains the data of the multiple processing systems sent by the interface chip 212 through the bus 213 and processes the data of the multiple processing systems. The data of the multiple processing systems sent by the interface chip 212 includes the first data.

[0111] As a possible implementation, after the interface chip 212 stores the first data in the address space corresponding to the processing system 230 in the memory, the management controller 211 reads the first data from the address space corresponding to the processing system 230 in the memory through the bus 213 .

[0112] Optionally, when the management controller 211 receives an interrupt signal from the interface chip 212 , it reads the first data from the address space corresponding to the processing system 230 through the bus 213 .

[0113] The management controller 211 may be connected to the interface chip 212 via a control interface, and the management controller 211 receives an interrupt signal transmitted from the interface chip 212 via the control interface.

[0114] Optionally, the management controller 211 polls the memory of the device management system 210 and reads the first data from the address space corresponding to the processing system 230 through the bus 213 .

[0115] In a possible embodiment, the management controller 211 resets the BT module 214 upon receiving a reset signal from the interface chip 212 , wherein the reset signal is generated by the interface chip 212 according to the reset request from the interface chip 232 and sent to the management controller 211 .

[0116] As a possible implementation method, taking the computing node shown in Figure 3 as an example, the first data sent by the first processing system may be a temperature data request, etc., and the processing of the first data by the management controller 211 may be a response returned based on the temperature data request, which response includes the temperature data of the processor 231.

[0117] The above describes in detail the process of data transmission from processing system 230 to device management system 210 based on steps 510-540. Next, the process of data transmission from in-band management system 210 to out-of-band system 230 will be described based on steps 550-580. Since the process of steps 550-580 is similar to that of steps 510-540, except for the different data transmission directions, steps 550-580 are not shown in FIG5 for the sake of brevity.

[0118] Step 550 : The management controller 211 sends second data to the interface chip 212 .

[0119] As a possible example, the management controller 211 stores the second data in an address space corresponding to the processing system 230 in the memory, so that the interface chip 212 obtains the second data from the address space corresponding to the processing system 230 in the memory.

[0120] As a possible implementation, the management controller 211 inputs the second data into the BT module 214 , and the BT module 214 sends the second data to the memory of the interface chip 212 via the bus 213 to store the second data into the address space corresponding to the out-of-band system 230 in the memory.

[0121] Optionally, the second data may be BT data and control information generated by an operating system (OS) and a basic input output system (BIOS) of the management controller 211 according to the first data, and stored in the BT module 214 by the management controller 211 .

[0122] The second data may be response data obtained after the management controller 211 processes the first data. Taking the computing node shown in FIG3 as an example, the management controller 211 may process the first data by generating response data based on the temperature data request, where the response includes the temperature data of the processor 231, and the second data is the response data including the temperature data of the processor 231.

[0123] Step 560 : The interface chip 212 sends the second data to the processing system 230 .

[0124] As a possible example, the interface chip 212 determines that the recipient of the second data is the processing system 230 according to the mapping relationship between the processing system and the address space, and sends the second data to the processing system 230 through the bus 220 .

[0125] As a possible implementation method, the interface chip 212 reads the second data from the address space corresponding to the processing system 230 in the memory, queries the identity of the processing system 230 in the mapping relationship according to the offset address A of the address space corresponding to the processing system 230, and sends the second data to the processing system 230 through the bus 220.

[0126] Step 570 : The interface chip 232 sends the second data to the processor 231 .

[0127] To improve communication efficiency and performance between the interface chip 232 and the processor 231, after step 570, the interface chip 232 may further send an interrupt signal to the processor 231 to trigger the processor 231 to execute step 580. The process of the interface chip 232 sending the interrupt signal to the processor 231 is similar to the process of the interface chip 212 sending the interrupt signal to the management controller 211, and is not further described here.

[0128] Step 580: The processor 231 processes the second data.

[0129] As a possible example, after the interface chip 232 sends the second data, the processor 231 obtains the second data from the BT module 234 and processes the second data.

[0130] As a possible implementation manner, when the processor 231 receives an interrupt signal from the interface chip 232 , the processor 231 obtains the second data from the BT module 234 and processes the second data.

[0131] As another possible implementation, the processor 231 polls the register of the BT module 234 , obtains the second data from the BT module 234 , and processes the second data.

[0132] In a possible embodiment, the processor 231 resets the BT module 234 upon receiving a reset signal from the interface chip 232 , wherein the reset signal is generated by the interface chip 232 according to the reset request from the interface chip 212 and sent to the processor 231 .

[0133] Taking the computing node shown in Figure 3 as an example, if the second data is response data containing temperature data of the processor 231, the processor 231's processing of the second data can notify the user of the temperature data, determine whether the processor 231 is operating normally based on the temperature data, etc.

[0134] Based on steps 510-580 of the aforementioned data transmission method, the device management system and processing system each use an interface chip to forward data. The interface chip in the device management system aggregates and distributes data from multiple processing systems, thereby enabling communication between a single device management system and multiple processing systems. This allows multiple processing systems to be managed by only one device management system, simplifying the topology for managing multiple processing systems and reducing hardware costs. Compared to the LPC bus, which requires multiple signal lines for signal exchange and requires isolation devices for device management systems and processing systems in different power domains, inter-board signals between a single device management system and processing system are transmitted via a serial bus between the interface chips, reducing the number of cables and pins.

[0135] The above description, combined with FIG5 , details a data transmission method applicable to computer system 200, particularly focusing on the data transmission process between hardware components such as management controller 211, interface chip 212, processor 231, and interface chip 232. To implement the forwarding function of interface chip 212 and interface chip 232, interface chip 212 and interface chip 232 may also be provided with a driver module to process and forward data in a software-driven manner. Next, the operating principle of the driver module of interface chip 212 will be described in conjunction with FIG6 .

[0136] As shown in FIG6 , taking the example of processing system 230 sending first data to in-band management system 210, interface chip 232 of processing system 230 includes, based on programmed driver modules, a data conversion module 235, a buffer processing module 236, and a transmission driver module 237. Correspondingly, interface chip 212 of device management system 210 includes a reception driver module 215, a buffer processing module 216, and a data conversion module 217.

[0137] In the first step, the data conversion module 235 receives the first data from the processor 231 through the bus 233 and performs data analysis and data conversion on the first data.

[0138] As a possible implementation manner, the data conversion module 235 receives the first data transmitted from the address latch signal line, the write enable signal line, and the address / data signal line of the bus 233 .

[0139] Optionally, taking bus 233 as a local bus, the first data includes an address latch signal transmitted by an address latch signal line, a write enable signal transmitted by a write enable signal line, and an address and data transmitted by an address / data signal line. Multiple address / data signal lines may be included for transmitting multi-bit address / data signals (using address / data signals 0-7 as an example in FIG6 ). The data transmitted by the address / data signal lines may be BT data. The following description will take the case where the data includes BT data as an example.

[0140] As a possible implementation manner, the data conversion module 235 performs data analysis on the first data, and derives the reset request, BT control information, BT interrupt mask information and BT data based on different addresses.

[0141] As a possible implementation method, since bus 233 is a parallel bus and bus 220 is a serial bus, the data conversion module 235 can perform parallel-to-serial data conversion on the results of data analysis, converting the results of data analysis from the data format of the parallel bus to the data format of the serial bus.

[0142] As a possible implementation, the data conversion module 235 further outputs an identity indicating the sender of the BT data, ie, the processing system 230, to the sending driver module 237 based on the address of the first data. Optionally, the identity is the serial number of the BT data.

[0143] Optionally, if the bus 233 is a local bus and the bus 220 is an I2C bus, the data conversion module 235 converts the data parsing result from parallel data to serial data, for example, from the data format of the local bus to the data format of the I2C bus.

[0144] In the second step, the data conversion module 235 sends the first data after data analysis and parallel-to-serial data conversion to the cache processing module 236. The cache processing module 236 caches the first data and sends it to the sending driving module 237 in sequence.

[0145] As a possible implementation manner, the cache processing module 236 caches the first data and sends the first data to the sending driving module 237 according to the transmission order of the bus 220 .

[0146] In this embodiment, the reset request, BT control information, BT interrupt mask information, and BT data processed between modules through data conversion, encapsulation, etc. can be regarded as first data, ie, data that the processor 231 needs to send to the management controller 211 .

[0147] In the third step, the sending driver module 237 sends the first data to the receiving driver module 215 .

[0148] As a possible implementation manner, the sending driver module 237 uses the serial number of the BT data as a frame header of the encapsulation packet, and sends the encapsulation packet containing the first data to the receiving driver module 215 through the bus 220 .

[0149] In the fourth step, the receiving driver module 215 parses the identity identifier of the first data, sends the identity identifier of the first data to the data conversion module 217 , and sends the data after removing the frame header to the buffer processing module 216 .

[0150] As a possible implementation manner, the receiving driving module 215 parses the BT data serial number in the frame header of the encapsulation packet and sends the BT data serial number to the data conversion module 217 .

[0151] As a possible implementation manner, the data excluding the frame header includes a reset request, BT control information, BT interruption mask information, and BT data.

[0152] In the fifth step, the cache processing module 216 caches the first data, sends the first data to the data conversion module 217, and generates an interrupt signal to instruct the management controller 211 to read the first data.

[0153] In another possible implementation, when the reset request included in the first data is valid, the cache processing module 216 sends a reset signal to the management controller 211. The reset signal is generated by the processor 231 when it fails to receive a response from the management controller 211 for a predetermined period of time, and is used to instruct the BT module 214 of the management controller 211 to reset.

[0154] In step 6, the data conversion module 217 stores the first data into the address space corresponding to the processing system 230 in the memory according to the identity identifier of the first data, so that the management controller 211 reads the first data from the address space corresponding to the processing system 230 in the memory.

[0155] As a possible implementation manner, the data conversion module 217 determines the corresponding offset address according to the mapping relationship between the BT data number and the offset address, and stores the first data into the register indicated by the offset address.

[0156] Optionally, the data conversion module 217 writes the first data through the address latch signal line, the write enable signal line, and the address / data signal line of the bus 213 .

[0157] Optionally, taking bus 213 as a local bus, the first data includes an address latch signal transmitted by an address latch signal line, a read enable signal transmitted by a read enable signal line, and an address and data transmitted by an address / data signal line. Multiple address / data signal lines may be provided for transmitting multi-bit address / data signals (using address / data signals 0-6 as an example in FIG6 ), and the data transmitted by the address / data signal lines may be BT data.

[0158] In a possible embodiment, the data conversion module 217 can also perform serial-to-parallel data conversion on the first data and then store the first data in the address space corresponding to the processing system 230 in the memory. The serial-to-parallel data conversion is the opposite of the above-mentioned parallel-to-serial data conversion steps and will not be repeated here.

[0159] Based on the internal data forwarding process of the driver modules of interface chips 212 and 232 shown in FIG6 , the logic circuits of interface chips 212 and 232 are programmed to implement logical signal transfer between boards. Power domains and power level types can be adjusted and matched, enabling a single device management system to aggregate and distribute data from multiple processing systems without the need for isolation devices. This further simplifies the topology for managing multiple processing systems and reduces hardware costs.

[0160] Figure 7 is a schematic diagram of the structure of a possible computing device provided in this embodiment. This computing device can be used to implement the functions of the processing system 230 or the in-band management system 210 in the above-mentioned embodiments, and thus also has the beneficial effects of the above-mentioned method embodiments. In this embodiment, the computing device can be the processing system 230 or the device management system 210 shown in Figure 2a, or other devices with communication functions, or a module (such as a chip) applied to a server.

[0161] As shown in FIG7 , a computing device 700 may include a chip 701 . Optionally, the computing device 700 may further include a memory 702 and / or a bus 703 . The processor 701 and the memory 702 are connected via the bus 703 .

[0162] The following is a detailed introduction to the various components of the computing device 700 with reference to FIG7 :

[0163] Chip 701 is the control center of computing device 700 and can be a processor or a collective term for multiple processing elements. Chip 701 can be processor 231 in processing system 230 or management controller 211 in device management system 210. Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor here can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0164] In a specific implementation, as an embodiment, the computing device 700 may also include multiple chips. For example, the computing device 700 also includes the chip 704 shown in FIG7 . The chip 704 may be the interface chip 232 in the processing system 230 or the interface chip 212 in the device management system 210 . For example, the chip 704 may be an application-specific integrated circuit (ASIC) or one or more integrated circuit devices configured to implement the embodiments of the present application, such as one or more field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or one or more microprocessors (DSPs). The chip 704 in FIG7 is shown as a field programmable gate array, and does not illustrate a case where the chip 704 is an electronic device including a CPU, such as a microprocessor.

[0165] For example, when computing device 700 is processing system 230, chip 701 includes one or more processors, and processor 231 of processing system 230 is any one of the one or more processors. In a specific implementation, chip 701 may be a chip system composed of one or more processors, such as CPU0 and CPU1 shown in FIG7 . CPU0 and CPU1 may be the two processors included in processing system 230 in FIG2 a. Chip 704 is interface chip 232.

[0166] For another example, when the computing device 700 is the device management system 210 , the chip 701 includes a processor, such as CPU0 shown in FIG7 , for implementing the functions of the management controller 211 . The chip 704 is the interface chip 212 .

[0167] Optionally, chip 701 and chip 704 may perform various functions of computing device 700 by running or executing software programs stored in memory 702 and calling data stored in memory 702 , such as steps 510 to 580 shown in FIG. 5 .

[0168] Among them, the memory 702 is used to store software programs that execute the solution of the present application, such as software programs that enable chip 701 and chip 704 to execute the functions implemented by steps 510 to 580 as shown in Figure 5, and the execution is controlled by chip 701 and chip 704. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0169] In a specific implementation, as an embodiment, the memory 702 may also be integrated into the chip 701 and the chip 704. For example, the computing device 700 corresponds to the device management system 210, and the memory 702 may also be used to store data of different processing systems using different address spaces.

[0170] Alternatively, the memory 702 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium, a register or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0171] Bus 703 is used to transmit data within computing device 700 , for example, to connect chip 701 , memory 702 , and chip 704 .

[0172] In addition to bus 703, computing device 700 can also communicate with other computing devices via an external bus (which can be seen as bus 220 in Figure 2a). For example, if computing device 700 is device management system 210, computing device 700 communicates with processing system 230 via an external bus. For another example, if computing device 700 is processing system 230, computing device 700 communicates with device management system 210 via an external bus.

[0173] Optionally, the bus 703 may be a local bus, an SPI bus, a USB, etc., and the external bus may be a serial bus such as an I2C bus, a Hisport bus, etc.

[0174] It should be noted that the structure of the computing device 700 shown in FIG7 does not constitute a limitation on the device. The actual device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0175] In addition, the technical effects of the computing device 700 can refer to the technical effects of the computer system 200 and the data transmission method described in the above embodiments, and will not be repeated here.

[0176] It should be understood that the processor in the embodiments of the present application may be a central processing unit, but may also be other general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0177] It should also be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory, or a flash memory. The volatile memory can be a random access memory, which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0178] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (such as infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0179] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0180] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0181] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0182] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0183] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0184] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0185] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c can be single or multiple.

[0186] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0187] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A device management system, characterized in that: The device management system comprises a management controller and an interface chip, wherein the management controller is connected to the interface chip via a first bus, and the interface chip is used to be connected to a plurality of processing systems respectively via a second bus; The interface chip is used to receive data from the multiple processing systems and send the data from the multiple processing systems to the management controller; The management controller is used to process data of the multiple processing systems.

2. The equipment management system according to claim 1, characterized in that: The device management system further comprises a first register, wherein the first register is connected to the management controller and the interface chip respectively; The interface chip is specifically used to store data of a first processing system into a first register corresponding to the first processing system, where the first processing system is one of the multiple processing systems; The management controller is specifically configured to read and process data of the first processing system from the first register.

3. The equipment management system according to claim 1 or 2, characterized in that: The interface chip includes a plurality of bus interfaces, and the interface chip is specifically used to connect with the plurality of processing systems through the plurality of bus interfaces.

4. The equipment management system according to any one of claims 1 to 3, characterized in that: The device management system and the multiple processing systems communicate based on the intelligent platform management interface IPMI protocol, and the data of the multiple processing systems include keyboard controller style KCS data, system management interface chip SMIC data and / or block transmission BT data.

5. The equipment management system according to claim 4, characterized in that: The multiple processing systems include a first processing system, the data of the first processing system includes the block transmission data, the block transmission data includes a reset request, BT control information, BT interrupt mask information, BT data and an identity of the BT data, and the identity is used to indicate the first processing system; The interface chip is specifically used to write the reset request, the BT control information and the BT data into a first register corresponding to the first processing system based on the identity identifier of the BT data, and send an interrupt signal to the management controller according to the BT interrupt mask information, wherein the interrupt signal is used to instruct the management controller to read data.

6. The equipment management system according to claim 5, characterized in that: The first bus is used to transmit the reset request, the BT control information and the BT data stored in the first register to the management controller through an address latch signal line, a write enable signal line and an address / data signal line.

7. The equipment management system according to any one of claims 1 to 6, characterized in that: The first bus is a local bus, a serial peripheral interface SPI bus or a universal serial bus USB.

8. The equipment management system according to any one of claims 1 to 7, characterized in that: The interface chip is also used to forward the data sent by the management controller to the multiple in-band systems.

9. A computer system, characterized in that: The computer system includes a device management system and multiple processing systems, the device management system includes a management controller and a first interface chip, the multiple processing systems include a first processing system, the first processing system includes a processor, the management controller is connected to the first interface chip via a first bus, and the first processing system is connected to the first interface chip via a second bus; The processor is configured to generate data and send the data to the first interface chip; The first interface chip is used to receive the data and send the data to the management controller; The management controller is used to process data of the multiple processing systems.

10. The computer system according to claim 9, characterized in that: The processor is one of a central processing unit (CPU), a graphics processing unit (GPU), and a network processing unit (NPU).

11. The computer system according to claim 9 or 10, characterized in that: The first processing system further includes a second interface chip, the second interface chip is connected to the processor via a third bus, the second interface chip is connected to the first interface chip via the second bus, the data of the first processing system includes the block transmission data, the block transmission data includes a reset request, BT control information, BT interrupt mask information, BT data and BT data; The third bus is used to transmit the block transmission data to the second interface chip through an address latch signal line, a write enable signal line and an address / data signal line; The second interface chip is specifically used for the address latch signal based on the address latch signal line and the write enable signal line The write enable signal parses the data transmitted by the address / data signal line, obtains the reset request, the BT control information, the BT interrupt mask information and the BT data, generates an identity of the BT data, and sends the reset request, the BT control information, the BT interrupt mask information, the BT data and the identity of the BT data to the second bus, where the identity is used to indicate the first processing system.

12. The computer system according to claim 11, characterized in that The second bus is specifically used to transmit the reset request, the BT control information, the BT interrupt mask information, the BT data and the identity of the BT data to the first interface chip through the address latch signal line, the write enable signal line and the address / data signal line.

13. The computer system according to claim 11 or 12, characterized in that: The third bus is a local bus, a serial peripheral interface SPI bus or a universal serial bus USB bus.

14. A data transmission method, characterized in that: Applied to a computer system, the computer system includes a device management system and multiple processing systems, the device management system includes a management controller and a first interface chip, the multiple processing systems include a first processing system, the first processing system includes a processor, the management controller is connected to the first interface chip via a first bus, and the processing system is connected to the first interface chip via a second bus, the method includes: The processor generates data, and sends the data to the first interface chip; The first interface chip receives the data and sends the data to the management controller; The management controller processes the data.

15. The method according to claim 14, characterized in that The device management system further includes a first register, the processor generates data, and sends the data to the first interface chip, including: The first interface chip receives the data and stores the data in a first register corresponding to the first processing system.

16. The method according to claim 15, characterized in that The first processing system further includes a second interface chip, the second interface chip is connected to the first interface chip via a second bus, the second interface chip is connected to the processor via a third bus, the processor generates data, and sends the data to the first interface chip, including: The processor generates data, and sends the data to the first interface chip through the second interface chip.

17. The method according to claim 15 or 16, characterized in that The method further comprises: The second interface chip adds an identity tag to the data, and the identity tag is used to indicate the processing system that sends the data.

18. The method according to any one of claims 15 to 17, characterized in that: The method further comprises: The first interface chip receives the data sent by the management controller, and forwards the data sent by the management controller to the second interface chip; The second interface chip receives the data sent by the first interface chip, and sends the data sent by the first interface chip to the processor.

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