Method for the creation of deep-lying p-n transitions in a BCD process, BCD substrate, and single-photon avalanche diode based thereon

Abstract

The present invention relates to a method for creating deep-lying p-n transitions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, and to a single-photon avalanche diode, SPAD, based thereon. The method comprises providing a carrier substrate (10); introducing a first doping substance (20) for forming a first region (22) of the first conduction type in a surface (S) of the carrier substrate (10); introducing a second doping substance (30) for forming a second region (32) of the second conduction type in the surface (S) of the carrier substrate (10), wherein the first region (22) and the second region (32) at last partially overlap; and growing an epitaxial layer (40) on the surface (S) of the carrier substrate (20), wherein the first region (22) and the second region (32) propagate by way of diffusion of the first doping substance (20) and the second doping substance (30) in the epitaxial layer (40), the diffusion behaviour of the first and the second doping substance (20, 30) being selected such that the first and the second doping substance (20, 30) form, by way of diffusion, a p-n transition (50, 52, 54a, 54b, 56a, 56b) lying in the epitaxial layer (40).

Description

[0001] Method for producing deep pn junctions in a BCD process, BCD substrate and single-photon avalanche diode based thereon

[0002] Subject of the invention

[0003] The present invention relates to a method for producing deep pn junctions in a BCD process, a BCD substrate with a deep pn junction, and a single-photon avalanche diode (SPAD) based thereon, in particular to a method for forming a deep pn junction by introducing or diffusing dopants in the boundary region between a carrier substrate and an epitaxial layer grown on a surface of the carrier substrate. The pn junction provided according to the invention can advantageously be used as a deep pn junction for an isolated SPAD manufactured using BCD technology.

[0004] Technological background

[0005] To construct integrated circuits using bipolar CMOS-DMOS (BCD) technology, substrates with buried layers (BL) of the first and / or second conductivity type (NBL, PBL) are typically required. The dopants used to create these dopants are typically implanted into a carrier substrate. The corresponding surface is then generally overgrown with an epitaxial layer (EPI layer) for further processing. The deeply doped layers provided in the BCD substrate can be used directly as part of an integrated circuit arranged above them. The layers can also serve to insulate and shield an integrated circuit from the carrier substrate.

[0006] Various techniques for producing deep n- and p-doped layers in a BCD process are known in the prior art. In particular, for the selective introduction of corresponding dopants to form NBL and PBL layers, a first region of the first conductivity type can first be created lithographically via a first mask, and then a second region of the second conductivity type can be created via a second mask. The distance between the NBL and PBL layers is predetermined by the process. The dopants are introduced shallowly into the surface of the carrier substrate via appropriately structured mask openings and then diffuse out. During the growth of the EPI layer, the high temperatures during processing lead to further diffusion of the dopants (dopant redistribution) until they have occupied fixed locations in the surrounding material and can thus form largely defined regions.In the prior art, the NBL and PBL layers are usually produced side by side, with the thickness of these regions being essentially determined by the diffusion behavior of the respective dopants.

[0007] One application example for an integrated circuit based on such BCD substrates with deep n- and p-doped layers is integrated single-photon avalanche diodes (SPADs). These are a type of photodetector similar to photodiodes and avalanche photodiodes, but with significantly increased sensitivity. If such an integrated circuit is optically excited, electron-hole pairs are generated by the photons introduced from outside into the sensor-active region of the semiconductor material (absorption region). The excited electrons are drawn to the cathode by electric fields, and the excited holes are drawn to the anode. In this process, the charge carriers also drift through a so-called avalanche region, within which a charge avalanche can be generated by enhanced impact ionization.

[0008] A SPAD is typically operated in Geiger mode, where a single photon is detected via the generated charge avalanche and subsequently registered as a single event. To reduce the dead time during registration, active or passive suppression of further charge carrier amplification can occur immediately after the onset of the avalanche formation. In addition to the SPAD, the integrated circuit can also include a so-called single-photon counter. In this case, instead of outputting a single detector pulse, an immediate statistical evaluation of the temporal distribution of the individual single-photon detection events is generally performed.

[0009] A distinction is made between nSPADs and pSPADs. The terms nSPAD and pSPAD indicate which type of charge carrier is primarily responsible for the formation of impact ionization, i.e., avalanche formation in the SPAD. In an nSPAD, these are primarily negatively charged electrons, whereas in a pSPAD, it is primarily positively charged holes that are responsible for avalanche formation. pSPADs are frequently implemented because they allow for simple low-side readout in terms of circuitry. However, nSPADs are preferred due to their higher avalanche probability and thus typically higher photon detection efficiency (PDE). Normally, in nSPADs, the avalanche region is close to the surface of the substrate, but inverted arrangements also exist in which the avalanche region is located deeper in the substrate.When implementing SPAD imagers ("SPAD arrays"), switching from a pSPAD to an nSPAD design typically also requires a switch from low-side to high-side readout. While this is feasible from a circuit perspective, it is significantly more complex for SPAD imagers.

[0010] In BCD technologies with a standard non-inverted nSPAD structure according to the state of the art, the effective detection depth for the absorption of penetrating photons into the integrated circuit (i.e., the absorption depth) is very low. In particular, electrons generated far below the nSPAD avalanche region in the substrate can no longer reach the cathode (n-doped region) on the surface of the BCD substrate. Due to the resulting reduced absorption depth, a correspondingly low useful current or low effectiveness in the near-infrared spectral range (NIR) results. However, by introducing a highly doped deep layer beneath a conventional nSPAD structure, this useful current can be increased by increasing the effective detection depth of photons.In particular, the useful current is increased because the region above the deep layer can provide additional separated charge carriers for avalanche generation (see, for example, Gramuglia, Francesco, et al. “Engineering breakdown probability profile for PDP and DOR optimization in a SPAD fabricated in a standard 55 nm BCD process.” IEEE Journal of Selected Topics in Quantum Electronics 28.2: Optical Detectors (2021): 1-10).

[0011] Inverted nSPAD structures have also been realized using BCD technologies. For example, a scalable single-photon avalanche diode (SPAD) with a virtual epitaxial guard ring based on BCD technology is known from Han, Dong, et al., “A scalable single-photon avalanche diode with improved photon detection efficiency and dark count noise.” Optik 212 (2020): 164692. A deep junction between a p-well (PW) and a medium-voltage p-well (MVNW) serves as an avalanche region to improve PDE and spectral sensitivity. In addition, a deep n +An n-type buried layer (NBL) is used to provide substrate isolation to reduce electrical crosstalk and facilitate pixel integration. In particular, a lightly doped p-type epitaxial layer is used as a virtual guard ring, which can effectively suppress the dark count rate (DCR) caused by interface traps. Inverted nSPADs in BCD technologies are also known from Veerappan, Chockalingam, and Edoardo Charbon. “A low dark count pin diode based SPAD in CMOS technology.” IEEE transactions on electron devices 63.1 (2015): 65-71 and Sanzaro, Mirko, et al. “Single-photon avalanche diodes in a 0.16 pm BCD technology with sharp timing response and red-enhanced sensitivity.” IEEE Journal of Selected Topics in Quantum Electronics 24.2 (2017): 1-9.

[0012] The inverted nSPADs implemented in the state of the art using BCD technology are predominantly based on pn structures, which use a deep n-well (DNW) introduced from the surface of a BCD substrate as the n-layer. Photon absorption and charge carrier generation in such SPADs predominantly occur in the wide intrinsic region between a first p-layer and a second p-layer. A wide intrinsic layer can increase the area effectively available for absorption and thus also the absorption probability and the PDE. Furthermore, this also reduces the junction capacitance, which can reduce the detector dead time. Despite the inverted nSPAD structure, the absorption depth of the photons is still too small to achieve a high photon capture efficiency, particularly in the near-infrared spectral range (NIR).

[0013] To further increase the absorption depth, the pn junction must be provided below the intrinsic region deeper in the BCD substrate. This is not trivial in already fully developed manufacturing processes for the integrated circuits and usually requires the addition of additional process steps. In particular, additional masking, lithography, and epitaxy steps may be required. It is important to note that these additional steps must also be compatible with the process steps for producing the other components of an integrated circuit, e.g., an integrated amplifier or a connected photon counter. High efficiencies can be achieved with high penetration depth and with electron-based breakdown. The deepest available n-layer within a typical BCD process with epitaxy is the NBL layer.However, a typical p-well introduced from the surface is then not suitable for providing a suitable breakdown mechanism (with a suitable value for the breakdown voltage VBD < 40 V). It is therefore an object of the present invention to provide a method for producing deep pn junctions in a BCD process, a BCD substrate with a deep pn junction, and a single-photon avalanche diode based thereon. The method for producing deep pn junctions in a BCD process should, if possible, require no additional process effort and be compatible with existing BCD processes. A corresponding BCD substrate with a deep pn junction can then form the basis for the construction of a highly efficient single-photon avalanche diode with a broad absorption region. The SPAD detectors should be controllable with simple circuit solutions and, at the same time, be highly effective for the NIR spectral range.

[0014] Description of the invention

[0015] The object of the invention is achieved by the subject matter of the independent patent claims. Preferred developments are the subject matter of the dependent claims.

[0016] A first aspect of the present disclosure relates to a method for producing deep pn junctions in a BCD process, comprising providing a carrier substrate; introducing a first dopant to form a first region of the first conductivity type into a surface of the carrier substrate; growing an epitaxial layer on the surface of the carrier substrate, wherein the first region spreads through diffusion of the first dopant in the epitaxial layer and in the carrier substrate; and introducing a second dopant to form a second region of the second conductivity type into a region of the first region, wherein the first region and the second region at least partially overlap, and the introduction of the second dopant is selected such that the first and second dopant form a pn junction lying in the epitaxial layer as a result of the introduction.

[0017] Preferably, a second dopant is introduced into a region of the first region to form a second region of the second conduction type by means of high-energy implantation of the second dopant.

[0018] In a preferred embodiment of the method, the second dopant is introduced into the surface of the carrier substrate before the epitaxial layer grows (i.e., analogously to the introduction of the first dopant). It is particularly preferred that (after the epitaxial layer grows) the first region and the second region spread through diffusion of the first dopant and the second dopant in the epitaxial layer and in the carrier substrate, wherein the diffusion behavior of the first and second dopant is selected such that the first and second dopant form the pn junction located in the epitaxial layer through diffusion.

[0019] A second aspect of the present disclosure relates to a method for producing deep pn junctions in a BCD process, comprising providing a carrier substrate; introducing a first dopant to form a first region of the first conductivity type into a surface of the carrier substrate; introducing a second dopant to form a second region of the second conductivity type into the surface of the carrier substrate, wherein the first region and the second region at least partially overlap;and growing an epitaxial layer on the surface of the carrier substrate, wherein the first region and the second region spread by diffusion of the first dopant and the second dopant in the epitaxial layer and in the carrier substrate, wherein the diffusion behavior of the first and the second dopant is selected such that the first and second dopant form a pn junction lying in the epitaxial layer by diffusion;

[0020] The following statements concern both aspects mentioned above equally and are therefore discussed together.

[0021] Preferably, the first and second dopants each form a pn junction located in the epitaxial layer and a pn junction located in the carrier substrate by introduction (in particular by introduction of the second dopant, although, for example, the spatial distribution during introduction of the first dopant also has an influence) and / or by diffusion (in addition to the selected diffusion parameters, the spatial distribution during introduction of the first and second dopant in particular has a significant influence). A diffusion movement with formation of at least one pn junction can also occur after introduction of dopants in a method according to the invention according to the described first aspect.

[0022] A pn junction is understood in particular to be a region or area within the substrate in which a p-doped semiconductor material is in planar contact with an n-doped semiconductor material, and in the transition region between the two materials, a depletion zone typical of p-n junctions can form. A pn ​​junction is thus defined locally by the respective structures at the corresponding location. In this respect, a corresponding pn junction can also be referred to as a pn junction region (or pn junction area). However, unless otherwise stated in the description in individual cases, the term "pn junction" should not be understood as a general designation for an electronic structure formed by such a pn junction region. Two directly adjacent pn junction regions in different regions (e.g.epitaxial layer and carrier substrate) therefore form separate pn junctions, even though they may well form a common connected structure (ie a common pn junction structure comprising two interconnected pn junction regions).

[0023] A pn junction located in the epitaxial layer is therefore characterized by a boundary region between a p-doped semiconductor material and an n-doped semiconductor material located in the epitaxial layer. Similarly, a pn junction located in the carrier substrate is characterized by a boundary region between a p-doped and an n-doped semiconductor material located in the carrier substrate.

[0024] The carrier substrate can preferably be a p-type substrate. However, n-type substrates or intrinsic substrates can also be used. The substrate material can, in particular, be silicon. A typical dopant for forming a p-type region is boron. Phosphorus can be used to form an n-type region. In silicon, for example, boron diffuses much faster and therefore further as a dopant than phosphorus. It can also be seen that the n-type regions created are largely dominant for both dopants at the typically selected doses, i.e. an n-type region already doped with phosphorus can retain its existing conductivity type even after the additional introduction of boron. This means that additional masking, lithography, and epitaxy steps in the conventional BCD process can be dispensed with to create the deep pn junctions.

[0025] Preferably, the first and second dopants exhibit different diffusion behavior in the carrier substrate and / or in the epitaxial layer. Preferably, the second dopant exhibits higher diffusivity (also referred to as diffusion mobility) in the carrier substrate and / or in the epitaxial layer than the first dopant. In particular, so-called diffusion engineering can also be applied from the surface, in which the individual dopants are introduced from the surface in such a way that a substantially increasing dopant profile is established towards the surface. However, this generally does not result in a strictly monotonic profile; rather, the transitions usually exhibit a certain degree of stepping or waviness.The diffusion behavior of various dopants in epitaxially grown layers and in materials typically used as carrier substrates is sufficiently known to the person skilled in the art or can be calculated at least roughly in a known manner. The first and second dopants, as well as the associated parameters for introduction into a surface of the carrier substrate for the inventive formation of a pn junction in the epitaxial layer and one in the carrier substrate by diffusion, can thus be readily determined by the person skilled in the art.

[0026] Preferably, after the introduction of the first dopant and / or the second dopant, the carrier substrate is heated to enhance diffusion. This can also be done during the epitaxial steps, as these generally require very high process temperatures. After the growth of the epitaxial layer(s), the carrier substrate can also be heated to enhance dopant diffusion.

[0027] Preferably, the first dopant and / or the second dopant are introduced masklessly or using a masking process. For maskless introduction, a direct ion beam writing process can be used, for example. In a masking process, the introduction is carried out using a previously provided mask, with the introduction being carried out, for example, using a chemical or physical deposition process or also using an ion beam writing process.

[0028] Preferably, immediately after the introduction of the second dopant, in a plan view of the surface of the carrier substrate, the first region or the second region completely overlaps the other region, or the first region and the second region overlap only in the edge regions. The term "edge region" means that at least one additional main region exists adjacent to the first region without overlap. Overlapping only in the edge regions can also involve enclosing one region by the other region, wherein the enclosed region is not overlapped by the other region in a central region.

[0029] Preferably, immediately after the introduction of the second dopant, in a plan view of the surface of the carrier substrate, the first region is overlaid at a left and right edge region by the edge regions of two second regions, or the second region is overlaid at a left and right edge region by the edge regions of two first regions.

[0030] Preferably, the first region is a deep n-layer (NBL layer) and the second region is a deep p-layer (PBL layer).

[0031] A method according to the invention enables the production of deep pn junctions in a conventional BCD process. Additional process effort can be largely dispensed with. In particular, a method according to the invention is thus also compatible with the further process steps of a conventional BCD technology based on the provision of deep n- and p-doped layers. The possibility of directly maskless production of deep pn junctions is provided. A particular advantage of a method according to the invention is that, depending on the design of the method, several independent pn junctions can be realized in a single process step at essentially the same location on the carrier substrate.In particular, in some embodiments of a method according to the invention, in addition to an upper first pn junction located essentially in the epitaxial layer, a largely identical lower second pn junction located essentially in the carrier substrate can also be provided. The configuration, in terms of shape and number, of the pn junctions provided can be adjusted via the dopant profile used and the desired position of the deep n- and p-doped layers.

[0032] A third aspect of the present disclosure relates to a BCD substrate with a deep pn junction, comprising a carrier substrate; and an epitaxial layer grown on the carrier substrate, wherein a pn junction located in the epitaxial layer was created between the carrier substrate and the epitaxial layer by a method according to the invention according to the described first aspect or by diffusion of dopants introduced into a surface of the carrier substrate below the epitaxial layer. In particular, a BCD substrate according to the invention can be provided by means of a corresponding method according to the invention. The descriptions and explanations made regarding the method according to the invention and its preferred embodiments apply accordingly to a BCD substrate according to the invention. This particularly relates to the formation and arrangement of the different regions.

[0033] Preferably, one pn junction is created in the epitaxial layer and one in the carrier substrate. In this case, the BCD substrate according to the invention thus has two jointly created pn junctions.

[0034] A further aspect of the present disclosure relates to a single-photon avalanche diode (SPAD) comprising a BCD substrate according to the invention, wherein a region around a pn junction forms an avalanche region, and an absorption region for converting photons into electron-hole pairs, wherein the absorption region is directly adjacent to the regions forming the pn junction (ie the NBL and PBL layers superimposed in a diffusion-driven manner according to the invention).

[0035] Preferably, the pn junction is formed at least partially between a deep n-layer (NBL layer) as the cathode and a deep p-layer (PBL layer) directly adjacent to the deep n-layer. Preferably, the absorption region directly adjoins the deep p-layer and is formed as a p-type region. It is further preferred that an anode formed as a p+ region directly adjoins the absorption region. To avoid excessive electric field at the corners, the detector region is typically formed radially symmetrically or at least with obtuse angles or, better yet, with rounded edges.

[0036] Preferably, the absorption region comprises a high-voltage p-well directly adjacent to the deep p-layer and, optionally, a p-well directly adjacent thereto. The absorption region effectively functions as the intrinsic zone of a corresponding pin photodiode.

[0037] Preferably, the absorption region between the deep p-layer and the anode is formed as a lightly n-doped, epitaxial region with a high-voltage p-well formed as a channel as a non-linear quenching resistor.

[0038] Preferably, a plurality of separate deep p-layers arranged directly above the deep n-layer are formed along the deep n-layer. Such a configuration enables the parallel arrangement of several identical or at least structurally similar diodes. As a result, a single-photon avalanche diode according to the invention can be formed with a plurality of adjacently arranged, largely independent active regions, which essentially corresponds to a parallel connection of a plurality of essentially identical single-photon avalanche diodes. Depending on the number of integrated diodes, such an overall configuration can be largely free of dead time, since one or more further photon events can be detected at other, remaining active diodes directly after an initial detection.

[0039] A typical thickness for the grown epitaxial layer (and thus for the depth of the pn junction in the BCD substrate) is approximately 5-10 pm. This allows for a particularly high breakdown voltage. The deep NBL layer and the p-wells introduced from the surface can then provide a large intrinsic zone, which also results in a high breakdown voltage and can serve as a broad absorption region for a corresponding SPAD.

[0040] By extensively utilizing conventional BCD techniques, a novel structure was created that systematically differs from other SPAD structures already known in the prior art. A single-photon avalanche diode according to the invention can, in particular, be an inverted nSPAD, which enables a higher PDE, particularly for detection in the infrared spectral range. The detector according to the invention offers all the advantages of an nSPAD and improves its properties through a wider absorption layer, although the single-photon detector can, in principle, be used like a conventional surface-related pSPAD. The terms nSPAD and pSPAD serve to indicate which type of charge carrier is predominantly responsible for the formation of impact ionization, i.e., for the avalanche formation in the SPAD.In an nSPAD, these are particularly the negatively charged electrons, whereas in a pSPAD, it is mainly the positively charged holes that are responsible for the avalanche formation.

[0041] Due to the BCD technology platform used, which enables optimal integration of a wide variety of applications from different areas, the components buried in the BCD substrate, in particular a single-photon avalanche diode according to the invention, can also be combined with other components directly above the buried component or immediately adjacent to the side. For example, in addition to analog and digital amplifier elements, digital storage elements and signal processors for statistical evaluation and for constructing single-photon counters can also be implemented. By shifting the pn junction relevant for the function of the single-photon avalanche diode to a greater depth, made possible by a method according to the invention, the surface of the BCD substrate used can be deliberately structured for improved optical properties (e.g., changing the active region / STI)."shallow trench isolation") and / or poly) without significantly changing or influencing the properties of the buried component. This allows for a high degree of flexibility in the design of corresponding integrated circuits and in the structuring of the surface. Since the relevant pn structure is not surface-related, the well-known BEOL interference condition does not have to be strictly considered, which means that the severity of the spectral resonance maxima and minima (spectral response fringes) can be reduced through simple ACTI / STI structuring or modulation.

[0042] The single-photon detectors according to the invention, especially when designed with a fully integrated non-linear quenching resistor, can be used in different ways, e.g., as individual pixels within an array or as so-called silicon photomultipliers (SiPM). The design according to the invention allows for detector areas of almost any size (a few pm 2 up to mm 2 ) without visible pixel boundaries when utilizing almost 100% of the effective area (i.e. with a high fill factor).

[0043] A further advantage of the inventive BCD structure of a single-photon avalanche diode is the possibility of variably adjusting the breakdown voltage of the diodes by simply adapting the underlying structural design. For example, the breakdown voltage can be significantly influenced by the size of the deep p-layer region and thus adjusted accordingly. The selected breakdown voltage can be uniform or deliberately varied, if the application requires it.

[0044] The deep location of the pn junction(s) provided according to the invention, and thus of the isolated and individually addressable single-photon avalanche diodes realized above them, also enables addressing or reading of the structures in a so-called low-side configuration. This low-side readout allows for greater flexibility in circuit design and the construction of corresponding integrated circuits.

[0045] Using a method according to the invention, two nearly identically constructed pn junctions can be created in the BCD substrate. This provides an ideal platform for future SPAD developments through appropriate scaling. While, for example, an upper pn junction formed in the epitaxial layer can provide a first SPAD, a second pn junction in the carrier substrate enables the formation of a largely identical second SPAD.

[0046] This enables, on the one hand, a particularly compact 3D integration of multiple detector elements, and, on the other hand, significant improvements in detection properties can be achieved and entirely new fields of application can be opened up. Both pn junctions are, in principle, suitable for both front-side and back-side illumination. The second SPAD is essentially a standalone component, largely independent of the first SPAD, so that separate readout is also possible via appropriate contacting. This also fundamentally enables the provision of a so-called back-side imager (BSI) at the lower pn junction, either alone or in combination with a so-called front-side imager (FSI) at the upper pn junction.

[0047] A further advantage of the inventive deep pn junction is its easy scalability. Separation of adjacent diode structures can be achieved by simply structuring corresponding isolation regions on the surface of the BCD substrate.

[0048] A further aspect of the present disclosure relates to an integrated circuit comprising at least one single-photon avalanche diode according to the invention.

[0049] Further aspects of the present invention are disclosed in the dependent claims or in the following description of the drawings.

[0050] Short description of the characters

[0051] The invention is explained below in exemplary embodiments with reference to the accompanying drawings. They show:

[0052] Figure 1 is a schematic representation of a first embodiment of a method for producing deep n- and p-doped layers in a BCD process according to the prior art;

[0053] Figure 2 is a schematic representation of a second embodiment of a method for providing deep n- and p-doped layers in a BCD process according to the prior art;

[0054] Figure 3 is a schematic representation of a first embodiment (“Saturn”) of a method according to the invention for providing deep pn junctions in a BCD process and a TCAD representation of the resulting dopant distribution;

[0055] Figure 4 is a schematic representation of a second embodiment (“donut”) of a method according to the invention for providing deep pn junctions in a BCD process and a TCAD representation of the resulting dopant distribution;

[0056] Figure 5 is a schematic representation of a third embodiment (“Pacman”) of a method according to the invention for providing deep pn junctions in a BCD process and a TCAD representation of the resulting dopant distribution;

[0057] Figure 6 Current-voltage characteristics of a blocking U rev operated deep pn junction produced using a method according to the invention according to the first embodiment of FIG. 3, including a passive quenching resistor and without illumination;

[0058] Figure ? a schematic representation of a single-photon avalanche diode manufactured using BCD technology according to the prior art;

[0059] Figure 8 is a schematic representation of a first embodiment of a single-photon avalanche diode according to the invention;

[0060] Figure 9 is a schematic representation of a second embodiment of a single-photon avalanche diode according to the invention; and

[0061] Figure 10 is a schematic representation of a third embodiment of a single-photon avalanche diode according to the invention.

[0062] Detailed description of the characters

[0063] Detailed embodiments will now be described, illustrated by way of example in the accompanying drawings. The effects and features of these embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals designate like elements, and redundant descriptions are omitted. The present disclosure may be embodied in various forms and should not be construed as limited only to the embodiments shown herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art.

[0064] Therefore, methods, elements, and techniques that are not necessary for a person skilled in the art to fully understand the aspects and features of the present disclosure may not be described. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0065] As used herein, the term "and / or" includes all combinations of one or more of the listed elements. Furthermore, the use of "may" in describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." In the following description of embodiments, the singular terms may also include the plural, unless the context clearly indicates otherwise.

[0066] Although the terms "first" and "second" are used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. Terms such as "at least one of," when preceded by a list of elements, modify the entire list, not just the individual elements of the list.

[0067] Terms such as "substantially," "approximately," and similar terms are used as approximations rather than degrees, and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. When the term "substantially" is used in connection with a characteristic that can be expressed by a numerical value, the term "substantially" means a range of at least + / - 5% of the value centered on the value.

[0068] Figure 1 shows a schematic representation of a first embodiment of a method for producing deep n- and p-doped layers in a BCD process according to the prior art. The method is essentially based on the three steps shown for this purpose, whereby the bars shown in the upper part of the figure are intended to illustrate the regions to be structured by a possible first mask layer ML1 and a possible second mask layer ML2 for the first and second steps in the representation, respectively. These are designated NBL for a deep n-type buried layer and PBL for a deep p-type buried layer, corresponding to the deep layers shown in the figure.

[0069] The figure shows a basic arrangement frequently used for BCD technologies, consisting of a wide, deep n-layer enclosed laterally between two deep p-layers. However, this is merely an illustrative example. The size and arrangement of the individual deep layers are not determined in more detail by the method used and can therefore be varied as desired. The order of the first and second steps shown can also be varied. In the example shown in FIG. 1, the NBL layer is provided first, and then the two PBL layers are created. The details given in parentheses below after the reference symbols therefore relate only to the facts shown as examples in the figures, but are not intended to restrict the method in any way in this regard.Furthermore, the process illustrations only show the doping profiles and the resulting diffusion profiles in a highly simplified form. Particularly at sharp edges of the doping profiles, deviations in the layer shape can occur due to various effects during practical implementation.

[0070] The method shown for producing deep n- and p-doped layers NBL and PBL in a BCD process comprises providing a carrier substrate 10 (this step is not explicitly shown); introducing a first dopant 20 to form a first region 22 (in the example shown, an NBL layer) of the first conductivity type (negative) into a surface S of the carrier substrate 10; introducing a second dopant 30 to form at least one second region 32 (PBL) of the second conductivity type (positive) into the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) are formed spaced apart from one another by a distance d; and growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) are formed by diffusion of the first dopant 20 and the second dopant 30 in the epitaxial layer 40 and in theCarrier substrate 10. The occurrence of dopant diffusion is known to those skilled in the art and can be taken into account when producing the desired layer thicknesses. To enhance the diffusion, heating of the carrier substrate 10 can take place after the introduction of the first dopant 20 and / or the second dopant 30 (so-called drive-in). Furthermore, heating of the carrier substrate 10 can take place after the growth of the epitaxial layer 40 to enhance dopant diffusion. The introduction of the first dopant 20 and / or the second dopant 30 can be carried out using a mask process. For the corresponding structure definition, in particular, a first and a second mask layer ML1 and ML2 can be used. Alternatively, the dopants can also be introduced using a maskless structuring process (e.g., direct ion beam writing). The two mask layers ML1 and ML2 shown representThe carrier substrate 10 may preferably be a p-substrate, but intrinsic or n-substrate may also be used depending on the respective requirements.

[0071] Figure 2 shows a schematic representation of a second embodiment of a method for providing deep n- and p-doped layers NBL, PBL in a BCD process according to the prior art. For simplicity, the method is presented in this and the following illustrations in abbreviated form using the generated structures and the respective mask sequence. However, steps 1 and 2 from FIG. 1, which are not shown, should be read along accordingly. The embodiment shown in FIG. 2 differs from the embodiment shown in FIG. 1 only in thatthat the first and second dopants 20 and 30 have different diffusion behavior in the carrier substrate 10 and in the epitaxial layer 40. In particular, the second dopant 30 in the second region 32 (PBL) has a higher diffusivity (and thus diffusion length) in the carrier substrate 10 and in the epitaxial layer 40 than the first dopant 10 in the first region 22 (NBL). The PBL layers produced therefore have a greater thickness in the provided BCD substrate 100 after complete dopant diffusion, i.e. after out-diffusion, than the produced NBL layer. The diffusion behavior in the carrier substrate 10 and in the epitaxial layer 40 depends directly on the selection of the dopants 20 and 30 used as well as on the respectively selected parameters (e.g. density, energy, area,geometry) during deposition. The differences in the thicknesses of the produced deep n- and p-layers NBL and PBL must therefore be taken into account accordingly when designing integrated circuits (e.g., SPADs). Figure 3 shows a schematic representation of a first embodiment ("Saturn") of a method according to the invention for providing deep pn junctions 50 and 52 in a BCD process and a TCAD representation (English: "technology computer-aided design,TCAD") of the resulting dopant distribution. The method according to the invention for producing deep pn junctions 50 and 52 in a BCD process comprises providing a carrier substrate 10; introducing a first dopant 20 to form a first region 22 (NBL) of the first conductivity type (donor) into a surface S of the carrier substrate 10; introducing a second dopant 30 to form a second region 32 (PBL) of the second conductivity type (acceptor) into the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap; growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) are formed by diffusion of the first dopant 20 and the second Dopant 30 in the epitaxial layer 40 and in the carrier substrate 10,wherein the diffusion behavior of the first and second dopants 20 and 30 is selected such that the first and second dopants 20, 30 each form a pn junction 50 and 52 located in the epitaxial layer 40 and one in the carrier substrate by diffusion. In the illustration, the first region 22 is a deep-lying NBL layer and the second region 32 is a deep-lying PBL layer. However, the order is interchangeable, so that the first region 22 can also be a deep-lying PBL layer and the second region 32 can correspondingly be a deep-lying NBL layer. By appropriately adapting the diffusion lengths of the individual dopants, the layer sequence in the generated pn junctions 50 and 52 can also be reversed, e.g. in FIG. 3 the NBL and PBL layers at the pn junctions 50 and 52 are also swapped.,

[0072] The described method thus differs in particular from the described methods for producing deep-lying n- and p-doped layers PBL and NBL in a BCD process according to the prior art in that the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap. Preferably, at least two pn junctions 50 and 52 located in different material regions (carrier substrate 10, epitaxial layer 40) (i.e., different pn junction regions) can be formed. In particular, immediately after the introduction of the second dopant 30, in a plan view of the surface S of the carrier substrate 10, the first region 22 or the second region 32 can completely overlap the other region 32, 22.Therefore, in the embodiment shown, immediately after the introduction of the second dopant 30 to form the second region 32 (PBL), the second dopant lies entirely in the first region 22 (NBL) in a plan view of the surface S of the carrier substrate 10. In order to be able to form one pn junction 50, 52 located in the epitaxial layer 40 and one in the carrier substrate 10, the first and second dopant 20, 30 preferably have different diffusion behaviors in the carrier substrate 10 and / or in the epitaxial layer 40. In particular, the second dopant 30 in the second region 32 (PBL), as shown, can have a higher diffusivity (and thus diffusion length) in the carrier substrate 10 and in the epitaxial layer 40 than the first dopant 20 in the first region 22 (NBL).

[0073] To enhance diffusion, the carrier substrate 10 can be heated after the introduction of the first dopant 20 and / or the second dopant 30. Furthermore, after the growth of the epitaxial layer 40, the carrier substrate 10 can be additionally heated to enhance dopant diffusion. In the method according to the invention, the first dopant 20 and / or the second dopant 30 can also be introduced either maskless or using a mask method. The first embodiment of the method according to the invention shown can be understood as a complete overlay of the first region 22 (NBL) with a single second region 32 (PBL) corresponding to the embodiment of a method according to the prior art shown in FIG. 2. In the prior art, however, the first and second regions 22 and 32 are typically formed spatially separate from one another.In particular, the distance d is generally chosen to be at least large enough to ensure that no overlapping regions are created even after the individual dopants have diffused out. Therefore, the described prior art method cannot create deep pn junctions 50 and 52 between the NBL and PBL layers.

[0074] The TCAD representation shown below the schematic diagram shows the dopant distribution within the contacted BCD substrate 100 according to the invention for simulating a corresponding integrated diode structure. Due to the double structure present in this embodiment with an upper pn junction 50 and a lower pn junction 52, the side view shown shows an effective constriction of the n-type region NBL enclosed in the area of ​​the pn junctions 50 and 52 by the two p-type regions PBL surrounding this n-type region NBL. Both pn junctions 50 and 52 can be formed with a doping density and field strength distribution suitable for generating an avalanche effect, thereby enabling a particularly dense realization of two mutually independent deep-lying SPADs in the area of ​​the pn junctions 50 and 52.

[0075] Figure 4 shows a schematic representation of a second embodiment ("donut") of a method according to the invention for providing deep pn junctions 54a, 54b, 56a and 56b in a BCD process and a TCAD representation of the resulting dopant distribution. The basic method corresponds to that described for FIG. 3. The reference numerals and their assignment to individual features therefore apply accordingly. In contrast to FIG. 3, immediately after the introduction of the second dopant 30, in a plan view of the surface S of the carrier substrate 10, the second region 32 (PBL) is overlaid or touched at the left and right edge regions by the edge regions of two first regions 22 (NBL). Alternatively, however, the first region 22 (NBL) can also be overlaid or touched at the left and right edge regions by the edge regions of two second regions 32 (PBL).In particular, immediately after the introduction of the second dopant 30, in a plan view of the surface S of the carrier substrate 10, the first region 22 or the second region 32 can also lie entirely within the respective other region 32 and 22, but without these regions 22 and 32 completely overlapping. For example, the first region 22 can overlap or touch the second region 32 (or vice versa) in a ring-like or box-like manner only in the edge regions. The term "edge region" means that, in addition to this edge region, at least one overlap-free "main region" exists.

[0076] In the illustration shown, two first regions 22 (NBL) and a second region 32 (PBL) overlying the two first regions 22 (NBL) in the edge regions are thus introduced into the surface S of the carrier substrate 10 in such a way that a first right-hand pn junction structure, comprising two pn junctions 54a and 56a located in the epitaxial layer 40 in each case, and a second left-hand pn junction structure, formed independently thereof, comprising two pn junctions 54b and 56b located in the carrier substrate 10 in each case, are produced in the horizontal direction. In this respect, this embodiment essentially corresponds to an embodiment rotated by 90° according to FIG. 3, in which a vertical arrangement (i.e. extending into the depth of the carrier substrate 10 with respect to the surface S) of the two pn junctions 50 and 52 produced in FIG. 3 is carried out. This can also be seen from the corresponding TCAD representation, which also shows a correspondingly rotated dopant distribution.The pn junctions 54a and 54b as well as 56a and 56b can be seen in the side view by the constriction of the central PBL layer created by the two edge NBL layers. Figure 5 shows a schematic representation of a third embodiment ("Pacman") of a method according to the invention for providing deep pn junctions 50, 52, 54a and 54b in a BCD process and a TCAD representation of the resulting dopant distribution. The basic method corresponds to that described for FIG. 4. The reference numerals and their assignment to individual features therefore apply accordingly. In contrast to FIG. 4, immediately after the introduction of the second dopant 30, in a plan view of the surface S of the carrier substrate 10, the first region 22 (NBL) and the second region 32 (PBL) overlap only in the edge regions.A first region 22 (NBL) and a second region 32 (PBL) are thus introduced into the surface S of the carrier substrate 10 in such a way that their distance d becomes negative after the out-diffusion of the individual dopants, ie that a part of one region overlays a part of the other region.

[0077] The schematic representation shows that in this embodiment, four connected pn junction regions 50, 52, 54a, and 54b are formed. These regions are an upper pn junction 50 in the epitaxial layer, a lower pn junction 52 in the carrier substrate 10, and a right-hand pn junction structure connecting the two pn junctions 50 and 52, comprising an upper pn junction 54a located in the epitaxial layer 40 and a lower pn junction 54b located in the carrier substrate. In the corresponding TCAD representation, these regions can be seen by the PBL layer constricting the central NBL layer on the right-hand side. The individual pn junction regions 50, 52, 54a, and 54b form a single connected pn junction structure.

[0078] Figure 6 shows several current-voltage characteristics of a blocking U revoperated deep-lying pn junction according to the invention, produced using an inventive method according to the first embodiment shown in FIG. 3, including a passive quenching resistor and without illumination. At a breakdown voltage UBV (BV) of approximately 18 V, the pn junction exhibits a steep breakdown current rising by several orders of magnitude. The curve shape is typical for a passively quenched pn junction of a SPAD with a characteristic of the so-called Geiger plateau in the range above the breakdown voltage U Bv to approximately 25 V. The breakdown voltage itself can be varied simply by appropriate design adaptations - without process adaptation! -. For example, values ​​from 10 V up to 70 V are possible. Figure 7 shows a schematic representation of a single-photon avalanche diode 200 manufactured using BCD technology according to the state of the art (cf. Veerappan, Chockalingam, and Edoardo Charbon. "A low dark count pin diode based SPAD in CMOS technology." IEEE transactions on electron devices 63.1 (2015): 65-71 and Sanzaro, Mirko, et al. "Single-photon avalanche diodes in a 0.16 pm BCD technology with sharp timing response and red-enhanced sensitivity." IEEE Journal of Selected Topics in Quantum Electronics 24.2 (2017): 1-9). The detector is constructed vertically (ie extending into the BCD substrate 100 with respect to the surface), with the anode A being formed by a p +region on the surface of the BCD substrate 100, and the cathode C are formed via a deep n-layer (NBL) or a deep n-type well (DNW). In between, a pn junction 58 is formed at the boundary between a p-type well (PW) arranged directly below the p+ region as an absorption region and a light n- or p-doped epitaxial region (NEPI or PEPI) arranged directly above the deep n-layer (NBL) as a conduction region. The p-well PW is introduced into the lightly n- or p-doped epitaxial region NEPI or PEPI from the top side, whereby the p-well PW is also laterally enclosed by the lightly n- or p-doped epitaxial region NEPI or PEPI and thus separated from other surrounding structures.The lightly n- or p-doped epitaxial region NEPI or PEPI functionally represents a broad intrinsic region for the formation of a pin structure between the p-well PW and the deep-lying n-layer NBL or the deep-lying n-well DNW. The pin structure relevant for the single-photon avalanche diode 200 shown is thus formed in the transition region between the p-well PW, the lightly n- or p-doped epitaxial region NEPI or PEPI, and the deep-lying n-layer NBL or the deep-lying n-well DNW. In particular, the lightly n- or p-doped epitaxial region NEPI or PEPI can increase the distance between the p-well PW and the other laterally surrounding structures, thereby significantly weakening a parasitic pn junction formed between these structures.

[0079] The BCD substrate 100 used can, in particular, have been manufactured using a conventional method according to the embodiment shown in FIG. 2, wherein an epitaxial layer 40 was grown on a carrier substrate 10 after forming spatially separated deep n- and p-layers NBL and PBL. For further details of the prior art method, reference is made to the description of FIGS. 1 and 2. Typically, the detector region is designed to be radially symmetrical to compensate for the different avalanche propagation directions and to avoid hot spots.

[0080] Contacting the buried cathode C of the detector can be achieved via high-voltage n-type wells (HVNW) laterally adjacent to the absorption region and an n+ region arranged thereon on the surface of the BCD substrate 100. In particular, corresponding contacts (CONT) can be realized via a metallization (MET1). The surface regions can each be separated from one another by isolation regions (ST1). The entrance window for the radiation to be detected is also located on the surface of the BCD substrate 100. This can be protected by an applied silicide blocking layer (SBL). To shield the detector from substrate influences, a p-isolation region extending from the surface down to a deep p-layer (PBL) can be arranged around the detector.However, the isolation region is not relevant to the actual function of the detector and will therefore not be described in detail below. The equivalent circuit diagram shown next to the diagram once again illustrates the exact location of the pn junction 58 (pin structure) in the BCD substrate 100 and indicates the corresponding connections (anode A, cathode / common n-well C / TW) on the provided diode.

[0081] The single-photon avalanche diode 200 presented here is a so-called nSPAD with a pn junction 58 arranged on the n-side of the BCD substrate 100, in which both the photon incidence and the contacting of the detector occur from the surface of the BCD substrate 100. Such a structure is technologically quite simple to implement and, due to the possible detection properties, is preferred over other SPAD designs. However, the disadvantage of a deep-lying n-layer (NBL) or deep-lying n-well (DNW) introduced above the surface without epitaxy at a relatively shallow depth (approximately 2-3 pm compared to approx. 5-10 pm in BCD technologies with epitaxy) in the prior art is the resulting relatively shallow absorption depth for incident photons, which particularly complicates detection in the infrared spectral range and limits the PDE.When the structures known from the prior art are directly transferred to BCD technologies with an epitaxial growth step, the large drift distance then present also results in very high breakdown voltages (VBD » 30-40 V), which are then generally more difficult to handle in the application. Figure 8 shows a schematic representation of a first embodiment of a single-photon avalanche diode 200 according to the invention. By means of a method according to the invention for generating deep pn junctions 50, 52, 54a, 54b, and 56a, 56b in a BCD process, the pn junction 50 and 52 used for detection can be provided significantly deeper than in the prior art in a simple manner, whereby the absorption region and thus the absorption depth can be significantly increased compared to conventional SPADs provided using BCD technology.

[0082] All embodiments of single-photon avalanche diodes 200 according to the invention presented in this application are constructed on BCD substrates 100 according to the invention with a deep pn junction 50, 52, 54a, 54b, 56a, and 56b. These comprise a carrier substrate 10 and an epitaxial layer 40 grown on the carrier substrate 10. A pn ​​junction 50, 52, 54a, 54b, 56a, and 56b located in the epitaxial layer 40 was created between the carrier substrate 10 and the epitaxial layer 40 by a method according to the invention according to the first aspect described in the description section or by diffusion of dopants introduced into a surface S of the carrier substrate 10 below the epitaxial layer 40 (e.g., using a method according to the invention).A single-photon avalanche diode 200 according to the invention therefore comprises a BCD substrate 100 according to the invention, wherein a region around a pn junction 50, 52 (optionally individually or together with 54a, 54b and / or 56a and 56b) forms an avalanche region, and an absorption region (PW, HPW) for converting photons into electron-hole pairs, wherein the absorption region (PW, HPW) is directly adjacent to the regions (NBL, PBL) forming the pn junction 50, 52 (54a, 54b and / or 56a, 56b).

[0083] In particular, in the single-photon avalanche diode 200 according to the invention shown, the upper pn junction 50 is formed at least partially between a deep-lying n-layer NBL as the cathode C and a deep-lying p-layer PBL directly adjoining the deep-lying n-layer NBL, the absorption region (PW, HPW) directly adjoins the deep-lying p-layer PBL and is formed as a p-region, and an anode A formed as a p+ region is formed directly adjoining the absorption region (PW, HPW). The absorption region (PW, HPW) preferably comprises a high-voltage p-well HPW directly adjoining the deep-lying p-layer PBL and optionally a p-well PW directly adjoining it. The detector structure shown thus largely corresponds to the structure shown in FIG. 7. The reference numerals and their assignment to individual features therefore apply accordingly. In contrast to FIG.However, in this embodiment, the pn junction 50 on the detector is formed directly by an inventive superposition of a deep n- and p-layer NBL, PBL, respectively, and thus significantly deeper in the BCD substrate 100. Instead of a lightly n-doped, epitaxial region NEPI, a high-voltage n-well is formed as an extended absorption region below the p-well PW as an absorption region. A lightly n-doped, epitaxial region NEPI can be arranged around the PBL layer above the pn junction 50. The process flow for producing a corresponding single-photon avalanche diode 200 according to the invention thus differs only slightly from that of the prior art single-photon avalanche diode 200 described in FIG. 7. The advantageous nSPAD design can therefore be largely adopted without requiring any adaptations to the basic detector structure.The use of a BCD substrate 100 according to the invention with a deep pn junction 50 (or two deep pn junctions 50, 52 parallel to the surface of the carrier substrate 10) thus enables a simple increase in the absorption depth and thus the sensitivity of the detector provided.

[0084] A further advantage of using the BCD substrate 100 according to the invention shown is the possible provision and use of an independent second pn junction 52 on the underside of the deep n-layer NBL. This enables, in particular, the use of a second nSPAD on the underside of the carrier substrate 10. The second nSPAD can be addressed and read out, for example, by laterally contacting the PBL regions and the p-substrate with the anode on the top side of the BCD substrate. This enables, on the one hand, a compact 3D integration of multiple detector elements and, on the other hand, significant improvements in detection properties can be achieved and new fields of application can be opened up. An integrated single-photon detector sensitive from two sides can, for example, detect photon streams from opposite directions and thus determine deviations between the photon streams.In addition, the second SPAD can also be used as a reference detector to reduce the detector noise of the first SPAD due to environmental influences (e.g., cosmic radiation). The corresponding equivalent circuit also shows two diodes connected in reverse bias between an anode A and a cathode / common n-well C / TX. The anode terminal of the lower diode is also referred to as the common substrate SX.

[0085] Figure 9 shows a schematic representation of a second embodiment of a single-photon avalanche diode 200 according to the invention. The detector structure shown largely corresponds to the structure shown in Figure 8. The reference numerals and their assignment to individual features therefore apply accordingly. In contrast to Figure 8, the corresponding absorption region (NEPI) between the deep p-layer PBL and the anode A is completely formed as a lightly n-doped, epitaxial region NEPI with a high-voltage p-well HPW formed as a channel as a fully integrated quenching resistor QR. The quenching resistor QR preferably has a nonlinear resistance function.After a charge avalanche is triggered by photon-induced charge carrier generation in the absorption region (NEPI), a voltage drop occurs across the quenching resistor QR, preventing further charge carrier generation through impact ionization and thus quenching the charge carrier avalanche. A reverse voltage can then build up again in the detector with a delay before another charge avalanche can be triggered.

[0086] The integration of the quenching resistor QR as a channel in a lightly n-doped, epitaxial region NEPI is quite simple to implement in terms of process technology and, through its formation as a high-voltage p-well HPW, enables flexible adaptation of the desired resistance behavior. Direct integration can increase the fill factor on the BCD substrate 100. In the equivalent circuit diagram, the quenching resistor QR is shown above the internal anode of the diode. The upper terminal AQR can also be connected to another active or passive quenching resistor.

[0087] Figure 10 shows a schematic representation of a third embodiment of a single-photon avalanche diode 200 according to the invention. The detector structure shown largely corresponds to the structure shown in FIG. 9. The reference numerals and their assignment to individual features therefore apply accordingly. In contrast to FIG. 9, a plurality of deep-lying p-layers PBL are formed along the deep-lying n-layer NBL, arranged separately directly above the deep-lying n-layer NBL. This enables a juxtaposition of a plurality of independent single-photon avalanche diodes 200, by means of which the effective detector dead time can be largely completely circumvented with appropriate parallel operation. For example, with existing BCD technology, up to seven single-photon avalanche diodes 200 can be arranged in a pixel of a conventional SPAD array, typically approximately 20 pm wide.In the corresponding equivalent circuit diagram, this circuit is shown as a parallel connection of a plurality of single-photon avalanche diodes 200 according to the embodiment of FIG. 9. In the embodiments of FIGS. 9 and 10, the lower pn junctions provided in the BCD substrate 100 can also be used, as already described for FIG. 8, to form additional single-photon avalanche diodes 200. In this case, with existing BCD technology, this double arrangement could even currently allow up to fourteen single-photon avalanche diodes 200 to be arranged one above the other in a single 20 pm wide pixel of a conventional SPAD array. Improvements in the BCD technology used can be expected to significantly increase the number of single-photon avalanche diodes 200 that can be arranged within such a pixel in the future.The significantly increased integration density can be used, for example, to further increase the PDE or to reduce the error rate in detection.

[0088] List of reference symbols

[0089] 10 Carrier substrate 20 First dopant 22 First region 30 Second dopant 32 Second region 40 Epitaxial layer 50, 52 pn junction (“top”, “bottom”) 54a, 54b pn junction (“top right”, “bottom right”) 56a, 56b pn junction (“top left”, “bottom left”) 58 pn junction (state of the art) 100 BCD substrate 200 Single-photon avalanche diode (SPAD)

[0090] NBL deep-lying n-layer (n-type buried layer) PBL deep-lying p-layer (p-type buried layer)

[0091] ML1 , ML2 first and second mask layer H(V)PW high-voltage p-type well H(V)NW high-voltage n-type well PW p-type well NW n-type well DPW deep p-type well DNW deep n-type well NEPI light n-type epitaxy PEPI light p-type epitaxy MET1 metallization CONT contact SBL silicide blocking layer STI shallow trench isolation P + p + -Area N + n + -Area

[0092] A anode C cathode TW common n-well (“twin-well”)

[0093] SX bulk area or common substrate

[0094] QR quenching resistor

[0095] AQR anode-side terminal behind the quenching resistor

[0096] S surface d distance

Claims

Patent claims 1. A method for producing deep pn junctions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, comprising: - providing a carrier substrate (10); - introducing a first dopant (20) to form a first region (22) of the first conduction type into a surface (S) of the carrier substrate (10); - growing an epitaxial layer (40) on the surface (S) of the carrier substrate (10), wherein the first region (22) spreads by diffusion of the first dopant (20) in the epitaxial layer (40) and in the carrier substrate (10); - introducing a second dopant (30) to form a second region (32) of the second conduction type into a region of the first region (22), wherein the first region (22) and the second region (32) at least partially overlap, and the introduction of the second dopant (20, 30) is selected such that the first and second dopant (20, 30) form a pn junction (50, 52, 54a, 54b, 56a, 56b) lying in the epitaxial layer (40) as a result of the introduction.

2. A method for producing deep pn junctions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, comprising: - providing a carrier substrate (10); - introducing a first dopant (20) to form a first region (22) of the first conduction type into a surface (S) of the carrier substrate (10); - introducing a second dopant (30) to form a second region (32) of the second conductivity type into the surface (S) of the carrier substrate (10), wherein the first region (22) and the second region (32) at least partially overlap; - growing an epitaxial layer (40) on the surface (S) of the carrier substrate (10), wherein the first region (22) and the second region (32) spread by diffusion of the first dopant (20) and the second dopant (30) in the epitaxial layer (40) and in the carrier substrate (10), wherein the diffusion behavior of the first and the second dopant (20, 30) is selected such that the first and second Dopant (20, 30) forms a pn junction (50, 52, 54a, 54b, 56a, 56b) lying in the epitaxial layer (40) by diffusion.

3. The method according to claim 1 or 2, wherein the first and second dopant (20, 30) form, by introduction and / or diffusion, a pn junction (50, 52, 54a, 54b, 56a, 56b) in the epitaxial layer (40) and a pn junction (50, 52, 54a, 54b, 56a, 56b) in the carrier substrate (10).

4. The method according to any one of claims 1 to 3, wherein the first and the second dopant (20, 30) have different diffusion behavior in the carrier substrate (10) and / or in the epitaxial layer (40).

5. The method according to any one of claims 1 to 4, wherein the second dopant (30) has a higher diffusivity in the carrier substrate (10) and / or in the epitaxial layer (40) than the first dopant (20).

6. Method according to one of the preceding claims, wherein after the introduction of the first dopant (20) and / or the second dopant (30), heating of the carrier substrate (10) takes place to enhance the diffusion, and / or wherein after the growth of the epitaxial layer (40), heating of the carrier substrate (10) takes place to enhance the dopant diffusion.

7. Method according to one of the preceding claims, wherein the introduction of the first dopant (20) and / or the second dopant (30) is carried out maskless or via a mask process.

8. The method according to any one of claims 1 to 7, wherein immediately after the introduction of the second dopant (30) in a plan view of the surface (S) of the carrier substrate (10), the first region (22) or the second region (32) completely overlaps the respective other region (32, 22), or the first region (22) and the second region (32) only overlap in the peripheral areas.

9. The method according to any one of claims 1 to 7, wherein immediately after the introduction of the second dopant (30) in a plan view of the surface (S) of the carrier substrate (10), the first region (22) is overlaid at a left and right edge region by the edge regions of two second regions (32), or the second region (32) is overlaid at a left and right edge region by the edge regions of two first regions (22).

10. The method according to any one of the preceding claims, wherein the first region (22) is a deep n-layer (NBL) and the second region (32) is a deep p-layer (PBL).

11. A BCD substrate (100) with a deep pn junction (50, 52, 54a, 54b, 56a, 56b), comprising: a carrier substrate (10); and an epitaxial layer (40) grown on the carrier substrate (10), wherein a pn junction (50, 52, 54a, 54b, 56a, 56b) lying in the epitaxial layer was created between the carrier substrate (10) and the epitaxial layer (40) by a method according to claim 1 or by diffusion of dopants introduced into a surface (S) of the carrier substrate (10) below the epitaxial layer (40).

12. BCD substrate (100) according to claim 11, wherein a pn junction (50, 52, 54a, 54b, 56a, 56b) is produced in the epitaxial layer (40) and in the carrier substrate (10).

13. Single-photon avalanche diode (200), SPAD, comprising: a BCD substrate (100) according to claim 11 or 12, wherein a region around a p- n-junction (50, 52, 54a, 54b, 56a, 56b) forming an avalanche region, and an absorption region (PW, HPW, NEPI) for converting photons into electron-hole pairs, wherein the absorption region (PW, HPW, NEPI) is directly adjacent to the regions (NBL, PBL) forming the pn-junction (50, 52, 54a, 54b, 56a, 56b).

14. Single-photon avalanche diode (200) according to claim 13, wherein the pn junction (50, 52, 54a, 54b, 56a, 56b) is formed at least partially between a deep-lying n-layer (NBL) as the cathode (C) and a deep-lying p-layer (PBL) directly adjoining the deep-lying n-layer (NBL), the absorption region (PW, HPW, NEPI) directly adjoins the deep-lying p-layer (PBL) and is formed as a p-region, and an anode (A) formed as a p+ region directly adjoins the absorption region (PW, HPW, NEPI).

15. Single-photon avalanche diode (200) according to claim 14, wherein the absorption region (PW, HPW, NEPI) comprises a high-voltage p-well (HPW) immediately adjacent to the deep p-layer (PBL) and optionally a p-well (PW) immediately adjacent thereto.

16. Single-photon avalanche diode (200) according to claim 14 or 15, wherein the absorption region (PW, HPW, NEPI) between the deep p-layer (PBL) and the anode (A) is formed as a lightly n-doped, epitaxial region (NEPI) with a high-voltage p-well (HPW) formed as a channel as a non-linear quenching resistor (QR).

17. The single-photon avalanche diode (200) of claim 16, wherein a plurality of separate deep p-layers (PBL) arranged immediately above the deep n-layer (NBL) are formed along the deep n-layer (NBL).

18. An integrated circuit comprising at least one single-photon avalanche diode (200) according to any one of claims 13 to 17.

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