Power conversion device

Abstract

A control unit (50) performs all-element soft switching control for outputting required power by controlling a first phase difference and a second phase difference such that all of a plurality of primary-side switching elements (Q1-Q4) and a plurality of secondary-side switching elements (Q5-Q8) perform soft switching. When it is not possible to perform all-element soft switching control, the control unit (50) performs partial-element soft switching control for outputting required power by controlling the first phase difference and the second phase difference such that all of either the plurality of primary-side switching elements (Q1-Q4) or the plurality of secondary-side switching elements (Q5-Q8) perform soft switching and such that at least one of the other performs hard switching.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] The power conversion device disclosed in Patent Document 1 includes a transformer, a primary-side full bridge circuit, a secondary-side full bridge circuit, and a control unit. The transformer includes a primary winding and a secondary winding. The primary-side full bridge circuit includes a plurality of primary-side switching elements. The secondary-side full bridge circuit includes a plurality of secondary-side switching elements. The control unit controls the primary-side full bridge circuit so that three levels of primary-side voltages are applied to the primary winding. The control unit controls the secondary-side full bridge circuit so that three levels of secondary-side voltages are applied to the secondary winding. The control unit realizes soft switching of the primary-side switching elements and the secondary-side switching elements by controlling the phase difference between the primary-side voltage and the secondary-side voltage.

[0003] International Publication No. 2020 / 003717

[0004] This type of power conversion device can increase the transmitted power by advancing the phase of the primary-side voltage relative to the phase of the secondary-side voltage, i.e., by changing from a lagging-phase mode to a leading-phase mode. Here, when one of the primary-side voltage and the secondary-side voltage is a two-level voltage and the other is a three-level voltage, soft switching may not be possible for all switching elements near the same-phase mode (near the transition between the light-load mode and the heavy-load mode). The lagging-phase mode is a load mode in which the three-level voltage rises from a low level to a middle level, and then the two-level voltage rises from a low level to a high level. The leading-phase mode is a load mode in which the three-level voltage rises from a middle level to a high level, and then the two-level voltage rises from a low level to a high level, or in which the two-level voltage rises from a low level to a high level, and then the three-level voltage rises from a low level to a middle level.

[0005] One way to achieve soft switching for all switching elements is to increase the current flowing through the transformer. However, using a transformer with a smaller excitation inductance than normal to increase the current may increase losses other than switching losses, such as conduction losses, and may result in a decrease in overall efficiency.

[0006] A power conversion device according to one aspect of the present disclosure includes: a transformer unit having a primary winding, a secondary winding, and a reactor connected to at least one of the primary winding or the secondary winding; a primary full bridge circuit connected to the primary winding and having a plurality of primary switching elements; a secondary full bridge circuit connected to the secondary winding and having a plurality of secondary switching elements; and a control unit that controls the plurality of primary switching elements and the plurality of secondary switching elements, wherein a condition for performing soft switching of the plurality of primary switching elements is condition 1, and a condition for performing soft switching of the plurality of secondary switching elements is condition 2, and condition 1 is a condition in which a current that flows in the primary winding when at least one of the plurality of primary switching elements switches between ON and OFF, the value of a current that flows in a forward direction of a diode connected in parallel to the primary switching element that switches from OFF to ON among the plurality of primary switching elements is greater than or equal to a value of a current that flows in a forward direction of a diode connected in parallel to the primary switching element that switches from OFF to ON among the plurality of primary switching elements, the second condition is that the value of a current flowing in the secondary winding when at least one of the plurality of secondary switching elements switches between ON and OFF, the value of a current flowing in a forward direction of a diode connected in parallel to the secondary switching element that switches from OFF to ON among the plurality of secondary switching elements, is equal to or greater than the absolute value of a secondary winding current threshold; the control unit is configured to control the primary full bridge circuit and the secondary full bridge circuit so that one of the primary full bridge circuit and the secondary full bridge circuit applies a two-level voltage to the transformer unit, and the other applies a three-level voltage to the transformer unit; a first phase difference is a difference between a first time when the three-level voltage rises from a low level to a middle level and a second time when the two-level voltage rises from a low level to a high level, and a second phase difference is a difference between the first time and a third time when the three-level voltage rises from the middle level to a high level; and the control unit isThe first phase difference and the second phase difference are controlled so that all of the plurality of primary-side switching elements and the plurality of secondary-side switching elements perform soft switching, thereby performing all-element soft switching control to output the required power, and when the all-element soft switching control cannot be performed, the first phase difference and the second phase difference are controlled so that all of one of the plurality of primary-side switching elements and the plurality of secondary-side switching elements perform soft switching, and at least one of the other performs hard switching, thereby performing partial-element soft switching control to output the required power.

[0007] When the control unit cannot perform soft switching control on all elements, it performs soft switching control on some of the elements. This allows soft switching to be performed on all of the multiple primary-side switching elements and the multiple secondary-side switching elements. This makes it possible to suppress a decrease in the overall efficiency of the power conversion device compared to when soft switching cannot be performed on all switching elements.

[0008] In the above-described power conversion device, the control unit may be configured to have a light load mode and a heavy load mode in which the maximum value of the output power is greater than that in the light load mode, and to perform soft switching control of some of the elements when switching between the light load mode and the heavy load mode.

[0009] FIG. 1 is a circuit diagram of a power conversion device according to a first embodiment. FIG. 2 is a diagram showing the relationship between the equivalent voltage ratio and the load mode. FIG. 3 is a diagram showing the primary-side voltage and the secondary-side voltage in the first buck delay phase mode. FIG. 4 is a diagram showing the primary-side voltage and the secondary-side voltage in the first buck inline phase mode. FIG. 5 is a diagram showing the primary-side voltage and the secondary-side voltage in the first buck lead phase mode. FIG. 6 is a diagram showing the primary-side current and the secondary-side current in the first boost delay phase mode. FIG. 7 is a diagram showing the primary-side voltage and the secondary-side voltage in the first boost inline phase mode. FIG. 8 is a diagram showing the primary-side voltage and the secondary-side voltage in the first boost lead phase mode. FIG. 9 is a flowchart showing the all-element soft switching control. FIG. 10 is a diagram showing the primary-side current and the secondary-side current in the first buck delay phase mode. FIG. 11 is a flowchart showing the partial-element soft switching control. FIG. 12 is a diagram showing the primary-side current and the secondary-side current when the partial-element soft switching control is performed. FIG. 13 is a diagram showing the primary-side current and the secondary-side current when partial element soft switching control is performed. FIG. 14 is a diagram showing the primary-side current and the secondary-side current when partial element soft switching control is performed. FIG. 15 is a diagram showing the primary-side current and the secondary-side current when partial element soft switching control is performed. FIG. 16 is a diagram showing the primary-side current and the secondary-side current when partial element soft switching control is performed. FIG. 17 is a diagram showing the primary-side current and the secondary-side current when partial element soft switching control is performed. FIG. 18 is a circuit diagram of the power conversion device of the second embodiment. FIG. 19 is a diagram showing the primary-side voltage and the secondary-side voltage in the second step-down delay phase mode. FIG. 20 is a diagram showing the primary-side voltage and the secondary-side voltage in the second step-down in-phase mode. FIG. 21 is a diagram showing the primary-side voltage and the secondary-side voltage in the second step-down lead phase mode. FIG. 22 is a diagram showing the primary-side voltage and the secondary-side voltage in the second step-up delay phase mode. 23 and 24 are diagrams showing the primary and secondary voltages in the second boost in-phase mode and the second boost lead phase mode, respectively.

[0010] [First Embodiment] A first embodiment of a power conversion device will be described. As shown in Fig. 1, a power supply system 100 includes a DC power supply 110, a load 120, and a power conversion device 10. The DC power supply 110 inputs DC power to the power conversion device 10. The DC power supply 110 is, for example, a battery or a power supply circuit. The power supply circuit is, for example, an AC / DC converter that converts AC power into DC power and outputs it. The load 120 is, for example, a secondary battery that can charge and discharge DC power. The secondary battery is, for example, a lithium-ion battery or a lead-acid battery.

[0011] <Power Conversion Device> The power conversion device 10 is a dual active bridge DC / DC converter. The power conversion device 10 is provided between a DC power supply 110 and a load 120. The power conversion device 10 is capable of converting DC power input from the DC power supply 110 and outputting the converted power to the load 120. The power conversion device 10 is capable of converting DC power input from the load 120 and outputting the converted power to the DC power supply 110. In the following description, the primary side is treated as the input and the secondary side as the output. That is, the power conversion device 10 converts a DC voltage input from the DC power supply 110 and outputs the converted power to the load 120.

[0012] The power conversion device 10 includes two primary terminals 11 and 12 and two secondary terminals 13 and 14. A DC power supply 110 is electrically connected to the primary terminals 11 and 12. A load 120 is electrically connected to the secondary terminals 13 and 14.

[0013] The power conversion device 10 includes a transformer unit TS. The transformer unit TS includes a transformer 20 and a reactor L1. The transformer 20 is an insulated type. The transformer 20 includes a magnetic core 21, a primary winding 22, and a secondary winding 23. The primary winding 22 and the secondary winding 23 are wound around the core 21. The transformer 20 is connected to a reactor L1. The reactor L1 may be an element such as a choke coil, or may be leakage inductance of the primary winding 22 and the secondary winding 23. In this embodiment, the reactor L1 is connected to the primary winding 22. The reactor L1 and the primary winding 22 form a series connection 24.

[0014] The power conversion device 10 includes a primary-side full-bridge circuit 30. The primary-side full-bridge circuit 30 includes a first leg 31 and a second leg 32. The first leg 31 and the second leg 32 are connected to primary-side terminals 11 and 12 so as to be connected in parallel with each other. As a result, the primary-side full-bridge circuit 30 is electrically connected to a DC power supply 110 via the primary-side terminals 11 and 12. The first leg 31 includes a first switching element Q1, a second switching element Q2, diodes D1 and D2, and capacitors C1 and C2. The first switching element Q1 and the second switching element Q2 are connected in series with each other. The second leg 32 includes a third switching element Q3, a fourth switching element Q4, diodes D3 and D4, and capacitors C3 and C4. The third switching element Q3 and the fourth switching element Q4 are connected in series with each other. The first switching element Q1 and the third switching element Q3 form an upper arm, and the second switching element Q2 and the fourth switching element Q4 form a lower arm.

[0015] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 constitute a plurality of primary-side switching elements Q1 to Q4. The primary-side switching elements Q1 to Q4 are, for example, n-type metal oxide semiconductor field effect transistors (MOSFETs). The primary-side switching elements Q1 to Q4 may also be p-type MOSFETs, IGBTs (insulated gate bipolar transistors), or GaN-HEMTs.

[0016] The diodes D1 to D4 and the capacitors C1 to C4 are connected in parallel to the primary-side switching elements Q1 to Q4, respectively. The diodes D1 to D4 may be parasitic diodes or elements. The capacitors C1 to C4 may be parasitic capacitances, elements, or a combination of parasitic capacitances and elements.

[0017] The connection point between the first switching element Q1 and the second switching element Q2, and the connection point between the third switching element Q3 and the fourth switching element Q4 are each connected to the primary winding 22. As a result, the primary full-bridge circuit 30 is connected to the primary winding 22. The primary full-bridge circuit 30 is also connected to the reactor L1.

[0018] The power conversion device 10 includes a primary-side voltage sensor 37. The primary-side voltage sensor 37 detects an input voltage Vin input from a DC power supply 110 to the primary-side full-bridge circuit 30. The power conversion device 10 includes a secondary-side full-bridge circuit 40. The secondary-side full-bridge circuit 40 includes a third leg 41 and a fourth leg 42. The third leg 41 and the fourth leg 42 are connected to secondary-side terminals 13 and 14 so as to be connected in parallel with each other. As a result, the secondary-side full-bridge circuit 40 is electrically connected to the load 120. The third leg 41 includes a fifth switching element Q5, a sixth switching element Q6, diodes D5 and D6, and capacitors C5 and C6. The fifth switching element Q5 and the sixth switching element Q6 are connected in series with each other. The fourth leg 42 includes a seventh switching element Q7, an eighth switching element Q8, diodes D7 and D8, and capacitors C7 and C8. The seventh switching element Q7 and the eighth switching element Q8 are connected in series. The fifth switching element Q5 and the seventh switching element Q7 form an upper arm. The sixth switching element Q6 and the eighth switching element Q8 form a lower arm.

[0019] The fifth switching element Q5, the sixth switching element Q6, the seventh switching element Q7, and the eighth switching element Q8 constitute a plurality of secondary-side switching elements Q5 to Q8. The secondary-side switching elements Q5 to Q8 are, for example, n-type MOSFETs. The secondary-side switching elements Q5 to Q8 may also be p-type MOSFETs, IGBTs, or GaN-HEMTs.

[0020] Diodes D5 to D8 and capacitors C5 to C8 are connected in parallel to secondary-side switching elements Q5 to Q8, respectively. Diodes D5 to D8 may be parasitic diodes or elements. Capacitors C5 to C8 may be parasitic capacitances, elements, or a combination of parasitic capacitances and elements.

[0021] The connection point between the fifth switching element Q5 and the sixth switching element Q6, and the connection point between the seventh switching element Q7 and the eighth switching element Q8 are each connected to the secondary winding 23. As a result, the secondary full bridge circuit 40 is connected to the secondary winding 23.

[0022] The output power of the secondary-side full-bridge circuit 40 is supplied to a load 120. The power conversion device 10 includes a secondary-side voltage sensor 47. The secondary-side voltage sensor 47 detects the output voltage Vout of the power conversion device 10.

[0023] The power conversion device 10 includes a control unit 50. The control unit 50 includes a processor and a memory unit. The processor may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). The memory unit includes a random access memory (RAM) and a read-only memory (ROM). The memory unit stores program code or instructions configured to cause the processor to execute processing. The memory unit, i.e., a computer-readable medium, includes any available medium accessible by a general-purpose or special-purpose computer. The control unit 50 may be configured with a hardware circuit such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The control unit 50, which is a processing circuit, may include one or more processors operating according to a computer program, one or more hardware circuits such as an ASIC or an FPGA, or a combination thereof.

[0024] The control unit 50 converts the input voltage Vin into the output voltage Vout by controlling the plurality of primary side switching elements Q1 to Q4 and the plurality of secondary side switching elements Q5 to Q8.

[0025] In this embodiment, the control unit 50 controls the primary full bridge circuit 30 in three levels and the secondary full bridge circuit 40 in two levels.

[0026] Three-level control is control in which the voltage applied to the transformer unit TS, i.e., the series connection 24 of the primary winding 22 and the reactor L1, is switched between three levels: positive, negative, or zero. Two-level control is control in which the voltage applied to the transformer unit TS, i.e., the secondary winding 23, is switched between two levels: positive and negative. In three-level control, a positive voltage applied to the series connection 24 is referred to as a high level, a zero voltage applied to the series connection 24 is referred to as a middle level, and a negative voltage applied to the series connection 24 is referred to as a low level. In two-level control, a positive voltage applied to the secondary winding 23 is referred to as a high level, and a negative voltage applied to the secondary winding 23 is referred to as a low level. The voltage applied to the series connection 24 is referred to as a primary voltage V1, and the voltage applied to the secondary winding 23 is referred to as a secondary voltage V2. The primary-side voltage V1 is the potential difference between the connection point between the first switching element Q1 and the second switching element Q2 and the connection point between the third switching element Q3 and the fourth switching element Q4. The secondary-side voltage V2 is the potential difference between the connection point between the fifth switching element Q5 and the sixth switching element Q6 and the connection point between the seventh switching element Q7 and the eighth switching element Q8. In the first embodiment, the primary-side voltage V1 is a three-level voltage. The secondary-side voltage V2 is a two-level voltage. The arrows in FIG. 1 indicate the positive directions of the primary-side voltage V1 and the secondary-side voltage V2. During normal operation when the output is not changed, the primary-side voltage V1 and the secondary-side voltage V2 have waveforms of the same frequency that are inverted in phase every 180 degrees.

[0027] When performing three-level control of the primary-side full-bridge circuit 30, the control unit 50 independently controls the first leg 31 and the second leg 32. The switching patterns of the primary-side full-bridge circuit 30 include first to fourth patterns.

[0028] The first pattern is a switching pattern in which the first switching element Q1 is turned on, the second switching element Q2 is turned off, the third switching element Q3 is turned off, and the fourth switching element Q4 is turned on.

[0029] The second pattern is a switching pattern in which the first switching element Q1 is turned on, the second switching element Q2 is turned off, the third switching element Q3 is turned on, and the fourth switching element Q4 is turned off.

[0030] The third pattern is a switching pattern in which the first switching element Q1 is turned off, the second switching element Q2 is turned on, the third switching element Q3 is turned on, and the fourth switching element Q4 is turned off.

[0031] The fourth pattern is a switching pattern in which the first switching element Q1 is turned off, the second switching element Q2 is turned on, the third switching element Q3 is turned off, and the fourth switching element Q4 is turned on.

[0032] When performing two-level control of the secondary-side full-bridge circuit 40, the control unit 50 controls the third leg 41 and the fourth leg 42 in conjunction with each other. The control unit 50 simultaneously turns on the fifth switching element Q5 and the eighth switching element Q8. The control unit 50 simultaneously turns on the sixth switching element Q6 and the seventh switching element Q7. The switching patterns of the secondary-side full-bridge circuit 40 include a fifth pattern and a sixth pattern.

[0033] The fifth pattern is a switching pattern in which the fifth switching element Q5 is turned on, the sixth switching element Q6 is turned off, the seventh switching element Q7 is turned off, and the eighth switching element Q8 is turned on.

[0034] The sixth pattern is a switching pattern in which the fifth switching element Q5 is turned off, the sixth switching element Q6 is turned on, the seventh switching element Q7 is turned on, and the eighth switching element Q8 is turned off.

[0035] The control unit 50 outputs an output voltage Vout from the secondary full bridge circuit 40 by combining any one of the first to fourth patterns of the primary full bridge circuit 30 with any one of the fifth and sixth patterns of the secondary full bridge circuit 40.

[0036] Here, the number of turns of the primary winding 22 of the transformer 20 is N1, and the number of turns of the secondary winding 23 is N2. The ratio of the input voltage Vin input to the primary full bridge circuit 30 to the output voltage Vout output from the secondary full bridge circuit 40 is the voltage ratio. The equivalent voltage ratio, which is the equivalent voltage ratio when the winding ratio of the transformer 20 is converted to 1:1, is (Vout × N1) / (Vin × N2). Vin × N2 is the equivalent input voltage when the winding ratio of the transformer is converted to 1:1. Vout × N1 is the equivalent output voltage when the winding ratio of the transformer is converted to 1:1. The control unit 50 has a first step-down mode and a first step-up mode as load modes. The first step-down mode is a load mode in which the equivalent voltage ratio is less than 1. The first step-up mode is a load mode in which the equivalent voltage ratio is greater than 1.

[0037] For example, if the turns ratio of transformer 20 is 1:2, the input voltage Vin=200V, and the output voltage Vout=400V, converting the turns ratio to 1:1 gives an equivalent voltage ratio = (Vout x 1) / (Vin x 2)=1. Therefore, if the turns ratio of transformer 20 is 1:2 and the input voltage Vin=200V, the output voltage Vout is in step-down mode if it is less than 400V, and in step-up mode if it is greater than 400V. Note that the following explanation will be given assuming a turns ratio of 1:1 unless otherwise specified.

[0038] <First Step-Down Mode> As shown in FIG. 2, the first step-down mode includes a first step-down delay phase mode, a first step-down in-phase mode, and a first step-down lead phase mode.

[0039] As shown in Fig. 3, the first step-down delay phase mode is a first step-down mode in which the primary-side voltage V1 is raised from a low level to a middle level, the secondary-side voltage V2 is raised from a low level to a high level, and then the primary-side voltage V1 is raised from the middle level to a high level. The first step-down delay phase mode is a first step-down mode in which a small amount of power is output in response to the power requested by the load 120. The first step-down delay phase mode is an example of a delay phase mode. The delay phase mode is a load mode in which the three-level voltage is raised from a low level to a middle level, and then the two-level voltage is raised from a low level to a high level.

[0040] In the load mode of the first embodiment, the difference between the first time T1 when the primary voltage V1 rises from a low level to a middle level and the second time T2 when the secondary voltage V2 rises from a low level to a high level is the first phase difference θ1. The difference between the first time T1 and the third time T3 when the primary voltage V1 rises from a middle level to a high level is the second phase difference θ2.

[0041] As described above, during normal operation with no change in output, the primary-side voltage V1 and the secondary-side voltage V2 have waveforms of the same frequency that are inverted in phase every 180 degrees. Therefore, the time when the primary-side voltage V1 falls from high to middle level is also the first time T1, the time when the secondary-side voltage V2 falls from high to low level is also the second time T2, and the time when the primary-side voltage V1 falls from middle to low level is also the third time T3.

[0042] As shown in FIG. 4 , the first in-phase step-down mode is a first step-down mode in which, after the primary voltage V1 is raised from a low level to a middle level, the secondary voltage V2 is raised from a low level to a high level and the primary voltage V1 is raised from the middle level to a high level simultaneously. In the first in-phase step-down mode, the second time T2 and the third time T3 are the same time. Therefore, the first phase difference θ1 is the same as the second phase difference θ2. The first in-phase step-down mode is a first step-down mode in which medium power is output in response to the power requested by the load 120. Medium power is power greater than low power.

[0043] As shown in FIG. 5 , the first buck-step-down lead phase mode is a first buck mode in which the primary-side voltage V1 is raised from a low level to a middle level, then the primary-side voltage V1 is raised from the middle level to a high level, and then the secondary-side voltage V2 is raised from a low level to a high level. The first buck-step-down lead phase mode is a first buck mode in which high power is output in response to the power required by the load 120. The high power is power greater than medium power. The first buck-step-down lead phase mode is an example of a lead phase mode. The lead phase mode of this embodiment is a load mode in which the three-level voltage is raised from a middle level to a high level, and then the two-level voltage is raised from a low level to a high level.

[0044] The first buck delay phase mode is an example of a light load mode. The first buck advance phase mode is an example of a heavy load mode. The heavy load mode has a higher maximum output power than the light load mode. The first buck in-phase mode is a load mode used when switching between the light load mode and the heavy load mode. The first buck mode switches between the first buck delay phase mode and the first buck advance phase mode when the first phase difference θ1 and the second phase difference θ2 are the same.

[0045] <First Boost Mode> As shown in FIG. 2, the first boost mode includes a first boost delay phase mode, a first boost in-phase mode, and a first boost lead phase mode.

[0046] As shown in FIG. 6 , the first boost delay phase mode is a first boost mode in which the primary-side voltage V1 is raised from a low level to a middle level, the secondary-side voltage V2 is raised from a low level to a high level, and then the primary-side voltage V1 is raised from the middle level to a high level. The first boost delay phase mode is a first boost mode used when outputting small power in accordance with the power requested by the load 120. The first boost delay phase mode differs from the first buck delay phase mode in that the high level of the secondary-side voltage V2 is higher in voltage than the high level of the primary-side voltage V1. The first boost delay phase mode also differs from the first buck delay phase mode in that the low level of the secondary-side voltage V2 is lower in voltage than the low level of the primary-side voltage V1. The first boost delay phase mode is an example of a delay phase mode.

[0047] As shown in FIG. 7 , the first in-phase boost mode is a first boost mode in which the primary voltage V1 is raised from a low level to a middle level, and then the secondary voltage V2 is raised from a low level to a high level and the primary voltage V1 is raised from a middle level to a high level simultaneously. In the first in-phase boost mode, the second time T2 and the third time T3 are the same. Therefore, the first phase difference θ1 is the same as the second phase difference θ2. The first in-phase boost mode is a first boost mode used when medium power is output in response to the power requested by the load 120. Medium power is greater than low power. The first in-phase boost mode differs from the first in-phase buck mode in that the high level of the secondary voltage V2 is higher than the high level of the primary voltage V1. The first in-phase buck mode also differs from the first in-phase buck mode in that the low level of the secondary voltage V2 is lower than the low level of the primary voltage V1.

[0048] As shown in FIG. 8 , the first boost-lead phase mode is a first boost mode in which the primary-side voltage V1 is raised from a low level to a middle level, then the primary-side voltage V1 is raised from a middle level to a high level, and then the secondary-side voltage V2 is raised from a low level to a high level. The first boost-lead phase mode is a first boost mode used when outputting large power in response to the power requested by the load 120. The first boost-lead phase mode differs from the first buck-lead phase mode in that the high level of the secondary-side voltage V2 is higher in voltage than the high level of the primary-side voltage V1. The first boost-lead phase mode also differs from the first buck-lead phase mode in that the low level of the secondary-side voltage V2 is lower in voltage than the low level of the primary-side voltage V1. The first boost-lead phase mode is an example of a lead phase mode.

[0049] The first boost delay phase mode is an example of a light load mode. The first boost advance phase mode is an example of a heavy load mode. The first boost same phase mode is a mode used when switching between the light load mode and the heavy load mode. The first boost mode switches between the first boost delay phase mode and the first boost advance phase mode when the first phase difference θ1 and the second phase difference θ2 are the same.

[0050] <All-element soft switching control> The control unit 50 performs all-element soft switching control. The all-element soft switching control is a control for outputting required power by controlling the first phase difference θ1 and the second phase difference θ2 so that all of the multiple primary-side switching elements Q1 to Q4 and the multiple secondary-side switching elements Q5 to Q8 perform soft switching. The all-element soft switching control will be described below.

[0051] 9 and 10 , in step S1, the control unit 50 derives a soft switching region. The soft switching region is set for each of the primary current I1 and the secondary current I2. The primary current I1 is a current flowing through the primary winding 22. The secondary current I2 is a current flowing through the secondary winding 23. In FIG. 1 , the arrows indicate the positive directions of the primary current I1 and the secondary current I2.

[0052] The condition for soft switching of the primary-side switching elements Q1 to Q4 is that, when the primary-side switching elements Q1 to Q4 switch between ON and OFF, the value of the primary-side current I1, which is a current flowing in the forward direction of a diode connected in parallel to one of the primary-side switching elements Q1 to Q4 that changes from OFF to ON, is equal to or greater than the absolute value of the primary-side winding current threshold TI1. Hereinafter, this condition will be referred to as condition 1. The region that satisfies this condition is the soft-switching region of the primary-side current I1. When the primary-side switching elements Q1 to Q4 switch between ON and OFF, this is the time when at least one of the primary-side switching elements Q1 to Q4 changes from ON to OFF or from OFF to ON. This is the same as the first time T1 or the third time T3. The first time T1 is the time when the primary voltage V1 rises from a low level to a middle level or falls from a high level to a middle level. The third time T3 is the time when the primary voltage V1 rises from a middle level to a high level or falls from a middle level to a low level.

[0053] The condition for soft switching of the multiple secondary-side switching elements Q5 to Q8 is that, when the secondary-side switching elements Q5 to Q8 switch between ON and OFF, the value of the secondary-side current I2, which is a forward current flowing through a diode connected in parallel with one of the secondary-side switching elements Q5 to Q8 that switches from OFF to ON, is equal to or greater than the absolute value of the secondary-side winding current threshold TI2. Hereinafter, this condition will be referred to as condition 2. The region that satisfies this condition is the soft-switching region of the secondary-side current I2. When the secondary-side switching elements Q5 to Q8 switch between ON and OFF, this is the time when at least one of the secondary-side switching elements Q5 to Q8 switches from ON to OFF or from OFF to ON. This is the same as second time T2, which is the time when the secondary-side voltage V2 rises from low to high or falls from high to low.

[0054] As described above, the primary voltage V1 and the secondary voltage V2 have waveforms of the same frequency that are inverted every 180 degrees in phase, so only the positive and negative signs are inverted during the rising and falling periods, and it is therefore sufficient to consider only one of them. The following explanation will focus on the rising period only.

[0055] FIG. 10 shows, as an example, the primary-side current I1 and the secondary-side current I2 in the first step-down delay phase mode. As can be seen from a comparison with the voltage waveforms in FIG. 3 , in the example shown in FIG. 10 , at the first time T1, the switching pattern of the primary-side full bridge circuit 30 is switched from the third pattern to the second pattern. At the third time T3, the switching pattern of the primary-side full bridge circuit 30 is switched from the second pattern to the first pattern. If condition 1 is satisfied at the first time T1 and the third time T3, soft switching of the primary-side switching elements Q1 to Q4 is achieved. At the second time T2, the switching pattern of the secondary-side full bridge circuit 40 is switched from the sixth pattern to the fifth pattern. At this time, if condition 2 is satisfied, soft switching of the secondary-side switching elements Q5 to Q8 is achieved.

[0056] The primary winding current threshold TI1 is defined by the following equation (1).

[0057] TI1: primary winding current threshold, k1: coefficient, V1: primary voltage, L: inductance of reactor L1, and C01: capacitance corresponding to one switching element relative to the combined capacitance of all capacitors C1 to C4 arranged in parallel with switching elements Q1 to Q4 of primary full-bridge circuit 30. If the capacitance of capacitor C1 is C11, the capacitance of capacitor C2 is C12, the capacitance of capacitor C3 is C13, and the capacitance of capacitor C4 is C14, then C01 = (C11 + C12 + C13 + C14) / 4 may be used. If Cx is the largest capacitance among C11 to C14, then C01 = Cx may be used. The secondary winding current threshold TI2 is similarly defined by replacing each value with a secondary value. In this way, the soft switching region is derived.

[0058] Next, in step S2, the control unit 50 calculates a target current. The target current is a current value that can output the power required by the load 120 and that satisfies conditions 1 and 2. Of the primary-side switching elements Q1 to Q4, the fourth switching element Q4 is the primary-side switching element that changes from OFF to ON at the third time T3. The fourth switching element Q4 is the primary-side switching element that changes from OFF to ON when the switching pattern changes from the second pattern to the first pattern.

[0059] To satisfy Condition 1, the primary current I1 at the first time T1 and the third time T3 is considered. However, it is sufficient to consider the primary current I1 at the third time T3, which is the time when the absolute value of the current is smaller between the first time T1 and the third time T3 in this load mode. Therefore, to satisfy Condition 1, the primary current I1 at the third time T3, which flows forward through the diode D4 connected in parallel with the fourth switching element Q4 that changes from OFF to ON at this time, must be equal to or greater than the absolute value "|TI1|" of the primary winding current threshold TI1. This current value is the value "-I1" in FIG. 1. As can be seen from FIG. 10, the primary current I1 is negative at the third time T3, so "-I1" becomes a positive value. Furthermore, which of the first time T1 and the third time T3 has the smaller absolute value varies depending on the load mode.

[0060] In this load mode, Condition 2 is satisfied when the secondary current I2 at the second time T2 is greater than or equal to the absolute value "|TI2|" of the secondary winding current threshold TI2, and the forward current value of the diodes D5 and D8 connected in parallel to the fifth switching element Q5 and the eighth switching element Q8, which change from OFF to ON at this time, is equal to or greater than the absolute value "|TI2|" of the secondary winding current threshold TI2. This current value is the value of "I2" in FIG. 1. The fifth switching element Q5 and the eighth switching element Q8 are secondary switching elements that change from OFF to ON when the switching pattern changes from the sixth pattern to the fifth pattern. As can be seen from FIG. 10, the secondary current I2 is a positive value at the second time T2, so "I2" also becomes a positive value.

[0061] In practice, for example, condition 1 may be satisfied by comparing TI1', which is the primary winding current threshold TI1 converted to the secondary winding, with the secondary current I2 at the first time T1, or vice versa. In this case, it is sufficient to consider either the primary current I1 or the secondary current I2. Furthermore, the inductance L of the reactor L1 may be set in advance so that if one of condition 1 or condition 2 is satisfied, the other will also be satisfied.

[0062] In this way, it is possible to calculate a combination of target currents that can output the requested power from the load 120 and that satisfies conditions 1 and 2. If there is no combination of target currents that can output the requested power and that satisfies conditions 1 and 2, this means that soft switching is not possible for that requested power and load mode.

[0063] Next, in step S3, the control unit 50 derives a combination of the first phase difference θ1 and the second phase difference θ2 from the calculated target current. Here, the control unit 50 derives the combination of the first phase difference θ1 and the second phase difference θ2 so as to follow the calculated target current at the first time T1 and the calculated target current at the second time T2. In other words, the combination of the first phase difference θ1 and the second phase difference θ2 is a combination that can output the required power of the load 120 and satisfies conditions 1 and 2.

[0064] In step S4, the control unit 50 controls the primary-side full-bridge circuit 30 and the secondary-side full-bridge circuit 40 so as to realize the first phase difference θ1 and the second phase difference θ2 derived in step S3.

[0065] The required power, the first phase difference θ1, and the second phase difference θ2 may be calculated each time, or may be calculated in advance and stored in a map or the like. <Partial Element Soft Switching Control> The control unit 50 performs partial element soft switching control. Partial element soft switching control is control that is performed when all element soft switching control cannot be performed. Partial element soft switching control may be performed when a combination of the first phase difference θ1 and the second phase difference θ2 cannot be derived as a result of performing all element soft switching control. Partial element soft switching control may be performed by determining whether all element soft switching control can be performed based on the required power, the first phase difference θ1, the second phase difference θ2, etc., and when it is determined that all element soft switching control cannot be performed.

[0066] The partial element soft switching control is a control for outputting the required power by controlling the first phase difference θ1 and the second phase difference θ2 so that all of one of the multiple primary side switching elements Q1 to Q4 and the multiple secondary side switching elements Q5 to Q8 perform soft switching and at least one of the other performs hard switching. That is, this is a control for preferentially soft switching one of the primary side switching elements Q1 to Q4 and the secondary side switching elements Q5 to Q8. First, a case will be described in which all of the primary side switching elements Q1 to Q4 perform soft switching and some of the secondary side switching elements Q5 to Q8 perform hard switching.

[0067] 11 , in step S11, the control unit 50 derives a combination of the first phase difference θ1 and the second phase difference θ2 that can output the power required by the load 120 and that satisfies Condition 1. That is, it is sufficient to derive the first phase difference θ1 and the second phase difference θ2 that enable soft switching of only the primary-side switching elements Q1 to Q4 among the primary-side switching elements Q1 to Q4 and the secondary-side switching elements Q5 to Q8.

[0068] Next, in step S12, the control unit 50 controls the primary-side full-bridge circuit 30 and the secondary-side full-bridge circuit 40 so as to achieve the combination of the first phase difference θ1 and the second phase difference θ2 derived in step S11. Since soft switching control of some elements is performed when soft switching control of all elements cannot be performed, even if control is performed to achieve the first phase difference θ1 and the second phase difference θ2 derived in step S11, it is not possible to soft-switch all of the switching elements Q1 to Q8. Therefore, condition 2 is not satisfied, and as a result, at least one of the secondary-side switching elements Q5 to Q8 is hard-switched.

[0069] The soft switching control of some elements is performed, for example, when the equivalent voltage ratio is close to 1. That is, the soft switching control of some elements is performed when switching from the light load mode to the heavy load mode or when switching from the heavy load mode to the light load mode.

[0070] 12 to 14 show the primary-side current I1 and the secondary-side current I2 when soft-switching control is performed on some elements so that soft-switching of the primary-side switching elements Q1 to Q4 is prioritized when switching from the first step-down delay phase mode to the first step-down lead phase mode. There are cases where condition 1 is satisfied but condition 2 is not. In the example shown in FIGS. 12 to 14, at second time T2 when the secondary-side voltage V2 rises from low level to high level or falls from high level to low level, two secondary-side switching elements Q5 to Q8 are hard-switched, respectively, i.e., four secondary-side switching elements Q5 to Q8 are hard-switched in one cycle.

[0071] Next, a case will be described in which all of the secondary-side switching elements Q5 to Q8 perform soft switching and some of the primary-side switching elements Q1 to Q4 perform hard switching. In this case, the control unit 50 derives a combination of the first phase difference θ1 and the second phase difference θ2 that can output the power required by the load 120 and satisfy Condition 2. That is, it is sufficient to derive the first phase difference θ1 and the second phase difference θ2 that allow only the secondary-side switching elements Q5 to Q8 to be soft-switched out of the primary-side switching elements Q1 to Q4 and the secondary-side switching elements Q5 to Q8.

[0072] 15 to 17 show the primary-side current I1 and the secondary-side current I2 when soft-switching control is performed on some elements so that soft-switching of the secondary-side switching elements Q5 to Q8 is prioritized when switching from the first step-down delay phase mode to the first step-down lead phase mode. There are cases where condition 1 is not met while condition 2 is met. In the examples shown in FIGS. 15 to 17, one of the primary-side switching elements Q1 to Q4 is hard-switched at a third time T3 when the primary-side voltage V1 rises from the middle level to the high level or when the primary-side voltage V1 falls from the middle level to the low level, i.e., two primary-side switching elements Q1 to Q4 are hard-switched in one cycle.

[0073] [Effects of the First Embodiment] (1-1) When soft switching control of all elements cannot be performed, the control unit 50 performs soft switching control of some elements. As a result, soft switching can be performed on all of the primary-side switching elements Q1 to Q4 and the secondary-side switching elements Q5 to Q8. This can suppress a decrease in the overall efficiency of the power conversion device 10 compared to when soft switching cannot be performed on all of the switching elements Q1 to Q8.

[0074] Second Embodiment A second embodiment of the power conversion device will be described, focusing on differences from the first embodiment.

[0075] 18 , the second embodiment differs from the first embodiment in that a reactor L2 is connected to a secondary winding 23 instead of a primary winding 22, and the three-level control and two-level control are reversed between the primary and secondary sides. The transformer unit TS includes a transformer 20 and a reactor L2. The secondary winding 23 and the reactor L2 form a series connection 25.

[0076] In the second embodiment, the control unit 50 performs two-level control on the primary full bridge circuit 30 and three-level control on the secondary full bridge circuit 40. The three-level control is a control in which the voltage applied to the transformer unit TS, i.e., the series connection 25 of the secondary winding 23 and the reactor L2, is switched between three levels: positive, negative, or zero. The two-level control is a control in which the voltage applied to the transformer unit TS, i.e., the primary winding 22, is switched between two levels: positive and negative. In the three-level control, a positive voltage applied to the series connection 25 is referred to as a high level, a zero voltage applied to the series connection 25 is referred to as a middle level, and a negative voltage applied to the series connection 25 is referred to as a low level. In the two-level control, a positive voltage applied to the primary winding 22 is referred to as a high level, and a negative voltage applied to the primary winding 22 is referred to as a low level. The voltage applied to the primary winding 22 is defined as the primary voltage V1. The voltage applied to the series-connected body 25 is defined as the secondary voltage V2. The primary voltage V1 is a two-level voltage. The secondary voltage V2 is a three-level voltage. The arrows in FIG. 18 indicate the positive directions of the primary voltage V1 and the secondary voltage V2. During normal operation with no change in output, the primary voltage V1 and the secondary voltage V2 have waveforms of the same frequency that are inverted in phase every 180 degrees.

[0077] When performing two-level control of the primary-side full-bridge circuit 30, the control unit 50 controls the first leg 31 and the second leg 32 in conjunction with each other. The control unit 50 simultaneously turns on the first switching element Q1 and the fourth switching element Q4. The control unit 50 simultaneously turns on the second switching element Q2 and the third switching element Q3. The switching patterns of the primary-side full-bridge circuit 30 include a seventh pattern and an eighth pattern.

[0078] The seventh pattern is a switching pattern in which the first switching element Q1 is turned on, the second switching element Q2 is turned off, the third switching element Q3 is turned off, and the fourth switching element Q4 is turned on.

[0079] The eighth pattern is a switching pattern in which the first switching element Q1 is turned off, the second switching element Q2 is turned on, the third switching element Q3 is turned on, and the fourth switching element Q4 is turned off.

[0080] When performing three-level control of the secondary-side full-bridge circuit 40, the control unit 50 independently controls the third leg 41 and the fourth leg 42. The switching patterns of the secondary-side full-bridge circuit 40 include ninth to twelfth patterns.

[0081] The ninth pattern is a switching pattern in which the fifth switching element Q5 is turned on, the sixth switching element Q6 is turned off, the seventh switching element Q7 is turned off, and the eighth switching element Q8 is turned on.

[0082] The tenth pattern is a switching pattern in which the fifth switching element Q5 is turned on, the sixth switching element Q6 is turned off, the seventh switching element Q7 is turned on, and the eighth switching element Q8 is turned off.

[0083] The eleventh pattern is a switching pattern in which the fifth switching element Q5 is turned off, the sixth switching element Q6 is turned on, the seventh switching element Q7 is turned on, and the eighth switching element Q8 is turned off.

[0084] The twelfth pattern is a switching pattern in which the fifth switching element Q5 is turned off, the sixth switching element Q6 is turned on, the seventh switching element Q7 is turned off, and the eighth switching element Q8 is turned on.

[0085] The control unit 50 outputs an output voltage Vout from the secondary full bridge circuit 40 by combining either the seventh or eighth pattern of the primary full bridge circuit 30 with either the ninth to twelfth patterns of the secondary full bridge circuit 40.

[0086] In the second embodiment, the control unit 50 has a second step-down mode and a second step-up mode as load modes. <Second Step-Down Mode> The second step-down mode has a second step-down delay phase mode, a second step-down in-phase mode, and a second step-down delay phase mode.

[0087] 19 , the second step-down delay phase mode is a second step-down mode in which the secondary-side voltage V2 is raised from a low level to an intermediate level, the primary-side voltage V1 is raised from a low level to a high level, and then the secondary-side voltage V2 is raised from the intermediate level to a high level. The second step-down delay phase mode is a second step-down mode in which a small amount of power is output in response to the power requested by the load 120. The second step-down delay phase mode is an example of a delay phase mode.

[0088] In the load mode of the second embodiment, the difference between the first time T11 when the secondary voltage V2 rises from a low level to a middle level and the second time T12 when the primary voltage V1 rises from a low level to a high level is the first phase difference θ11. The difference between the first time T11 and the third time T13 when the secondary voltage V2 rises from a middle level to a high level is the second phase difference θ12.

[0089] As described above, during normal operation with no change in output, the primary-side voltage V1 and the secondary-side voltage V2 have waveforms of the same frequency that are inverted in phase every 180 degrees. Therefore, the time when the secondary-side voltage V2 falls from high to middle level is also the first time T11, the time when the primary-side voltage V1 falls from high to low level is also the second time T12, and the time when the secondary-side voltage V2 falls from middle to low level is also the third time T13.

[0090] 20 , the second in-phase step-down mode is a second step-down mode in which the secondary-side voltage V2 is raised from a low level to a middle level and the primary-side voltage V1 is raised from a low level to a high level simultaneously, and then the secondary-side voltage V2 is raised from a middle level to a high level. In the second in-phase step-down mode, the first time T11 and the second time T12 are the same time. Therefore, the first phase difference θ11 is 0. The second in-phase step-down mode is a second step-down mode in which medium power is output in response to the power requested by the load 120.

[0091] As shown in Fig. 21 , the second step-down lead phase mode is a second step-down mode in which the primary-side voltage V1 is raised from a low level to a high level, the secondary-side voltage V2 is raised from a low level to a middle level, and then the secondary-side voltage V2 is raised from the middle level to a high level. The second step-down lead phase mode is a second step-down mode in which a large amount of power is output in response to the power requested by the load 120. The second step-down lead phase mode is an example of a lead phase mode. The lead phase mode of this embodiment is a load mode in which a two-level voltage is raised from a low level to a high level, and then a three-level voltage is raised from a low level to a middle level.

[0092] The second buck delay phase mode is an example of a light load mode. The second buck advance phase mode is an example of a heavy load mode. The second buck in-phase mode is a load mode used when switching between the light load mode and the heavy load mode. In the second buck mode, switching occurs between the second buck delay phase mode and the second buck advance phase mode when the first phase difference θ11 is 0.

[0093] <Second Boost Mode> The second boost mode includes a second boost delay phase mode, a second boost in-phase mode, and a second boost delay phase mode.

[0094] As shown in FIG. 22 , the second boost delay phase mode is a second boost mode in which the secondary-side voltage V2 is raised from a low level to a middle level, the primary-side voltage V1 is raised from a low level to a high level, and then the secondary-side voltage V2 is raised from the middle level to a high level. The second boost delay phase mode is a second boost mode in which a small amount of power is output in response to the power requested by the load 120. The second boost delay phase mode differs from the second buck delay phase mode in that the high level of the secondary-side voltage V2 is higher in voltage than the high level of the primary-side voltage V1. The second boost delay phase mode also differs from the second buck delay phase mode in that the low level of the secondary-side voltage V2 is lower in voltage than the low level of the primary-side voltage V1. The second boost delay phase mode is an example of a delay phase mode.

[0095] As shown in FIG. 23 , the second in-phase boost mode is a second boost mode in which the secondary-side voltage V2 is raised from a low level to a middle level and the primary-side voltage V1 is raised from a low level to a high level simultaneously, and then the secondary-side voltage V2 is raised from a middle level to a high level. In the second in-phase boost mode, the first time T11 and the second time T12 are the same. Therefore, the first phase difference θ11 is zero. The second in-phase boost mode is a second boost mode in which medium power is output in response to the power requested by the load 120. The second in-phase boost mode differs from the second in-phase buck mode in that the high level of the secondary-side voltage V2 is higher than the high level of the primary-side voltage V1. The second in-phase boost mode also differs from the second in-phase buck mode in that the low level of the secondary-side voltage V2 is lower than the low level of the primary-side voltage V1.

[0096] As shown in FIG. 24 , the second boost-advance phase mode is a second boost mode in which the primary-side voltage V1 is raised from a low level to a high level, the secondary-side voltage V2 is raised from a low level to a middle level, and then the secondary-side voltage V2 is raised from the middle level to a high level. The second boost-advance phase mode is a second boost mode in which a large amount of power is output in response to the power requested by the load 120. The second boost-advance phase mode differs from the second buck-advance phase mode in that the high level of the secondary-side voltage V2 is higher in voltage than the high level of the primary-side voltage V1. The second boost-advance phase mode also differs from the second buck-advance phase mode in that the low level of the secondary-side voltage V2 is lower in voltage than the low level of the primary-side voltage V1. The second boost-advance phase mode is an example of an advance phase mode.

[0097] The second boost delay phase mode is an example of a light load mode. The second boost advance phase mode is an example of a heavy load mode. The second boost in-phase mode is a load mode used when switching between the light load mode and the heavy load mode. In the second boost mode, switching occurs between the second boost delay phase mode and the second boost advance phase mode when the first phase difference θ11 is 0.

[0098] <Control of Second Embodiment> The all-element soft switching control and partial-element soft switching control performed by the control unit 50 in the second embodiment are the same as those in the first embodiment. The control unit 50 performs all-element soft switching control to output the required power by controlling the first phase difference θ11 and the second phase difference θ12 so that all of the multiple primary-side switching elements Q1 to Q4 and the multiple secondary-side switching elements Q5 to Q8 perform soft switching. When the control unit 50 cannot perform all-element soft switching control, it performs partial-element soft switching control to output the required power by controlling the first phase difference θ11 and the second phase difference θ12 so that all of one of the multiple primary-side switching elements Q1 to Q4 and the multiple secondary-side switching elements Q5 to Q8 perform soft switching and at least one of the other performs hard switching.

[0099] [Effects of the Second Embodiment] (2-1) Even in a circuit configuration in which the reactor L2 is connected to the secondary winding 23, the same effects as those in (1-1) can be obtained.

[0100] [Modifications] The embodiment can be modified as follows: The embodiment and the following modifications can be combined and implemented within the scope of technical compatibility.

[0101] In the first embodiment, the control unit 50 may control the primary full bridge circuit 30 and the secondary full bridge circuit 40 in the first step-down mode to apply two-level voltages to the series-connected body 24 and three-level voltages to the secondary winding 23. Furthermore, the control unit 50 may control the primary full bridge circuit 30 and the secondary full bridge circuit 40 in the first step-up mode to apply two-level voltages to the series-connected body 24 and three-level voltages to the secondary winding 23.

[0102] In the second embodiment, the control unit 50 may control the primary full bridge circuit 30 and the secondary full bridge circuit 40 in the second step-down mode to apply three-level voltages to the primary winding 22 and two-level voltages to the series-connected body 25. Furthermore, the control unit 50 may control the primary full bridge circuit 30 and the secondary full bridge circuit 40 in the second step-up mode to apply three-level voltages to the primary winding 22 and two-level voltages to the series-connected body 25.

[0103] In each embodiment, the power conversion device 10 may include a reactor L1 connected to the primary winding 22 and a reactor L2 connected to the secondary winding 23. The reactor L1 connected to the primary winding 22 is referred to as a first reactor L1, and the reactor L2 connected to the secondary winding 23 is referred to as a second reactor L2. In this case, the voltage applied to a series connection 24 of the primary winding 22 and the first reactor L1 is the primary voltage V1. The voltage applied to a series connection 25 of the secondary winding 23 and the second reactor L2 is the secondary voltage V2. The control performed by the control unit 50 is the same as in each embodiment.

[0104] In this case, a three-level voltage is applied to one of the series connection 24 of the primary winding 22 and the first reactor L1 and the series connection 25 of the secondary winding 23 and the second reactor L2, and a two-level voltage is applied to the other. In each of the first step-down mode, the first step-up mode, the second step-down mode, and the second step-up mode, the series connection 24, 25 to which the three-level voltage is applied and the series connection 24, 25 to which the two-level voltage is applied may be fixed.

[0105] In the first step-down mode, the control unit 50 may control the primary-side full bridge circuit 30 and the secondary-side full bridge circuit 40 to apply two-level voltages to the series-connected body 24 and three-level voltages to the series-connected body 25. In the first step-up mode, the control unit 50 may control the primary-side full bridge circuit 30 and the secondary-side full bridge circuit 40 to apply two-level voltages to the series-connected body 24 and three-level voltages to the series-connected body 25.

[0106] In the second step-down mode, the control unit 50 may control the primary-side full bridge circuit 30 and the secondary-side full bridge circuit 40 to apply three-level voltages to the series-connected body 24 and two-level voltages to the series-connected body 25. In the second step-up mode, the control unit 50 may control the primary-side full bridge circuit 30 and the secondary-side full bridge circuit 40 to apply three-level voltages to the series-connected body 24 and two-level voltages to the series-connected body 25.

[0107] L1, L2...reactor, Q1 to Q4...primary side switching elements, Q5 to Q8...secondary side switching elements, TS...transformer section, 10...power conversion device, 22...primary side winding, 23...secondary side winding, 24, 25...series-connected body, 30...primary side full bridge circuit, 40...secondary side full bridge circuit, 50...control section.

Claims

1. A power supply comprising: a transformer unit having a primary winding, a secondary winding, and a reactor connected to at least one of the primary winding or the secondary winding; a primary full bridge circuit having a plurality of primary switching elements connected to the primary winding; a secondary full bridge circuit having a plurality of secondary switching elements connected to the secondary winding; and a control unit for controlling the plurality of primary switching elements and the plurality of secondary switching elements, wherein a condition for performing soft switching of the plurality of primary switching elements is condition 1 and a condition for performing soft switching of the plurality of secondary switching elements is condition 2, and condition 1 is a current flowing in the primary winding when at least one of the plurality of primary switching elements switches between ON and OFF, the value of a current flowing in a forward direction of a diode connected in parallel to the primary switching element that switches from OFF to ON among the plurality of primary switching elements is equal to or greater than an absolute value of a primary winding current threshold, The second condition is that a current flows through the secondary winding when at least one of the multiple secondary switching elements switches between ON and OFF, and a value of a forward current flowing through a diode connected in parallel to the secondary switching element that switches from OFF to ON among the multiple secondary switching elements is equal to or greater than an absolute value of a secondary winding current threshold, the control unit is configured to control the primary full bridge circuit and the secondary full bridge circuit so that one of the primary full bridge circuit and the secondary full bridge circuit applies a two-level voltage to the transformer unit and the other applies a three-level voltage to the transformer unit, a difference between a first time when the three-level voltage rises from a low level to a middle level and a second time when the two-level voltage rises from a low level to a high level is a first phase difference, and a difference between the first time and a third time when the three-level voltage rises from a middle level to a high level is a second phase difference, and the control unit isa first phase difference and a second phase difference so that all of the plurality of primary side switching elements and the plurality of secondary side switching elements perform soft switching, thereby performing an all-element soft switching control to output the required power; and when the all-element soft switching control cannot be performed, a partial element soft switching control to output the required power by controlling the first phase difference and the second phase difference so that all of one of the plurality of primary side switching elements and the plurality of secondary side switching elements perform soft switching and at least one of the other performs hard switching.

2. The power conversion device according to claim 1, wherein the control unit has a light load mode and a heavy load mode in which the maximum value of the output power is greater than that in the light load mode, and the control unit is configured to perform soft switching control of some of the elements when switching between the light load mode and the heavy load mode.

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