Device for generating DQS gating signal of DDR phy using DQS counter

Abstract

Disclosed is an SoC including: a DQS reception unit that provides a data strobe signal received on a first DQS channel connecting the SoC and a memory; a DQS control unit that generates a read gate signal for masking the data strobe signal; and a DQS clock driving unit that generates an internal DQS clock. The internal DQS clock has the same level as the data strobe signal during a time interval in which the read gate signal is at a first level, and has a different prescribed level during a time interval in which the read gate signal is at a second level. Here, data is to be read, using the internal DQS clock, from DQ received on a DQ channel connecting the SoC and the memory.

Description

A device that generates a DQS gating signal of a DDR PHY using a DQS counter.

[0001] The present invention relates to a technology for a SoC including a memory controller to read data from a memory, and more particularly, to a technology for generating a DQS gating signal to prevent noise from entering from a DQS channel.

[0002] The SoC can be connected to multiple memories through commonly used DQ channels and DQS (data strobe signal) channels.

[0003] While any one of the above SoC and the plurality of memories occupies the DQ channel and the DQS channel, terminals of the other remaining devices connected to the DQ channel and the DQS channel can be set to a floating state.

[0004] In one implementation, the SoC may transmit a read command to a first memory among the plurality of memories to read data from the first memory. After a predetermined delay time has elapsed from the time at which the read command is transmitted, the first memory may occupy the DQ channel and the DQS channel. Then, the DQ (read data) read from the first memory may be transmitted to the SoC through the DQ channel, and the DQS may be transmitted to the SoC through the DQS channel. The DQS is a pulse train signal indicating a reference timing at which the SoC acquires the DQ.

[0005] While the first memory occupies the DQ channel and the DQS channel for transmission of the DQ and DQS, the terminals of the SoC and the remaining memories other than the first memory connected to the DQ channel and the DQS channel can be set to a floating state.

[0006] The DQS output from the terminal of the first memory is a pulse train signal in the form of a square wave. If the pulse period of the pulse train signal is short, the shape of the DQS detected at the terminal of the SoC may have a distorted shape from the square wave shape. Therefore, the SoC can restore the shape of the DQS detected at the terminal of the SoC to the square wave shape.

[0007] When the first memory terminates the transmission of the DQ and DQS and terminates the occupation of the DQ channel and the DQS channel, the DQ channel and the DQS channel enter a high impedance state. That is, in a state where there is no device occupying the DQ channel and the DQS channel among the SoC and the plurality of memories, the DQ channel and the DQS channel can maintain a high impedance state.

[0008] While the DQS channel maintains a high impedance state, noise may exist in the DQS channel, and this noise may be introduced into the SoC connected to the DQS channel. The SoC is configured to generate an internal DQS clock that provides timing for acquiring read data transmitted through the DQ channel using the DQS received from the DQS channel, but there is a problem that an error may occur in the generated internal DQS clock due to the noise.

[0009] Therefore, immediately after the first memory ends transmission of the DQS, it is necessary to block the signal flowing into the SoC from the DQS channel.

[0010] To this end, the SoC can block the DQS channel itself immediately after the transmission of the DQS is terminated, and for this purpose, a DQS masking signal, which is an internal signal, can be generated and used. The DQS masking signal is configured to allow reception of a signal from the DQS channel only during a time period from a predetermined start time delayed from the time when the SoC transmits a read command to the memory to the end time when the memory ends transmission of the DQS corresponding to the read command.

[0011] According to the prior art, the SoC generates an internal DQS clock (=internal DQS) corresponding to the DQS using an internal clock. The acquisition timing of the DQ transmitted together with the DQS is determined by the internal DQS clock. At this time, the DQS and the internal DQS clock must be synchronized and aligned with each other. However, since the internal clock of the SoC and the DQS generated by the memory are signals generated independently of each other, it is necessary to execute a process referred to as a training process in order to synchronize and align the internal DQS clock generated using the internal clock with the DQS.

[0012] The above training process must be performed during a time period when the DQ channel and the DQS channel are not occupied for reading / writing data. That is, there is a problem that the training process cannot be performed during a time period when the SoC and the plurality of memories occupy the DQ channel and the DQS channel for reading / writing data.

[0013] In addition, even if the internal DQS clock is synchronized to the DQS by the training process, there is a problem that the training process must be performed repeatedly because timing drift may occur due to temperature or supply voltage drift.

[0014] The present invention aims to provide a technology for masking DQS without interfacing the DQS provided by the memory with the internal signal of the SoC.

[0015] The SoC includes a DDR PHY, a memory controller, and other major functional units. The above-described DQS and DQ processing is performed in the DDR PHY.

[0016] The above DQS may include a preamble (= preamble clock), a read clock (read_clk), and a postamble (= postamble clock) that are sequentially generated. In the operation of the DDR PHY, the DQS channel becomes high impedance at the point in time when the postamble of the DQS transmitted by the memory ends. As a result, an incorrect toggle may occur in the DQS channel due to a reflected wave, etc. In this case, the signal level of the DQS channel may fluctuate, and the internal DQS clock generated by the DDR PHY may be generated incorrectly. As a result, an error may occur.

[0017] According to one aspect of the present invention, a DQS masking method provided can find an appropriate DQS area by counting a preamble, a read clock, and a postamble clock of a DQS transmitted by a memory, and can generate an internal DQS clock using the found area.

[0018] The above memory can transmit the inverted DQS (=DQSc) together with the above DQS (=DQSt).

[0019] The DDR PHY can set the value of the first count inside the DDR PHY to a predetermined first initial value and set the value of the second count inside the DDR PHY to a predetermined second initial value at a time when the rising edge of the inverted DQS (=DQSc) is detected while the DQS (=DQSt) is low, or at a time before that.

[0020] In this specification, the first count may be referred to as a preamble count and may be indicated by the symbol Pt. Cnt. In addition, the second count may be referred to as a BL count and may be indicated by the symbol BL Cnt.

[0021] The first initial value may be equal to a predefined number of pulses of the preamble clock, and the second initial value may be equal to a predefined number of pulses of the read clock (read_clk) for a set of data having a predetermined length (burst length).

[0022] The above DDR PHY can count down the value of the first count at each rising edge of the inverted DQS (=DQSc) during the time period in which the preamble clock is generated.

[0023] The above DDR PHY may not count down the value of the second count before the read clock is generated.

[0024] And the DDR PHY can count down the value of the second count at each rising edge of the inverted DQS (= DQSc) during the time period in which the read clock occurs.

[0025] Next, when the second count becomes 0, the DDR PHY checks the value of a predetermined continuous read signal (NextRead) (1301) described later, and if it is confirmed that there is continuous read data, the value of the second count is set back to the second initial value, and thereafter, the second count is counted down at each rising edge of the inverted DQS (=DQSc). In contrast, when the second count becomes 0, the value of the continuous read signal is checked, and if it is confirmed that there is no more continuous read data, the pulse of the read complete signal (ReadDone) is generated, and the range of the DQS masking signal (ReadOn) is determined using the pulse of the read complete signal (ReadDone).

[0026] For example, the DDR PHY may be configured to read the signal level of the DQS channel when the DQS masking signal (ReadOn) is high, and not to read the signal level of the DQS channel when the DQS masking signal (ReadOn) is low. The DQS masking signal (ReadOn) may be designed to rise when the preamble clock starts to be generated, or to rise when the read clock starts to be generated. In addition, the DQS masking signal (ReadOn) may be designed to fall when the pulse of the read complete signal (ReadDone) is generated.

[0027] According to a DQS masking method provided according to one aspect of the present invention, the point in time at which the postamble of DQS ends within the DDR PHY can be calculated through a countdown process of the first count and the second count. As a result, the DQS can be masked within the DDR PHY at or before the point at which the DQS channel becomes high impedance. As a result, even if the signal level of the DQS channel fluctuates after the postamble clock of DQS ends, the DDR PHY can be prevented from generating the internal DQS clock, thereby preventing errors.

[0028] According to the prior art, DQS is masked by linking it with the internal clock of the SoC. In contrast, according to the DQS masking method provided according to one aspect of the present invention, there is no need to link the DQS transmitted from the memory (DRAM) with the internal signal of the DDR PHY (the internal signal of the SoC), particularly the internal clock of the DDR PHY, thereby reducing power consumption and ensuring operational stability.

[0029] According to the present invention, a technology for masking DQS without interlinking the DQS provided by the memory and the internal signal of the SoC can be provided.

[0030] Figure 1 is a drawing explaining the configuration of a functional unit for data readout of SoC and signals used for data readout of memory.

[0031] FIG. 2 illustrates the structure of a DDR PHY provided according to one embodiment of the present invention.

[0032] FIG. 3 is a timing diagram of DQSt, DQSc, and DQ of FIG. 2.

[0033] FIG. 4 illustrates a method for generating a read start signal (ReadStart) using DQSt and DQSc provided by a read start unit according to one embodiment of the present invention.

[0034] Figure 5 is a timing diagram of signals output by each component of the DDR PHY presented in Figure 2.

[0035] Fig. 6 is a timing diagram showing how the DQS masking signal generation unit of Fig. 2 changes the level of the readout gate signal (ReadOn).

[0036] FIG. 7 is a timing diagram showing how the DQS clock driver of FIG. 2 generates an internal DQS clock (DQSi_ck).

[0037] Fig. 8 shows the structure of a DDR PHY having a modified configuration from Fig. 2.

[0038] FIG. 9 is a timing diagram illustrating a method for generating the extended second read gate signal (ReadRange) presented in FIG. 8.

[0039] FIG. 10 is a timing diagram showing how the DQS clock driver of FIG. 8 generates an internal DQS clock (DQSi_ck).

[0040] FIG. 11 is a timing diagram illustrating the timing of reading DQ from an SoC provided according to one embodiment of the present invention.

[0041] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terminology used herein is intended to aid understanding of the embodiments and is not intended to limit the scope of the present invention. Furthermore, the singular forms used below also include the plural forms, unless the context clearly indicates otherwise.

[0042] Figure 1 is a drawing explaining the configuration of a functional unit for data readout of SoC and signals used for data readout of memory.

[0043] The SoC (1) and the plurality of memories (4, 5) may be parts of an independently operating computing device.

[0044] The SoC (1) can be connected to one or more memories (4, 5) through multiple channels. The multiple channels can include a DQSt channel, a DQSc channel, and a DQ channel.

[0045] In this specification, the DQSt channel may be referred to as a DQS channel, and the DQSc channel may be referred to as an inverted DQS channel.

[0046] The above SoC (1) may include a DDR PHY (10), a memory controller (20), and other main functional units (30). When the memory controller (20) transmits a read command (ReadCmd) to the DDR PHY (10), the DDR PHY (10) transmits the read command to the memory indicated by the read command through a communication channel not shown in FIG. 1, and in response thereto, receives and processes the DQSt, DQSc, and DQ transmitted by the memory, and provides the result of the processing to the memory controller (20).

[0047] The above memory may be, for example, DRAM. The memories (4, 5) may each include a DQS transmitter (40). The DQS transmitter (40) may transmit DQSt, DQSc, and DQ in response to a read command received by the memory to which it belongs. While one memory (ex: 4) occupies the DQSt channel, the DQSc channel, and the DQ channel, the terminals of the remaining other memories (ex: 5) and the SoC (1) connected to the DQSt channel, the DQSc channel, and the DQ channel may be configured to remain in a floating state.

[0048] FIG. 2 illustrates the structure of a DDR PHY provided according to one embodiment of the present invention.

[0049] The above DDR PHY (10) may include a DQS receiver (11), a DQS controller (12), a read command checker (13), and a DQS clock driver (DQS CLK DRV) (14).

[0050] The above DDR PHY (10) can receive DQSt and DQSc and generate an internal DQS clock (DQSi_ck) (1401). The internal DQS clock (DQSi_ck) (1401) is a clock that determines the timing for acquiring DQ. The internal DQS clock (DQSi_ck) (1401) is synchronized and aligned with DQSt and DQSc.

[0051] The above DQS receiver (11) receives DQSt and DQSc and uses them to generate and output DQS_out (1103) and DQS_ck (1104).

[0052] The above DQS receiver (11) can generate DQS_out (1103) and DQS_ck (1104) by amplifying and restoring DQSt and / or DQSc into a square wave using a high-speed signal comparator that compares them with a reference voltage inside the DQS receiver (11).

[0053] Since DQS_out(1103) is generated by correcting the distorted shape of DQSt(1101) as it passes through the DQSt channel, DQS_out(1103) is essentially the same as DQSt(1101).

[0054] Since DQS_ck(1104) is generated by correcting the distorted shape of DQSc(1102) as it passes through the DQSc channel, DQS_ck(1104) is essentially identical to DQSc(1102).

[0055] The above read command confirmation unit (13) can determine the value of the subsequent read signal (NextRead) (1301) based on the BL completion signal (BL_done) (1221) provided by the DQS counter (122) of the DQS control unit (12) and the read command (ReadCmd) (2001) provided by the memory controller (20) and provide the value to the DQS counter unit (122) of the DQS control unit (12).

[0056] The above DQS control unit (12) generates a read gate signal (ReadOn) (1231) based on the DQS_out (1103), the DQS_ck (1104), and the subsequent read signal (NextRead) (1301) and provides it to the DQS clock driving unit (14).

[0057] The above DQS clock driving unit (14) generates and outputs the internal DQS clock (DQSi_ck) (1401) based on the DQS_out (1103) and the readout gate signal (ReadOn) (1231).

[0058] In one embodiment, the DQS_out (1103) is a signal output by converting the DQSt (1101) into a digital signal by the DQS receiver (11). Alternatively, in another modified embodiment, the DQS_out (1103) is a signal output by converting into a digital signal by the DQS receiver (11) a signal having a value obtained by subtracting the level of the DQSc (1102) from the level of the DQSt (1101). For the convenience of the following description, it is assumed that the DQS_out (1103) is a signal output by converting the DQSt (1101) into a digital signal by the DQS receiver (11).

[0059] The above DQS_ck (1104) is a signal that is converted into digital by the above DQSc (1102) and output by the above DQS receiver (11).

[0060] At this time, the DQS receiver (11) is characterized in that it does not use the local clock inside the DDR PHY (10) to generate the DQS_out (1103) and the DQS_ck (1104).

[0061] The above DQS_out (1103) is input to the DQS control unit (12) and the DQS clock driving unit (14).

[0062] The above DQS_ck (1104) is input to the DQS control unit (12).

[0063] The above DQS control unit (12) may include a read start unit (121), a DQS counter unit (122), and a DQS masking signal generation unit (123).

[0064] The above read start unit (121) generates and outputs a read start signal (ReadStart) (1211) using the above DQS_out (1103) and the above DQS_ck (1104).

[0065] The above DQS counter unit (122) generates and outputs a read completion signal (ReadDone) (1222) and a BL completion signal (BL_done) (1221) using the above DQS_ck (1104) and the subsequent read signal (NextRead) (1301).

[0066] The above DQS masking signal generation unit (123) generates and outputs the read gate signal (ReadOn) (1231) using the read start signal (ReadStart) (1211) and the read complete signal (ReadDone) (1222).

[0067] FIG. 3 is a timing diagram of DQSt, DQSc, and DQ of FIG. 2.

[0068] Immediately after the SoC(1) sends a read command to the memory, the DQSt channel, the DQSc channel, and the DQ channel may be in a high impedance (Hi-Z) state.

[0069] The above memory can occupy a DQSt channel and a DQSc channel and output the DQSt (1101) and the DQSc (1102). The DQSt (1101) and the DQSc (1102) are each pulse trains and their voltage levels are complementary to each other. The DQSt (1101) and the DQSc (1102) can each be configured with a preamble clock having a predetermined number of pulses, a read clock having a predetermined number of pulses, and a postamble clock having a predetermined number of pulses. When the postamble clock ends, the memory stops occupying the DQSt channel and the DQSc channel, and as a result, the DQSt channel and the DQSc channel return to a high impedance state (Hi-Z).

[0070] At the time when the preamble clock ends, the memory can occupy the DQ channel and output the DQ. The memory can provide the DQ in synchronization with the read clock. When the time period during which a predetermined number of data is transmitted by the DQ ends, the memory stops occupying the DQ channel, resulting in the DQ channel returning to a high impedance state.

[0071] In one embodiment of the present invention, since the DQS_out (1103) is a shape restored to a square wave form of the DQSt (1101), the DQS_out (1103) can be regarded as DQSt. In addition, since the DQS_ck (1104) is a shape restored to a square wave form of the DQSc (1102), the DQS_ck (1104) can be regarded as DQSc.

[0072] FIG. 4 illustrates a method for generating a read start signal (ReadStart) using DQSt and DQSc provided by a read start unit according to one embodiment of the present invention.

[0073] At the point when the memory starts outputting the DQSt(1101) and the DQSc(1102), both the DQSt(1101) and the DQSc(1102) have values ​​of the second level. Then, as the DQSc(1102) changes to the first level before the DQSt(1101), the DQSt(1101) and the DQSc(1102) have complementary level values.

[0074] The first and second levels may be high and low levels, respectively. Alternatively, the first and second levels may be low and high levels, respectively. This specification describes an example in which the first and second levels are high and low levels, respectively.

[0075] The above read start unit (121) is configured to recognize the point in time when the DQSt (1101) has the second level and the DQSc (1102) has the first level and generate a pulse of the read start signal (ReadStart) (1211).

[0076] The above read start unit (121) generates a pulse of the read start signal (ReadStart) (1211) whenever a rising edge is detected in the DQSc (1102).

[0077] In this specification, generating a pulse of a signal may mean temporarily changing the value of a signal having a second level value to a first level, thereby generating a level change in the form of a pulse.

[0078] After a certain period of time has passed since the above-mentioned signal changed to the first level, it may change back to the second level.

[0079] In one embodiment, the read start signal (ReadStart) (1211) may be generated in the form of a pulse train (1211_p) composed of pulses having a relatively long duration at the first level.

[0080] In another embodiment, the read start signal (ReadStart) (1211) may be generated in the form of a pulse train (1211_sp) composed of pulses having a relatively short duration at the first level.

[0081] Figure 5 is a timing diagram of signals output by each component of the DDR PHY presented in Figure 2.

[0082] In Fig. 5, reference symbol IV represents an initial value, HZ represents high impedance, Pr.Cnt represents a preamble count, and BL Cnt represents a BL count.

[0083] In Fig. 5, reference symbol DQS_Cnt indicates Pr. Cnt and BL Cnt, which are count variables used within the DQS counter unit (122).

[0084] After the SoC (1) transmits a read command to the memory, while the DQS counter unit (122) waits for reception of the DQSc (1102), the SoC (1) can set the preamble count to the first initial value and the BL count to the second initial value.

[0085] The first initial value may be a value corresponding to the number of pulses constituting the preamble clock of the DQSt (1101) and the DQSc (1102). The second initial value may be a value corresponding to the number of pulses constituting the read clock constituting a set of data having a predetermined length.

[0086] At the time of the first rising edge after the above DQSc (1102) starts to occur, the preamble count may be set to a predetermined first initial value.

[0087] Thereafter, whenever a pulse of the DQSc (1102) occurs, that is, at each rising edge of the DQSc (1102), the value of the preamble count can be decreased by 1.

[0088] SoC(1) can determine that the preamble clock has ended and the read clock has started when the value of the preamble count becomes 0.

[0089] Thereafter, whenever a pulse of the DQSc (1102) occurs, that is, at each rising edge of the DQSc (1102), the value of the BL count can be decreased by 1.

[0090] When the value of the above BL count becomes 0, the DQS counter unit (122) can generate a pulse of the BL completion signal (BL_done) (1221).

[0091] If the value of the subsequent read signal (NextRead) (1301) is the second level at the time when the pulse of the BL completion signal (BL_done) (1221) is generated, the DQS counter unit (122) can generate a pulse of the read completion signal (ReadDone) (1222).

[0092] In contrast, if the value of the subsequent read signal (NextRead) (1301) is at the first level at the time when the pulse of the BL completion signal (BL_done) (1221) is generated, the DQS counter unit (122) may not generate the pulse of the read completion signal (ReadDone) (1222).

[0093] SoC(1) can determine that the read clock ends and the postamble clock starts when the next read signal (NextRead)(1301) is at the second level at the time when the value of the BL count becomes 0.

[0094] For example, referring to the example of FIG. 5, since the subsequent read signal (NextRead) (1301) is at the second level at the first time point (t1) and the fourth time point (t4) when the pulse of the BL complete signal (BL_done) (1221) occurs, the pulse of the read complete signal (ReadDone) (1222) occurs at the first time point (t1) and the fourth time point (t4). In contrast, since the subsequent read signal (NextRead) (1301) is at the first level at the third time point (t3) when the pulse of the BL complete signal (BL_done) (1221) occurs, the pulse of the read complete signal (ReadDone) (1222) does not occur at the third time point (t2).

[0095] Here, the fact that the value of the above-mentioned subsequent read signal (NextRead) (1301) is the first level means that in addition to a set of data having a predetermined length (ex: BL16) being read out at the time when the above-mentioned subsequent read signal (NextRead) (1301) is the first level, there is another set of data that is scheduled to be transmitted continuously. In other words, even if all of the above-mentioned one set of data is read out, the data of the other set and the read clocks for reading it are immediately continuously transmitted.

[0096] In contrast, the fact that the value of the subsequent read signal (NextRead) (1301) here is the second level indicates that when the subsequent read signal (NextRead) (1301) is at the second level and a set of data having a predetermined length (ex: BL16) is completely read out, there is no other set of data to be transmitted continuously after the set of data. In other words, this means that the postamble clock is transmitted immediately when a set of data having the predetermined length (ex: BL16) is completely read out.

[0097] The value of the above-mentioned subsequent read signal (NextRead) (1301) can be determined by the read command confirmation unit (13) based on the BL completion signal (BL_done) (1221) and the read command (ReadCmd) (2001).

[0098] Before the memory transmits the preamble clock of the DQSc (1102), the SoC (1) has transmitted the read command (ReadCmd) (2001) generated by the memory controller (20) to the memory. At this time, the read command (ReadCmd) (2001) may include a command to continuously read a set of data having a predetermined length (ex: BL16) N times (N=1, 2, 3, ...). According to the command, the memory may transmit the DQSt composed of a preamble clock, a read clock, and a postamble clock. At this time, the time length of the read clock may be the same as the time length taken by the memory to continuously read the set of data N times. Here, N may be referred to as the number of consecutive reads.

[0099] At this time, the read command confirmation unit (13) can analyze the read command (ReadCmd) (2001) transmitted to the memory to confirm the continuous read count N. Then, the read command confirmation unit (13) can set the third count managed by the read command confirmation unit (13) to N before the DQSt (1101) for the read command (ReadCmd) (2001) is received.

[0100] For example, the read command confirmation unit (13) can set the subsequent read signal (NextRead) (1301) to the second level when the third count has a value of '1', and can set the subsequent read signal (NextRead) (1301) to the first level when the third count is greater than '1'.

[0101] If the third count is 2 or more at the time when the pulse of the BL completion signal (BL_done) (1221) occurs, the read command confirmation unit (13) can decrease the third count by 1.

[0102] In one embodiment, when the third count is 1 at the time when the pulse of the BL completion signal (BL_done) (1221) occurs, the read command confirmation unit (13) can maintain the value of the third count as 1 or decrease it by 1 to make it 0.

[0103] The example of Fig. 5 shows a situation where the SoC (1) issued the read command (ReadCmd) (2001) just before the second time (t2) and N=2. At this time, since N=2, a data set having a length of, for example, BL16 can be transmitted twice in succession. Since N=2, the value of the third count is set to 2 at the second time (t2). And since the third count has a value greater than 1 at the second time (t2), the subsequent read signal (NextRead) (1301) is set to the first level. And at the third time (t3), the read command confirmation unit (13) can confirm that the pulse of the BL completion signal (BL_done) (1221) has occurred, and thus can decrease the value of the third count by 1. Therefore, the value of the third count is converted from 2 to 1 at the third time (t3). As a result, immediately after the third time point (t3), since the value of the third count has a value of 1, the subsequent read signal (NextRead) (1301) is set to the second level. At this time, since the subsequent read signal (NextRead) (1301) is at the first level at the third time point (t3), despite the generation of the pulse of the BL complete signal (BL_done) (1221), the pulse of the read complete signal (ReadDone) (1222) is not generated. Then, at the fourth time point (t4), the read command confirmation unit (13) can confirm that the pulse of the BL complete signal (BL_done) (1221) has been generated, but since the value of the third count is 1 at this time, the value of the third count can be maintained at 1 or decreased by 1 without decreasing it. And at the fourth time point (t4), since the subsequent read signal (NextRead) (1301) is at the second level, the pulse of the read complete signal (ReadDone) (1222) is generated by the pulse of the BL complete signal (BL_done) (1221).

[0104] It can be seen that the pulse of the above read completion signal (ReadDone) (1222) is a signal synchronized to the edge of the last DQSt before the post-amplifier clock is generated.

[0105] Fig. 6 is a timing diagram showing how the DQS masking signal generation unit of Fig. 2 changes the level of the readout gate signal (ReadOn).

[0106] The above-mentioned readout gate signal (ReadOn) (1231) may have the first level (high level) only during some of the time periods during which the above-mentioned DQSt (1101) occurs, and may have the second level during the remaining periods.

[0107] The falling edge of the above read gate signal (ReadOn) (1231) may be synchronized with the pulse generation time of the above read completion signal (ReadDone) (1222).

[0108] The rising edge of the above read gate signal (ReadOn) (1231) can be synchronized with any one of the pulses of the above read start signal (ReadStart) (1211).

[0109] In Fig. 6, the graph indicated by reference number 1231_1 shows the form of a readout gate signal (ReadOn) generated according to one embodiment of the present invention, and the graph indicated by reference number 1231_2 shows the form of a readout gate signal (ReadOn) generated according to another embodiment of the present invention. For convenience of explanation, graph (1231_1) and graph (1231_2) are presented together in Fig. 6.

[0110] In the graph indicated by reference number 1231_1 in FIG. 6, the rising edge of the read gate signal (ReadOn) (1231) is synchronized with the pulse of the first read start signal (ReadStart) (1211) that occurs after the point in time when the DQSt (1101) occurs.

[0111] In another graph indicated by reference number 1231_2 in FIG. 6, the rising edge of the read gate signal (ReadOn) (1231) is synchronized with the pulse of the read start signal (ReadStart) (1211) that occurs just before the read clock starts.

[0112] In this specification, the section from the rising edge to the falling edge of the readout gate signal (ReadOn) (1231) may be referred to as a 'gating pulse', and the readout gate signal may also be referred to as a 'DQS gating signal' or a 'DQS masking signal'.

[0113] FIG. 7 is a timing diagram showing how the DQS clock driver of FIG. 2 generates an internal DQS clock (DQSi_ck).

[0114] The above DQS clock driving unit (14) generates the internal DQS clock (DQSi_ck) (1401) by masking the waveform of the DQS_out (1103) with the readout gate signal (ReadOn) (1231). That is, the internal DQS clock (DQSi_ck) (1401) has a second level during a time period when the readout gate signal (ReadOn) (1231) is a second level (low level), and has the same level as the DQS_out (1103) during a time period when the readout gate signal (ReadOn) (1231) is a first level (high level). The internal DQS clock (DQSi_ck) (1401) provides a reference timing for acquiring the DQ.

[0115] Fig. 8 shows the structure of a DDR PHY having a modified configuration from Fig. 2.

[0116] The structure of the DDR PHY (10) shown in Fig. 8 is identical to the structure of the DDR PHY (10) shown in Fig. 2. However, in Fig. 8, a DQS masking signal expansion unit (124) is further included between the DQS clock driving unit (14) and the DQS masking signal generation unit (123).

[0117] The above DQS masking signal expansion unit (124) generates an extended second read gate signal (ReadRange) (1241) based on the read gate signal (ReadOn) (1231).

[0118] In this specification, the section from the rising edge to the falling edge of the extended second read gate signal (ReadRange) (1241) may be referred to as a gating pulse.

[0119] FIG. 9 is a timing diagram illustrating a method for generating the extended second read gate signal (ReadRange) presented in FIG. 8.

[0120] The above DQS masking signal expansion unit (124) synchronizes the rising edge of the second read gate signal (ReadRange) (1241) with the rising edge of the read gate signal (ReadOn) (1231).

[0121] However, the DQS masking signal expansion unit (124) causes the falling edge of the second read gate signal (ReadRange) (1241) to occur later than the falling edge of the read gate signal (ReadOn) (1231). The DQS masking signal expansion unit (124) synchronizes the falling edge of the second read gate signal (ReadRange) (1241) with the rising edge of the last pulse of the DQSc (1102).

[0122] FIG. 10 is a timing diagram showing how the DQS clock driver of FIG. 8 generates an internal DQS clock (DQSi_ck).

[0123] The above DQS clock driving unit (14) generates the internal DQS clock (DQSi_ck) (1401) by masking the waveform of the DQS_out (1103) with the second read gate signal (ReadRange) (1241). That is, the internal DQS clock (DQSi_ck) (1401) has a second level during a time period when the second read gate signal (ReadRange) (1241) is a second level (low level), and has the same level as the DQS_out (1103) during a time period when the second read gate signal (ReadRange) (1241) is a first level (high level). The internal DQS clock (DQSi_ck) (1401) provides a reference timing for acquiring the DQ.

[0124] FIG. 11 is a timing diagram illustrating the timing of reading DQ from an SoC provided according to one embodiment of the present invention.

[0125] As described above, the readout timing of DQ is determined by the internal DQS clock (DQSi_ck) (1401) generated by the readout gate signal (ReadOn) (1231) masking the DQSt (1101).

[0126] By utilizing the embodiments of the present invention described above, those skilled in the art will be able to easily implement various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other claims that are not in a citation relationship within the scope of this specification, as long as it is understood.

[0127] Acknowledgement

[0128] The invention of this patent application was supported by the following national research and development projects: [Project Identification Number] 20200031; [Project Number] 2020-0-01303; [Ministry] Ministry of Science and ICT; [Project Management (Specialist) Agency] National IT Industry Promotion Agency; [Research Project Name] Development (Design) of Next-Generation Intelligent Semiconductor Technology; [Research Project Name] Development of AI HBM3-Level or Higher Interface Technology for High-Performance Servers; [Contribution Ratio] 1 / 1; [Project Implementing Agency] OpenEdge Technology Co., Ltd.; [Research Period] April 1, 2020 - December 31, 2023

Claims

1. As a SoC (1) that communicates with memory, A DQS receiver (11) that provides a data strobe signal received from a first DQS channel connecting the SoC and the memory; A DQS control unit (12) that generates a read gate signal (1231) for masking the above data strobe signal; and A DQS clock driver (14) that generates an internal DQS clock (1401); Includes, The internal DQS clock has the same level as the data strobe signal during a time period when the read gate signal is at the first level and has a different level during a time period when the read gate signal is at the second level. It is configured to read data using the internal DQS clock (1401) from the DQ received from the DQ channel connecting the SoC and the memory. SoC.

2. In paragraph 1, The above DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, The above DQS control unit is configured to generate the read gate signal using the data strobe signal and the inverted data strobe signal. SoC.

3. In paragraph 1, The above DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, The end point of the gating pulse of the above-mentioned read gate signal is determined by the counted value of the pulse of the above-mentioned inverted data strobe signal. SoC.

4. In paragraph 1, The above DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, A memory controller (20) that provides a read command (ReadCmd) (2001) to be transmitted to the memory by the SoC; A DQS counter unit (122) that provides a predetermined BL completion signal (BL_done) (1221) and a read completion signal (ReadDone) (1222) indicating the end point of the gating pulse of the read gate signal; and A read command confirmation unit (13) that generates a subsequent read signal (NextRead) (1301) based on the above BL completion signal and the read command; Including more, The above DQS counter unit is configured to count the inverted data strobe signal to generate the BL completion signal, and to generate the read completion signal using the inverted data strobe signal and the subsequent read signal. SoC.

5. In paragraph 4, The above DQS counter section includes a second count (BL Cnt) that counts pulses of the inverted data strobe signal, The above DQS counter section is configured to generate a pulse of the BL completion signal when the countdown of the second count is completed. SoC.

6. In paragraph 5, The above read command is transmitted to the memory that generates the data strobe signal by the memory controller, The above read command confirmation unit is configured to set the subsequent read signal to the first level before receiving the data strobe signal if the read command includes a command to read two or more sets of data having a predetermined length, and to set the subsequent read signal to the second level before receiving the data strobe signal if the read command includes a command to read only one set of data having a predetermined length. The above read command confirmation unit is configured to change the subsequent read signal to the second level if there is only one set of data to be read continuously at the time of confirming the pulse of the BL complete signal when the pulse of the BL complete signal is confirmed, and to maintain the subsequent read signal at the first level if there are two or more sets of data to be read continuously at the time of confirming the pulse of the BL complete signal. SoC.

7. In paragraph 6, The above DQS counter section is configured to not generate a pulse of the read completion signal when the subsequent read signal is at the first level at the time when the countdown of the second count is completed, and to generate a pulse of the read completion signal when the subsequent read signal is at the second level at the time when the countdown of the second count is completed. SoC.

8. In paragraph 7, The pulse of the read completion signal is characterized in that it is generated at the time when the countdown of the second count is completed, or at the time when the postamble clock of the inverted data strobe signal ends. SoC.

9. In paragraph 5, The above DQS counter section is configured to initialize the second count to a predetermined second value before receiving the data strobe signal, and to initialize the second count to the second value when the countdown of the second count is completed. SoC.

10. In paragraph 9, The above DQS counter section is configured to count down the second count at each rising edge or falling edge of the inverted data strobe signal after the preamble clock of the data strobe signal ends. SoC.

11. In paragraph 1, The above DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, A read start unit (121) that generates and outputs a read start signal (ReadStart) (1211) based on the above-mentioned inverted data strobe signal; DQS counter unit (122) providing a read completion signal (ReadDone) (1222) indicating the end point of the gating pulse of the above read gate signal; and A DQS masking signal generation unit (123) that generates the reading gate signal based on the reading start signal and the reading completion signal; Including more, The above read start unit is configured to generate a pulse of the read start signal at each rising edge of the inverted data strobe signal, The above DQS masking signal generation unit is configured to synchronize the falling edge of the read gate signal with the generation time of the pulse of the read completion signal. SoC.

12. In paragraph 11, The above DQS masking signal generation unit is configured to synchronize the rising edge of the read gate signal with one of the pulses of the read start signal. SoC.

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