Memory cell, memory and preparation method therefor, and electronic device

Abstract

The present disclosure relates to the technical field of storage, and relates to a memory cell, a memory and a preparation method therefor, and an electronic device, which are used to improve the performance and reliability of a memory cell and a memory. The memory cell comprises: a write transistor (TW) and a read transistor (TR). The write transistor (TW) comprises a first gate electrode (11), a first source-drain electrode (12), and a second source-drain electrode (13). The read transistor (TR) comprises a second gate electrode (21), a third source-drain electrode (22), and a fourth source-drain electrode (23). The first gate electrode (11) is electrically connected to a write word line (WL1), the first source-drain electrode (12) is electrically connected to a write bit line (BL1), and the second source-drain electrode (13) is electrically connected to the second gate electrode (21). The read transistor (TR) further comprises: a third gate electrode (31), which is insulatedly provided on a side of a connection portion between the second source-drain electrode (13) and the second gate electrode (21). The third gate electrode (31) is electrically connected to a read word line (WL2), the fourth source-drain electrode (23) is electrically connected to a read bit line (BL2), and the third source-drain electrode (22) is electrically connected to a common source line (SL).

Description

Storage unit, memory and preparation method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on September 28, 2023, with application number 202311271588X and invention name “Memory unit, memory and its preparation method, electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and better performance. Memory, which can easily achieve higher integration density and larger storage capacity, has gradually become one of the important research directions in the current storage field.

[0005] Summary of the Invention

[0006] According to some embodiments, the present disclosure provides a memory cell comprising: a write transistor and a read transistor; the write transistor comprising a first gate, a first source / drain, and a second source / drain; the read transistor comprising a second gate, a third source / drain, and a fourth source / drain; the first gate being electrically connected to a write word line, the first source / drain being electrically connected to a write bit line, and the second source / drain being electrically connected to the second gate. The read transistor further comprises: a third gate insulated and disposed on one side of a connection between the second source / drain and the second gate; the third gate being electrically connected to a read word line, the fourth source / drain being electrically connected to a read bit line, and the third source / drain being electrically connected to a common source line.

[0007] According to some embodiments, a read bit line and a write bit line are arranged in parallel and spaced apart, extending along a first direction. A write transistor and a read transistor are arranged side by side in a second direction and disposed within the space between the read bit line and the write bit line; the second direction intersects the first direction. A common source line surrounds the read transistor and extends away from the read transistor. A centerline of the common source line extends along the second direction.

[0008] According to some embodiments, the write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer. The first gate and the write bit line extend along a third direction; the third direction intersects both the first and second directions. The first semiconductor layer is disposed around the periphery of the first gate, with the centerline of the first semiconductor layer extending along the third direction. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer contacting the second gate and located on the side of the first gate facing away from the first source and drain is the second source and drain. The second gate extends along the second direction and includes: a first portion electrically connected to the second source and drain, and a second portion located on the side of the first portion facing away from the second source and drain and electrically connected to the first portion. The second semiconductor layer is disposed around the periphery of the second portion and on the side of the second portion facing away from the first portion. The centerline of the second semiconductor layer extends along the second direction. The portion of the second semiconductor layer disposed around the periphery of the second portion and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second portion facing away from the first portion is the fourth source and drain.

[0009] According to some embodiments, the third gate extends along a third direction and is insulated and disposed on one side of the first portion in the first direction.

[0010] According to some embodiments, the write transistor further includes a first gate dielectric layer; the read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected thereto. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer surrounds the third gate and is connected to both the second gate dielectric layer and the second gate.

[0011] According to some embodiments, the write word line is multiplexed as the read word line during the data reading phase. The first gate is multiplexed as the third gate during the data reading phase.

[0012] According to some embodiments, a size of the first portion in the first direction is larger than a size of the second portion in the first direction, and a size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

[0013] According to some embodiments, the write transistor further includes a first gate dielectric layer. The read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected thereto. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer is located between the first portion and the second semiconductor layer.

[0014] According to some embodiments, a dimension of the first semiconductor layer in the first direction is larger than a maximum dimension of the second gate in the first direction.

[0015] According to some embodiments, the present disclosure further provides a memory, comprising one or more storage units as described in any one of the aforementioned embodiments.

[0016] According to some embodiments, the present disclosure further provides a data reading and writing method, which is applied to the memory as described in any of the above embodiments; the connection between the second source and drain of the write transistor and the second gate of the read transistor is a storage node of the memory cell. The data reading and writing method includes:

[0017] In the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; the write word line controls the write transistor to turn on, and the storage node is discharged to a stable state to write data corresponding to the data voltage.

[0018] In the data reading stage, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the third gate connected to the read word line set to a low potential attracts more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is in an electrically non-conductive state.

[0019] According to some embodiments, the write word line is multiplexed as the read word line during the data reading phase; and the first gate is multiplexed as the third gate during the data reading phase.

[0020] In the data reading stage, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the first gate connected to the read word line set to a low potential attracts more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is in an electrically non-conductive state.

[0021] According to some embodiments, the present disclosure further provides a method for preparing a memory, comprising the following steps:

[0022] Depositing a first conductive material layer and an insulating material layer in sequence on the wafer to form a stacked structure;

[0023] forming read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along a first direction;

[0024] A read transistor and a write transistor are formed in the gap between the read bit line and the write bit line, and are arranged side by side in a second direction; the write transistor includes a first gate, a first source and drain, and a second source and drain; the read transistor includes a second gate, a third gate, a third source and drain, and a fourth source and drain; wherein the first source and drain are electrically connected to the write bit line, the second source and drain are electrically connected to the second gate, and the fourth source and drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection between the second source and drain and the second gate; the first direction and the second direction intersect, and the first direction and the second direction are both parallel to the wafer surface;

[0025] forming a write word line electrically connected to the first gate;

[0026] forming a read word line electrically connected to the third gate;

[0027] A common source line electrically connected to the third source and drain is formed.

[0028] According to some embodiments, forming read bit lines and write bit lines arranged in parallel and spaced apart and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the spaces between the read bit lines and the write bit lines, includes the following steps:

[0029] Forming a first conductive material layer and patterning the first conductive material layer to form a read bit line and a write bit line that are arranged in parallel and spaced apart, and a dummy gate located between and connecting the read bit line and the write bit line; wherein the read bit line and the write bit line extend along a first direction, and the dummy gate extends along a second direction;

[0030] Filling dielectric material on two opposite sides of the dummy gate in the first direction;

[0031] Etching the dummy gate and dielectric material in a first target area of ​​the dummy gate close to the write bit line to form an etched hole;

[0032] Based on the etched hole, the dummy gate is selectively etched along the second direction by wet etching to remove the retained dummy gate to form an accommodating groove; the accommodating groove exposes the corresponding side wall of the read bit line;

[0033] Depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence on the inner wall of the receiving groove by an atomic layer deposition process;

[0034] removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer within the etched hole so that the remaining gate dielectric material layer constitutes a second gate dielectric layer and the remaining second conductive material layer constitutes a second gate electrode; and removing the semiconductor material layer within a second target area near the etched hole so that the remaining semiconductor material layer constitutes a second semiconductor layer and exposes the sidewall of the second gate dielectric layer;

[0035] removing the semiconductor material layer in the second target area near the etched hole, so that the remaining semiconductor material layer constitutes a second semiconductor layer and exposes the sidewall of the second gate dielectric layer;

[0036] Etching dielectric material outside the sidewall of the second gate exposed in the first direction to form an accommodating hole; the accommodating hole exposes the sidewalls of the second gate dielectric layer and the second semiconductor layer facing away from the read bit line;

[0037] forming a third gate dielectric layer and a third gate electrode in sequence in the receiving hole;

[0038] A first semiconductor layer, a first gate dielectric layer and a first gate electrode are sequentially formed on the hole wall of the etched hole to obtain a write transistor.

[0039] The portion of the second semiconductor layer surrounding the second gate and connected to the common source line is the third source and drain, and the portion of the second semiconductor layer located on the side of the second gate facing away from the first gate is the fourth source and drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate facing away from the first source and drain is the second source and drain. The write word line is formed synchronously with the first gate. The read word line is formed synchronously with the third gate.

[0040] According to some embodiments, the write word line is multiplexed as the read word line during the data reading phase, and the first gate is multiplexed as the third gate during the data reading phase. The steps of forming a read bit line and a write bit line that are arranged in parallel and spaced apart and extend along a first direction, and forming a read transistor and a write transistor that are arranged side by side in a second direction in the space between the read bit line and the write bit line include the following steps:

[0041] Forming a first conductive material layer and patterning the first conductive material layer to form a read bit line and a dummy write bit line that are arranged in parallel and spaced apart, and a dummy gate located between and connected to the read bit line and the dummy write bit line; wherein the read bit line and the dummy write bit line extend along a first direction, and the dummy gate extends along a second direction;

[0042] Filling dielectric material on two opposite sides of the dummy gate in the first direction;

[0043] Etching the dummy gate and dielectric material in a first target area of ​​the dummy gate near the dummy write bit line to form an etched hole;

[0044] Based on the etched hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space including the etched hole; the accommodation space exposes the corresponding side wall of the read bit line;

[0045] Depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence in the accommodating space;

[0046] removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the third target region and the fourth target region adjacent to the first target region along the second direction, so that the remaining semiconductor material layer constitutes the second semiconductor layer, the remaining gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained on the side of the third target region close to the read bit line serves as the second portion of the second gate, and the second conductive material layer retained on the side of the fourth target region away from the read bit line serves as the write bit line;

[0047] forming a third gate dielectric layer on sidewalls of the second semiconductor layer and the second gate dielectric layer facing away from the read bit line;

[0048] forming a first portion of a second gate electrode at a second portion of the third target region and a sidewall of the third gate dielectric layer facing away from the read bit line;

[0049] A first semiconductor layer, a first gate dielectric layer and a first gate are sequentially formed on the hole wall of the hole etched between the first portion and the write bit line to obtain a write transistor.

[0050] The portion of the second semiconductor layer surrounding the second portion and connected to the common source line is the third source and drain, and the portion of the second semiconductor layer located on the side of the second portion facing away from the first portion is the fourth source and drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate facing away from the first source and drain is the second source and drain. The write word line is formed simultaneously with the first gate.

[0051] According to some embodiments, based on the etching hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space, which also includes: performing a wet etching process along the second direction and the first direction on the dummy write bit line and the retained dummy gate to form an accommodation space.

[0052] According to some embodiments, the present disclosure further provides an electronic device on another aspect, including: one or more memories as described in the above embodiments.

[0053] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0055] FIG1 is a schematic structural diagram of a storage unit provided in some embodiments of the present disclosure;

[0056] FIG2 is a schematic cross-sectional view of the structure shown in FIG1 at section M1;

[0057] FIG3 is a schematic diagram of an equivalent circuit of a memory cell provided in some embodiments of the present disclosure;

[0058] FIG4 is a schematic structural diagram of another storage unit provided in some embodiments of the present disclosure;

[0059] FIG5 is a schematic cross-sectional view of the structure shown in FIG4 at section M1;

[0060] FIG6 is a schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0061] FIG7 is a schematic diagram of a process for forming a read transistor and a write transistor in a method for manufacturing a memory provided in some embodiments;

[0062] FIG8 is a schematic cross-sectional view of a structure obtained in step S20 of a memory manufacturing method provided in some embodiments;

[0063] FIG9 is a schematic cross-sectional view of a structure obtained in step S31 in a method for manufacturing a memory device according to some embodiments;

[0064] FIG10 is a schematic cross-sectional view of a structure obtained in step S32 in a method for manufacturing a memory device according to some embodiments;

[0065] FIG11 is a schematic cross-sectional view of a structure obtained in step S33 in a method for manufacturing a memory device according to some embodiments;

[0066] FIG12 is a schematic cross-sectional view of a structure obtained in step S34 in a method for manufacturing a memory device according to some embodiments;

[0067] FIG13 is a schematic cross-sectional view of a structure obtained in step S35 in a method for manufacturing a memory device according to some embodiments;

[0068] FIG14 is a schematic cross-sectional view of a structure obtained in step S36 in a method for manufacturing a memory device according to some embodiments;

[0069] FIG15 is a schematic cross-sectional view of a structure obtained in step S37 in a method for manufacturing a memory device according to some embodiments;

[0070] FIG16 is a schematic cross-sectional view of a structure obtained in step S50 of a memory manufacturing method provided in some embodiments;

[0071] FIG17 is a schematic cross-sectional view of a structure obtained in step S60 in a method for manufacturing a memory provided in some embodiments;

[0072] FIG18 is another schematic diagram of a process for forming a read transistor and a write transistor in a method for manufacturing a memory provided in some embodiments;

[0073] FIG19 is a cross-sectional schematic diagram of another structure obtained in step S20 of a memory manufacturing method provided in some embodiments;

[0074] FIG20 is a schematic cross-sectional view of a structure obtained in step S31′ in a method for manufacturing a memory device according to some embodiments;

[0075] FIG21 is a schematic cross-sectional view of a structure obtained in step S32′ in a method for manufacturing a memory device according to some embodiments;

[0076] FIG22 is a schematic cross-sectional view of a structure obtained in step S33′ in a method for manufacturing a memory device according to some embodiments;

[0077] FIG23 is a schematic cross-sectional view of a structure obtained in step S34′ in a method for manufacturing a memory device according to some embodiments;

[0078] FIG24 is a schematic cross-sectional view of a structure obtained in step S35′ in a method for manufacturing a memory device according to some embodiments;

[0079] FIG25 is a schematic cross-sectional view of a structure obtained in step S36′ in a method for manufacturing a memory device according to some embodiments;

[0080] FIG26 is a schematic cross-sectional view of a structure obtained in step S37′ in a method for manufacturing a memory device according to some embodiments;

[0081] FIG27 is a cross-sectional schematic diagram of another structure obtained in step S50 of a memory manufacturing method provided in some embodiments;

[0082] FIG. 28 is a schematic cross-sectional view of another structure obtained in step S60 in a method for manufacturing a memory provided in some embodiments. DETAILED DESCRIPTION

[0083] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0085] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0086] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0087] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0088] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0089] Referring to Figures 1 to 3 , some embodiments of the present disclosure provide a memory cell including: a write transistor TW and a read transistor TR; the write transistor TW includes a first gate 11, a first source and drain 12, and a second source and drain 13. The read transistor TR includes a second gate 21, a third source and drain 22, and a fourth source and drain 23; the first gate 11 is electrically connected to a write word line WL1, the first source and drain 12 is electrically connected to a write bit line BL1, and the second source and drain 13 is electrically connected to the second gate 21. The read transistor TR further includes: a third gate 31, insulated and disposed on one side of the connection between the second source and drain 13 and the second gate 21; the third gate 31 is electrically connected to a read word line WL2, the fourth source and drain 23 is electrically connected to a read bit line BL2, and the third source and drain 22 is electrically connected to a common source line SL.

[0090] In the embodiment of the present disclosure, a third gate 31 is added to the read transistor TR of the storage unit, and the third gate 31 is insulated and arranged on one side of the connection portion (i.e., the storage node) between the second source and drain 13 of the write transistor TW and the second gate 21 of the read transistor TR, and the third gate 31 is electrically connected to the read word line WL2. In this way, when performing a read operation, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential. The third gate 31 corresponding to the low-potential read word line WL2 can attract more positive charge from the channel of the read transistor TR to ensure that the read transistor TR of the unselected memory cell is in an electrically disconnected state, thereby solving the multi-path problem caused by the read current bypassing multiple storage nodes due to the same read word line WL2 corresponding to the storage nodes of multiple read transistors TR during the read operation. It can also avoid the voltage drop problem on the target read bit line BL2 caused by leakage current flowing out of different read bit lines BL2 under the control of the same read word line WL2, and avoid the problem of interference between different memory cells, thereby helping to improve the performance and reliability of the memory cell and the memory.

[0091] In addition, in the embodiment of the present disclosure, the third source and drain 22 of the read transistor TR is electrically connected to the common source line SL, which is conducive to connecting the corresponding adjacent multiple memory cells into a piece through the common source line SL to solve the problem of current congestion and optimize the structure of the memory.

[0092] For example, the write word line WL1 and the first gate 11 can be formed simultaneously. The read word line WL2 and the third gate 31 can be formed simultaneously. For example, the write word line WL1 and the first gate 11 can be an integrated structure formed simultaneously using a synchronous process. The read word line WL2 and the third gate 31 can be an integrated structure formed simultaneously using a synchronous process.

[0093] In some embodiments, referring to Figures 1 and 2 , read bit lines BL2 and write bit lines BL1 are arranged in parallel and spaced apart, extending along a first direction (e.g., the X direction). Write transistors TW and read transistors TR are arranged side by side in a second direction (e.g., the Y direction) and disposed within the space between read bit lines BL2 and BL1. The second direction (e.g., the Y direction) intersects the first direction (e.g., the X direction). A common source line SL surrounds the read transistor TR and extends away from the read transistor TR. The centerline of the common source line SL extends along a second direction (e.g., the Y direction). A third direction (e.g., the Z direction) intersects both the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0094] In some embodiments, referring to FIG. 2 , the write transistor TW includes a first semiconductor layer 14. The read transistor TR includes a second semiconductor layer 24. The first gate 11 and the write word line WL1 extend along a third direction (e.g., the Z direction). The first semiconductor layer 14 surrounds the first gate 11, with the centerline of the first semiconductor layer 14 extending along the third direction (e.g., the Z direction). The portion of the first semiconductor layer 14 extending along the first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source and drain 12. The portion of the first semiconductor layer 14 that contacts the second gate 21 and is located on the side of the first gate 11 facing away from the first source and drain 12 is the second source and drain 13. The second gate 21 extends along the second direction (e.g., the Y direction) and includes a first portion A electrically connected to the second source and drain 13, and a second portion B located on the side of the first portion A facing away from the second source and drain 13 and electrically connected to the first portion A. The second semiconductor layer 24 surrounds the second portion B and the side of the second portion B facing away from the first portion A. The centerline of the second semiconductor layer 24 extends along the second direction (e.g., the Y direction). The portion of the second semiconductor layer 24 surrounding the second portion B and connected to the common source line SL is the third source / drain 22. The portion of the second semiconductor layer 24 located on the side of the second portion B facing away from the first portion A is the fourth source / drain 23.

[0095] In some embodiments, the third gate 31 extends along a third direction (eg, direction Z). The third gate 31 is insulated and disposed on one side of the first portion A in the first direction (eg, direction X).

[0096] In some embodiments, the write transistor TW further includes a first gate dielectric layer 15. The read transistor TR further includes a second gate dielectric layer 25 and a third gate dielectric layer 32 connected thereto. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 surrounds the third gate 31 and is connected to both the second gate dielectric layer 25 and the second gate 21.

[0097] In some embodiments, referring to FIG3 , first gate 11 is electrically connected to write word line WL1, first source and drain 12 is electrically connected to write bit line BL1, and second source and drain 13 is electrically connected to second gate 21. Third gate 31 is electrically connected to read word line WL2, fourth source and drain 23 is electrically connected to read bit line BL2, and third source and drain 22 is electrically connected to common source line SL.

[0098] 4 and 5 , the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase. The first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0099] In the disclosed embodiment, the write word line WL1 is reused as the read word line WL2 during the data reading phase, and the first gate 11 of the write transistor TW is reused as the third gate 31 of the read transistor TR during the data reading phase, which is beneficial to further simplify the structure and process of the storage unit and the memory.

[0100] In some embodiments, referring to FIG. 5 , the dimension of the first portion A in a first direction (e.g., the X direction) is larger than the dimension of the second portion B in the first direction (e.g., the X direction). The dimension of the first portion A in a second direction (e.g., the Y direction) is smaller than the dimension of the second portion B in the second direction (e.g., the Y direction).

[0101] In the disclosed embodiment, the size of the first portion A in a first direction (e.g., the X direction) is larger than the size of the second portion B in the first direction (e.g., the X direction), and the size of the first portion A in a second direction (e.g., the Y direction) is smaller than the size of the second portion B in the second direction (e.g., the Y direction). This makes the contact between the read transistor TR and the write transistor TW wider, and the channel of the read transistor TR narrower, thus giving the write word line WL1 greater control over the read word line WL2.

[0102] In some embodiments, the write transistor TW further includes a first gate dielectric layer 15. The read transistor TR further includes a second gate dielectric layer 25 and a third gate dielectric layer 32 connected thereto. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 is located between the first portion A and the second semiconductor layer 24.

[0103] In some embodiments, a dimension of the first semiconductor layer 14 in the first direction (eg, X direction) is larger than a maximum dimension of the second gate 21 in the first direction (eg, X direction).

[0104] In some embodiments, the present disclosure further provides a memory comprising one or more storage units as described in any of the aforementioned embodiments. The memory also possesses the technical advantages of the aforementioned storage units and will not be described in detail here.

[0105] Some embodiments of the present disclosure also provide a data reading and writing method, which is applied to a memory as described in any of the above embodiments. The data reading and writing method also has the technical advantages of the above memory, which will not be described in detail here. The connection between the second source and drain 13 of the write transistor TW and the second gate 21 of the read transistor TR is the storage node of the memory cell. The data reading and writing method includes:

[0106] S1: In the data writing phase, in response to a write command, the write bit line BL1 provides a data voltage to the write transistor TW; the write word line WL1 controls the write transistor TW to turn on, and the storage node is discharged to a stable state to write data corresponding to the data voltage.

[0107] S2: In the data reading stage, in response to the read command, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential, so that the third gate 31 corresponding to the read word line WL2 set to a low potential attracts more positive charges from the channel of the read transistor TR, and the read transistor TR in the unselected memory cell is in an electrically blocked state.

[0108] In some other embodiments, the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase. The first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0109] In the data reading stage, in response to the read command, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential, so that the first gate 11 corresponding to the read word line WL2 set to a low potential attracts more positive charges from the channel of the read transistor TR, and the read transistor TR in the unselected memory cell is in an electrically blocked state.

[0110] Some embodiments of the present disclosure also provide a method for manufacturing a memory, which is used to manufacture the memory in some of the above embodiments. This manufacturing method also possesses the technical advantages of the above memories.

[0111] Please refer to FIG. 6 and understand in combination with FIG. 1 to FIG. 3 that the manufacturing method includes the following steps.

[0112] S10: depositing a first conductive material layer and an insulating material layer in sequence on the wafer to form a stacked structure.

[0113] S20: forming read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along a first direction.

[0114] S30: A read transistor and a write transistor are formed in the gap between the read bit line and the write bit line, and are arranged side by side in the second direction; the write transistor includes a first gate, a first source and drain, and a second source and drain; the read transistor includes a second gate, a third gate, a third source and drain, and a fourth source and drain; wherein the first source and drain are electrically connected to the write bit line, the second source and drain are electrically connected to the second gate, and the fourth source and drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection portion between the second source and drain and the second gate; the first direction and the second direction intersect, and the first direction and the second direction are both parallel to the wafer surface.

[0115] S40: forming a write word line electrically connected to the first gate.

[0116] S50: forming a read word line electrically connected to the third gate.

[0117] S60: forming a common source line electrically connected to the third source and drain.

[0118] In some embodiments, step S20 forms read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along a first direction, including: forming a first conductive material layer, and patterning the first conductive material layer to form read bit lines and write bit lines that are arranged in parallel and spaced apart, and a virtual gate located between the read bit lines and the write bit lines and connecting the read bit lines and the write bit lines; wherein the read bit lines and the write bit lines extend along the first direction, and the virtual gate extends along the second direction.

[0119] In some embodiments, referring to FIG. 7 , step S30 of forming a read transistor and a write transistor arranged side by side in a second direction in the space between the read bit line and the write bit line includes the following steps:

[0120] S31: filling dielectric material on two opposite sides of the dummy gate in the first direction.

[0121] S32: etching the dummy gate and the dielectric material in a first target area of ​​the dummy gate close to the write bit line to form an etched hole.

[0122] S33: Based on the etched hole, the retained dummy gate is removed to form an accommodating groove; the accommodating groove exposes the corresponding side wall of the read bit line.

[0123] S34: depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence on the inner wall of the receiving groove.

[0124] S35: removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the etching hole, so that the retained gate dielectric material layer constitutes a second gate dielectric layer, and the retained second conductive material layer constitutes a second gate; and removing the semiconductor material layer in the second target area near the etching hole, so that the retained semiconductor material layer constitutes a second semiconductor layer, and exposing the side wall of the second gate dielectric layer.

[0125] S36: etching dielectric material outside the sidewall of the second gate dielectric layer exposed in the first direction to form an accommodating hole; the accommodating hole exposes the sidewall of the second semiconductor layer away from the read bit line.

[0126] S37: forming a third gate dielectric layer and a third gate in sequence in the receiving hole.

[0127] S38: forming a first semiconductor layer, a first gate dielectric layer, and a first gate electrode in sequence on the hole wall of the etched hole to obtain a write transistor.

[0128] In order to more clearly illustrate the memory manufacturing methods in some of the above embodiments, the following embodiments exemplarily provide some possible specific implementations of some steps.

[0129] In step S20, referring to FIG. 8 , a first conductive material layer (not shown) is formed and patterned to form a read bit line BL2 and a write bit line BL1 that are arranged in parallel and spaced apart, and a virtual gate VG located between and connecting the read bit line BL2 and the write bit line BL1; wherein the read bit line BL2 and the write bit line BL1 extend along a first direction (e.g., the X direction), and the virtual gate VG extends along a second direction (e.g., the Y direction).

[0130] It is important to note that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. This means that multiple first conductive material layers and multiple sacrificial layers are alternately stacked. The sacrificial layers are removed as needed to allow for subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layers of each write transistor.

[0131] Illustratively, the first conductive material layer includes a metal layer, such as a metal tungsten layer.

[0132] Illustratively, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0133] Here, each first conductive material layer and each sacrificial layer can be formed by a deposition process.

[0134] In step S31 , referring to FIG. 9 , a dielectric material L1 is filled on two opposite sides of the dummy gate VG in a first direction (eg, the X direction).

[0135] Illustratively, the dielectric material L1 includes but is not limited to silicon oxide.

[0136] Here, the dielectric material L1 may be formed by a deposition process. After the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process may be used to polish the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0137] In step S32 , referring to FIG. 10 , the dummy gate VG and the dielectric material L1 are etched in a first target region of the dummy gate VG close to the write bit line BL1 to form an etched hole K1 .

[0138] Here, dry etching may be used to form the etching hole K1.

[0139] In step S33 , referring to FIG. 11 , based on the etched hole K1 , the dummy gate VG is selectively etched along the second direction (eg, the Y direction) by wet etching to remove the retained dummy gate VG, thereby forming a receiving groove C1 ; the receiving groove C1 exposes the corresponding sidewall of the read bit line BL2 .

[0140] Here, wet etching may be used to remove the retained dummy gate VG to form the accommodating groove C1 .

[0141] In step S34 , referring to FIG. 12 , a semiconductor material layer 1 , a gate dielectric material layer 2 , and a second conductive material layer 3 are sequentially deposited on the inner wall of the receiving groove C1 by an atomic layer deposition process.

[0142] Here, an atomic layer deposition (ALD) process may be used to sequentially deposit the semiconductor material layer 1 , the gate dielectric material layer 2 , and the second conductive material layer 3 .

[0143] For example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0144] For example, the gate dielectric material layer 2 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0145] For example, the material of the second conductive material layer 3 includes but is not limited to metal tungsten.

[0146] In step S35, referring to Figure 13, the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the etching hole K1 are removed, so that the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, and the retained second conductive material layer 3 constitutes the second gate 21; and the semiconductor material layer 1 in the second target area near the etching hole K1 is removed, so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, and the side wall of the second gate dielectric layer 25 is exposed.

[0147] Here, after removing the semiconductor material layer 1 in the second target area near the etching hole K1 , it is necessary to backfill with the insulating material L2 .

[0148] Illustratively, the insulating material L2 includes, but is not limited to, silicon oxide.

[0149] For example, step S35 further includes: backfilling the second conductive material layer 3 in the area of ​​the etched hole K1 close to the write bit line BL1 .

[0150] In step S36, referring to FIG. 14 , dielectric material is etched outside the sidewall of the second gate 21 exposed in the first direction (e.g., the X direction) to form an accommodating hole K2; the accommodating hole K2 exposes the sidewalls of the second gate dielectric layer 25 and the second semiconductor layer 24 facing away from the read bit line BL2.

[0151] Here, the receiving hole K2 and the etching hole K1 are spaced apart along the second direction (eg, the Y direction).

[0152] For example, dry etching may be used to form the etching hole K2.

[0153] In step S37 , referring to FIG. 15 , a third gate dielectric layer 32 and a third gate electrode 31 are sequentially formed in the receiving hole K2 .

[0154] For example, the third gate dielectric layer 32 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, which is, for example, greater than 3.9. The material of the third gate 31 includes but is not limited to metal tungsten.

[0155] In step S38 , referring to FIG. 16 , a first semiconductor layer 14 , a first gate dielectric layer 15 and a first gate electrode 11 are sequentially formed on the wall of the etched hole K1 to obtain a write transistor TW.

[0156] For example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an IGZO layer. The first gate dielectric layer 15 includes but is not limited to an HK dielectric layer. The material of the first gate 11 includes but is not limited to metal tungsten.

[0157] Please continue to refer to Figure 16 to understand that the write transistor TW includes a first gate 11, a first source and drain 12, and a second source and drain 13; the read transistor includes a second gate 21, a third gate 31, a third source and drain 22, and a fourth source and drain 23. The first source and drain 12 is electrically connected to the write bit line BL1, the second source and drain 13 is electrically connected to the second gate 21, and the fourth source and drain 23 is electrically connected to the read bit line BL2. The third gate 31 is insulated and disposed on one side of the connection between the second source and drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second gate 21 facing away from the first gate 11 is the fourth source and drain 23. The portion of the first semiconductor layer 14 extending along the first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source and drain 12, and the portion of the first semiconductor layer 14 extending along the first direction (e.g., the X direction) and located on the side of the first gate 11 facing away from the first source and drain 12 is the second source and drain 13.

[0158] In step S40 , referring to FIG. 16 , a write word line WL1 electrically connected to the first gate 11 is formed.

[0159] Here, the write word line WL1 is formed synchronously with the first gate electrode 11 .

[0160] In step S50 , please continue to refer to FIG. 16 , a read word line WL2 electrically connected to the third gate 31 is formed.

[0161] Here, the read word line WL2 is formed synchronously with the third gate 31 .

[0162] In step S60 , referring to FIG. 17 , a common source line SL electrically connected to the third source and drain electrodes 22 is formed.

[0163] Here, the common source line SL includes, but is not limited to, metal tungsten.

[0164] For example, forming the common source line SL electrically connected to the third source / drain 22 includes: first etching the dielectric material L1 to expose the peripheral side of the second semiconductor layer 24 , and then backfilling the material to form the common source line SL.

[0165] The portion of the second semiconductor layer 24 surrounding the second gate 21 and connected to the common source line SL serves as the third source and drain 22 .

[0166] In some other embodiments, the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase, and the first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0167] Accordingly, in other embodiments, forming read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along the first direction in step S20 includes: forming a first conductive material layer, and patterning the first conductive material layer to form read bit lines and virtual write bit lines that are arranged in parallel and spaced apart, and a virtual gate VG located between the read bit lines and the virtual write bit lines and connecting the read bit lines and the virtual write bit lines; wherein the read bit lines and the virtual write bit lines extend along the first direction, and the virtual gate VG extends along the second direction (for example, the Y direction).

[0168] Accordingly, in other embodiments, referring to FIG. 18 and in combination with FIG. 4 and FIG. 5 , step S30 of forming a read transistor and a write transistor arranged side by side in the second direction in the gap between the read bit line and the write bit line may further include the following steps:

[0169] S31 ′: filling dielectric material on two opposite sides of the dummy gate in the first direction;

[0170] S32′: etching the dummy gate and the dielectric material in a first target area of ​​the dummy gate close to the dummy write bit line to form an etched hole;

[0171] S33′: Based on the etched hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space including the etched hole; the accommodation space exposes the corresponding sidewall of the read bit line;

[0172] S34′: depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence in the accommodating space;

[0173] S35′: removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the third target region and the fourth target region adjacent to the first target region along the second direction, so that the remaining semiconductor material layer constitutes the second semiconductor layer, the remaining gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained on the side of the third target region close to the read bit line serves as the second portion of the second gate, and the second conductive material layer retained on the side of the fourth target region away from the read bit line serves as the write bit line;

[0174] S36′: forming a third gate dielectric layer on sidewalls of the second semiconductor layer and the second gate dielectric layer facing away from the read bit line;

[0175] S37′: forming a first portion of a second gate in the second portion of the third target region and on a sidewall of the third gate dielectric layer facing away from the read bit line;

[0176] S38 ′: etching the hole wall between the first portion and the write bit line to sequentially form a first semiconductor layer, a first gate dielectric layer, and a first gate to obtain a write transistor.

[0177] In order to more clearly illustrate the memory manufacturing methods in some of the above embodiments, the following embodiments exemplarily provide some possible specific implementations of some steps.

[0178] In step S20, referring to FIG. 19 , forming read bit lines BL2 and write bit lines BL1 that are arranged in parallel and spaced apart and extend along a first direction (e.g., the X direction) includes: forming a first conductive material layer (not shown) and patterning the first conductive material layer to form read bit lines BL2 and virtual write bit lines VBL1 that are arranged in parallel and spaced apart, and a virtual gate VG located between the read bit lines BL2 and the virtual write bit lines VBL1 and connecting the read bit lines BL2 and the virtual write bit lines VBL1; wherein the read bit lines BL2 and the virtual write bit lines VBL1 extend along the first direction (e.g., the X direction), and the virtual gate VG extends along the second direction (e.g., the Y direction).

[0179] It is important to note that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. This means that multiple first conductive material layers and multiple sacrificial layers are alternately stacked. The sacrificial layers are removed as needed to allow for subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layers of each write transistor.

[0180] Illustratively, the first conductive material layer includes a metal layer, such as a metal tungsten layer.

[0181] Illustratively, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0182] Here, each first conductive material layer and each sacrificial layer can be formed by a deposition process.

[0183] In step S31 ′, referring to FIG. 20 , a dielectric material L1 is filled on two opposite sides of the dummy gate VG in a first direction (eg, X direction).

[0184] Illustratively, the dielectric material L1 includes but is not limited to silicon oxide.

[0185] Here, the dielectric material L1 may be formed by a deposition process. After the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process may be used to polish the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0186] In step S32 ′, referring to FIG. 21 , the dummy gate VG and the dielectric material L1 are etched in a first target region of the dummy gate VG close to the dummy write bit line VBL1 to form an etched hole K1 .

[0187] Here, dry etching may be used to form the etching hole K1.

[0188] In step S33 ′, referring to FIG. 22 , based on the etching hole K1 , the dummy write bit line VBL1 and the retained dummy gate VG are removed to form an accommodating space C2 including the etching hole K1 ; the accommodating space exposes the corresponding sidewall of the read bit line BL2 .

[0189] For example, based on the etching hole K1, the virtual write bit line VBL1 and the retained virtual gate VG are removed to form an accommodating space C2, and the process also includes: performing a wet etching process on the virtual write bit line VBL1 and the retained virtual gate VG along the second direction (for example, the Y direction) and the first direction (for example, the X direction) to form the accommodating space C2.

[0190] In step S34 ′, referring to FIG. 23 , a semiconductor material layer 1 , a gate dielectric material layer 2 , and a second conductive material layer 3 are sequentially deposited in the accommodating space C2 .

[0191] For example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0192] Illustratively, the gate dielectric material layer 2 includes but is not limited to a HK dielectric layer.

[0193] For example, the material of the second conductive material layer 3 includes but is not limited to metal tungsten.

[0194] Here, the semiconductor material layer 1 , the gate dielectric material layer 2 and the second conductive material layer 3 may be deposited in sequence using an ALD process.

[0195] In step S35', referring to Figure 24, the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target area, as well as the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the third target area and the fourth target area adjacent to the first target area along the second direction (for example, the Y direction) are removed, so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, the second conductive material layer 3 retained in the third target area close to the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained in the fourth target area away from the read bit line BL2 is the write bit line BL1.

[0196] Here, dry etching can be used to first remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target area, and then wet etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the third target area and the fourth target area along the second direction (for example, the Y direction). The second conductive material layer 3 retained in the third target area close to the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained in the fourth target area away from the read bit line BL2 is the write bit line BL1.

[0197] In step S36 ′, referring to FIG. 25 , a third gate dielectric layer 32 is formed on the sidewalls of the second semiconductor layer 24 and the second gate dielectric layer 25 away from the read bit line BL2 .

[0198] Illustratively, the third gate dielectric layer 32 includes but is not limited to a HK dielectric layer.

[0199] In step S37 ′, referring to FIG. 26 , a first portion A of the second gate 21 is formed in the second portion B of the third target region and on the sidewall of the third gate dielectric layer 32 facing away from the read bit line BL2 .

[0200] Here, while forming the first portion A of the second gate 21 , the second conductive material layer 3 is backfilled in the fourth target region.

[0201] In step S38 ′, referring to FIG. 27 , a first semiconductor layer 14 , a first gate dielectric layer 15 and a first gate electrode 11 are sequentially formed by etching the wall of a hole K1 between the first portion A and the write bit line BL1 to obtain a write transistor TW.

[0202] For example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0203] Illustratively, the first gate dielectric layer 15 includes but is not limited to a HK dielectric layer.

[0204] For example, the material of the first gate 11 includes but is not limited to metal tungsten.

[0205] Here, the first semiconductor layer 14 , the first gate dielectric layer 15 and the first gate 11 may be deposited in sequence by using an ALD process.

[0206] Please continue to refer to Figure 27 to understand that the write transistor TW includes a first gate 11, a first source and drain 12, and a second source and drain 13; the read transistor includes a second gate 21, a third gate 31, a third source and drain 22, and a fourth source and drain 23. The first source and drain 12 is electrically connected to the write bit line BL1, the second source and drain 13 is electrically connected to the second gate 21, and the fourth source and drain 23 is electrically connected to the read bit line BL2. The third gate 31 is insulated and disposed on one side of the connection between the second source and drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second portion B facing away from the first portion A is the fourth source and drain 23. The portion of the first semiconductor layer 14 extending along the first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source and drain 12. The portion of the first semiconductor layer 14 extending along the first direction (e.g., the X direction) and located on the side of the first gate 11 facing away from the first source and drain 12 is the second source and drain 13.

[0207] In step S40 , referring to FIG. 27 , a write word line WL1 electrically connected to the first gate 11 is formed.

[0208] Here, the write word line WL1 is formed synchronously with the first gate electrode 11 .

[0209] In step S50 , please continue to refer to FIG. 27 , a read word line WL2 electrically connected to the third gate 31 is formed.

[0210] Here, the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase, and the first gate 11 is multiplexed as the third gate 31 during the data reading phase. The read word line WL2 and the third gate 31 are formed synchronously.

[0211] In step S60 , referring to FIG. 28 , a common source line SL electrically connected to the third source and drain electrodes 22 is formed.

[0212] Here, the common source line SL includes, but is not limited to, metal tungsten.

[0213] For example, forming the common source line SL electrically connected to the third source / drain 22 includes: first etching the dielectric material L1 to expose the peripheral side of the second semiconductor layer 24 , and then backfilling the material to form the common source line SL.

[0214] The portion of the second semiconductor layer 24 surrounding the second portion B and connected to the common source line SL serves as the third source and drain 22 .

[0215] Some embodiments of the present disclosure further provide an electronic device comprising: one or more memories as described in the aforementioned embodiments. Examples include data storage devices, photocopiers, network equipment, household appliances, instruments, mobile phones, computers, and other devices with data storage capabilities. The electronic device may include a housing, a circuit board disposed within the housing, and a memory or data read / write circuit integrated on the circuit board. The structure of the memory can be found in the relevant descriptions of some of the aforementioned embodiments. The electronic device may also include other necessary elements or components, which are not limited in the present disclosure.

[0216] In some embodiments, the memory may be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory and can control the read and write operations of the memory.

[0217] In some embodiments, the memory is 3D dynamic random access memory.

[0218] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0219] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage unit, comprising: A write transistor and a read transistor; the write transistor comprises a first gate, a first source and a drain, and a second source and a drain; the read transistor comprises a second gate, a third source and a drain, and a fourth source and a drain; The first gate is electrically connected to a write word line, the first source and drain are electrically connected to a write bit line, and the second source and drain are electrically connected to the second gate; Wherein, the read transistor further comprises: a third gate, insulated and arranged on one side of a connection portion between the second source and drain and the second gate; The third gate is electrically connected to a read word line, the fourth source and drain are electrically connected to a read bit line, and the third source and drain are electrically connected to a common source line.

2. The storage unit according to claim 1, wherein: The read bit lines and the write bit lines are arranged in parallel and spaced apart from each other, and extend along a first direction; The write transistor and the read transistor are arranged side by side in a second direction and are disposed in a space between the read bit line and the write bit line; The second direction intersects the first direction; The common source line surrounds the peripheral side of the read transistor and extends in a direction away from the read transistor; the surrounding center line of the common source line extends along the second direction.

3. The storage unit according to claim 1 or 2, wherein: The write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer; The first gate and the write word line extend along a third direction; the third direction intersects both the first direction and the second direction; The first semiconductor layer is disposed around the first gate, and the center line of the first semiconductor layer extends along the third direction; the portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer contacting the second gate and located on the side of the first gate away from the first source and drain is the second source and drain; The second gate extends along the second direction and includes: a first portion electrically connected to the second source and drain, and a second portion located on a side of the first portion away from the second source and drain and electrically connected to the first portion; The second semiconductor layer is arranged around the periphery of the second part and on the side of the second part away from the first part; the center line of the second semiconductor layer extends along the second direction; the part of the second semiconductor layer arranged around the periphery of the second part and connected to the common source line is the third source and drain; the part of the second semiconductor layer located on the side of the second part away from the first part is the fourth source and drain.

4. The storage unit according to claim 3, wherein: The third gate extends along the third direction; The third gate insulation is disposed on one side of the first portion in the first direction.

5. The storage unit according to claim 3 or 4, wherein: The write transistor further includes a first gate dielectric layer; the read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is disposed around the third gate electrode and is connected to both the second gate dielectric layer and the second gate electrode.

6. The storage unit according to any one of claims 1 to 3, wherein: The write word line is multiplexed as the read word line during a data reading phase; the first gate is multiplexed as the third gate during the data reading phase.

7. The storage unit according to any one of claims 3 to 6, wherein: The size of the first portion in the first direction is greater than the size of the second portion in the first direction; A size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

8. The storage unit according to any one of claims 3 to 6, wherein: The write transistor further includes a first gate dielectric layer; the read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is located between the first portion and the second semiconductor layer.

9. The storage unit according to any one of claims 3 to 8, wherein: A size of the first semiconductor layer in the first direction is greater than a maximum size of the second gate in the first direction.

10. A memory comprising: One or more storage units as claimed in any one of claims 1 to 9.

11. A data reading and writing method, applied to the memory according to claim 10; the connection portion between the second source and drain of the write transistor and the second gate of the read transistor is a storage node of the storage unit; the data reading and writing method comprises: In the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; The write word line controls the write transistor to be turned on, and the storage node is discharged to a stable state, so as to write the data corresponding to the data voltage; In the data reading stage, in response to the read command, the read word line in the selected storage cell is set to a normal potential, and the read word line in the unselected storage cell is set to a low potential, so that the third gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected storage cell is in an electrically non-conductive state.

12. The data reading and writing method according to claim 11, wherein: The write word line is multiplexed as the read word line during the data reading phase; the first gate is multiplexed as the third gate during the data reading phase; In the data reading stage, in response to the read command, the read word line in the selected storage cell is set to a normal potential, and the read word line in the unselected storage cell is set to a low potential, so that the first gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected storage cell is in an electrically blocked state.

13. A method for preparing a memory, comprising: Depositing a first conductive material layer and an insulating material layer on the wafer in sequence to form a stacked structure; forming read bit lines and write bit lines which are arranged in parallel and spaced apart and extend along a first direction; A read transistor and a write transistor arranged side by side in a second direction are formed in the interval between the read bit line and the write bit line; the write transistor includes a first gate, a first source and a drain, and a second source and a drain; the read transistor includes a second gate, a third gate, a third source and a drain, and a fourth source and a drain; wherein the first source and the drain are electrically connected to the write bit line, the second source and the drain are electrically connected to the second gate, and the fourth source and the drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection portion between the second source and the drain and the second gate; the first direction and the second direction intersect, and the first direction and the second direction are both parallel to the surface of the wafer; forming a write word line electrically connected to the first gate; forming a read word line electrically connected to the third gate; A common source line electrically connected to the third source and drain is formed.

14. The method for preparing a memory according to claim 13, wherein: The method comprises forming read bit lines and write bit lines arranged in parallel and spaced apart and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the space between the read bit lines and the write bit lines, comprising: Patterning the first conductive material layer to form the read bit line and the write bit line that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the read bit line and the write bit line; wherein the read bit line and the write bit line extend along the first direction, and the virtual gate extends along the second direction; Filling dielectric material on two opposite sides of the virtual gate in the first direction; Etching the dummy gate and the dielectric material in a first target area of ​​the dummy gate close to the write bit line to form an etching hole; Based on the etching hole, the dummy gate is selectively etched along the second direction by wet etching to remove the retained dummy gate to form a receiving groove; the receiving groove exposes the corresponding side wall of the read bit line; A semiconductor material layer, a gate dielectric material layer and a first dielectric material layer are sequentially deposited on the inner wall of the receiving groove by an atomic layer deposition process. Second conductive material layer; Removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the etching hole, so that the remaining gate dielectric material layer constitutes a second gate dielectric layer, and the remaining second conductive material layer constitutes the second gate; and removing the semiconductor material layer in a second target area close to the etching hole, so that the remaining semiconductor material layer constitutes a second semiconductor layer, and exposing the sidewall of the second gate dielectric layer; The dielectric material is etched outside the side wall of the second gate exposed in the first direction to form a receiving hole; the receiving hole exposes the side wall of the second gate dielectric layer and the second semiconductor layer away from the read bit line; forming a third gate dielectric layer and the third gate in the receiving hole in sequence; Sequentially forming a first semiconductor layer, a first gate dielectric layer and the first gate on the hole wall of the etched hole to obtain the write transistor; The portion of the second semiconductor layer surrounding the second gate and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second gate away from the first gate is the fourth source and drain; The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain; The write word line is formed synchronously with the first gate; The read word line is formed synchronously with the third gate.

15. The method for preparing a memory according to claim 13 or 14, wherein: The write word line is multiplexed as the read word line in a data reading phase, and the first gate is multiplexed as the third gate in the data reading phase; The method comprises forming read bit lines and write bit lines arranged in parallel and spaced apart and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the space between the read bit lines and the write bit lines, comprising: Forming a first conductive material layer, and patterning the first conductive material layer to form the read bit line and the virtual write bit line arranged in parallel and spaced apart, and a virtual gate located between the read bit line and the virtual write bit line and connecting the read bit line and the virtual write bit line; wherein the read bit line and the virtual write bit line extend along the first direction, and the virtual gate extends along the second direction; Filling dielectric material on two opposite sides of the virtual gate in the first direction; Etching the virtual gate and the dielectric material at a first target area of ​​the virtual gate close to the virtual write bit line to form an etching hole; Based on the etched hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space including the etched hole; the accommodation space exposes the corresponding side wall of the read bit line; Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in the accommodating space in sequence; removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the third target region and the fourth target region on both sides of the first target region along the second direction, so that the retained semiconductor material layer constitutes a second semiconductor layer, the retained gate dielectric material layer constitutes a second gate dielectric layer, the second conductive material layer retained in the third target region close to the read bit line is the second part of the second gate, and the second conductive material layer retained in the fourth target region away from the read bit line is the write bit line; forming a third gate dielectric layer on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the read bit line; forming a first portion of the second gate in the third target region at the second portion and a sidewall of the third gate dielectric layer away from the read bit line; Sequentially forming a first semiconductor layer, a first gate dielectric layer and the first gate on the hole wall of the etched hole between the first portion and the write bit line to obtain the write transistor; The portion of the second semiconductor layer surrounding the second portion and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second portion away from the first portion is the fourth source Drain; The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain; The write word line is formed synchronously with the first gate.

16. The method for preparing a memory according to claim 15, wherein: The method of removing the dummy write bit line and the retained dummy gate based on the etched hole to form an accommodation space further includes: A wet etching process is performed on the dummy write bit line and the retained dummy gate along the second direction and the first direction to form the accommodation space.

17. An electronic device comprising: One or more memories as claimed in claim 10.

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