Capacitive detection circuit and touch detection device

Abstract

The present application relates to a capacitive detection circuit and a touch detection device. The capacitive detection circuit is connected to a first touch panel and a second touch panel in a peripheral circuit, and comprises a coarse tuning capacitor array, a fine tuning capacitor array, a logic circuit and a comparator; the comparator compares the voltage difference between the first touch panel and the second touch panel and generates and outputs a first comparison signal to the logic circuit; the logic circuit generates a first control signal on the basis of the first comparison signal, and on the basis of the first control signal, controls the coarse tuning capacitor array to work, so that the coarse tuning capacitor array adjusts the equivalent capacitance difference between the first touch panel and the second touch panel to reduce same to a target range; the logic circuit is further used for acquiring a second comparison signal generated by the comparator, generating a second control signal on the basis of the second comparison signal, and on the basis of the second control signal, controlling the fine tuning capacitor array to sample the current equivalent capacitance difference between the first touch panel and the second touch panel. The use of the capacitive detection circuit can improve the sensitivity of touch detection.

Description

Capacitive detection circuit and touch detection equipment

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311250334X, filed on September 26, 2023, entitled “Capacitance detection circuit and touch detection device,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of touch detection technology, and in particular to a capacitance detection circuit and a touch detection device. Background Art

[0004] Capacitive touch buttons are widely used in various fields such as automobiles, home appliances, and security. Currently, the most widely used detection technology for touch buttons is RC ring oscillator-based touch button detection technology, which converts capacitance changes into digital signals for touch detection. Therefore, it is also called capacitance-to-digital converter.

[0005] However, the touch button detection technology based on RC ring oscillation has the problem of low detection sensitivity.

[0006] Summary of the Invention

[0007] Based on this, it is necessary to provide a capacitance detection circuit and a touch detection device that improve the sensitivity of touch detection.

[0008] In a first aspect, the present application provides a capacitance detection circuit connected to a first touch pad and a second touch pad in a peripheral circuit; the capacitance detection circuit includes a coarse-tuning capacitor array, a fine-tuning capacitor array, a logic circuit, and a comparator; the comparator is configured to compare the voltage difference between the first touch pad and the second touch pad, generate a first comparison signal based on the comparison result, and output the first comparison signal to the logic circuit; the logic circuit is configured to generate a first control signal based on the first comparison signal, and control the operation of the coarse-tuning capacitor array based on the first control signal, so as to adjust the equivalent capacitance difference between the first touch pad and the second touch pad to a target range through the coarse-tuning capacitor array; when the equivalent capacitance difference between the first touch pad and the second touch pad is reduced to the target range, the logic circuit is further configured to obtain a second comparison signal generated by the comparator, generate a second control signal based on the second comparison signal, and control the fine-tuning capacitor array to sample the current equivalent capacitance difference between the first touch pad and the second touch pad based on the second control signal.

[0009] In one embodiment, the peripheral circuit also includes a first parasitic capacitance circuit corresponding to the first touch pad and a second parasitic capacitance circuit corresponding to the second touch pad; the capacitance detection circuit also includes a first bridge circuit connected to the first touch pad and a second bridge circuit connected to the second touch pad; the coarse adjustment capacitor array includes multiple first switch arrays; the first control signal includes M first single-bit signals; the logic circuit is specifically used to: control the first parasitic capacitance circuit, the second parasitic capacitance circuit, the first bridge circuit and the second bridge circuit to form a bridge according to a first clock signal input by an external controller, and based on successive approximation logic, successively obtain M first single-bit signals according to the first comparison signal, and sequentially control the operation of each first switch array in the coarse adjustment capacitor array according to the M first single-bit signals; wherein the value of M is the same as the number of the first switch arrays.

[0010] In one embodiment, the second control signal includes N second single-bit signals; the fine-tuning capacitor array includes a first fine-tuning capacitor array connected to the first touch pad and a second fine-tuning capacitor array connected to the second touch pad; the first fine-tuning capacitor array includes first capacitors respectively connected to the N second single-bit signals; the second fine-tuning capacitor array includes second capacitors respectively connected to N third single-bit signals opposite to the N second single-bit signals; the logic circuit is specifically used to: based on a second clock signal input by an external controller and based on successive approximation logic, successively obtain the N second single-bit signals and generate the N third single-bit signals according to the second comparison signal, sequentially control each first capacitor to be grounded or connected to a power supply according to the N second single-bit signals, and sequentially control each second capacitor to be grounded or connected to a power supply according to the N third single-bit signals.

[0011] In one embodiment, the logic circuit is connected to an external controller; the logic circuit is specifically used to: when the second clock signal ends, output the N second single-bit signals to the external controller, so that the external controller calculates the current equivalent capacitance difference based on the N second single-bit signals.

[0012] In one embodiment, the capacitance detection circuit further includes an offset compensation capacitance circuit, which is connected to the logic circuit; the logic circuit is further configured to control the offset compensation capacitance circuit to be connected to the first touch panel or the second touch panel according to the highest bit of the first control signal.

[0013] In one embodiment, the offset compensation capacitor circuit includes a third capacitor, and the capacitance value of the third capacitor is greater than or equal to the capacitance value of the parasitic capacitance generated by the coarse tuning capacitor array.

[0014] In one embodiment, the offset compensation capacitor circuit further includes a second switch and a third switch, the third capacitor is connected in parallel with the second switch, one end of the third capacitor is grounded, and the other end of the third capacitor is connected to one end of the third switch, and the third switch is connected to the first touch pad or the second touch pad under the control of the highest bit of the first control signal.

[0015] In one embodiment, the highest-order first switch array in the coarse-tuning capacitor array includes two first switches, and the two first switches in the highest-order first switch array are controlled by the highest-order first single-bit signal of the first control signal; the other first switch arrays in the coarse-tuning capacitor array respectively include two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are controlled in turn by the other-order first single-bit signals of the first control signal.

[0016] In one embodiment, one end of each other first switch array is grounded, and the other end is connected to the highest first switch array; for each other first switch array, the fourth capacitor is connected in parallel with the first first switch in the other first switch array, and one end of the fourth capacitor is grounded, the other end of the fourth capacitor is connected to one end of the second first switch, and the other end of the second first switch is connected to the highest first switch array.

[0017] In a second aspect, the present application further provides a touch detection device, which includes the peripheral circuit and the capacitance detection circuit as described in any one of the above aspects.

[0018] In the above-mentioned capacitance detection circuit and touch detection device, the capacitance detection circuit is connected to the first touch pad and the second touch pad in the peripheral circuit; the capacitance detection circuit includes a coarse adjustment capacitor array, a fine adjustment capacitor array, a logic circuit and a comparator; the comparator is used to compare the voltage difference between the first touch pad and the second touch pad, generate a first comparison signal based on the comparison result, and output the first comparison signal to the logic circuit; the logic circuit is used to generate a first control signal based on the first comparison signal, and control the operation of the coarse adjustment capacitor array based on the first control signal, so as to adjust the equivalent capacitance difference between the first touch pad and the second touch pad to a target range through the coarse adjustment capacitor array; when the equivalent capacitance difference between the first touch pad and the second touch pad is reduced to the target range, the logic circuit is also used to obtain a second comparison signal generated by the comparator, generate a second control signal based on the second comparison signal, and control the fine adjustment capacitor array to sample the current equivalent capacitance difference between the first touch pad and the second touch pad based on the second control signal. In this way, based on the combination of the coarse-tuning capacitor array and the fine-tuning capacitor array, the coarse-tuning capacitor array is first used to reduce the equivalent capacitance difference between the first touch pad and the second touch pad to a target range. Then, when the fine-tuning capacitor array samples the current equivalent capacitance difference between the first and second touch pads, the current equivalent capacitance difference that needs to be sampled is very small. Therefore, sampling can be achieved with a smaller data bit width, reducing sampling time and improving the sensitivity of the detection process. Furthermore, because the equivalent capacitance difference between the first and second touch pads has been reduced to the target range after coarse adjustment, the operating frequency of the coarse-tuning capacitor array is much lower than the operating frequency of the fine-tuning capacitor array. Sampling is performed through the fine-tuning capacitor array most of the time, effectively saving power consumption of the capacitance detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0020] FIG1 is a schematic structural diagram of a capacitance detection circuit in one embodiment;

[0021] FIG2 is a schematic structural diagram of another capacitance detection circuit according to an embodiment;

[0022] FIG3 is a schematic structural diagram of another capacitance detection circuit in one embodiment;

[0023] FIG4 is a schematic diagram of some signal waveforms of a coarse adjustment calibration process according to an embodiment;

[0024] FIG5 is a schematic diagram of the structure of a coarse tuning capacitor array in one embodiment;

[0025] FIG6 is a schematic structural diagram of another capacitance detection circuit in one embodiment;

[0026] FIG7 is a schematic structural diagram of an offset compensation capacitor circuit according to an embodiment;

[0027] FIG8 is a schematic structural diagram of another offset compensation capacitor circuit according to an embodiment;

[0028] FIG9 is a schematic structural diagram of another capacitance detection circuit in one embodiment;

[0029] FIG10 is a schematic diagram of the structure of a fine-tuning capacitor array in one embodiment;

[0030] FIG11 is a schematic structural diagram of another capacitance detection circuit in one embodiment;

[0031] FIG12 is a waveform diagram of a fine adjustment correction process in one embodiment. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0035] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0036] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0037] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0038] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0039] Capacitive touch buttons are widely used in automotive, home appliance, and security applications. Compared to physical buttons, they offer advantages such as smooth appearance, easy cleaning, and long life. Capacitive touch buttons work by detecting the equivalent capacitance between an internal probe and the button surface. Once the change in capacitance exceeds a set threshold, it determines that a finger is pressing. Technically, most capacitive touch buttons in the industry currently rely on the following two principles.

[0040] The first is an RC ring oscillator structure, where the resonant frequency of the ring oscillator is inversely proportional to the size of the equivalent capacitance of the touch button. If a finger touches the button, the resonant frequency of the ring oscillator will decrease. The resonant frequency of the ring oscillator is digitized using an on-chip reference frequency, and a suitable threshold is set to determine whether a finger has touched the button. However, this method has the disadvantages of slow judgment speed, the need for a reference clock, and poor common-mode interference resistance. Therefore, its detection sensitivity is generally low. High-performance systems using capacitive touch buttons generally require a certain degree of common-mode interference resistance, which is manifested as a certain ability to filter out AC interference signals between the human body ground potential and the circuit ground potential.

[0041] The basic analog circuitry of nearly all capacitive touch button structures is unable to filter out AC interference signals from finger input. This is because the interference signal is single-ended to the circuit, meaning it originates from the same source as the target signal. This makes it impossible for the system to directly distinguish between the target and interference signals. This is typically achieved through a subsequent digital filter that removes high-frequency interference signals while retaining the low-frequency target signal. However, achieving such a low cutoff frequency is difficult for analog circuits. RC ring oscillator touch button circuits have poor common-mode interference immunity because they lack a sampling clock to control sampling timing. If strong interference occurs at the moment the comparator flips, the comparator is prone to multiple false flips, generating erroneous clock signals. Another issue with RC ring oscillator structures is their sensitivity to parasitic resistance in the wiring. Even at the moment the comparator flips, current flows through the load capacitor, and the voltage drop caused by the parasitic resistance can introduce errors. This problem is exacerbated by the large resistance of the human body and the significant parasitic resistance between the body ground and the circuit ground. In summary, RC ring oscillator-based touch button detection technology is not suitable for applications requiring high common-mode interference immunity. Even digital filtering cannot filter out AC interference signals.

[0042] The second is a touch button detection technology based on charge sharing, which uses a fixed-frequency clock to periodically share the charge of the periodically charged touch button capacitor and a large-capacity integration capacitor, which is manifested as the charge of the touch capacitor being periodically transferred to the large integration capacitor. The voltage of the integration capacitor gradually increases from zero voltage at the beginning of the first clock. When it increases to the preset value, an integration cycle ends and the corresponding clock accumulation number is output. Different touch button capacitors correspond to different clock accumulation numbers, so the change in the touch button capacitance can be detected to determine whether the finger is touching or not. However, its disadvantages are more obvious: first, a separate large integration capacitor is required, and the consumption of one more pin leads to an increase in cost; second, when only one more pin is allowed, general applications require multiple touch buttons, and multiple touch buttons can only share one integration capacitor, which greatly reduces the sampling speed and is not suitable for higher-speed sampling applications. In addition, in order to obtain higher sensitivity, it is necessary to increase the value of the integral, which results in only increasing C INT , which leads to a further decrease in sampling speed.

[0043] In view of this, in an embodiment of the present application, a capacitance detection circuit is provided, which adopts a differential structure, has good resistance to common-mode interference, can improve the sensitivity and accuracy of touch detection, has a high sampling speed and low power consumption.

[0044] In one embodiment, as shown in FIG1 , a schematic diagram of the structure of a capacitance detection circuit provided by an embodiment of the present application is shown. The capacitance detection circuit 100 is connected to a first touch panel 201 and a second touch panel 202 in a peripheral circuit 200 ; the capacitance detection circuit 100 includes a coarse adjustment capacitor array 101, a fine adjustment capacitor array 102, a logic circuit 103, and a comparator 104. The comparator 104 is used to compare the voltage difference between the first touch panel 201 and the second touch panel 202, generate a first comparison signal based on the comparison result, and output the first comparison signal to the logic circuit 103; the logic circuit 103 is used to generate a first control signal based on the first comparison signal, and control the operation of the coarse tuning capacitor array 101 based on the first control signal, so as to adjust the equivalent capacitance difference between the first touch panel 201 and the second touch panel 202 to a target range through the coarse tuning capacitor array 101; when the equivalent capacitance difference between the first touch panel 201 and the second touch panel 202 is reduced to the target range, the logic circuit 103 is further used to obtain the second comparison signal generated by the comparator 104, generate a second control signal based on the second comparison signal, and control the fine tuning capacitor array 102 to sample the current equivalent capacitance difference between the first touch panel 201 and the second touch panel 202 based on the second control signal.

[0045] Among them, record C touch1 and C touch2 = is the equivalent capacitance between the finger and the first touch panel 201 and the second touch panel 202 after the finger touches. Generally, only one finger touches, so only one of the capacitances exists, and the other capacitance is zero. It should be noted that touching both touch panels simultaneously will also result in a capacitance difference, but this can be considered to have approximately the same effect as touching only one of them.

[0046] C touch1 and C touch2 The equivalent ground is GND, which is different from the circuit ground V SS . Touch capacitance C touch1 or C touch2 The value of is usually very small, especially in the case of air touch, it may be as low as 100fF. S1 and V S2 , V is also used in the following description S1 and V S2 To characterize the voltage of the two touch panels respectively.

[0047] Assume that there is no finger touching at the beginning, C touch1 and C touch2 The voltage value V corresponding to the first touch panel 201 is 0. S1 Parasitic capacitance to ground C S1 and the voltage value V corresponding to the second touch panel 202 S2 Parasitic capacitance to ground CS2 It is impossible to be exactly the same. In extreme cases, the difference may reach several pF. S1 and V S2 To achieve high sensitivity and cover such a large detection range, a higher data bit width is required and the single sampling time will be longer. The detailed reason is that in order to improve the detection sensitivity of touch capacitance, the minimum value of the unit detection capacitance must be reduced, but V S1 and V S2 The large difference in initial parasitic capacitance requires the sampling device (e.g., capacitance-to-digital converter (CDC)) to have a detection capability higher than the large parasitic capacitance difference. Generally speaking, there is a trade-off between detection sensitivity and maximum detection range. Even if this can be achieved, a high number of conversion bits is required, which results in high power consumption and long conversion time. Based on this, the embodiment of the present application adopts a combination of coarse and fine adjustment.

[0048] During the coarse adjustment phase, starting at a certain point in time after initial power-up or a setting, logic circuit 103 receives a first comparison signal generated by comparator 104 comparing the voltage difference between first touch panel 201 and second touch panel 202. Logic circuit 103 generates a first control signal based on the first comparison signal and sends it to coarse adjustment capacitor array 101, thereby controlling the operation of coarse adjustment capacitor array 101 through the first control signal.

[0049] Initially, to improve the sensitivity of the capacitance detection circuit 100 , the coarse adjustment capacitor array 101 is connected to one of the first touch panel 201 and the second touch panel 202 . For example, in FIG. 1 , the coarse adjustment capacitor array 101 is connected to the first touch panel 201 .

[0050] During the operation of the coarse adjustment capacitor array 101, the parasitic capacitance C of the two ports is S1 and C S2 The equivalent capacitance difference between the first touch panel 201 and the second touch panel 202 is sampled and corrected. This means that the equivalent capacitance difference between the first touch panel 201 and the second touch panel 202 is corrected and reduced. After the correction is complete, the data is locked. After the coarse adjustment is complete, the equivalent capacitance difference can be reduced to a target range without a finger touching the touch panel. Alternatively, the target range can be half the maximum range of the fine adjustment.

[0051] Optionally, during the coarse adjustment phase, that is, the phase in which the coarse adjustment capacitor array 101 operates, the finger does not touch any key to prevent the introduction of calibration errors.

[0052] In the coarse adjustment stage, the fine adjustment capacitor array 102 does not work. After the coarse adjustment stage is completed, the fine adjustment capacitor array 102 starts to work.

[0053] Fine-tuning capacitor array 102 is connected to both first touch pad 201 and second touch pad 202. During the fine-tuning phase, comparator 104 continues to compare the voltage difference between first touch pad 201 and second touch pad 202. Based on the comparison result, comparator 104 generates a second comparison signal and outputs the second comparison signal to logic circuit 103. Logic circuit 103 generates a second control signal based on the second comparison signal to control the operation of fine-tuning capacitor array 102 based on the second control signal. In other words, logic circuit 103 logically controls fine-tuning capacitor array 102 to sample the equivalent capacitance difference remaining after coarse-tuning, i.e., the current equivalent capacitance difference between first touch pad 201 and second touch pad 202.

[0054] It is understandable that since the coarse adjustment has already been performed, the value of the equivalent capacitance difference that needs to be sampled in the fine adjustment stage is very small. Therefore, even if a very high sampling sensitivity is achieved, a very high number of bits is not required.

[0055] It should also be noted that, in the embodiment of the present application, the coarse adjustment capacitor array 101 can generally only operate once in a long period of time, because its purpose is only to adjust C S1 and C S2 The equivalent capacitance difference between the two can be corrected to a smaller range. No coarse adjustment is required for a long period of time. The reasons are as follows:

[0056] After the general system circuit is manufactured, due to the asymmetry of the wiring and the poor consistency of the manufacturing process, its inherent capacitance C S1 and C S2 It is not possible to do the same, but fortunately for a certain system circuit, under standard environment, C S1 and C S2 It is fixed and will not change. Although it changes with environmental factors such as temperature, humidity, time, etc., C S1 and C S2 The absolute value of will change, but the difference between the two will be small, and can be corrected using fine adjustment. Therefore, in the embodiment of the present application, the coarse adjustment capacitor array 101 can generally only be operated once when the system is turned on or after a fixed interval. The fixed interval can be, for example, a longer period of time, which can be set by the system default or customized by the user.

[0057] During the remaining time, the fine-tuning capacitor array 102 is mainly used to sample the current equivalent capacitance difference. In this way, since the maximum sampling range of the fine-tuning only needs to be 2 to 3 times larger than the minimum sensitivity of the coarse-tuning to perfectly cover the residual error after the coarse-tuning correction, a high sampling sensitivity can be achieved without a high number of bits.

[0058] In the embodiment of the present application, the fine-tuning capacitor array 102 is in a real-time working state, and is used to sample V S1and V S2 The small current equivalent capacitance difference between the two, that is, C caused by finger touch touch1 or C touch2 A small increase in capacitance.

[0059] By combining coarse adjustment with fine adjustment, you can S1 and C S2 On the basis of the large capacitance difference, it is possible to use fewer quantization bits to achieve higher sensitivity. Compared with the CDC that only uses a high-bit single loop, it has low power consumption and fast sampling speed.

[0060] In the above-mentioned capacitance detection circuit 100 and touch detection device, the capacitance detection circuit 100 is connected to the first touch panel 201 and the second touch panel 202 in the peripheral circuit 200; the capacitance detection circuit 100 includes a coarse adjustment capacitor array 101, a fine adjustment capacitor array 102, a logic circuit 103 and a comparator 104; the comparator 104 is used to compare the voltage difference between the first touch panel 201 and the second touch panel 202, generate a first comparison signal based on the comparison result, and output the first comparison signal to the logic circuit 103; the logic circuit 103 is used to generate a first control signal based on the first comparison signal , and controls the coarse tuning capacitor array 101 to operate according to the first control signal, so as to reduce the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 to a target range through the coarse tuning capacitor array 101; when the equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 is reduced to the target range, the logic circuit 103 is further used to obtain the second comparison signal generated by the comparator 104, generate a second control signal according to the second comparison signal, and control the fine tuning capacitor array 102 to sample the current equivalent capacitance difference between the first touch pad 201 and the second touch pad 202 according to the second control signal. In this way, based on the combination of coarse-tuning capacitor array 101 and fine-tuning capacitor array 102, the equivalent capacitance difference between first touch panel 201 and second touch panel 202 is first reduced to a target range through coarse-tuning capacitor array 101. Then, when fine-tuning capacitor array 102 samples the current equivalent capacitance difference between first touch panel 201 and second touch panel 202, the current equivalent capacitance difference to be sampled is very small. Therefore, sampling can be achieved with a smaller data bit width, reducing sampling time and improving the sensitivity of the detection process. Furthermore, since the equivalent capacitance difference between first touch panel 201 and second touch panel 202 has been reduced to the target range after coarse-tuning, the operating frequency of coarse-tuning capacitor array 101 is much lower than the operating frequency of fine-tuning capacitor array 102. Therefore, sampling is performed by fine-tuning capacitor array 102 most of the time, thereby effectively saving power consumption of capacitance detection circuit 100.

[0061] First, the generation of the first control signal by the logic circuit 103 and other arrangements of the peripheral circuit 200 will be described below.

[0062] In one embodiment, as shown in FIG2 , a schematic diagram of the structure of another capacitance detection circuit provided by an embodiment of the present application is shown. The peripheral circuit 200 also includes a first parasitic capacitance circuit 203 corresponding to the first touch panel 201 and a second parasitic capacitance circuit 204 corresponding to the second touch panel 202; the capacitance detection circuit 100 also includes a first bridge circuit 105 connected to the first touch panel 201 and a second bridge circuit 106 connected to the second touch panel 202; the coarse adjustment capacitor array 101 includes multiple first switch arrays; the first control signal includes M first single-bit signals; the logic circuit 103 is specifically configured to: control the first parasitic capacitance circuit 203, the second parasitic capacitance circuit 204, the first bridge circuit 105, and the second bridge circuit 106 to form a bridge according to a first clock signal CLKS input by an external controller, and based on successive approximation logic, sequentially obtain M first single-bit signals according to the first comparison signal, and sequentially control the operation of each first switch array in the coarse adjustment capacitor array 101 according to the M first single-bit signals; wherein the value of M is the same as the number of first switch arrays.

[0063] 2, the capacitor C in the first parasitic capacitor circuit 203 is S1 One end of the first touch panel 201 (V in FIG. 2 S1 The other end is connected to the circuit ground V SS The capacitor C in the second parasitic capacitance circuit 204 S2 One end of the second touch panel 202 (V in FIG. 2 S2 The other end is connected to the circuit ground V SS .

[0064] In the first bridge circuit 105, the bridge capacitor C F1 One end of the switch is connected to the first touch panel 201, and the other end is connected to the switch S2; the switch S2 is a single-pole double-throw switch, and its fixed end is connected to the reference voltage V REF1 and V SS In addition, one end of the switch S4 in the first bridge circuit 105 is connected to the first touch panel 201, and the other end is connected to V SS .

[0065] The second bridge circuit 106 includes a bridge capacitor C F2 One end of the switch is connected to the second touch panel 202, and the other end is connected to the switch S3; the switch S3 is a single-pole double-throw switch, and its fixed end is connected to the reference voltage V REF1 and V SS In addition, one end of the switch S5 in the second bridge circuit 106 is connected to the second touch panel 202, and the other end is connected to V SS .

[0066] Each switch in the first bridge circuit 105 and the second bridge circuit 106 is connected to the logic circuit 103 , and the logic circuit 103 may be connected to an external controller.

[0067] In the coarse adjustment stage, driven by the system slow clock CLKS, the logic circuit 103 generates a reset signal RESET with a narrow pulse width at the first rising edge of CLKS, thereby controlling S4 and S5 to close, and V S1 and V S2 Reset to V SS That is, the capacitor C S1 and C S2 The charge of S2 and S3 is cleared; and S2 and S3 are gated to V SS , that is, the bridge capacitance C F1 and C F2 The charge is cleared.

[0068] After a short time, the RESET signal is released, and then the logic circuit 103 controls S2 and S3 to be gated to V REF1 , that is, C F1 and C F2 Not with V S1 and V S2 Connect the plate to V REF1 connection; at this time, C F1 , C S1 , C F2 , C S2 Thus, assuming that C F1 =C F2 , the mismatch of the large capacitors on the chip is very small, and the small difference has little effect on the results, so, V S1 and V S2 Increase synchronously, V S1 and V S2 The difference is proportional to C S2 and C S1 Then, the logic circuit 103 can control the coarse tuning capacitor array 101 to operate and perform coarse tuning.

[0069] In the embodiment of the present application, the logic circuit 103 may be a successive approximation logic circuit. Thus, the logic circuit 103 may obtain M first single-bit signals D according to the first comparison signal based on the successive approximation logic. coar <M-1:0> , and sequentially controls the operation of each first switch array in the coarse tuning capacitor array 101 according to the M first single-bit signals. The value of M is the same as the number of first switch arrays, so that each first single-bit signal can control a corresponding first switch array.

[0070] The commonly used coarse adjustment method is to S1 and V S2A configurable switched capacitor array is arranged on both sides to ground. This method will introduce a large basic capacitance. The control signal controls the capacitance on both sides of the basic capacitance to increase or decrease. However, the basic capacitance introduced by it will cause the sensitivity of the entire CDC to deteriorate. Because its basic capacitance is equivalent to the parasitic capacitance C S1 or C S2 , and usually we hope that the parasitic capacitance is as small as possible, so as to obtain a larger V under the same finger touch capacitance. S1 and V S2 The change in the difference between , that is, to improve the sensitivity of the entire CDC.

[0071] In view of this, in an embodiment of the present application, during RESET, the logic circuit 103 incorporates the coarse adjustment capacitor array 101 into one of the first touch panel 201 and the second touch panel 202 to ensure that the sensitivity of the capacitance detection circuit 100 is high. Please refer to the structural diagram of another capacitance detection circuit shown in Figure 3. The capacitance detection circuit 100 includes a switch S1. The switch S1 is a single-pole double-throw switch, one end of which is connected to the coarse adjustment capacitor array 101, the other fixed end is connected to the first touch panel 201, and the other fixed end is connected to the second touch panel 202. In this way, during RESET, the logic circuit 103 controls S1 to connect to the first touch panel 201 or the second touch panel 202, so that the coarse adjustment capacitor array 101 is initially incorporated into V S1 or V S2 One of them.

[0072] Continuing with Figure 3, the following is a complete description of the process of a coarse adjustment:

[0073] During RESET, the control logic has already incorporated the coarse tuning capacitor array 101 into V S1 or V S2 In practical applications, its polarity can be switched. For analysis, it is assumed that the highest bit first single bit signal D coar <m-1>When it is equal to 1, the coarse adjustment capacitor array 101 is incorporated into V S1 ;D coar <m-1>When it is equal to 0, the coarse adjustment capacitor array 101 is incorporated into V S2 .

[0074] Assumption D coar <m-1>The initial value is 1, that is, the coarse adjustment capacitor array 101 is incorporated into V S1 , but all the trimming capacitors inside are disconnected, and only a small parasitic capacitance exists. In the remaining phase of CLKS, the comparator 104 compares V S1 and V S2 The voltage difference comparison result is obtained and a single-bit first comparison signal DAT is output. F1 =C F2 , if C S1 Less than C S2 , then V S1 Greater than V S2 , so DAT outputs logic 1; if C S1 Greater than C S2 , then V S1 Less than V S2 , so DAT outputs logic 0.

[0075] Then enter the second CLKS cycle, and its RESET process is the same as the first CLKS cycle. According to the DAT signal output before the end of the first CLKS, the logic circuit 103 generates the most significant first single-bit signal D coar <m-1>And output it to the corresponding first switch array, and in this cycle D coar <m-1>remains unchanged, that is, if DAT=1 is obtained before the end of the first cycle, then D coar <m-1>Still 1, the coarse adjustment capacitor array 101 is still connected to V S1 ; If DAT=0 before the end of the first cycle, D coar <m-1>Switching from 1 to 0, that is, the coarse adjustment capacitor array 101 switches to V S2 .

[0076] During the second CLKS period when RESET is not released, D coar <m-2>Set to 1, the highest order first switch array of the coarse adjustment capacitor array 101 is turned on, and the highest order coarse adjustment capacitor in the highest order first switch array is connected to the capacitor bridge, and its size is 2 M-2 C C . Among them C C It is the LSB (Least Significant Bit) of the coarse tuning capacitor.

[0077] Assumption D coar <m-1>If DAT is equal to 1 before the end of the CLKS cycle, it means that the S2 Small C S1 In parallel with a highest bit coarse adjustment capacitor 2 M-2 C C After that, it is still better than C S2 If it is small, then the highest bit coarse adjustment capacitor 2 is set in the next CLKS cycle. M-2 C C Should continue to access. If DAT is 0 before the end of the CLKS cycle, it means that the S2 Small C S1 In parallel with a highest bit coarse adjustment capacitor 2 M-2 C C After C S2 If it is too large, it indicates that the highest bit coarse adjustment capacitor should not be connected in the next CLKS cycle. Therefore, at the beginning of the next CLKS, the second highest bit first single bit signal D generated by the DAT signal coar <m-2>It will be delivered to its corresponding second highest first switch array and maintain the same polarity.

[0078] Assumption D coar <m-1>If DAT is equal to 0, and DAT is 1 before the end of the CLKS cycle, it means that the S1 Small C S2 In parallel with a highest bit coarse adjustment capacitor 2 M-2 C C After C S1 If DAT is 0 before the end of the CLKS cycle, it indicates that the highest capacitor should not be connected in the next CLKS cycle. S1 Small C S2 In parallel with a highest bit coarse adjustment capacitor 2 M-2 C C After C S1 If it is smaller, it means that the first single-bit signal D of the second highest bit should be inverted. coar <m-2>The signal is transmitted to the corresponding second highest bit first switch array.

[0079] Please refer to the second cycle for the third cycle process. Follow the above process until the last cycle, thus completing the coarse adjustment process and obtaining the corresponding M first single-bit signals D coar <m-1:0>Please refer to Figure 4, which shows a C S1 Less than C S2 Schematic diagram of some signal waveforms of the coarse adjustment correction process under the condition of , where EN_COAR is the enable signal of the coarse adjustment correction process.

[0080] It should be noted that after the system is powered on or at a set time, one or more coarse adjustment calibrations are performed. After a coarse adjustment calibration process is completed, coarse adjustment data is obtained and locked. That is, the control signal of the coarse adjustment capacitor array 101 is locked until the next coarse adjustment calibration begins. Optionally, except when the system is powered off, the system is in the fine adjustment calibration phase during all times except the coarse adjustment calibration phase.

[0081] The structure of the coarse tuning capacitor array 101 will be described below.

[0082] Please refer to FIG5 , which shows a schematic diagram of the structure of a coarse tuning capacitor array provided by an embodiment of the present application. The most significant first switch array in the coarse tuning capacitor array 101 includes two first switches, and the two first switches in the most significant first switch array are controlled by the most significant first single-bit signal D of the first control signal. coar <m-1>Control, wherein the control signal corresponding to the first switch can be used to identify the first switch, such as the two first switches -D in Figure 5 coar <m-1>and D coar <m-1>, where the sign indicates the polarity of the signal, -D coar <m-1>and D coar <m-1>The polarity is opposite, if D coar <m-1>Equal to 1, then -D coar <m-1>Equal to 0.

[0083] The other first switch arrays in the coarse adjustment capacitor array 101 respectively include two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are sequentially controlled by the other first single-bit signal of the first control signal. For example, in FIG5 , the second highest first switch array includes two first switches D coar <m-2>and -D coar <m-2>, including the fourth capacitor C M-2 The second lowest first switch array includes two first switches D coar <1> and -D coar <1> , including a fourth capacitor C1. The lowest first switch array includes two first switches D coar <0> and -D coar <0> , including a fourth capacitor C0.

[0084] In addition, as shown in FIG5 , one end of each other first switch array is grounded V SS The other end is connected to the highest first switch array, that is, connected to one end of the two first switches included in the highest first switch array. For each other first switch array, the fourth capacitor therein is connected to the first first switch therein (for example, -D coar <0> ) in parallel, and one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is connected to the second first switch (for example, D coar <0> ), and the other end of the second first switch is connected to the highest first switch array.

[0085] It should be noted that S1 in FIG. 5 is the same as S1 in FIG. 3 .

[0086] In addition, the coarse tuning capacitor array 101 is incorporated into V at the first CLKS. S1 After that, all the internal trimming capacitors are not turned on, which is equivalent to not connecting any capacitor to V S1 In actual circuits, this is impossible to achieve because the switch array has parasitic capacitance to ground, assuming it is C P Now let’s analyze C P Impact on circuit coarse adjustment correction:

[0087] If the system circuit is perfectly matched initially, C S2 =C S1 , C F1 =C F2 , then ideally after the bridge is released V S1 =V S2 At this time, due to C P The addition of V S1 The capacitance on the S2 , so DAT = 0 before the end of the first CLKS cycle. At the beginning of the second CLKS, the first switch array will be switched and merged into V S2 , then execute the above coarse adjustment process. However, at this time C P The addition of V S2 The capacitance on the S2 Therefore, the coarse adjustment capacitor array 101, which only increases the capacitance, can only obtain DAT of all 1s, that is, D coar <m-2:0>All are 0, that is, all the fourth capacitors are disconnected. The consequence is that after completing the entire coarse adjustment process, V S2 The capacitance on V S1 Big C P If C P Relatively large and exceeds the minimum step capacitance C for coarse adjustment C , the final coarse adjustment sensitivity depends on C P In reality, the worst case is not C S2 =C S1 , but C S2 with C S1 The absolute value of the difference is slightly smaller than C P When the coarse adjustment sensitivity can only reach 2C P .

[0088] In view of this, in the embodiment of the present application, an offset compensation capacitor circuit is added next to the coarse adjustment capacitor array 101. The offset compensation capacitor circuit solves the above problem by introducing an intentional mismatch. The explanation is as follows: If C S2 =C S1 , C F1 =C F2 , then at the first CLKS to V S1 Adding coarse tuning capacitor array 101 introduces parasitic capacitance C P At the same time, the switch capacitor C in the offset compensation capacitor circuit OS Merged into V S2 If you do C OS =C P , the parasitic capacitance is offset, which is the same as the ideal situation. In actual situations, it may not be possible to completely offset it. In this case, you can set C OS Greater than C P Since the coarse adjustment capacitor array 101 has the function of increasing capacitance but not reducing capacitance, C OS Greater than C P The coarse tuning capacitor array 101 will compensate for the excess part that is not offset during the coarse tuning stage.

[0089] In one embodiment, as shown in FIG6 , it shows a schematic diagram of the structure of another capacitance detection circuit provided by an embodiment of the present application. The capacitance detection circuit 100 further includes an offset compensation capacitance circuit 107 connected to a logic circuit 103; the logic circuit 103 is further configured to generate an offset compensation capacitance according to the highest bit of the first control signal (i.e., the highest bit first single-bit signal D coar <m-1>), controlling the offset compensation capacitor circuit 107 to connect to the first touch panel 201 or the second touch panel 202.

[0090] The offset compensation capacitor circuit 107 includes a third capacitor C OS The capacitance of the third capacitor is greater than or equal to the capacitance of the parasitic capacitance generated by the coarse adjustment capacitor array 101. Offset compensation capacitor circuit 107 further includes a second switch and a third switch. The third capacitor is connected in parallel with the second switch. One end of the third capacitor is grounded, and the other end of the third capacitor is connected to one end of the third switch. The third switch is connected to the first touch pad 201 or the second touch pad 202 under the control of the most significant bit of the first control signal.

[0091] When the offset compensation capacitor circuit 107 is connected to the first touch panel 201 and the second touch panel 202, the polarity of the highest-order first single-bit signal controlled by the second switch and the third switch is different. Please refer to Figures 7 and 8, which respectively show the structural schematic diagrams of an offset compensation capacitor circuit provided by an embodiment of the present application. Figure 7 shows the offset compensation capacitor circuit 107 connected to the first touch panel 201, wherein the second switch is controlled by D coar <m-1>Control, the third switch S0 is controlled by -D coar <m-1>FIG8 shows an offset compensation capacitor circuit 107 connected to the second touch panel 202, wherein the second switch is controlled by -D coar <m-1>Control, the third switch S0 is controlled by D coar <m-1>control.

[0092] After the above coarse adjustment is completed, D coar <m-1:0>The data is stored in the logic circuit 103 or an external controller connected to the logic circuit 103 and locked, and the coarse adjustment process is not performed for a long time afterwards. The specific time may depend on the user, and the remaining time is the fine adjustment process.

[0093] The following continues to describe the fine tuning capacitor array 102 and the fine tuning calibration process.

[0094] In one embodiment, as shown in FIG9 , a schematic diagram of another capacitance detection circuit provided by an embodiment of the present application is shown. The fine-tuning capacitor array 102 includes a first fine-tuning capacitor array 102a connected to the first touch pad 201 and a second fine-tuning capacitor array 102b connected to the second touch pad 202. The second control signal includes N second single-bit signals D fine <n-1:0>The first fine-tuning capacitor array 102a includes first capacitors connected to N second single-bit signals respectively. That is, each first capacitor is respectively connected to N second single-bit signals D fine <n-1:0>The second fine-tuning capacitor array 102b includes a second capacitor connected to N third single-bit signals opposite to the N second single-bit signals, that is, each second capacitor is respectively affected by the N third single-bit signal -D fine <n-1:0>FIG10 is a schematic diagram of the structure of a fine-tuning capacitor array provided in an embodiment of the present application.

[0095] The logic circuit 103 is specifically configured to sequentially obtain N second single-bit signals and generate N third single-bit signals according to the second comparison signal based on a successive approximation logic according to a second clock signal CLKF input from an external controller, and sequentially control each first capacitor to be connected to ground or to a power supply according to the N second single-bit signals, and sequentially control each second capacitor to be connected to ground or to a power supply according to the N third single-bit signals.

[0096] Referring to Figures 9 and 10, the process of a fine-tuning calibration is as follows:

[0097] Assume that the coarse tuning capacitor array 101 is incorporated into C S1 And with C S1 The equivalent capacitance after parallel connection is C S1 ， Assuming the finger is not touching, V S1 The capacitance is C S1 ， , V S2 The capacitance is C S2 N CLKF cycles correspond to one CLKS cycle.

[0098] At the initial stage of CLKS rising edge, a reset RESET narrow pulse signal is generated. The control logic clears the charge of all capacitors to zero during the RESET stage, including C touch1 , C touch2 , C F1 , C F2 , C S1 , C S2 The first capacitor C of the first fine-tuning capacitor array 102a in FIG. 10 11 ~C 1(N-1) N bit control signal D fine <n-1:0>All are 0, the second capacitor C of the second fine-tuning capacitor array 102b 21 ~C 2(N-1) N bit control signal -D fine <n-1:0>All are 0, only in the remaining phase D of RESET corresponding to the first CLKF fine <n-1:0>and -D fine <n-1:0>At the same time, it is 0, and D fine <n-1:0>and -D fine <n-1:0>Logically opposite signals that correspond one to one.

[0099] Then RESET is released, C F1 and C F2 The control switches S2 and S3 will C F1 , C F2 The corresponding plate voltage is switched to V REF1 , its specific implementation circuit is shown in Figure 10, where S2 corresponds to R STD Signal, which is 0 when RESET is 1. After RESET is released, it is V REF1 . V REF1 is the power supply voltage of the delay unit DL.

[0100] After RESET is released, V S1 and V S2 The voltage of C increases instantly. F1 、C S1 、C touch1 、C 11 ~C 1(N-1) and the coarse adjustment capacitor array 101 that may be connected constitute a capacitor voltage divider circuit; similarly, C F2 、C S2 、C touch2 、C 21 ~C 2(N-1) Together with the coarse adjustment capacitor array 101 that may be connected, a capacitor voltage divider circuit is formed.

[0101] Assumption C F1 =C F2 , but the coarse adjustment capacitor array 101 cannot completely offset C S1 and C S2 The difference before, and the finger can only touch one of the touchpads relatively, C touch1 Not equal to C touch2 , so V S1 Not equal to V S2 .

[0102] From the first CLKF rising edge to the end of the period, the second comparison signal output V S1 and V S2 The comparison value, if V S1 Greater than V S2 , then the logic circuit 103 outputs logic 1; if V S1 Less than V S2 , then the output is logic 0, and the signal is instantly transmitted to D in Figure 10 at the end of the clock. fine <n-1>and -D fine <n-1>The first capacitor and the second capacitor correspond respectively.

[0103] From the second CLKF rising edge to the end of the period, D fine <n-1>Keep the value sent at the end of the previous cycle, -D fine <n-1>Its logical opposite value. At this time, D fine <n-2:0>and -D fine <n-2:0>Or keep all 0. The DAT signal at the end of the second CLKF is sampled and sent to D fine <n-2>and -D fine <n-2>. And during the third CLKF period, D fine <n-2>and -D fine <n-2>The value of DAT remains unchanged. The third CLKF ends and samples the value of DAT and sends it to D fine <n-3>and -D fine <n-3>, and so on, and the DAT signal obtained at the end of the Nth CLKF clock corresponds to D fine <0> and -D fine <0> .

[0104] In one embodiment, as shown in FIG11 , a schematic diagram of the structure of another capacitance detection circuit provided by an embodiment of the present application is shown. A logic circuit 103 is connected to an external controller 300 ; the logic circuit 103 is specifically configured to output N second single-bit signals to the external controller 300 upon the termination of the second clock signal, so that the external controller 300 calculates the current equivalent capacitance difference based on the N second single-bit signals.

[0105] That is, the DAT signal obtained at the end of the Nth CLKF clock corresponds to D fine <0> and -D fine <0> After that, all D fine <n-1:0>, the logic circuit 103 converts the N second single-bit signals D fine <n-1:0>The signal is sent to the external controller 300. Optionally, the signal processing circuit of the external controller 300 can filter the signal and calculate the current equivalent capacitance difference. Optionally, the logic circuit 103 can also calculate the M first single-bit signals D coar <m-1:0>The data is sent to the external controller 300 for storage.

[0106] In addition, FIG. 12 shows an embodiment of the present application provided in V S1 The equivalent capacitance to ground is slightly smaller than V S2 The waveforms of the two fine-tuning calibration processes are shown in Figure 1. EN_FINE is the enable signal for fine-tuning calibration mode. CLKF is the N-divided frequency of CLKS.

[0107] In the embodiment of the present application, based on the fully differential structure, for V SS The common-mode interference on the circuit can be effectively filtered out; it is controlled by the system clock CLKF, which avoids the problem that the CDC with a ring oscillation structure will cause confusion in the sampling clock due to CS interference. Compared with the CDC with a capacitor sharing structure, the capacitance detection circuit in this application does not require a separate off-chip integration capacitor, and can work in parallel in multiple channels, which greatly improves the speed. It uses a coarse adjustment combined with fine adjustment. Most of the time, the coarse adjustment part does not work, and only the fine adjustment works. Therefore, it has high sensitivity and saves power consumption. In addition, the coarse adjustment structure uses a unilateral coarse adjustment form, which avoids the problem of increased parasitic capacitance caused by the bilateral coarse adjustment form, and at the same time adds an offset compensation structure to improve the coarse adjustment compensation sensitivity.

[0108] In one embodiment, the present application further provides a touch detection device. The touch detection device includes a peripheral circuit and a capacitance detection circuit as described in any of the above embodiments. The implementation solution provided by the touch detection device is similar to the implementation solution described in the above capacitance detection circuit. Therefore, the specific definition of the touch detection device can be found in the definition of the capacitance detection circuit above and will not be repeated here.

[0109] It is understandable that the above-mentioned coarse tuning capacitor array, fine tuning capacitor array, peripheral circuit and offset capacitor circuit can also adopt other forms, and are not limited to the forms mentioned in the above embodiments, as long as they can achieve the functions they need to achieve.

[0110] Throughout this specification, references to "some embodiments," "other embodiments," and the like indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, the illustrative descriptions of these terms do not necessarily refer to the same embodiment or example.

[0111] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A capacitance detection circuit, characterized in that: The capacitance detection circuit is connected to the first touch panel and the second touch panel in the peripheral circuit; the capacitance detection circuit includes a coarse adjustment capacitance array, a fine adjustment capacitance array, a logic circuit and a comparator; The comparator is used to compare the voltage difference between the first touch panel and the second touch panel, generate a first comparison signal according to the comparison result, and output the first comparison signal to the logic circuit; The logic circuit is used to generate a first control signal according to the first comparison signal, and control the coarse adjustment capacitor array to operate according to the first control signal, so as to reduce the equivalent capacitance difference between the first touch pad and the second touch pad to a target range through the coarse adjustment capacitor array; When the equivalent capacitance difference between the first touch pad and the second touch pad is reduced to the target range, the logic circuit is further used to obtain a second comparison signal generated by the comparator, generate a second control signal according to the second comparison signal, and control the fine-tuning capacitor array to sample the current equivalent capacitance difference between the first touch pad and the second touch pad according to the second control signal.

2. The capacitance detection circuit according to claim 1, characterized in that: The peripheral circuit also includes a first parasitic capacitance circuit corresponding to the first touch panel and a second parasitic capacitance circuit corresponding to the second touch panel; the capacitance detection circuit also includes a first bridge circuit connected to the first touch panel and a second bridge circuit connected to the second touch panel; the coarse adjustment capacitance array includes a plurality of first switch arrays; the first control signal includes M first single-bit signals; The logic circuit is specifically used for: According to a first clock signal input by an external controller, the first parasitic capacitance circuit, the second parasitic capacitance circuit, the first bridge circuit, and the second bridge circuit are controlled to form a bridge, and based on a successive approximation logic, M first single-bit signals are successively acquired according to the first comparison signal, and each first switch array in the coarse adjustment capacitor array is sequentially controlled to work according to the M first single-bit signals; The value of M is the same as the number of the first switch arrays.

3. The capacitance detection circuit according to claim 1, characterized in that: The second control signal includes N second single-bit signals; the fine-tuning capacitor array includes a first fine-tuning capacitor array connected to the first touch pad and a second fine-tuning capacitor array connected to the second touch pad; the first fine-tuning capacitor array includes first capacitors respectively connected to the N second single-bit signals; the second fine-tuning capacitor array includes second capacitors respectively connected to N third single-bit signals opposite to the N second single-bit signals; The logic circuit is specifically used for: According to the second clock signal input by the external controller, based on the successive approximation logic, the second comparison signal is successively Acquire N second single-bit signals and generate N third single-bit signals, control each of the first capacitors to be grounded or connected to a power supply in sequence according to the N second single-bit signals, and control each of the second capacitors to be grounded or connected to a power supply in sequence according to the N third single-bit signals.

4. The capacitance detection circuit according to claim 3, characterized in that: The logic circuit is connected to an external controller; the logic circuit is specifically used for: When the second clock signal ends, the N second single-bit signals are output to the external controller, so that the external controller calculates the current equivalent capacitance difference according to the N second single-bit signals.

5. The capacitance detection circuit according to claim 1, characterized in that: The capacitance detection circuit further includes an offset compensation capacitance circuit, and the offset compensation capacitance circuit is connected to the logic circuit; the logic circuit is further used for: According to the highest bit of the first control signal, the offset compensation capacitor circuit is controlled to be connected to the first touch panel or the second touch panel.

6. The capacitance detection circuit according to claim 5, characterized in that: The offset compensation capacitor circuit includes a third capacitor, and the capacitance value of the third capacitor is greater than or equal to the capacitance value of the parasitic capacitance generated by the coarse adjustment capacitor array.

7. The capacitance detection circuit according to claim 6, characterized in that: The offset compensation capacitor circuit also includes a second switch and a third switch, the third capacitor is connected in parallel with the second switch, one end of the third capacitor is grounded, and the other end of the third capacitor is connected to one end of the third switch, and the third switch is connected to the first touch pad or the second touch pad under the control of the highest bit of the first control signal.

8. The capacitance detection circuit according to claim 2, characterized in that: The highest-order first switch array in the coarse adjustment capacitor array includes two first switches, and the two first switches in the highest-order first switch array are controlled by the highest-order first single-bit signal of the first control signal; The other first switch arrays in the coarse adjustment capacitor array respectively include two first switches and a fourth capacitor, and the two first switches in the other first switch arrays are sequentially controlled by the other first single-bit signal of the first control signal.

9. The capacitance detection circuit according to claim 8, characterized in that: One end of each of the other first switch arrays is grounded, and the other end is connected to the highest first switch array; For each of the other first switch arrays, the fourth capacitor is connected in parallel with the first first switch in the other first switch array, and one end of the fourth capacitor is grounded, and the other end of the fourth capacitor is connected to the first end of the second first switch. The other end of the second first switch is connected to the highest first switch array.

10. A touch detection device, characterized in that: The touch detection device comprises the peripheral circuit as claimed in any one of claims 1 to 9 and the capacitance detection circuit as claimed in any one of claims 1 to 9.

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