CXL memory module, controller, method for accessing data and storage system

Abstract

A CXL memory module, a controller, a method for accessing data and a storage system, relating to the data storage technology. The CXL memory module comprises a controller and a group of memory chips connected to the controller, and the controller is provided with a CXL protocol-based KV interface. The controller is configured to receive a KV instruction sent by an external device by means of the KV interface, and store object-based data into the memory chips or take out the object-based data from the memory chips.

Description

CXL memory module and controller, data access method and storage system

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 28, 2023, with application number 202311264078.X and invention name “Method and controller for accessing data, CXL memory module and storage system”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, data storage technology, and more particularly to a CXL memory module and controller, a data access method, and a storage system. Background Art

[0003] The Compute Express Link (CXL) protocol is a memory interface protocol based on the PCIe (Peripheral Component Interconnect Express) physical layer. Based on the PCIe link, the CXL interface serves as an interface between the host and storage devices. It provides an efficient interconnect between the host CPU and NVMe SSDs (Non-Volatile Memory Express Solid State Drives), enabling fast data transfer and low-latency access.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a CXL memory module, including a controller and a group of memory chips connected to the controller. The controller has a KV (Key-Value) interface based on the CXL protocol. The controller is configured to receive KV instructions sent by an external device through the KV interface, store object-based data in the memory chip, or retrieve object-based data from the memory chip.

[0007] An embodiment of the present disclosure also provides a controller in a CXL memory module, comprising a processor, a cache, a CXL interface, and a memory interface. A KV interface based on the CXL protocol is constructed on top of the CXL interface. The processor is configured to perform the following data storage operations: receiving a data storage request sent by an external device through the KV interface, the data storage request carrying an identifier of a first object and information about the data of the first object; caching the data of the first object in the cache, assigning a memory address to the first object, and storing the data of the first object in a memory chip connected to the memory interface according to the memory address; and updating an address mapping table to record the correspondence between the identifier of the first object and the memory address.

[0008] .

[0009] An embodiment of the present disclosure also provides a method for accessing data, which is applied to a CXL memory module. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on the CXL protocol. The method includes: receiving a KV instruction sent by an external device through the KV interface, storing object-based data in the memory chip, or retrieving object-based data from the memory chip.

[0010] An embodiment of the present disclosure further provides a storage system, comprising a host and a CXL memory module as described in any embodiment of the present disclosure. The host communicates with the CXL memory module via a CXL interface to achieve discovery, configuration, and data transmission of the CXL memory module; and communicates with the CXL memory module via a KV interface constructed based on the CXL protocol to achieve object-based data access between the host and the CXL memory module.

[0011] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0012] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0013] Summary of the Figures

[0014] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0015] FIG1 is a schematic diagram of implementing KV storage based on a CXL memory module according to an embodiment of the present disclosure;

[0016] FIG2 is a hardware architecture diagram of an embodiment of the present disclosure for implementing KV storage based on a CXL memory module;

[0017] FIG3A is a flow chart of a method for accessing data according to an embodiment of the present disclosure;

[0018] FIG3B is a flow chart of a data storage method according to an embodiment of the present disclosure;

[0019] FIG4 is a flow chart of a method for obtaining data according to an embodiment of the present disclosure;

[0020] FIG5 is a schematic diagram of a method for implementing KV storage based on a CXL memory module according to an embodiment of the present disclosure applied to process code segment storage;

[0021] FIG6 is a module diagram of implementing KV storage based on a CXL memory module according to an embodiment of the present disclosure.

[0022] Details

[0023] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0024] The present disclosure describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that more embodiments and implementations may be included within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0025] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present application may also be combined with any conventional features or elements to form the scheme protected by the present disclosure. Any features or elements of any embodiment may also be combined with features or elements from other disclosed schemes to form the scheme protected by the present disclosure. Therefore, it should be understood that any feature shown and discussed in the present disclosure may be realized individually or in any appropriate combination. Therefore, except for the limitations made according to the protected technical solution and its equivalent replacements, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the protected technical solution.

[0026] In addition, when describing representative embodiments, the specification may have presented the method and process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described in the present disclosure, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the technical solutions protected by the present disclosure. In addition, the technical solutions for the method and process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.

[0027] In the era of big data, the amount of unstructured data is exploding. KV storage is a data storage method based on key-value pairs, which is suitable for storing unstructured data. KV represents a data item consisting of a unique key and an associated value. The key is generally used to identify a specific data item, while the value contains the actual data associated with the key. For example, a key may be a user's username, and the associated value may be the user's password, email address, or other related information. In this disclosure, the "key" in a key-value pair is referred to as the object's identifier, and the "value" in a key-value pair is referred to as the object's data. The KV storage (KV storing) interface (referred to as the KV interface) can use KV instructions including put, get, and delete. The put instruction is also referred to as a data save request in this disclosure, and the get instruction is also referred to as a data get request in this disclosure. Both the data save request and the data get request contain the object's identifier (i.e., the specified key value). KV instructions also include instructions for responding to a data save request (referred to as a data save response in this disclosure) and instructions for responding to a data get request (referred to as a data get response in this disclosure). In addition to the above basic instructions, different KV storage systems may use some other KV instructions.

[0028] Currently, KV-based memory applications (such as Redis) do not access data based on object identification, but rather through byte addressing. When the CPU reads or writes object data from or to memory, it operates on a cache line basis. A cache line is a fixed-length byte array, typically containing 64 or 128 bytes. This method of accessing data requires repeated memory accesses for larger objects, such as those with data volumes significantly larger than a page size (flash memory page size), increasing instruction interaction and resulting in lower efficiency. Furthermore, data is not compressed when stored in memory, or is transparently compressed outside the memory controller (MC), with software maintaining the mapping between addresses and compressed data, resulting in lower efficiency.

[0029] To this end, the embodiments of the present disclosure provide a KV storage method and corresponding device based on the CXL memory module. It can also use the KV-based hardware compression / decompression mechanism and interleaving access method to improve the efficiency of data access. The embodiments of the present disclosure can be applied to related applications based on KV memory access.

[0030] An embodiment of the present disclosure provides a CXL memory module, including a controller and a group of memory chips connected to the controller. The controller has a KV interface based on the CXL protocol. The controller is configured to receive KV instructions sent by an external device through the KV interface and store object-based data in the memory chips or retrieve object-based data from the memory chips.

[0031] The controller of the CXL memory module of the embodiment of the present disclosure is provided with a KV interface based on the CXL protocol, and KV-based data access operations are implemented between the external device and the CXL memory module. By carrying the object identifier (K ​​value) in the instruction, the data (V value) of the corresponding object can be accessed (stored or retrieved), enriching the data access method between the external device and the CXL memory module. Compared with the data access method based on cacheline, accessing the object data as a whole between the controller and the memory chip can improve storage efficiency. The external device of this embodiment can be a local host connected to the CXL memory module, or it can be a remote host or other processing device that can initiate data access. The present disclosure is not limited to this.

[0032] In an exemplary embodiment of the present disclosure, the controller stores object-based data in the memory chip, including: obtaining the original data of the object; compressing the original data of the object to obtain compressed data of the object; and writing the compressed data of the object to the memory chip. The controller retrieves the object-based data from the memory chip, including: reading the compressed data of the object stored in the memory chip; decompressing the compressed data of the object to obtain the original data of the object and transmitting it to an external device. This embodiment reduces storage space usage and speeds up storage through data compression.

[0033] FIG1 is a schematic diagram showing an embodiment of the present disclosure implementing KV storage based on a CXL memory module. The illustrated storage system includes a host 10 and a CXL memory module. The CXL memory module includes a CXL controller 20 and a memory chip connected thereto (i.e., the DRAM chip 30 in the figure). The CXL controller is referred to as the controller in the present disclosure and may also be referred to as a CXL memory controller (CXL Memory Controller). The CXL controller 20 can be physically implemented using a CXL chip but is not limited thereto. The CXL controller 20 is used to manage one or more memory chips connected thereto. For example, the CXL controller 20 can access the memory chip through an interleaving access instruction. The DRAM chip 30 is used as an example of a memory chip in the figure, but the present disclosure is not limited thereto. Other types of memory chips may also be used, such as SRAM (Static Random Access Memory), Flash memory, volatile random access memory (NVRAM, Non-Volatile Random Access Memory), etc. The CXL controller 20 and the memory chip may be separated and connected via various types of interfaces such as a PCIe interface. The CXL controller 20 and the memory chip may also be integrated together, such as on a PCB or a chip.

[0034] When the CXL controller 20 starts up, it establishes a communication link with the connected DRAM chip 30 and initializes the DRAM chip 30. During normal operation, the CXL controller 20 receives KV instructions (such as data store or data fetch requests) from external devices (such as a host or other device) and converts them into corresponding memory access operations. To improve memory access efficiency and performance, the CXL controller 20 buffers and pre-fetches data from the DRAM chip 30, reducing memory access latency and improving bandwidth utilization.

[0035] As shown in Figure 1, a host 10 (e.g., a CPU) can connect to a CXL controller 20 via a CXL interface, interacting with the CXL controller 20 of the CXL memory module based on the CXL input / output (CXL.io) protocol and the CXL memory protocol (CXL.mem). This embodiment also establishes a Key-Value (KV) interface based on the CXL.io protocol between the host 10 and the CXL controller 20, enabling the host 10 to interact with the CXL controller 20 using KV instructions, implementing object-based memory read and write operations. For accessing large object data (e.g., data larger than a single flash memory page (4KB / 16KB)), the host 10 uses fewer instructions to access the CXL memory module than when using byte addressing, reducing system latency and improving storage efficiency. Furthermore, when storing data, the CXL controller 20 can compress the object's data before storing it in the CXL memory module's DRAM chip 30. When retrieving data, the CXL controller 20 reads the object's compressed data from the DRAM chip 30, decompresses it, and then outputs it. Compared to the object's original data, the compressed data requires less access time and occupies less storage space, thereby improving data storage efficiency.

[0036] In one example of this embodiment, as shown in FIG6 , a KV interface based on the CXL protocol can be implemented by a KV interpreter 61 built on top of the CXL.io protocol layer (i.e., the CXL storage protocol layer) 62. Referring to FIG3 , the KV interpreter 61 is configured to extract a KV request encapsulated in a CXL.io instruction as data to be transmitted, parse the KV request, and encapsulate the KV response as data to be transmitted into the CXL.io instruction and send it. In another example, a KV interface based on the CXL protocol can be implemented by a KV interpreter built on top of the CXL.mem protocol layer. The KV interpreter is configured to extract a KV request encapsulated in a CXL.mem instruction as data to be transmitted, parse the KV request, and encapsulate the KV response as data to be transmitted into the CXL.mem instruction and send it, wherein the KV request includes a data storage request and a data retrieval request, and the KV response includes a data storage response and a data retrieval response. When building a KV interpreter on top of the CXL.mem protocol layer, when KV instructions are transmitted as data through CXL.mem instructions, CXL.io instructions can be used to assist in the transmission, such as indicating the start and end of data transmission.

[0037] In an exemplary embodiment of the present disclosure, the controller receives a KV instruction sent by an external device through the KV interface and stores object-based data into the memory chip, including: receiving a data storage request sent by an external device through the KV interface, the data storage request carrying an identifier of a first object and information about the data of the first object; caching the data of the first object, allocating a memory address to the first object, and writing the data of the first object into the memory chip according to the memory address; and updating the address mapping table to record the correspondence between the identifier of the first object and the memory address.

[0038] In this article, the "first object" can be any object whose data needs to be stored in the memory. It does not refer to a special object and can be used to distinguish it from other objects stored at the same time. The above-mentioned "external device" can be any device with memory reading and writing requirements, such as a host, graphics card, network adapter, embedded system, etc. In addition to being a DRAM chip, the above-mentioned "memory chip" can also be other types of memory chips, such as SRAM, FRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Meory), etc. "Object-based data" refers to V or the address of V in KV, and the store and fetch instructions contain K in KV, that is, the object identifier.

[0039] In an exemplary embodiment of the present disclosure, the controller receives a KV instruction sent by an external device through the KV interface, and retrieves object-based data from the memory chip, including: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carrying an identifier of the first object; finding a memory address corresponding to the identifier of the first object from the address mapping table, and reading the data of the first object from the memory chip according to the memory address; and transmitting the data of the first object to the outside.

[0040] The CXL memory module of the disclosed embodiment has built a KV interface (also known as a KV storage interface) based on the CXL protocol on the original CXL interface. The controller can receive KV instructions sent by external devices through the KV interface. If a data storage request is received, the data of the object is cached and a memory address is allocated. The data of the object is stored in the memory chip according to the memory address, and the correspondence between the object's identifier and the memory address allocated for the object is recorded, so as to facilitate reading the stored data according to the object's identifier. If a data retrieval request is received, the memory address corresponding to the object's identifier is found, and the data of the object is read from the memory chip and cached and output. The CXL memory module of this embodiment implements KV-based data access. External devices (such as a host) can access the CXL memory module to perform object access operations on unstructured data. The amount of data accessed at one time is not limited by the amount of cacheline data. Data access to one or more objects only requires sending a request instruction and receiving a response instruction, which can reduce the number of instructions required for access and improve data storage efficiency.

[0041] Some technologies do not compress data when storing data in memory. Other technologies perform compression outside the storage controller, and the overall efficiency of the storage system is low. However, in the embodiment of the present disclosure, for KV objects, the CXL memory module can complete data compression before storing the object's data, and when reading the object's data, the data is decompressed and then output, that is, transparent compression is completed in the CXL memory module. After the data is compressed, the amount of data becomes smaller, the storage space occupied is less, the writing speed is fast, and the external software does not need to maintain the mapping between the compressed data and the address, which will not bring a burden to the external device, which is conducive to improving the overall efficiency of the storage system.

[0042] In embodiments where object data is compressed and decompressed, the cached, uncompressed data of the first object is referred to as the raw data of the first object, to distinguish it from the compressed data of the first object (i.e., the compressed data of the first object). The buffer within the cache used to cache data to be written to the memory chip is referred to as the first buffer, and the buffer within the cache used to cache data read from the memory chip is referred to as the second buffer. The data of an object read from a source address by the CXL memory module controller, or the data of an object parsed from a data storage request, before being compressed, is referred to as the raw data of the object. The raw data may be data processed by an external device such as a host.

[0043] In an exemplary embodiment of the present disclosure, the controller caches the data of the first object, including: caching the original data of the first object in a first buffer; the controller is also configured to: when it is determined that the cached original data of the first object is data to be compressed, compress the original data of the first object using the following multi-object compression method: judge whether the total amount of cached data to be compressed in the first buffer is greater than or equal to a set first threshold: when the total amount of cached data to be compressed is greater than or equal to the first threshold, record the offset of the original data of each object in the cached data to be compressed, compress the cached data to be compressed, and obtain compressed data to be stored; when the total amount of cached data to be compressed is less than the first threshold, when the original data of a new object is added, so that the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, record the offset of the original data of each object in the cached data to be compressed, compress the cached data to be compressed, and obtain compressed data to be stored.

[0044] In an example of this embodiment, there are three objects in the cached data to be compressed, the data size of the original data of the first object is 1KB, the data size of the original data of the second object is 3KB, and the data size of the original data of the third object is 7KB. Then the offset of the original data of the first object is 0, the offset of the original data of the second object is 1KB, and the offset of the original data of the third object is 4KB.

[0045] In one example of this embodiment, the first threshold can be determined based on the size of the first buffer. For example, the first threshold is not less than 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, or 256KB. When determining the first threshold based on the size of the first buffer, the larger the space in the first buffer, the larger the first threshold can be set, but still smaller than the size of the first buffer. The larger the first threshold is set, the more data is compressed at one time, and the compression efficiency is improved.

[0046] The CXL memory module of this embodiment supports a multi-object compression mode. In the multi-object compression mode, when the total amount of raw data of multiple cached objects reaches a first threshold, the raw data of multiple cached objects can be compressed as a whole to obtain compressed data to be stored. However, in the multi-object compression mode, it is not necessary to compress the raw data of multiple objects together, and compression of the raw data of a single object is also allowed. For example, when the amount of raw data of a single object is greater than or equal to the first threshold and less than the size of the first buffer, even if the multi-object compression mode is adopted, the raw data of the object is compressed separately; and when the amount of raw data of the object is greater than or equal to the size of the first buffer, the raw data of the object can be compressed multiple times in batches.

[0047] In one example of this embodiment, a multi-object compression method is used for all objects, and the cached data to be compressed includes the original data of all cached objects. The controller directly determines the cached original data of the first object as the data to be compressed, that is, the original data of all objects to be written to the memory chip in this example need to be compressed. In another example of this embodiment, a multi-object compression method is used only for specified objects. In this case, the cached data to be compressed only includes the original data of the cached specified object. The controller determines the cached original data of the first object as the data to be compressed only when the first object is the specified object; wherein, the specified object is an object whose original data volume is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

[0048] The following examples illustrate the multi-object compression method:

[0049] In one example, a controller compresses all objects, regardless of their data size. The cached data to be compressed includes the cached raw data of all objects. Assume that the raw data of the first object is 4KB, the raw data of the second object previously cached in the first buffer is 12KB, and the first threshold is 16KB. Since all objects' raw data is data to be compressed, after caching the raw data of the first object, the total amount of cached data to be compressed in the first buffer reaches 16KB, equal to the first threshold. At this point, the offset of the first object's raw data in the cached data to be compressed is recorded as 12KB. The offset of the second object's raw data in the cached data to be compressed is 0KB. This 16KB of cached data to be compressed is compressed as a whole to obtain compressed data to be stored. Assuming a compression rate of 50%, the amount of compressed data to be stored is 8KB. When the controller retrieves data, whether for the first or second object, it first retrieves the compressed data to be stored, decompresses it to obtain the cached data to be compressed, and then extracts the raw data of the first or second object from it, depending on the encoding.

[0050] In another example, the first threshold is 32KB, and other conditions are the same as the previous example. After the first buffer caches the original data of the first object, the total amount of cached data to be compressed is 16KB, which is less than the first threshold. At this point, the system waits for new object data to be added. When new object data is added, bringing the total amount of cached data to be compressed in the first buffer to greater than or equal to 32KB, the offset of the original data of each object in the cached data to be compressed is recorded, and the cached data to be compressed is compressed as a whole.

[0051] In another example, only the original data of the designated object is compressed. For example, the object is a designated object only when the data of the object is greater than or equal to 1KB. Assume again that the amount of the original data of the first object is 4KB, and the first buffer previously cached 11.5KB of the original data of the second object and 0.5KB of the original data of the third object, and the first threshold is 16KB. At this time, although the total amount of cached data has reached the first threshold of 16KB, the original data of the third object is less than 1KB and is not a designated object, so the cached data to be compressed is only 15.5KB. It is necessary to continue waiting for the data of new objects to be added so that the total amount of cached data to be compressed in the first buffer reaches 16KB, and then record the offset of the original data of each object in the cached data to be compressed, and compress the cached data to be compressed as a whole. It should be noted that the designated objects and non-designated objects can be stored in partitions in the first buffer, and the total amount of cached original data of the designated objects can be counted in real time. In this example, the cached data includes the original data of the designated objects and the original data of the non-designated objects, and the cached data to be compressed only includes the original data of the designated objects.

[0052] In this embodiment, the controller compresses the original data of one or more objects contained in the cached data to be compressed after reaching a set first threshold. This fully utilizes the buffer space and improves the compression effect. The setting of the first threshold ensures that the compressed data to be stored after each compression is not too small. When stored in memory, it can be divided into multiple data blocks and stored in parallel in the memory chip using an interleaved method. This fully utilizes the channel between the controller and the memory chip, allowing more data to be stored at once, thereby reducing the number of storage medium accesses and improving system efficiency.

[0053] In an example of this embodiment, when the original data of the first object is compressed using a multi-object compression method, the controller allocates a memory address to the first object, and writes the data of the first object into the memory chip according to the memory address, which may include: dividing the compressed data to be stored into multiple data blocks, the compressed data of the first object being located in at least one of the data blocks; allocating memory addresses of different memory areas in the same interleaved area to different data blocks among the multiple data blocks, and using the memory addresses allocated to the multiple data blocks as memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; and writing the multiple data blocks into their respective corresponding memory areas in an interleaved access manner according to the memory addresses allocated to the multiple data blocks; wherein, an interleaved area includes one or more memory areas in the flash memory chip.

[0054] In memory chips such as DRAM, internal data access can adopt an interleaving access method. The interleaving access method divides the continuous memory address space of a flash memory chip into multiple interleave areas, and each interleave area contains multiple memory areas (Banks). Interleaving access is to evenly distribute data to multiple banks, each bank stores a part of the data, and the system can access data from multiple banks in parallel, thereby improving the efficiency of memory access. For example, a storage system has 4 banks and adopts a 2-way interleaving method, then the memory address space is divided into two interleave areas, each interleave area contains 2 banks. The system can access multiple banks in the same interleave area at the same time. The embodiment of the present disclosure extends the interleaving method to multiple flash memory chips, and an interleave area can contain banks in multiple flash memory chips to simultaneously utilize the parallel read and write capabilities of multiple DRAM chips to improve storage performance and throughput.

[0055] To store compressed data to be stored in memory chips using an interleaving approach, the data must first be striped. The specific striping operation can vary depending on the storage architecture and algorithm. For example, during striping, data blocks can be distributed across as many available storage devices as possible to achieve optimal performance and load balancing. After the compressed data to be stored is divided into multiple consecutive data blocks (with the size of all data blocks except the last one equal to a set value), different banks can be selected for different data blocks using round-robin selection, hash functions, or other algorithms to minimize conflicts and improve concurrency. In one example, the controller creates a continuous memory address space based on the storage space of all connected memory chips for allocation, where each memory address corresponds to an actual physical address (identified by the memory chip ID, bank ID, row ID, and column ID). When allocating memory addresses within the same interleaved region to different data blocks from this created memory address space, a starting address can be assigned to the first data block. An offset value can be added to this starting address to assign it to the second data block. Two offset values ​​can be added to this starting address to assign it to the third data block, and so on. In this way, there is no need to separately record the memory address allocated for each data block. The memory addresses allocated for all data blocks can be obtained based on the memory address allocated for the first data block, the set offset value and the allocation order.

[0056] The multi-object compression method supported by this embodiment can compress data of multiple objects together. Accordingly, the size of the divided data blocks can be set to be relatively large, thereby achieving higher access efficiency.

[0057] In an exemplary embodiment of the present disclosure, the controller may compress only the raw data of a designated object and not compress non-designated objects. The controller is further configured to, when the cached data to be compressed only includes the cached raw data of a designated object and the first object is not a designated object, allocate a memory address to the first object in the following manner, and write the data of the first object to the memory chip according to the memory address: without compressing the raw data of the first object, directly allocate a memory address to the first object based on the raw data of the first object, and write the raw data of the first object to the memory chip according to the allocated memory address.

[0058] This embodiment takes into account that if an object's data size is relatively small (e.g., less than 1KB), and if this object is compressed together with other objects, data retrieval requires reading the compressed data of all the objects compressed together (i.e., the compressed data to be stored), decompressing it, and caching it, reducing data retrieval efficiency. Therefore, this embodiment divides objects into two types based on their size: designated objects and non-designated objects. For designated objects (larger objects), their data is compressed using a multi-object compression method and then stored in the DRAM chip. For non-designated objects (smaller objects), a memory address is assigned to the object's raw data and stored directly in the DRAM chip. This allows the raw data of the non-designated object to be read from the DRAM chip according to the assigned memory address and cached in a second buffer, eliminating the need to read data from other unneeded objects or decompress the read data, thereby improving data retrieval efficiency. Furthermore, smaller objects occupy less storage space and require fewer writes, so directly storing them in the DRAM chip has a minimal impact on data storage efficiency. By treating different objects differently, this embodiment improves the overall performance of the storage system.

[0059] In another exemplary embodiment of the present disclosure, the controller can only compress the original data of the designated object. For non-designated objects, there are two cases: one is not compressed, and the other is compressed using a single-object compression method. The controller of this embodiment is also configured to allocate a memory address to the first object in the following manner when the cached data to be compressed only includes the original data of the cached designated object, and the first object is not a designated object, and write the data of the first object into the memory chip according to the memory address: first determine whether the amount of the original data of the first object is greater than or equal to a set third threshold, and the third threshold is less than the second threshold; when the amount of the original data of the first object is greater than or equal to the third threshold, use a single-object compression method to compress the original data of the first object separately, allocate a memory address to the first object according to the compressed data of the first object, and write the compressed data of the first object into the memory chip according to the allocated memory address; when the amount of the original data of the first object is less than the third threshold, do not compress the original data of the first object, allocate a memory address to the first object according to the original data of the first object, and write the original data of the first object into the memory chip according to the allocated memory address.

[0060] This embodiment performs a detailed processing based on the distinction between the two objects. When it is determined that the first object is not a specified object, the data storage processing is divided into two cases. That is, this embodiment divides objects into three types according to the size of the original data of the object:

[0061] For objects whose data size is less than a third threshold (e.g., 32 bytes, 64 bytes, 128 bytes, etc.) (referred to as small objects), compression is not performed and their original data is written directly to the memory chip. Without compressing the original data of the object, the original data of one small object can be written at a time, or the original data of multiple small objects can be stored together in the memory chip when the cached data of multiple small objects reaches a set fourth threshold (the fourth threshold is less than the second threshold and greater than the third threshold);

[0062] For objects with a data size greater than or equal to a third threshold and less than a second threshold (e.g., 512 bytes, 1KB, 2KB, etc.) (intermediate-sized objects), a single-object compression method is used, where the original data of a single object is compressed and then stored in the memory chip. The compressed data of a single object can also be stored in the memory chip using an interleaving method. For example, the compressed data of the object is first divided into multiple data blocks, and memory addresses in different banks of the same interleaving area are assigned to each of the multiple data blocks. The multiple data blocks are then stored in parallel in the memory chip using an interleaving method based on the assigned addresses.

[0063] For objects whose data volume is greater than or equal to the second threshold (called large objects), a multi-object compression method is used. When the data volume of the large object is less than the first threshold (such as 4KB, 8KB, 16KB, etc.), it is compressed together with the original data of other objects and stored in the memory chip; when the original data of the large object is greater than or equal to the first threshold, the large object can be compressed separately, which is a case where separate compression is required under the multi-object compression method.

[0064] To record the compression method used for a particular object, the object's metadata can be searched to obtain the amount of the object's original data, and the compression method of the object can be determined based on this amount. Alternatively, a compression method flag can be added to each object locally (e.g., in a mapping table) to indicate the compression method used for the object. The compression method can include at least two of the following three methods: no compression, single-object compression, and multi-object compression.

[0065] This embodiment adds a single-object compression method for objects of intermediate size. This reduces the amount of compressed data when storing, resulting in faster storage and less space usage. When retrieving data, the compressed data for this object can be retrieved separately, decompressed, and cached, eliminating the need to read data from other objects. This embodiment distinguishes between three different object processing methods, further improving overall storage system performance by, for example, achieving a better balance between data storage and retrieval speeds.

[0066] In another exemplary embodiment of the present disclosure, different from the aforementioned embodiment, a multi-object compression method is used for designated objects (larger objects), and a single-object compression method is used for non-designated objects. Whether the object belongs to a designated object or a non-designated object can be determined by comparing the data volume of the object's original data with a set second threshold.

[0067] In an exemplary embodiment of the present disclosure, the information of the data of the first object may include the data volume and source address of the original data of the first object; the controller caches the data of the first object, including: parsing the storage data request to obtain the data volume and source address, reading the original data of the first object from the outside according to the data volume and source address and caching it in a first buffer; or, the information of the data of the first object includes the original data of the first object; the controller caches the data of the first object, including: parsing the storage data request to obtain the original data of the first object, and caching the original data of the first object in the first buffer.

[0068] That is, the data of the object to be stored in the memory can be directly carried in the data storage request, or the object data can be first stored in an external memory (such as the cache or other memory used by the host). When the object data needs to be stored in the memory, the external device carries the current external address of the object data as the source address in the data storage request sent, and the CXL controller can read the data from the source address and write it to the first buffer.

[0069] External devices can choose which data transmission method to use based on a set data volume threshold. For example, when the object's data volume is less than the set data volume threshold, the object's data can be directly included in the data storage request. This transmission method simplifies operations, saves bandwidth, and can speed up storage and reduce latency in scenarios with many small objects. When the object's data volume is greater than or equal to the data volume threshold, the data's source address can be included in the data storage request. If the first buffer can cache all data, the CXL controller can read all the object's data from the external device at once and store it in the first buffer. If the first buffer lacks space, the controller can also read the object's data in multiple batches, each time reading and caching a portion of the data, writing this portion of data to the memory, and then performing the next read.

[0070] In an exemplary embodiment of the present disclosure, the controller is further configured to: after receiving a data storage request sent by an external device, extract the metadata of the first object from the data storage request, the metadata of the first object including the identifier and data volume of the first object; and, through the memory interface, save the metadata of the first object to the storage space created for the metadata of the object in the memory chip. The metadata of the object may also include the creation time, modification time, etc. of the object. The storage space created for the metadata of the object may be a space allocated in the DRAM chip (or called reserved space), and the storage of metadata may be optimized by constructing a linked list, using a multi-level directory, etc. Although the present embodiment stores the metadata of the object in DRAM, in other embodiments, the metadata of the object may also be stored in the buffer of the controller, for example, it may be stored together with the address mapping table that needs to be updated when storing data, or it may be stored separately in the cache of the controller or in the space allocated in the memory chip.

[0071] In an exemplary embodiment of the present disclosure, when the original data of the first object is compressed using a multi-object compression method, the controller receives a KV instruction sent by an external device through the KV interface, and retrieves the object-based data from the memory chip, including: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carries the identifier of the first object; searching the address mapping table according to the identifier of the first object, and finding the memory address allocated to the multiple data blocks into which the compressed data to be stored is divided; reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into the compressed data to be stored, decompressing the compressed data to be stored, obtaining the cached data to be compressed and caching it in a second buffer; extracting the original data of the first object from the cached data to be compressed according to the data volume of the original data of the first object and the offset in the cached data to be compressed, and transmitting part or all of the original data of the first object to the outside.

[0072] Taking the case where the first object is a designated object as an example, the compressed data to be stored may include compressed data of one or more objects. If the compressed data includes multiple objects (including the first object), the memory address where the compressed data of each object is located is not recorded. Instead, the memory addresses allocated to the multiple data blocks into which the compressed data to be stored are used as the memory addresses uniformly allocated to the multiple objects. When recording the correspondence between the identifier of the first object and the memory address allocated to the first object in the address mapping table, the correspondence between the identifier of the first object and the uniformly allocated memory address is also recorded. In this case, the identifiers of the multiple objects in the address mapping table all correspond to the uniformly allocated memory addresses. When reading the data of any of the multiple objects, the uniformly allocated memory address can be found from the address mapping table based on the identifier of the object. Based on the memory address, multiple data blocks are read from the memory chip and spliced ​​into the original compressed data to be stored in the original order. After decompressing the compressed data to be stored, the original data of the multiple objects arranged in the original order can be obtained, that is, the cached data to be compressed that includes the original data of the first object when storing the data. The cached data to be compressed is cached in the second buffer. Then, based on the offset of the original data of the first object in the cached data to be compressed and the amount of the original data of the object recorded when the data is stored, the original data of the object can be extracted from the cached data to be compressed.

[0073] The amount of raw data of the first object can be obtained by parsing the data storage request. The second buffer and the first buffer cache data to be written and read, respectively, and can be buffers in the same buffer or buffers in different buffers. Multiple buffers belonging to the same buffer can be divided according to the configuration information of the buffer. The buffer can use SRAM (Static Random Access Memory), but is not limited to this.

[0074] In another exemplary embodiment of the present disclosure, without compressing the original data of the first object, the controller receives a KV instruction sent by an external device through the KV interface, and retrieves the object-based data from the memory chip, including: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carrying an identifier of the first object; finding a memory address corresponding to the identifier of the first object from the address mapping table, reading the original data of the first object from the memory chip according to the found memory address, and caching the original data of the first object in a second buffer; transmitting part or all of the original data of the first object to the outside.

[0075] In this embodiment, for objects that are not compressed when storing data, the original data of the object can be directly read from the memory chip according to the memory address, cached, and then transmitted to the outside.

[0076] In another exemplary embodiment of the present disclosure, when the original data of the first object is compressed using a single-object compression method, the controller receives a KV instruction sent by an external device through the KV interface, and retrieves the object-based data from the memory chip, including: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carrying an identifier of the first object; finding the memory address corresponding to the identifier of the first object from the address mapping table, reading the compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; decompressing the compressed data of the first object to obtain the original data of the first object, and transmitting part or all of the original data of the first object to the outside.

[0077] In this embodiment, for objects that use a single-object compression method when storing data, the compressed data of the object can be read from the memory chip according to the memory address and cached, and the original data of the object can be obtained after decompression and transmitted to the outside.

[0078] In an exemplary embodiment of the present disclosure, the data retrieval request also carries information about the amount of data to be retrieved and the offset of the data to be retrieved within the original data of the first object. The controller externally transmits a portion of the original data of the first object, including extracting the data to be retrieved from the original data of the first object based on the amount and offset information, and externally transmitting the data to be retrieved. This embodiment supports partial data retrieval from an object, provides greater flexibility, and improves the overall performance of the storage system.

[0079] In an exemplary embodiment of the present disclosure, the controller transmits part or all of the original data of the first object to the outside, including: carrying part or all of the original data of the first object in a data retrieval response and sending it to the external device; or, the data retrieval request also carries information of an external address for storing the retrieved data, that is, the external device specifies the storage space to which the retrieved data is to be saved, and the controller transmits part or all of the original data of the first object to the outside, including: writing part or all of the original data of the first object to the storage space corresponding to the external address. Of these two ways of transmitting the read data to the outside, the first way (carrying the data in the data retrieval response) can utilize the data response to achieve fast transmission of small objects. The second way can support the transmission of larger data blocks.

[0080] The above-mentioned embodiments of the present disclosure implement KV-based data access based on the CXL memory module. They can also utilize KV-based hardware compression / decompression mechanisms and interleaving access methods to achieve better storage efficiency. They can be applied to applications related to KV memory access.

[0081] An embodiment of the present disclosure provides a controller in a CXL memory module, as shown in FIG2 , including a processor 21, a cache 24, a CXL interface 22, and a memory interface 26, wherein a KV interface 23 based on the CXL protocol is constructed on the CXL interface. The processor 21 can be connected to each interface and buffer via a bus. The processor 21 is configured to perform the following data storage operations: receiving a data storage request sent by an external device (such as a host 10) through the KV interface 23, wherein the data storage request carries the identifier of the first object and information about the data of the first object; caching the data of the first object in the cache 24, assigning a memory address to the first object, and storing the data of the first object in the memory chip 30 connected to the memory interface 26 according to the memory address; and updating the address mapping table to record the correspondence between the identifier of the first object and the memory address.

[0082] After receiving the data storage request and caching the data of the first object in the buffer 24, the processor 21 can return a data storage response to the external device without waiting for the data to be written into the memory chip.

[0083] The processor 21 in the controller 20 of this embodiment can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc., or other conventional processors; the processor can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), discrete logic or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; or a combination of the above devices. That is, the processor of the above embodiment can be any processing device or device combination that implements the various methods, steps and logic block diagrams in the embodiments of the present disclosure. If the embodiments of the present disclosure are partially implemented in software, the instructions for the software can be stored in a suitable non-volatile computer-readable storage medium, and one or more processors can be used to execute the instructions in hardware to implement the methods of the embodiments of the present disclosure.

[0084] In an exemplary embodiment of the present disclosure, the processor 21 is also configured to perform the following data retrieval operations: receiving a data retrieval request sent by an external device through the KV interface 23, the data retrieval request carrying the identifier of the first object; finding the memory address corresponding to the identifier of the first object from the address mapping table, and reading the data of the first object from the memory chip 30 according to the memory address; and transmitting the data of the first object to the outside.

[0085] In one example of this embodiment, referring to Figures 2 and 6 , a KV interface based on the CXL protocol can be implemented using a KV interpreter 61 built on top of the CXL.io protocol layer 62. The KV interpreter 61 is configured to extract KV requests encapsulated in CXL.io instructions, parse the KV requests, and encapsulate the KV responses into CXL.io instructions and send them. The KV requests include data storage requests and data retrieval requests, and the KV responses include data storage responses and data retrieval responses. In another example, the KV interface based on the CXL protocol can be implemented using a KV interpreter 61 built on top of the CXL.io protocol layer 62 and the CXL.mem protocol layer 62, or a KV interpreter 61 built on top of the CXL.mem protocol layer 62. The KV interpreter 61 is configured to extract KV requests encapsulated in CXL.mem instructions, parse the KV requests, and encapsulate the KV responses into CXL.mem instructions and send them. In this embodiment, the KV request and KV response can be encapsulated as data to be transmitted in CXL.io instructions or CXL.mem instructions. The KV interpreter 61 in the CXL memory module and the CPU can identify and parse the KV instruction according to the set KV instruction data format.

[0086] This embodiment uses KV storage to store object data in large blocks (e.g., data volume larger than that of one flash memory page), thereby fully utilizing the interleaving access method of multiple memory chips and improving system bandwidth.

[0087] In an exemplary embodiment of the present disclosure, the processor caches data of the first object, including: caching original data of the first object in a first buffer of the cache; the controller further includes a compression engine 25, and the processor is further configured to: when determining that the cached original data of the first object is data to be compressed, use the compression engine to compress the original data of the first object using the following multi-object compression method: determine whether the total amount of cached data to be compressed in the first buffer is greater than or equal to a set first threshold; if the total amount of cached data to be compressed is greater than or equal to the first threshold, record the offset of the original data of each object in the cached data to be compressed, and compress the cached data to be compressed to obtain compressed data to be stored;

[0088] When the total amount of cached data to be compressed is less than the first threshold, when the original data of a new object is added, so that the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, the offset of the original data of each object in the cached data to be compressed is recorded, and the cached data to be compressed is compressed to obtain the compressed data to be stored.

[0089] In an example of this embodiment, when the original data of the first object is compressed using a multi-object compression method, the processor allocates a memory address to the first object, and stores the data of the first object into the memory chip connected to the memory interface according to the memory address, including: dividing the compressed data to be stored into multiple data blocks, and the compressed data of the first object is located in at least one of the data blocks; allocating memory addresses of different memory areas in the same interleaved area to different data blocks among the multiple data blocks, and using the memory addresses allocated to the multiple data blocks as the memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; according to the memory addresses allocated to the multiple data blocks, the multiple data blocks are respectively written into their respective corresponding memory areas in an interleaved access manner; wherein, an interleaved area includes one or more memory areas in the flash memory chip.

[0090] In an example of this embodiment, the first threshold may be determined according to the size of the first buffer, and the first threshold is not less than 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB.

[0091] In an example of this embodiment, the cached data to be compressed includes the original data of all cached objects, and the processor directly determines the cached original data of the first object as the data to be compressed; or, the cached data to be compressed only includes the original data of the cached specified object, and the processor determines that the cached original data of the first object is the data to be compressed only when the first object is the specified object; wherein, the specified object is an object whose original data volume is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

[0092] In an exemplary embodiment of the present disclosure, the processor is further configured to: when the cached data to be compressed includes only cached raw data of a designated object and the first object is not the designated object, allocate a memory address to the first object in the following manner, and store the data of the first object into a memory chip connected to the memory interface according to the memory address: without compressing the raw data of the first object, directly allocate a memory address to the first object based on the raw data of the first object, and write the raw data of the first object into the memory chip according to the allocated memory address; or, first determine whether the amount of the raw data of the first object is greater than or equal to a set third threshold, where the third threshold is less than the second threshold; if the amount of the raw data of the first object is greater than or equal to the third threshold, compress the raw data of the first object separately using a single-object compression method, allocate a memory address to the first object based on the compressed data of the first object, and write the compressed data of the first object into the memory chip according to the allocated memory address; if the amount of the raw data of the first object is less than the third threshold, not compress the raw data of the first object, allocate a memory address to the first object based on the raw data of the first object, and write the raw data of the first object into the memory chip according to the allocated memory address.

[0093] In an exemplary embodiment of the present disclosure, the information about the data of the first object may include the data volume and source address of the original data of the first object; the processor caches the data of the first object, including: parsing the storage data request to obtain the data volume and source address, reading the original data of the first object from the outside according to the data volume and source address, and caching the original data of the first object in a first buffer; or, the information about the data of the first object includes the original data of the first object; the processor caches the data of the first object, including: parsing the storage data request to obtain the original data of the first object, and caching the original data of the first object in the first buffer.

[0094] In an exemplary embodiment of the present disclosure, when the original data of the first object is compressed using a multi-object compression method, the processor is also configured to perform the following data retrieval operations: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carries the identifier of the first object; searching the address mapping table according to the identifier of the first object, and finding the memory address allocated to the multiple data blocks into which the compressed data to be stored is divided; reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into the compressed data to be stored, decompressing the compressed data to be stored, obtaining the cached data to be compressed and caching it in a second buffer; extracting the original data of the first object from the cached data to be compressed according to the data volume of the original data of the first object and the offset in the cached data to be compressed, and transmitting part or all of the original data of the first object to the outside.

[0095] In an exemplary embodiment of the present disclosure, without compressing the original data of the first object, the processor is also configured to perform the following data retrieval operations: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carrying the identifier of the first object; finding the memory address corresponding to the identifier of the first object from the address mapping table, reading the original data of the first object from the memory chip according to the found memory address, and caching the original data of the first object in a second buffer; transmitting part or all of the original data of the first object to the outside.

[0096] In an exemplary embodiment of the present disclosure, when the original data of the first object is compressed using a single-object compression method, the processor is also configured to perform the following data retrieval operations: receiving a data retrieval request sent by an external device through the KV interface, the data retrieval request carrying the identifier of the first object; finding the memory address corresponding to the identifier of the first object from the address mapping table, reading the compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; decompressing the compressed data of the first object to obtain the original data of the first object, and transmitting part or all of the original data of the first object to the outside.

[0097] In an exemplary embodiment of the present disclosure, the data retrieval request also carries data volume information of the data to be retrieved and offset information of the data to be retrieved in the original data of the first object; the processor transmits part of the original data of the first object to the outside, including: extracting the data to be retrieved from the original data of the first object according to the data volume information and the offset information, and transmitting the data to be retrieved to the outside.

[0098] In an exemplary embodiment of the present disclosure, the processor transmits part or all of the original data of the first object to the outside, including: carrying part or all of the original data of the first object in a data retrieval response and sending it to the external device; or the data retrieval request also carries information of an external address for storing the retrieved data, and the controller transmits part or all of the original data of the first object to the outside, including: writing part or all of the original data of the first object to the storage space corresponding to the external address.

[0099] In an exemplary embodiment of the present disclosure, the processor is further configured to: upon receiving a data storage request from an external device, extract metadata for the first object from the data storage request, the metadata for the first object including an identifier and data size of the first object; and, via the memory interface, store the metadata for the first object in a storage space created for object metadata in the memory chip. The address mapping table can be stored together with the metadata, but can also be stored separately in a controller cache or in a space allocated in the memory chip.

[0100] The above-mentioned embodiments of the present disclosure implement KV-based memory storage based on the CXL memory module. They can also utilize KV-based hardware compression / decompression mechanisms and interleaving access methods to achieve better storage efficiency. They can be applied to applications related to KV-based memory access.

[0101] An embodiment of the present disclosure also provides a storage system, as shown in Figures 1 and 2, including a host 10 and a CXL memory module described in any embodiment of the present disclosure, including a controller 20 and a memory chip (i.e., a DRAM chip 30), the host 10 communicates with the CXL memory module through a CXL interface to realize discovery, configuration, and data transmission of the CXL memory module; and communicates with the CXL memory module through a KV interface constructed based on the CXL protocol to realize object-based data access between the host and the CXL memory module. Among them, the CXL interface can support the CXL.io protocol and the CXL.mem protocol, and the discovery, configuration, and data transmission of the CXL memory module can be realized through the CXL.io protocol, and data transmission can also be realized through the CXL.mem protocol. KV instructions can be encapsulated in CXL.io instructions (or CXL.mem instructions) as data to be transmitted. This allows the host to communicate with the CXL memory module through the KV interface to realize object-based data access between the host and the CXL memory module.

[0102] An embodiment of the present disclosure further provides a method for accessing data, which is applied to a CXL memory module. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on the CXL protocol. As shown in FIG3A , the method includes:

[0103] Step 100: receiving a KV instruction sent by an external device through the KV interface;

[0104] Step 105: Store the object-based data into the memory chip or retrieve the object-based data from the memory chip.

[0105] The above method for accessing data may be executed by the controller of the CXL memory module in any of the above embodiments. The method for accessing data may include a process of storing data or a process of retrieving data.

[0106] In an exemplary embodiment of the present disclosure, as shown in FIG3B , a data storage process is provided, wherein receiving a KV instruction sent by an external device through the KV interface and storing object-based data into the memory chip includes:

[0107] Step 110: receiving a data storage request sent by an external device through the KV interface, wherein the data storage request carries an identifier of a first object and information about the data of the first object;

[0108] Step 120: cache the data of the first object, allocate a memory address for the first object, and write the data of the first object into the memory chip according to the memory address;

[0109] Step 130: Update the address mapping table to record the correspondence between the identifier of the first object and the memory address.

[0110] The above data storage process can be executed by the controller in the CXL memory module.

[0111] This embodiment of the method receives a KV instruction sent by an external device via a KV interface. If the received instruction is a data storage request, the object's data is cached and a memory address is allocated. Based on the memory address, the object's data is stored in the memory chip, and the correspondence between the object's identifier and the memory address allocated for the object is recorded. This embodiment uses KV-based memory storage to enable external devices, such as hosts, to access the CXL memory module for object storage of unstructured data. The amount of data stored at a time is not limited by the cacheline data size, thereby reducing the number of storage cycles on the storage medium and improving data storage efficiency.

[0112] In an exemplary embodiment of the present disclosure, caching the data of the first object includes: caching the original data of the first object in a first buffer; the method further includes: when determining that the cached original data of the first object is data to be compressed, compressing the original data of the first object using the following multi-object compression method: determining whether the total amount of data to be compressed cached in the first buffer is greater than or equal to a set first threshold;

[0113] When the total amount of the cached data to be compressed is greater than or equal to the first threshold, recording the offset of the original data of each object in the cached data to be compressed, and compressing the cached data to be compressed to obtain compressed data to be stored;

[0114] When the total amount of cached data to be compressed is less than the first threshold, when the original data of a new object is added, so that the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, the offset of the original data of each object in the cached data to be compressed is recorded, and the cached data to be compressed is compressed to obtain the compressed data to be stored.

[0115] The method in this embodiment may be executed by the controller in the CXL memory module in any of the above embodiments.

[0116] In an exemplary embodiment of the present disclosure, when the original data of the first object is compressed using a multi-object compression method, a memory address is allocated to the first object, and the data of the first object is written into the memory chip according to the memory address, including: dividing the compressed data to be stored into multiple data blocks, the compressed data of the first object is located in at least one of the data blocks; allocating memory addresses of different memory areas in the same interleaved area to different data blocks among the multiple data blocks, and using the memory addresses allocated to the multiple data blocks as memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; according to the memory addresses allocated to the multiple data blocks, the multiple data blocks are respectively written into their respective corresponding memory areas in an interleaved access manner; wherein, an interleaved area includes one or more memory areas in the flash memory chip.

[0117] The method in this embodiment may be executed by the controller in the CXL memory module in any of the above embodiments.

[0118] In an example of this embodiment, the first threshold may be determined according to the size of the first buffer, and the first threshold may be no less than 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB.

[0119] In an exemplary embodiment of the present disclosure, the cached data to be compressed includes the original data of all cached objects, and the cached original data of the first object is directly determined as the data to be compressed; or the cached data to be compressed only includes the original data of a cached specified object, and only when the first object is the specified object, the cached original data of the first object is determined to be the data to be compressed; wherein, the specified object is an object whose amount of original data is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

[0120] The method in this embodiment may be executed by the controller in the CXL memory module in any of the above embodiments.

[0121] In an exemplary embodiment of the present disclosure, the method further includes: when the cached data to be compressed includes only cached original data of a designated object and the first object is not the designated object, allocating a memory address to the first object in the following manner, and writing the data of the first object to the memory chip according to the memory address: directly allocating a memory address to the first object based on the original data of the first object without compressing the original data of the first object, and writing the original data of the first object to the memory chip according to the allocated memory address; or first determining whether the data volume of the original data of the first object is greater than or equal to a set third threshold, and the third threshold is less than the second threshold; when the data volume of the original data of the first object is greater than or equal to the third threshold, compressing the original data of the first object separately using a single-object compression method, allocating a memory address to the first object based on the compressed data of the first object, and writing the compressed data of the first object to the memory chip according to the allocated memory address; when the data volume of the original data of the first object is less than the third threshold, not compressing the original data of the first object, allocating a memory address to the first object based on the original data of the first object, and writing the original data of the first object to the memory chip according to the allocated memory address.

[0122] The method in this embodiment may be executed by the controller in the CXL memory module in any of the above embodiments.

[0123] In an exemplary embodiment of the present disclosure, the information of the data of the first object includes the data volume and source address of the original data of the first object; the caching of the data of the first object includes: parsing the storage data request to obtain the data volume and source address, reading the original data of the first object from the outside according to the data volume and source address and caching it in a first buffer; or the information of the data of the first object includes the original data of the first object; the caching of the data of the first object includes: parsing the storage data request to obtain the original data of the first object, and caching the original data of the first object in the first buffer.

[0124] In an exemplary embodiment of the present disclosure, as shown in FIG4 , a process for retrieving data is provided, wherein the process of receiving a KV instruction sent by an external device through the KV interface and retrieving object-based data from the memory chip includes:

[0125] Step 210: receiving a data retrieval request sent by an external device through the KV interface, wherein the data retrieval request carries an identifier of the first object;

[0126] Step 220: Find the memory address corresponding to the identifier of the first object from the address mapping table, and read the data of the first object from the memory chip according to the memory address;

[0127] Step 230: Transmit the data of the first object to the outside.

[0128] The above data fetching process may be executed by the controller in the CXL memory module in any of the aforementioned embodiments.

[0129] In an exemplary embodiment of the present disclosure, when a multi-object compression method is used to compress the original data of the first object when storing data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: searching the address mapping table according to the identifier of the first object to find the memory address allocated for the first object, that is, the memory address allocated for the multiple data blocks into which the compressed data to be stored is divided, and the compressed data of the first object is located in at least one of the data blocks; reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into compressed data to be stored, decompressing the compressed data to be stored, obtaining cached data to be compressed and caching it in a second buffer; extracting the original data of the first object from the cached data to be compressed according to the data amount of the original data of the first object and the offset in the cached data to be compressed, and transmitting part or all of the original data of the first object to the outside.

[0130] The method of this embodiment may be executed by the controller in the CXL memory module in any of the aforementioned embodiments.

[0131] In an exemplary embodiment of the present disclosure, when the original data of the first object is not compressed when storing data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: finding the memory address corresponding to the identifier of the first object in the second cache area from the address mapping table, reading the original data of the first object from the memory chip according to the found memory address, caching the original data of the first object in the second buffer area; and transmitting part or all of the original data of the first object to the outside.

[0132] The method of this embodiment may be executed by the controller in the CXL memory module in any of the aforementioned embodiments.

[0133] In an exemplary embodiment of the present disclosure, when a single-object compression method is used to compress the original data of the first object when storing data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: finding the memory address corresponding to the identifier of the first object from the address mapping table; reading the compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; decompressing the compressed data of the first object to obtain the original data of the first object, and transmitting part or all of the original data of the first object to the outside.

[0134] The method of this embodiment may be executed by the controller in the CXL memory module in any of the aforementioned embodiments.

[0135] In an exemplary embodiment of the present disclosure, the data retrieval request also carries data volume information of the data to be retrieved and offset information of the data to be retrieved in the original data of the first object; transmitting part of the original data of the first object to the outside includes: extracting the data to be retrieved from the original data of the first object according to the data volume information and the offset information, and transmitting the data to be retrieved to the outside.

[0136] In an exemplary embodiment of the present disclosure, the transmitting part or all of the original data of the first object to the outside includes: carrying part or all of the original data of the first object in a data retrieval response and sending it to the external device; or, the data retrieval request also carries information of an external address for storing the retrieved data, and the controller transmitting part or all of the original data of the first object to the outside includes: writing part or all of the original data of the first object to the storage space corresponding to the external address.

[0137] The data storing process and data retrieving process of the above embodiments of the present disclosure correspond to the processing of the controller, and reference may be made to the relevant embodiments of the above controller.

[0138] FIG5 shows an example of a specific application of an embodiment of the present disclosure. It is a possible implementation plan for a process. As shown in the figure, the process includes the following:

[0139] System represents the system, such as the operating system kernel space (kernel space), including the operating system kernel code and data structures.

[0140] Env, argc, and argv represent information related to the process's running environment and command line parameters.

[0141] Stack represents a stack, which is used to store context information of function calls, local variables, function parameters, and other data.

[0142] Heap stands for heap, which is used for dynamic memory allocation. When a program needs to use a variable or object, it can apply for a piece of memory with an appropriate amount of data from the heap, and release it back to the heap after use.

[0143] Shared Lib represents a shared library, also known as a dynamic link library. It is a code library that can be shared by multiple processes and contains common functions and data called by multiple programs.

[0144] Text segment: Also known as a read-only code segment, it is used to store the executable code of the program. When the program starts, the code segment is mapped into the memory and is usually read-only to prevent the program from accidentally modifying its own code.

[0145] Date Segment (data segment) is used to store initialized global variables and static variables in the program. When the program starts, these variables will be allocated in the data segment and exist during the entire program execution.

[0146] Taking a text segment as an example, this example treats the content of each code segment as the data (value) of an object and assigns it an object identifier. This data can then be stored in the CXL memory module of the disclosed embodiment and retrieved in a key-value format.

[0147] In the above process memory layout, code segments are frequently accessed resources. For example, for large applications, code segments occupy a large amount of memory space, and if they include linked libraries, the space occupied is even larger. Code segments cannot be modified after compilation and therefore have read-only attributes. Based on the above characteristics, the code segments of a process can be mapped to CXL memory using a KV method according to the methods of the above embodiments of the present disclosure. KV storage can reduce the number of accesses to the storage medium, improve access efficiency, and reduce memory usage by compressing data.

[0148] As shown in the figure, the code segment is taken as an object, and the key (Key) of the object can be expressed as: PID.Text seg.attri, where PID is the process identifier; Text seg represents the code segment; attri represents the attribute, such as read-only or read-write. The value (Value) is the content of the code segment (Text seg context). The code segment of a process can be taken as an object or divided into multiple objects. When divided into multiple objects, the corresponding index number can be added to the Key. The host 10 and the CXL controller 20 can interact through KV instructions, and the method of the above embodiment of the present disclosure can be used to save the code segment data in the object form to the DRAM chip 30, and read the code segment data from the DRAM chip 30. Other content in the process shown in the figure can also be mapped to the CXL memory using the KV method.

[0149] Figure 6 is a block diagram of a CXL memory module-based KV storage implementation in accordance with one embodiment of the present disclosure. As shown, a host 50 includes a processor (e.g., a CPU) 51, a KV interpreter 53, a CXL storage protocol (CXL.mem) layer 55, and a CXL input / output (CXL.io) protocol layer 57. The host 50 includes:

[0150] The KV interpreter 53 is configured to extract the KV response encapsulated in the CXL.io instruction and parse the KV response, and encapsulate the KV request into the CXL.io instruction, wherein the KV request includes a data storage request and a data retrieval request, and the KV response includes a data storage response and a data retrieval response.

[0151] The CXL storage protocol layer 55 is configured to transmit data. In this embodiment, KV instructions and object-based data can be transmitted between the host and the CXL memory module, and other forms of data can also be transmitted;

[0152] The CXL I / O protocol layer 57, located below the KV interpreter 53, is configured to perform device discovery, configuration, and data transfer for CXL devices (including the CXL memory module 60) during system initialization. It also implements functions such as enumeration and I / O control. For example, to transfer data for a specific object and notify the processor 51 or CXL memory module 60 that the data transfer has been completed, KV instructions are encapsulated within CXL instructions as the data to be transferred.

[0153] The processor 51 is configured to: access the CXL memory module 60 , send KV instructions to the CXL memory module 60 , and receive KV instructions sent by the CXL memory module 60 .

[0154] The CXL memory module 60 includes a controller and DRAM 69, wherein the controller includes:

[0155] The KV interpreter 61 is configured to extract and parse KV requests encapsulated in CXL.io instructions, and to encapsulate KV responses into CXL.io instructions. KV requests include data store requests and data retrieval requests, and KV responses include data store responses and data retrieval responses. Both KV requests and KV responses in this disclosure are KV instructions, and KV instructions can be encapsulated in CXL.io instructions as data to be transmitted.

[0156] The CXL storage protocol layer 62 is configured to transmit data.

[0157] The CXL input / output protocol layer 63 is located below the KV interpreter 61 and is configured to transmit KV instructions and implement register control of the CXL memory module 60 .

[0158] Mapping table 65 is configured to record the mapping of object data to physical memory resources (e.g., DRAM memory addresses). This mapping table may include the address mapping table of the above-described embodiment and may also record object metadata. The data in mapping table 65 may be stored in the reserved space of the DRAM or in the buffer 66.

[0159] The cache 66 can be implemented using SRAM and can be divided into multiple buffers. It is configured to cache part or all of the data of the object during the transmission process. For example, it can cache data to be written to the memory chip and data read from the memory chip. After the cached data reaches a threshold, it is written (flushed) to the DRAM.

[0160] Compression engine 67, configured to implement transparent compression in the CXL memory module, including compression and decompression of data;

[0161] The data distributor 68 is configured to implement data distribution, such as splitting the compressed data to be stored and writing it into the DRAM in an interleaved access manner.

[0162] The control module 64 is configured to control the various modules in the controller to achieve object-based data access. The figure only shows the connection between the control module 64 and some modules, and the connection between the control module and the compression engine 67 and the data distributor 68 is not shown.

[0163] The disclosed embodiments utilize a KV interpreter layered above the CXL.io protocol layer to establish a CXL-based KV interface, or KV API (Application Programming Interface), within the host and CXL controller. The KV interpreter can encapsulate KV instructions into CXL.io instructions (or CXL.mem instructions), extract KV instructions from CXL.io instructions (or CXL.mem instructions), and parse KV instructions to identify object identifiers, object data, and other information contained within them.

[0164] As an exemplary implementation, the host 50 and the CXL memory module 60 may agree on a format of a KV instruction, such as a format for object content transfer and termination.

[0165] The CXL memory module of this embodiment can provide KV access instructions to external devices (such as a CPU). A hardware-accelerated compression / decompression storage mechanism can also be implemented within the CXL controller to improve memory utilization and reduce access latency. KV raw data or compressed data can also be stored in an interleaving manner across multiple DRAM chips within the CXL controller to increase system bandwidth. The above-described embodiments of the present disclosure utilize CXL memory modules to further expand memory capacity.

[0166] After building a KV interpreter based on the CXLio protocol, when the CXL memory module receives a KV instruction to store data (Put), it can retrieve all the object's data (V value) based on the object's identifier (Key value) in the instruction and cache it in a cache such as SRAM. After receiving a KV instruction to retrieve data (Get), the object's data can be encapsulated in a CXL.io instruction between the host and the CXL memory module and transmitted to the host. This avoids the full-path transmission of instruction data for each cacheline between the host and the CXL memory module (primarily DRAM). By loading larger blocks of data based on the object identifier within the CXL memory module, the control overhead of multiple CXL.io calls is avoided. Between the CXL controller and the memory chip, interleaved access can be used to transfer large data blocks, improving storage efficiency.

[0167] In this embodiment, KV instructions and CXL protocol instructions (referred to as CXL instructions) are located at different levels. For example: when a host (such as a CPU) sends a KV instruction to store object data (Put Object), the instruction can first be encapsulated by the KV interpreter (this part is transparent to the CXL layer). When the KV instruction is transmitted to the CXL.io protocol layer, the CXL.io protocol layer simply treats it as ordinary data transmission (without caring about the specific content). In other words, KV instructions are an application layer protocol formed on top of the CXL.io interface. Assuming that a KV instruction to store object data (Put Object) is encapsulated, what the CXL.io layer sees are several packets of data to be transmitted. After the CXL memory module receives this data, the KV interpreter is responsible for parsing it. For the object data, the data itself (V value) can be encapsulated in the data packet; or only the address of the data (V value) can be encapsulated so that the CXL memory module can obtain the object data based on the address.

[0168] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A CXL memory module, comprising a controller and a group of memory chips connected to the controller, wherein: The controller has a key-value pair KV interface based on the CXL protocol, and is configured to receive a KV instruction sent by an external device through the KV interface, and store object-based data into the memory chip or retrieve object-based data from the memory chip.

2. The CXL memory module of claim 1, wherein: The controller stores the object-based data into the memory chip, including: acquiring original data of the object; compressing the original data of the object to obtain compressed data of the object; and writing the compressed data of the object into the memory chip; The controller takes out the object-based data from the memory chip, including: reading out the compressed data of the object stored in the memory chip; decompressing the compressed data of the object to obtain the original data of the object and transmitting it to the outside.

3. The CXL memory module according to claim 1 or 2, wherein: The controller receives a KV instruction sent by an external device through the KV interface, and stores object-based data into the memory chip, including: Receiving a data storage request sent by an external device through the KV interface, the data storage request carrying an identifier of a first object and information about data of the first object; caching the data of the first object, allocating a memory address to the first object, and writing the data of the first object into the memory chip according to the memory address; The address mapping table is updated to record the corresponding relationship between the identifier of the first object and the memory address.

4. The CXL memory module of claim 3, wherein: The controller receives a KV instruction sent by an external device through the KV interface, and takes out object-based data from the memory chip, including: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, and reading data of the first object from the memory chip according to the memory address; The data of the first object is transmitted to the outside.

5. The CXL memory module of claim 3, wherein: The controller caches the data of the first object, including: caching the original data of the first object in a first buffer; The controller is further configured to, when determining that the cached original data of the first object is data to be compressed, compress the original data of the first object using the following multi-object compression method: Determine whether the total amount of data to be compressed that has been cached in the first buffer is greater than or equal to a set first threshold; When the total amount of the cached data to be compressed is greater than or equal to the first threshold, recording the offset of the original data of each object in the cached data to be compressed, compressing the cached data to be compressed, and obtaining compressed data to be stored; When the total amount of cached data to be compressed is less than the first threshold, when there is new raw data of the object Add, so that when the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, the offset of the original data of each object in the cached data to be compressed is recorded, and the cached data to be compressed is compressed to obtain the compressed data to be stored.

6. The CXL memory module of claim 5, wherein: In the case of compressing the original data of the first object in a multi-object compression manner, the controller allocates a memory address to the first object, and writes the data of the first object into the memory chip according to the memory address, including: dividing the compressed data to be stored into a plurality of data blocks, wherein the compressed data of the first object is located in at least one of the data blocks; Allocating memory addresses of different memory areas in the same interleaved area to different data blocks among the multiple data blocks, and using the memory addresses allocated to the multiple data blocks as memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; Writing the plurality of data blocks into the respective corresponding memory areas in an interleaved access manner according to the memory addresses allocated to the plurality of data blocks; Wherein, an interleaved area includes one or more memory areas in the memory chip.

7. The CXL memory module of claim 5, wherein: The first threshold is determined according to the size of the first buffer, and the first threshold is not less than 4KB, 8KB, 16KB, 32KB, 64KB, 128KB or 256KB.

8. The CXL memory module of claim 5, wherein: The cached data to be compressed includes original data of all cached objects, and the controller directly determines the cached original data of the first object as the data to be compressed; or The cached data to be compressed only includes the original data of the cached designated object. The controller determines that the cached original data of the first object is the data to be compressed only when the first object is the designated object; wherein the designated object is an object whose original data volume is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

9. The CXL memory module of claim 8, wherein: The controller is further configured to, when the cached data to be compressed only includes original data of a cached designated object and the first object is not a designated object, allocate a memory address to the first object in the following manner, and write the data of the first object into the memory chip according to the memory address: without compressing the original data of the first object, directly allocating a memory address for the first object according to the original data of the first object, and writing the original data of the first object into the memory chip according to the allocated memory address; or First, determine whether the data volume of the original data of the first object is greater than or equal to a set third threshold, and the third threshold is less than the second threshold; when the data volume of the original data of the first object is greater than or equal to the third threshold, compress the original data of the first object separately using a single-object compression method, allocate a memory address to the first object according to the compressed data of the first object, and write the compressed data of the first object into the memory chip according to the allocated memory address; when the data volume of the original data of the first object is less than the third threshold, do not compress the original data of the first object, allocate a memory address to the first object according to the original data of the first object, and write the original data of the first object into the memory chip according to the allocated memory address.

10. The CXL memory module of claim 3, wherein: The information of the data of the first object includes the data volume and source address of the original data of the first object; The controller caches the data of the first object, including: parsing the data storage request to obtain the data volume and the source address, reading the original data of the first object from the outside according to the data volume and the source address, and caching the original data in the first buffer; or The information of the data of the first object includes the original data of the first object; the controller caches the data of the first object, including: parsing the data storage request to obtain the original data of the first object, and caching the original data of the first object in a first buffer.

11. The CXL memory module of claim 6, wherein: In the case of compressing the original data of the first object in a multi-object compression manner, the controller receives a KV instruction sent by an external device through the KV interface, and takes out the object-based data from the memory chip, including: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Searching the address mapping table according to the identifier of the first object to find the memory addresses allocated to the multiple data blocks into which the compressed data to be stored is divided; Reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into the compressed data to be stored, decompressing the compressed data to be stored, obtaining the cached data to be compressed and caching it in a second buffer; According to the data volume of the original data of the first object and its offset in the cached data to be compressed, the original data of the first object is extracted from the cached data to be compressed, and part or all of the original data of the first object is transmitted to the outside.

12. The CXL memory module of claim 9, wherein: In the case of not compressing the original data of the first object, the controller receives a KV instruction sent by an external device through the KV interface, and takes out the object-based data from the memory chip, including: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, reading original data of the first object from the memory chip according to the found memory address, and caching the original data of the first object in a second buffer; Part or all of the original data of the first object is transmitted to the outside.

13. The CXL memory module of claim 9, wherein: In the case of compressing the original data of the first object in a single object compression manner, the controller receives a KV instruction sent by an external device through the KV interface, and takes out the object-based data from the memory chip, including: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, and reading compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; The compressed data of the first object is decompressed to obtain the original data of the first object, and part or all of the original data of the first object is transmitted to the outside.

14. The CXL memory module according to any one of claims 11 to 13, wherein: The data fetching request also carries the data volume information of the data to be fetched and the offset information of the data to be fetched in the original data of the first object; The controller transmits part of the original data of the first object to the outside, including: extracting the data to be retrieved from the original data of the first object according to the data amount information and the offset information, and transmitting the data to be retrieved to the outside.

15. The CXL memory module according to any one of claims 11 to 13, wherein: The controller transmits part or all of the original data of the first object to the outside, including: carrying part or all of the original data of the first object in a data acquisition response and sending it to the external device; or The data retrieval request also carries information of an external address for storing the retrieved data, and the controller transmits part or all of the original data of the first object to the outside, including: writing part or all of the original data of the first object to the storage space corresponding to the external address.

16. The CXL memory module of claim 1, wherein: The CXL protocol-based KV interface is implemented by a KV interpreter built on the CXL.io protocol layer and / or the CXL.mem protocol layer, and the KV interpreter is configured to: extract the KV request encapsulated in the CXL.io instruction or the CXL.mem instruction as the data to be transmitted and parse the KV request; and encapsulate the KV response as the data to be transmitted into the CXL.io instruction or the CXL.mem instruction; wherein the KV request includes a data storage request and a data retrieval request, and the KV response includes a data storage response and a data retrieval response.

17. A controller in a CXL memory module, comprising a processor, a cache, a CXL interface and a memory interface, wherein: A key-value pair KV interface based on the CXL protocol is built on the CXL interface, and the processor is configured to perform the following data storage operations: Receiving a data storage request sent by an external device through the KV interface, the data storage request carrying an identifier of a first object and information about data of the first object; caching the data of the first object in the buffer, allocating a memory address for the first object, and storing the data of the first object in a memory chip connected to the memory interface according to the memory address; The address mapping table is updated to record the corresponding relationship between the identifier of the first object and the memory address.

18. The controller of claim 17, wherein: The processor caches the data of the first object, including: caching the original data of the first object in a first buffer of the cache; The controller also includes a compression engine, and the processor is further configured to: when it is determined that the cached original data of the first object is data to be compressed, use the compression engine to compress the original data of the first object using the following multi-object compression method: determine whether the total amount of cached data to be compressed in the first buffer is greater than or equal to a set first threshold; when the total amount of cached data to be compressed is greater than or equal to the first threshold, record the offset of the original data of each object in the cached data to be compressed, compress the cached data to be compressed, and obtain the compressed data to be stored; when the total amount of cached data to be compressed is less than the first threshold, when the original data of a new object is added, so that the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, record the offset of the original data of each object in the cached data to be compressed, compress the cached data to be compressed, and obtain the compressed data to be stored.

19. The controller of claim 18, wherein: In the case of compressing the original data of the first object in a multi-object compression manner, the processor allocates a memory address to the first object, and stores the data of the first object in a memory interface connected to the memory interface according to the memory address. Memory chips, including: dividing the compressed data to be stored into a plurality of data blocks, wherein the compressed data of the first object is located in at least one of the data blocks; Allocating memory addresses of different memory areas in the same interleaved area to different data blocks among the multiple data blocks, and using the memory addresses allocated to the multiple data blocks as memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; Writing the plurality of data blocks into the respective corresponding memory areas in an interleaved access manner according to the memory addresses allocated to the plurality of data blocks; Wherein, an interleaved area includes one or more memory areas in the memory chip.

20. The controller of claim 18, wherein: The first threshold is determined according to the size of the first buffer, and the first threshold is not less than 4KB, 8KB, 16KB, 32KB, 64KB, 128KB or 256KB.

21. The controller of claim 18, wherein: The cached data to be compressed includes original data of all cached objects, and the processor directly determines the cached original data of the first object as the data to be compressed; or The cached data to be compressed only includes the original data of the cached specified object. The processor determines that the cached original data of the first object is the data to be compressed only when the first object is the specified object; wherein the specified object is an object whose original data volume is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

22. The controller of claim 21, wherein: The processor is further configured to, when the cached data to be compressed only includes original data of the cached designated object and the first object is not the designated object, allocate a memory address for the first object in the following manner, and store the data of the first object into the memory chip connected to the memory interface according to the memory address: without compressing the original data of the first object, directly allocating a memory address for the first object according to the original data of the first object, and writing the original data of the first object into the memory chip according to the allocated memory address; or First, determine whether the data volume of the original data of the first object is greater than or equal to a set third threshold, and the third threshold is less than the second threshold; when the data volume of the original data of the first object is greater than or equal to the third threshold, compress the original data of the first object separately using a single-object compression method, allocate a memory address to the first object according to the compressed data of the first object, and write the compressed data of the first object into the memory chip according to the allocated memory address; when the data volume of the original data of the first object is less than the third threshold, do not compress the original data of the first object, allocate a memory address to the first object according to the original data of the first object, and write the original data of the first object into the memory chip according to the allocated memory address.

23. The controller of claim 17, wherein: The information of the data of the first object includes the data volume and source address of the original data of the first object; The processor caches the data of the first object, including: parsing the data storage request to obtain the data volume and the source address, reading the original data of the first object from the outside according to the data volume and the source address, and caching the original data in a first buffer; or The information of the data of the first object includes the original data of the first object; the processor caches the data of the first object, including: parsing the storage data request to obtain the original data of the first object, and caching the original data of the first object in the first buffer.

24. The controller of claim 18, wherein: In the case where the original data of the first object is compressed in a multi-object compression manner, the processor is further configured to perform the following data fetching operation: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Searching the address mapping table according to the identifier of the first object to find the memory addresses allocated to the multiple data blocks into which the compressed data to be stored is divided; Reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into the compressed data to be stored, decompressing the compressed data to be stored, obtaining the cached data to be compressed and caching it in a second buffer; According to the data volume of the original data of the first object and its offset in the cached data to be compressed, the original data of the first object is extracted from the cached data to be compressed, and part or all of the original data of the first object is transmitted to the outside.

25. The controller of claim 21, wherein: In the case where the original data of the first object is not compressed, the processor is further configured to perform the following data fetching operation: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, reading original data of the first object from the memory chip according to the found memory address, and caching the original data of the first object in a second buffer; Part or all of the original data of the first object is transmitted to the outside.

26. The controller of claim 21, wherein: In the case where the original data of the first object is compressed in a single object compression manner, the processor is further configured to perform the following data fetching operation: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, and reading compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; The compressed data of the first object is decompressed to obtain the original data of the first object, and part or all of the original data of the first object is transmitted to the outside.

27. A controller as claimed in any one of claims 24 to 26, wherein: The data fetching request also carries the data volume information of the data to be fetched and the offset information of the data to be fetched in the original data of the first object; The processor transmits part of the original data of the first object to the outside, including: extracting the data to be retrieved from the original data of the first object according to the data amount information and the offset information, and transmitting the data to be retrieved to the outside.

28. A controller as claimed in any one of claims 24 to 26, wherein: The processor transmits part or all of the original data of the first object to the outside, including: Part or all of the original data of the object is carried in a data acquisition response and sent to the external device; or The data retrieval request also carries information of an external address for storing the retrieved data, and the controller transmits part or all of the original data of the first object to the outside, including: writing part or all of the original data of the first object to the storage space corresponding to the external address.

29. The controller of claim 17, wherein: The CXL protocol-based KV interface is implemented by a KV interpreter built on the CXL.io protocol layer and / or the CXL.mem protocol layer; the KV interpreter is configured to: extract the KV request encapsulated in the CXL.io instruction or the CXL.mem instruction as the data to be transmitted and parse the KV request; and encapsulate the KV response as the data to be transmitted into the CXL.io instruction or the CXL.mem instruction; wherein the KV request includes a data storage request and a data retrieval request, and the KV response includes a data storage response and a data retrieval response.

30. A method for accessing data, applied to a CXL memory module, wherein the CXL memory module comprises a controller and a group of memory chips connected to the controller, wherein the controller has a key-value pair (KV) interface based on the CXL protocol, wherein: The method comprises: receiving a KV instruction sent by an external device through the KV interface, storing object-based data into the memory chip or taking object-based data out of the memory chip.

31. The method of claim 30, wherein: The step of receiving a KV instruction sent by an external device through the KV interface and storing object-based data into the memory chip includes: Receiving a data storage request sent by an external device through the KV interface, the data storage request carrying an identifier of a first object and information about data of the first object; caching the data of the first object, allocating a memory address to the first object, and writing the data of the first object into the memory chip according to the memory address; The address mapping table is updated to record the corresponding relationship between the identifier of the first object and the memory address.

32. The method of claim 31, wherein: The caching the data of the first object comprises: caching the original data of the first object in a first buffer; The method further includes: when determining that the cached original data of the first object is data to be compressed, compressing the original data of the first object using the following multi-object compression method: determining whether the total amount of cached data to be compressed in the first buffer is greater than or equal to a set first threshold; When the total amount of cached data to be compressed is greater than or equal to the first threshold, the offset of the original data of each object in the cached data to be compressed is recorded, and the cached data to be compressed is compressed to obtain the compressed data to be stored; when the total amount of cached data to be compressed is less than the first threshold, when the original data of a new object is added, so that the total amount of cached data to be compressed in the first buffer is greater than or equal to the first threshold, the offset of the original data of each object in the cached data to be compressed is recorded again, and the cached data to be compressed is compressed to obtain the compressed data to be stored.

33. The method of claim 32, wherein: In the case where the original data of the first object is compressed in a multi-object compression manner, allocating a memory address for the first object and writing the data of the first object into the memory chip according to the memory address includes: dividing the compressed data to be stored into a plurality of data blocks, wherein the compressed data of the first object is located in at least one of the data blocks; Assign memory addresses of different memory areas in the same interleaved area to different data blocks in the plurality of data blocks, The memory addresses allocated to the multiple data blocks are used as memory addresses uniformly allocated to all objects to which the compressed data to be stored belongs; Writing the plurality of data blocks into the respective corresponding memory areas in an interleaved access manner according to the memory addresses allocated to the plurality of data blocks; Wherein, an interleaved area includes one or more memory areas in the memory chip.

34. The method of claim 32, wherein: The cached data to be compressed includes original data of all cached objects, and the cached original data of the first object is directly determined as the data to be compressed; or The cached data to be compressed only includes the original data of the cached specified object. Only when the first object is the specified object, the cached original data of the first object is determined to be the data to be compressed; wherein, the specified object is an object whose original data volume is greater than or equal to a set second threshold, and the second threshold is less than the first threshold.

35. The method of claim 34, further comprising: In the case that the cached data to be compressed only includes original data of the cached designated object, and the first object is not the designated object, a memory address is allocated to the first object in the following manner, and the data of the first object is written into the memory chip according to the memory address: without compressing the original data of the first object, directly allocating a memory address for the first object according to the original data of the first object, and writing the original data of the first object into the memory chip according to the allocated memory address; or First, determine whether the data volume of the original data of the first object is greater than or equal to a set third threshold, and the third threshold is less than the second threshold; when the data volume of the original data of the first object is greater than or equal to the third threshold, compress the original data of the first object separately using a single-object compression method, allocate a memory address to the first object according to the compressed data of the first object, and write the compressed data of the first object into the memory chip according to the allocated memory address; when the data volume of the original data of the first object is less than the third threshold, do not compress the original data of the first object, allocate a memory address to the first object according to the original data of the first object, and write the original data of the first object into the memory chip according to the allocated memory address.

36. The method of claim 31, wherein: The receiving a KV instruction sent by an external device through the KV interface and taking out the object-based data from the memory chip includes: Receiving a data acquisition request sent by an external device through the KV interface, wherein the data acquisition request carries an identifier of the first object; Finding a memory address corresponding to the identifier of the first object from the address mapping table, and reading data of the first object from the memory chip according to the memory address; The data of the first object is transmitted to the outside.

37. The method of claim 36, wherein: In the case where the original data of the first object is compressed by adopting a multi-object compression method when storing data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: The address mapping table is searched according to the identifier of the first object to find the memory address allocated for the first object, that is, the memory address allocated for the multiple data blocks into which the compressed data to be stored is divided. The compressed data of the first object is located at In at least one of the data blocks; Reading the multiple data blocks from the memory chip according to the memory address, splicing the multiple data blocks into compressed data to be stored, decompressing the compressed data to be stored, obtaining cached data to be compressed and caching it in a second buffer; According to the data volume of the original data of the first object and its offset in the cached data to be compressed, the original data of the first object is extracted from the cached data to be compressed, and part or all of the original data of the first object is transmitted to the outside.

38. The method of claim 36, wherein: In the case where the original data of the first object is not compressed when storing the data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: Finding a memory address corresponding to the identifier of the first object in the second buffer area from the address mapping table, reading original data of the first object from the memory chip according to the found memory address, and caching the original data of the first object in the second buffer area; and, Part or all of the original data of the first object is transmitted to the outside.

39. The method of claim 36, wherein: In the case where the original data of the first object is compressed by a single object compression method when storing data, the memory address corresponding to the identifier of the first object is found from the address mapping table, the data of the first object is read from the memory chip according to the memory address, and the data of the first object is transmitted to the outside, including: Finding a memory address corresponding to the identifier of the first object from the address mapping table; Reading the compressed data of the first object from the memory chip according to the found memory address and caching it in a second buffer; The compressed data of the first object is decompressed to obtain the original data of the first object, and part or all of the original data of the first object is transmitted to the outside.

40. A storage system comprising a host and a CXL memory module as claimed in any one of claims 1 to 16, wherein: The host communicates with the CXL memory module through a CXL interface to achieve discovery, configuration and data transmission of the CXL memory module; communicates with the CXL memory module through a KV interface built based on the CXL protocol to achieve object-based data access between the host and the CXL memory module.

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