CP signal measurement circuit and charging pile

Abstract

A CP signal measurement circuit and a charging pile. The CP signal measurement circuit comprises a CP signal generation module (1), a rectification module (2) electrically connected to an output end of the CP signal generation module (1), and a hysteresis comparison circuit (3) and a voltage follower circuit (4) which are electrically connected to an output end of the rectification module (2); the CP signal generation module (1) is used for processing an input PWM signal, so as to output a first CP signal; the rectification module (2) is used for rectifying the first CP signal, so as to convert same into a second CP signal; the hysteresis comparison circuit (3) is used for outputting, on the basis of the second CP signal, a waveform signal, so as to measure the duty ratio of the first CP signal; and the voltage follower circuit (4) is used for outputting, on the basis of the second CP signal, a voltage amplitude signal, so as to measure the amplitude of the first CP signal, thus improving the electrical safety of charging systems.

Description

A CP signal detection circuit and charging pile

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application No. 202322621660.9, filed on September 26, 2023, and entitled “A CP signal detection circuit and charging pile,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the technical field of new energy charging systems, and in particular to a CP signal detection circuit and a charging pile. Background Art

[0004] The charging pile industry has experienced rapid growth in recent years. Charging piles now come in a wide variety of configurations. Based on output voltage, they can be categorized as DC and AC; based on installation method, they can be further categorized as fixed, mobile, and portable. While AC charging piles vary in form, their core functionality remains largely the same. The structure and appearance of an AC charging pile can be broadly divided into an incoming cable, charging plug, housing, LCD touchscreen, LED indicator, RFID card reader, emergency stop button, and charging plug holder. Wall-mounted and floor-standing charging piles also have a wall mount and support, respectively.

[0005] During the operation of the charging pile, the voltage value of the charging control pilot (CP) signal will switch between different voltage values ​​at different stages, such as when the charging gun is not inserted, when the charging gun is inserted but not charging, and during the charging process. The CP signal is essentially a PWM square wave signal. The charging pile and the electric vehicle control device confirm the connection status of the vehicle and the pile, as well as the charging status, through the voltage value and duty cycle of the CP signal. Before the charging pile charges the electric vehicle, it is necessary to confirm whether the electric vehicle and the charging pile are properly connected. In addition, during the entire charging process, the entire charging process needs to be monitored in real time. When an abnormal situation occurs, the charging pile needs to be powered off immediately.

[0006] However, existing technologies currently monitor the amplitude of the CP signal, but neglect to monitor the duty cycle of the output PWM wave. This poses a significant risk to the entire charging system. Therefore, monitoring the duty cycle of the PWM wave output by the charging pile is an urgent problem that the industry needs to solve.

[0007] Summary of the Invention

[0008] The present disclosure provides a CP signal detection circuit and a charging pile, which are used to solve the problem in the prior art that the duty cycle of the PWM wave output by the charging pile cannot be monitored.

[0009] The present disclosure provides a CP signal detection circuit, comprising:

[0010] a CP signal generating module, configured to process the received PWM signal to output a first CP signal;

[0011] a rectifier module, wherein an input end of the rectifier module is electrically connected to an output end of the CP signal generating module, and is configured to rectify the first CP signal to convert it into a second CP signal;

[0012] a hysteresis comparator circuit, wherein the input end of the hysteresis comparator circuit is electrically connected to the output end of the rectifier module; the output end of the hysteresis comparator circuit is electrically connected to the control module, and the hysteresis comparator circuit is used to output a waveform signal based on the second CP signal to detect the duty cycle of the first CP signal;

[0013] A voltage follower circuit, wherein the input end of the voltage follower circuit is electrically connected to the output end of the rectifier module, the voltage follower circuit is electrically connected to the control module, and the voltage follower circuit is used to output a voltage amplitude signal based on the second CP signal to detect the amplitude of the first CP signal.

[0014] According to the CP signal detection circuit provided by the present disclosure, the hysteresis comparison circuit includes:

[0015] a third operational amplifier U3, wherein the non-inverting input terminal of the third operational amplifier U3 is electrically connected to the output terminal of the rectifier module; and the output terminal of the third operational amplifier U3 is electrically connected to the GPIO port of the control module;

[0016] a third resistor R3, one end of the third resistor R3 being connected to the power supply voltage VCC, and the other end of the third resistor R3 being electrically connected to the inverting input terminal of the third operational amplifier U3;

[0017] A seventh resistor R7, one end of the seventh resistor R7 is grounded, and the other end of the seventh resistor R7 is electrically connected to the inverting input terminal of the third operational amplifier U3.

[0018] According to the CP signal detection circuit provided by the present disclosure, the hysteresis comparison circuit further includes:

[0019] An eighth resistor R8 , one end of the eighth resistor R8 is electrically connected to the other end of the seventh resistor R7 , and the other end of the eighth resistor R8 is electrically connected to the output end of the third operational amplifier U3 .

[0020] According to the CP signal detection circuit provided by the present disclosure, the CP signal generation module includes:

[0021] a second resistor R2, one end of the second resistor R2 being used to receive a PWM signal;

[0022] a photocoupler U1, wherein an anode of the photocoupler U1 is electrically connected to the other end of the second resistor R2, a cathode of the photocoupler U1 is grounded, a Vcc pin of the photocoupler U1 is connected to a first power supply VCC0, and a VEE pin of the photocoupler U1 is connected to a second power supply VCC1;

[0023] an NMOS transistor Q1, wherein a gate of the NMOS transistor Q1 is electrically connected to the output end of the photocoupler U1, and a source of the NMOS transistor Q1 is connected to a second power supply VCC1;

[0024] A PMOS transistor Q2, wherein the gate of the PMOS transistor Q2 is electrically connected to the output end of the photocoupler U1, and the source of the PMOS transistor Q2 is connected to a first power supply VCC0;

[0025] A first resistor R1 , one end of which is electrically connected to the drain of the NMOS transistor Q1 and the drain of the PMOS transistor Q2 , and the other end of which is electrically connected to the input end of the rectifier module.

[0026] According to the CP signal detection circuit provided by the present disclosure, the voltage follower circuit includes:

[0027] a fourth resistor R4, one end of the fourth resistor R4 being electrically connected to the output end of the rectifier module;

[0028] a fifth resistor R5, one end of the fifth resistor R5 being electrically connected to the other end of the fourth resistor R4, and the other end of the fifth resistor R5 being grounded;

[0029] A second operational amplifier U2, the non-inverting input terminal of the second operational amplifier U2 is electrically connected to the other end of the fourth resistor R4, the inverting input terminal of the second operational amplifier U2 is electrically connected to the output terminal of the second operational amplifier U2, and the inverting input terminal of the second operational amplifier U2 is also electrically connected to the ADC port of the control module.

[0030] According to the CP signal detection circuit provided in the present disclosure, the CP signal detection circuit further includes:

[0031] A filtering module, one end of which is electrically connected to the output end of the second operational amplifier U2, and the other end of which is grounded.

[0032] According to the CP signal detection circuit provided in the present disclosure, the filtering module includes:

[0033] a sixth resistor R6, one end of the sixth resistor R6 being electrically connected to the output terminal of the second operational amplifier U2, and the other end of the sixth resistor R6 being electrically connected to the inverting input terminal of the second operational amplifier U2;

[0034] A first capacitor C1 , one end of the first capacitor C1 is electrically connected to the other end of the sixth resistor R6 , and the other end of the first capacitor C1 is grounded.

[0035] According to the CP signal detection circuit provided by the present disclosure, the rectifier module includes:

[0036] A rectifier, wherein the input end of the rectifier is electrically connected to the output end of the CP signal generating module, and the output end of the rectifier is electrically connected to the input end of the hysteresis comparator circuit and the input end of the voltage follower circuit.

[0037] According to the CP signal detection circuit provided in the present disclosure, the rectifier includes:

[0038] A diode D1, wherein the anode of the diode D1 is electrically connected to the output end of the CP signal generating module, and the cathode of the diode D1 is electrically connected to the input end of the hysteresis comparator circuit and the input end of the voltage follower circuit.

[0039] The present disclosure also provides a charging pile, a charging circuit and a CP signal detection circuit including any of the above; the charging circuit is electrically connected to the CP signal detection circuit.

[0040] The present disclosure provides a CP signal detection circuit and charging pile. The CP signal detection circuit receives a PWM signal through a CP signal generation module, processes the PWM signal to obtain a first CP signal, and then outputs the first CP signal; receives the first CP signal through a rectifier module, rectifies the first CP signal to convert it into a second CP signal; receives the second CP signal through a hysteresis comparison circuit, and outputs a waveform signal CP_CHECK2 based on the second CP signal. The control module detects the duty cycle of the first CP signal based on the received waveform signal CP_CHECK2, thereby improving the power safety of the charging system;

[0041] The CP signal detection circuit receives a PWM signal through a CP signal generation module, processes the PWM signal to obtain a first CP signal, and then outputs the first CP signal; receives the first CP signal through a rectifier module, rectifies the first CP signal to convert it into a second CP signal; receives the second CP signal through a voltage follower circuit, and outputs a voltage amplitude signal CP_CHECK1 based on the second CP signal. The control module detects the amplitude of the first CP signal according to the received voltage amplitude signal CP_CHECK1, thereby improving the power safety of the charging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a functional block diagram of a CP signal detection circuit provided by the present disclosure;

[0043] FIG2 is a circuit diagram of a CP signal detection circuit provided by the present disclosure;

[0044] FIG3 is a circuit diagram of a photoelectric coupler in a CP signal detection circuit provided by the present disclosure;

[0045] 4 is an equivalent circuit diagram of the third resistor R3, the eighth resistor R8, and the seventh resistor R7 when the level of the non-inverting input terminal of the third operational amplifier U3 is greater than the level of the inverting input terminal;

[0046] 5 is an equivalent circuit diagram of the third resistor R3 , the eighth resistor R8 , and the seventh resistor R7 when the level of the non-inverting input terminal of the third operational amplifier U3 is not greater than the level of the inverting input terminal. DETAILED DESCRIPTION

[0047] The technical solutions in the present disclosure will be described below in conjunction with the drawings in the present disclosure. The described embodiments are only part of the embodiments of the present disclosure, but not all of the embodiments.

[0048] As shown in Figure 1, a specific embodiment of the present disclosure provides a CP signal detection circuit. The CP signal detection circuit includes a CP signal generating module 1, a rectifier module 2, a hysteresis comparison circuit 3 and a voltage follower circuit 4; the CP signal generating module 1 is used to process the received PWM signal to output a first CP signal; the input end of the rectifier module 2 is electrically connected to the output end of the CP signal generating module 1, and is used to rectify the first CP signal to convert it into a second CP signal; the input end of the hysteresis comparison circuit 3 is electrically connected to the output end of the rectifier module 2; the output end of the hysteresis comparison circuit 3 is connected to the control module 6, and the hysteresis comparison circuit 3 is used to output a waveform signal based on the second CP signal to detect the duty cycle of the first CP signal; the input end of the voltage follower circuit 4 is electrically connected to the output end of the rectifier module 2, and the voltage follower circuit 4 is electrically connected to the control module 6. The voltage follower circuit 4 is used to output a voltage amplitude signal based on the second CP signal to detect the amplitude of the first CP signal.

[0049] In this embodiment, the CP signal generating module 1 receives an input PWM signal, processes it to obtain a first CP signal, and outputs the first CP signal; the rectifier module 2 is used to receive the first CP signal, chop and rectify the first CP signal to convert the first CP signal into a second CP signal; the hysteresis comparator circuit 3 is used to receive the second CP signal and output a waveform signal CP_CHECK2 based on the second CP signal. The control module detects the duty cycle of the first CP signal based on the received waveform signal CP_CHECK2, thereby improving the power safety of the charging system.

[0050] In addition, after receiving the input PWM signal, the CP signal generating module 1 processes it to obtain a first CP signal and outputs the first CP signal; the rectifier module 2 is used to receive the first CP signal, and chop and rectify the first CP signal to convert the first CP signal into a second CP signal; the voltage follower circuit 4 is used to receive the second CP signal and output a voltage amplitude signal CP_CHECK1 based on the second CP signal. The control module detects the amplitude of the first CP signal according to the received voltage amplitude signal CP_CHECK1, thereby improving the power safety of the charging system.

[0051] In one embodiment, the output end of the control module 6 is electrically connected to the input end of the CP signal generating module 1 for inputting a PWM signal to the CP signal generating module 1 .

[0052] Furthermore, the PWM signal is generated by the universal I / O configuration of the MCU inside the charging pile that communicates with the vehicle. Furthermore, the low level of the PWM signal is 0V, and the high level is 3.3V or 5V.

[0053] Furthermore, the control module 6 includes, but is not limited to, an MCU.

[0054] Furthermore, the first CP signal includes a PWM wave with an amplitude of ±12V and a duty cycle of 53.33%.

[0055] When the input PWM signal is at a high level of 3.3V or 5V, the CP signal generation module 1 outputs a first CP signal at a high level of 12V. When the input PWM signal is at a low level of 0V, the CP signal generation module 1 outputs a first CP signal at a low level of -12V. In other words, the CP signal generates the same mapping as the high and low levels of the PWM wave, achieving the same frequency and phase as the input PWM signal and the first CP signal output by the CP signal generation module.

[0056] In one embodiment, as shown in FIG2 , the CP signal generating module includes a second resistor R2, an optocoupler U1, an NMOS transistor Q1, a PMOS transistor Q2, and a first resistor R1; one end of the second resistor R2 is used to receive a PWM signal; an anode of the optocoupler U1 is electrically connected to the other end of the second resistor R2, a cathode of the optocoupler U1 is grounded, a Vcc pin of the optocoupler U1 is connected to a first power supply VCC0, and a VEE pin of the optocoupler U1 is connected to a second power supply VCC1; a gate of the NMOS transistor Q1 is electrically connected to a Vo pin of the optocoupler U1, and a source of the NMOS transistor Q1 is connected to the second power supply VCC1; a gate of the PMOS transistor Q2 is electrically connected to the Vo pin of the optocoupler U1, and a source of the PMOS transistor Q2 is connected to the first power supply VCC0; one end of the first resistor R1 is electrically connected to the drain of the NMOS transistor Q1 and the drain of the PMOS transistor Q2, and the other end of the first resistor R1 is electrically connected to the input end of the rectifier module.

[0057] In one embodiment, as shown in Figures 1 and 2, the PWM signal, i.e., the PWM wave, emitted by the MCU is current-limited by the second resistor R2 to control the on / off of the light-emitting diode (LED) of the photocoupler U1. The circuit diagram of the photocoupler U1 is shown in Figure 3. When the input PWM signal is at a high level, the LED is turned on. When the PWM signal is at a low level, the LED is turned off. When the LED of the photocoupler U1 is turned on, the upper transistor of the photocoupler U1 is turned on. Since the Vcc pin of the photocoupler U1 is pulled up to the first power supply VCC0, the output end of the photocoupler U1 outputs the voltage of the first power supply VCC0. When the LED is turned off, the lower transistor of the photocoupler U1 is turned on. Since the VEE pin of the photocoupler U1 is pulled down to the second power supply VCC1, the output end of the photocoupler U1 outputs the voltage of the second power supply VCC1. The voltage of the second power supply VCC1 is -12V, and the voltage of the first power supply VCC0 is +12V. In other words, the output of the optocoupler U1 maps in the same way as the PWM signal. The mapping relationship between the output of the Vo pin of the optocoupler U1 and the input PWM signal is shown in Table 1. Therefore, the output of the Vo pin of the optocoupler U1 and the input PWM signal are in the same frequency and phase. In addition, the optocoupler U1 also provides complete electrical isolation. Accidents during the charging process, such as short circuits, will not directly cause damage to the control board and other hardware, thus providing protection for the control board and other hardware.

[0058] Table 1 Mapping relationship between the Vo pin output of the optocoupler U1 and the input PWM signal

[0059] It can be understood that the resistance of the second resistor R2 is determined by formula (1). R2=(V PWM-VF) / IF formula (1)

[0060] Among them, V PWM is the PWM wave amplitude; VF is the forward voltage of the light-emitting diode in the optocoupler U1, and IF is the forward current of the light-emitting diode.

[0061] In one embodiment, the first CP signal of the AC charging pile should be a PWM wave with an amplitude of ±12V and a duty cycle of 53.33%. In the following description, unless otherwise specified, the first CP signal refers to a PWM wave with an amplitude of ±12V and a duty cycle of 53.33%.

[0062] It is understandable that the first CP signal is not limited to a PWM wave with an amplitude of ±12V and a duty cycle of 53.33%, and its amplitude and duty cycle can be adjusted according to actual needs.

[0063] In one embodiment, as shown in Figure 3, the internal structure of the optocoupler U1 includes a triode, which exhibits a conduction voltage drop. Therefore, when the top transistor is on, the voltage outputted by the Vo pin of the optocoupler U1 cannot reach 12V, failing to meet the requirements for the first CP signal. Therefore, a push-pull output driver circuit composed of a CMOS transistor is connected to the Vo pin of the optocoupler U1. The top transistor Q2 of the push-pull output driver circuit is a PMOS transistor, and the bottom transistor Q1 is an NMOS transistor. The Vo pin is connected to the CMOS gate input. When the Vo pin of the optocoupler U1 inputs a high level to the CMOS gate, the NMOS transistor Q1 turns on, and the first CP signal is pulled to the second power supply VCC1 via the first resistor R1 and the NMOS transistor Q1. When the Vo pin of the optocoupler U1 inputs a low level to the CMOS gate, the PMOS transistor Q2 turns on, and the first CP signal is pulled to the first power supply VCC0 via the first resistor R1 and the PMOS transistor Q2. Among them, VCC0 is equal to +12V and VCC1 is equal to -12V. At this time, the first CP signal output can reach a ±12V PWM wave, and the input PWM signal and the first CP signal output by the CP signal generating module 1 achieve the same frequency and anti-phase relationship, and the high-level amplitude of the first CP signal can reach 11.971V, which fully meets the national standard requirements for the first CP signal.

[0064] In one embodiment, the resistance of the first resistor R1 is 1K.

[0065] In one embodiment, the rectifier module 2 includes a rectifier; the input end of the rectifier is electrically connected to the output end of the CP signal generating module 1, and the output end of the rectifier is electrically connected to the input end of the hysteresis comparator circuit 3 and the input end of the voltage follower circuit 4. The function of the rectifier is to chop and rectify the first CP signal to convert the first CP signal into a second CP signal.

[0066] It is understandable that the rectifier includes, but is not limited to, a circuit or hardware device with chopping and rectifying functions.

[0067] In one embodiment, the rectifier includes a diode D1; the anode of diode D1 is electrically connected to the output of CP signal generation module 1, and the cathode of diode D1 is electrically connected to the input of hysteresis comparator circuit 3 and the input of voltage follower circuit 4. Diode D1 enables chopping and rectification of the first CP signal, simplifying the CP signal detection circuit. The first CP signal output by CP signal generation module 1, which is a PWM wave with an amplitude of ±12V and a duty cycle of 53.33%, is converted into a second CP signal after chopping and rectification by the rectifier. The second CP signal is a PWM wave with an amplitude of 0V to 12V and a duty cycle of 53.33%.

[0068] In one embodiment, as shown in FIG2 , the rectifier includes a diode D1 ; an anode of the diode D1 is electrically connected to the other end of the first resistor R1 , a cathode of the diode D1 is electrically connected to the non-inverting input of the third operational amplifier U3 , and is also electrically connected to one end of the fourth resistor R4 .

[0069] In one embodiment, as shown in Figure 2, the hysteresis comparison circuit 3 includes a third operational amplifier U3, a third resistor R3 and a seventh resistor R7; the non-inverting input terminal of the third operational amplifier U3 is electrically connected to the output terminal of the rectifier module 2; the output terminal of the third operational amplifier U3 is electrically connected to the GPIO port of the control module 6; the negative power supply terminal of the third operational amplifier U3 is grounded, and the positive power supply terminal of the third operational amplifier U3 is connected to the power supply voltage VCC; one end of the third resistor R3 is connected to the power supply voltage VCC, and the other end of the third resistor R3 is electrically connected to the inverting input terminal of the third operational amplifier U3; one end of the seventh resistor R7 is grounded, and the other end of the seventh resistor R7 is electrically connected to the inverting input terminal of the third operational amplifier U3.

[0070] The third operational amplifier U3 detects the duty cycle of the first CP signal. When the level of the non-inverting input terminal of the third operational amplifier U3 is greater than the level of the inverting input terminal, the level of the output terminal of the third operational amplifier U3 is equal to the power supply voltage VCC; when the level of the non-inverting input terminal of the third operational amplifier U3 is not greater than the level of the inverting input terminal, the level of the output terminal of the third operational amplifier U3 is 0V. The inverting input terminal of the third operational amplifier U3 is the voltage divided by the third resistor R3 and the seventh resistor R7 on the power supply voltage VCC. The voltage of the inverting input terminal of the third operational amplifier U3 is the reference voltage V REF , so the reference voltage V of the third operational amplifier U3 REF It can be calculated by formula (2): V REF=VCC*R7 / (R3+R7) Formula (2)

[0071] Wherein, in formula (2), R3 is the resistance value of the third resistor R3; R7 is the resistance value of the seventh resistor R7; and VCC is the power supply voltage.

[0072] In some embodiments, the resistance of the third resistor R3 is equal to the resistance of the seventh resistor R7, and the power supply voltage VCC is 5V, so V REF =VCC / 2=2.5V.

[0073] In one embodiment, as shown in Figure 2 , the hysteresis comparator circuit 3 further includes an eighth resistor R8 ; one end of the eighth resistor R8 is electrically connected to the other end of the seventh resistor R7 , and the other end of the eighth resistor R8 is electrically connected to the output of the third operational amplifier U3 . The eighth resistor R8 serves as a hysteresis resistor, and the value of R8 determines the noise margin at the output of U3 . The following detailed analysis assumes a noise margin of 400 mV.

[0074] When the level of the non-inverting input terminal of the third operational amplifier U3 is greater than the level of the inverting input terminal, that is, when V3+>V3-, the level of the output terminal V3O of the third operational amplifier U3 is equal to the power supply voltage VCC, V3O=VCC=5V. At this time, the third resistor R3 and the eighth resistor R8 are connected in parallel and then in series with the seventh resistor R7. The equivalent circuit is shown in Figure 4. At this time, a voltage VOH can be obtained. VOH is calculated by formula (3): VOH=VCC*R7 / (R3 / / R8+R7) Formula (3)

[0075] In formula (3), R3 / / R8 represents the total resistance value of the third resistor R3 and the eighth resistor R8 connected in parallel; R7 is the resistance value of the seventh resistor R7; and VCC is the power supply voltage value.

[0076] When the level of the non-inverting input terminal of the third operational amplifier U3 is not greater than the level of the inverting input terminal, that is, when V3+≤V3-, the level of the output terminal V3O of the third operational amplifier U3 is 0V. At this time, the seventh resistor R7 and the eighth resistor R8 are connected in parallel and then in series. The equivalent circuit is shown in Figure 5. At this time, a voltage VOL can be obtained. VOL is calculated by formula (4): VOL=VCC*(R7 / / R8) / (R7 / / R8+R3) Formula (4)

[0077] In formula (4), R7 / / R8 represents the total resistance value of the seventh resistor R7 and the eighth resistor R8 connected in parallel; R3 is the resistance value of the third resistor R3; and VCC is the power supply voltage value.

[0078] According to VOH-VOL=400mV, the resistance value of the eighth resistor R8 can be calculated.

[0079] Adding a noise margin can effectively address misjudgments caused by high-frequency components attached to the first CP signal. The third operational amplifier U3 outputs the waveform signal CP_CHECK2 to the MCU's GPIO port. As shown in Figure 1, the waveform period corresponding to the high-level time of the waveform signal CP_CHECK2 output by the third operational amplifier U3 can be monitored to detect the CP signal duty cycle.

[0080] In one embodiment, as shown in Figure 2, the voltage follower circuit 4 includes a fourth resistor R4, a fifth resistor R5 and a second operational amplifier U2; one end of the fourth resistor R4 is electrically connected to the output end of the rectifier module; one end of the fifth resistor R5 is electrically connected to the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is grounded; the non-inverting input end of the second operational amplifier U2 is electrically connected to the other end of the fourth resistor R4, the inverting input end of the second operational amplifier U2 is electrically connected to the output end of the second operational amplifier U2, and the inverting input end of the second operational amplifier U2 is electrically connected to the ADC port of the control module 6; the negative power supply of the second operational amplifier U2 is grounded, and the positive power supply of the second operational amplifier U2 is electrically connected to the positive power supply of the third operational amplifier U3.

[0081] In one embodiment, the amplitude of the first CP signal is detected by a voltage follower circuit formed by an operational amplifier. The voltage at the non-inverting input terminal of the second operational amplifier U2 is equal to the voltage at the output terminal. According to the basic characteristics of the operational amplifier, high input impedance and low output impedance, incomplete isolation can be achieved. The voltage at the in-phase input terminal of the second operational amplifier U2 is divided by the fourth resistor R4 and the fifth resistor R5. The first CP signal is also connected to the charging circuit of the electric vehicle. The first resistor R1 and the ground resistance at the vehicle end form a voltage divider, so that the voltage at the charging pile detection point is divided into 12V, 9V, and 6V. Therefore, the voltage V2+ at the in-phase input terminal of the second operational amplifier U2 can be calculated by formula (5): V2+=V 检测点 *R5 / (R4+R5) Formula (5)

[0082] When the voltage at the detection point of the charging pile is 12V, V2+=12*R5 / (R4+R5);

[0083] When the voltage at the detection point of the charging pile is 9V, V2+=9*R5 / (R4+R5);

[0084] When the voltage at the detection point at the charging pile is 6V, V2+=6*R5 / (R4+R5).

[0085] The non-inverting input of the second operational amplifier U2 should be lower than the maximum input voltage of the second operational amplifier U2 and also lower than the maximum withstand voltage of the MCU's ADC pin. Similarly, the minimum value of the non-inverting input of the second operational amplifier U2 must be higher than the minimum input voltage of the second operational amplifier U2 and also higher than the minimum input voltage of the MCU's ADC pin. Furthermore, the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are also limited by the maximum input current of the second operational amplifier U2, which is not detailed here.

[0086] In one embodiment, one end of the fourth resistor R4 is electrically connected to the cathode of the diode D1 .

[0087] It can be understood that the output voltage amplitude signal CP_CHECK1 of the second operational amplifier U2 is connected to the ADC interface of the MCU, and the MCU monitors the current charging state by judging the magnitude of the input voltage.

[0088] In one embodiment, as shown in Figure 1, the CP signal detection circuit further includes a filtering module 5; one end of the filtering module 5 is electrically connected to the output of the second operational amplifier U2, and the other end of the filtering module 5 is grounded. Because the CP signal also contains overshoot and undershoot waveforms, these overshoot signals are unwanted. However, these overshoot signals will be output after entering the second operational amplifier U2. Therefore, the filtering module 5 is added to the output of the second operational amplifier U2 to reduce the overshoot signals in the output waveform of the second operational amplifier U2.

[0089] In one embodiment, as shown in FIG2 , the filter module 5 includes a sixth resistor R6 and a first capacitor C1. One end of the sixth resistor R6 is electrically connected to the output terminal of the second operational amplifier U2, and the other end of the sixth resistor R6 is electrically connected to the inverting input terminal of the second operational amplifier U2. One end of the first capacitor C1 is electrically connected to the other end of the sixth resistor R6, and the other end of the first capacitor C1 is grounded. The sixth resistor R6 and the first capacitor C1 form an RC low-pass filter module, which together effectively reduce overshoot and undershoot in the output waveform of the second operational amplifier U2.

[0090] In one embodiment of the present disclosure, a charging pile is further provided, comprising a charging circuit and a CP signal detection circuit according to any of the above embodiments; the charging circuit is electrically connected to the CP signal detection circuit; the CP signal detection circuit detects the amplitude and duty cycle of the PWM signal output by the charging circuit, thereby improving the charging safety of the entire charging system.

[0091] In one embodiment of the present disclosure, a charging system is further provided, which includes a charging pile, a charging gun and a device to be charged; the charging pile is used to be electrically connected to the charging gun, and the charging gun is used to be electrically connected to the device to be charged.

[0092] It is understandable that the device to be charged includes a battery pack, an electric bicycle, an electric motorcycle or an electric car.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in each of the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of each embodiment of the present disclosure.

Claims

1. A CP signal detection circuit, characterized in that: include: A CP signal generating module, used for processing the received PWM signal to output a first CP signal; a rectifier module, wherein an input end of the rectifier module is electrically connected to an output end of the CP signal generating module, and is used for rectifying the first CP signal to convert it into a second CP signal; a hysteresis comparison circuit, wherein the input end of the hysteresis comparison circuit is electrically connected to the output end of the rectifier module; the output end of the hysteresis comparison circuit is electrically connected to the control module, and the hysteresis comparison circuit is used to output a waveform signal based on the second CP signal to detect the duty cycle of the first CP signal; A voltage follower circuit, wherein the input end of the voltage follower circuit is electrically connected to the output end of the rectifier module, the voltage follower circuit is electrically connected to the control module, and the voltage follower circuit is used to output a voltage amplitude signal based on the second CP signal to detect the amplitude of the first CP signal.

2. The CP signal detection circuit according to claim 1, characterized in that: The hysteresis comparison circuit comprises: A third operational amplifier U3, wherein the in-phase input terminal of the third operational amplifier U3 is electrically connected to the output terminal of the rectifier module; and the output terminal of the third operational amplifier U3 is electrically connected to the GPIO port of the control module; a third resistor R3, one end of the third resistor R3 is connected to the power supply voltage VCC, and the other end of the third resistor R3 is electrically connected to the inverting input end of the third operational amplifier U3; A seventh resistor R7, one end of the seventh resistor R7 is grounded, and the other end of the seventh resistor R7 is electrically connected to the inverting input terminal of the third operational amplifier U3.

3. The CP signal detection circuit according to claim 2, characterized in that: The hysteresis comparison circuit also includes: An eighth resistor R8, one end of the eighth resistor R8 is electrically connected to the other end of the seventh resistor R7 The other end of the eighth resistor R8 is electrically connected to the output end of the third operational amplifier U3.

4. The CP signal detection circuit according to claim 1, characterized in that: The CP signal generating module comprises: A second resistor R2, one end of the second resistor R2 is used to receive a PWM signal; A photocoupler U1, wherein an anode of the photocoupler U1 is electrically connected to the other end of the second resistor R2, a cathode of the photocoupler U1 is grounded, a Vcc pin of the photocoupler U1 is connected to a first power supply VCC0, and a VEE pin of the photocoupler U1 is connected to a second power supply VCC1; An NMOS transistor Q1, wherein the gate of the NMOS transistor Q1 is electrically connected to the output end of the photocoupler U1, and the source of the NMOS transistor Q1 is connected to a second power supply VCC1; A PMOS tube Q2, wherein the gate of the PMOS tube Q2 is electrically connected to the output end of the photocoupler U1, and the source of the PMOS tube Q2 is connected to a first power supply VCC0; A first resistor R1, one end of the first resistor R1 is electrically connected to the drain of the NMOS transistor Q1 and the drain of the PMOS transistor Q2, and the other end of the first resistor R1 is electrically connected to the input end of the rectifier module.

5. The CP signal detection circuit according to claim 1, characterized in that: The voltage follower circuit comprises: a fourth resistor R4, one end of which is electrically connected to the output end of the rectifier module; a fifth resistor R5, one end of the fifth resistor R5 is electrically connected to the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is grounded; A second operational amplifier U2, wherein the non-inverting input terminal of the second operational amplifier U2 is electrically connected to the other end of the fourth resistor R4, the inverting input terminal of the second operational amplifier U2 is electrically connected to the output terminal of the second operational amplifier U2, and the inverting input terminal of the second operational amplifier U2 is also electrically connected to the ADC port of the control module.

6. The CP signal detection circuit according to claim 5, characterized in that: The CP signal detection circuit also includes: A filter module, one end of which is electrically connected to the output end of the second operational amplifier U2, and the other end of which is grounded.

7. The CP signal detection circuit according to claim 6, characterized in that: The filtering module comprises: a sixth resistor R6, one end of the sixth resistor R6 is electrically connected to the output end of the second operational amplifier U2, and the other end of the sixth resistor R6 is electrically connected to the inverting input end of the second operational amplifier U2; A first capacitor C1, one end of the first capacitor C1 is electrically connected to the other end of the sixth resistor R6, and the other end of the first capacitor C1 is grounded.

8. The CP signal detection circuit according to any one of claims 1 to 7, characterized in that: The rectifier module comprises: A rectifier, wherein the input end of the rectifier is electrically connected to the output end of the CP signal generating module, and the output end of the rectifier is electrically connected to the input end of the hysteresis comparator circuit and the input end of the voltage follower circuit.

9. The CP signal detection circuit according to claim 8, characterized in that: The rectifier comprises: A diode D1, wherein the anode of the diode D1 is electrically connected to the output end of the CP signal generating module, and the cathode of the diode D1 is electrically connected to the input end of the hysteresis comparison circuit and the input end of the voltage follower circuit.

10. A charging pile, characterized in that: It comprises a charging circuit and the CP signal detection circuit according to any one of claims 1 to 9; the charging circuit is electrically connected to the CP signal detection circuit.

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