Data backup method and apparatus based on cache line, and processor and computing device

Abstract

A data backup method and apparatus based on a cache line, and a processor and a computing device, all of which belong to the technical field of storage. In the method, in response to a first data write instruction, data in the first data write instruction is written into a first cache line in a cache, such that the state of the first cache line is a modified state; and a backup cache line for the first cache line is stored in the cache. In this method, the modified state indicates that the data in the first cache line is new data, and is not present in other caches and is inconsistent with data in a memory. Therefore, storing the backup cache line for the first cache line in the cache can avoid the problem of data inconsistency caused by an error in the data in the first cache line.

Description

Data backup method, device, processor and computing equipment based on cache line

[0001] This application claims priority to Chinese patent application No. 202311290687.2, filed on September 28, 2023, entitled “Cache line-based data backup method, device, processor and computing device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a cache line-based data backup method, apparatus, processor, and computing device. Background Art

[0003] Cache memory (cache for short) is a high-speed, small-capacity memory located between the central processing unit (CPU) and main memory in the hierarchical structure of a computer's storage system. Cache is divided into L1 cache (L1cache), L2 cache (L2cache), and L3 cache (L3cache). The L1 cache, L2 cache, and L3 cache each move away from the CPU, increasing in capacity and slowing down data access speeds. In a multi-core processor, each core has its own exclusive L1 and L2 cache, while all cores share the L3 cache. When the CPU writes data, it first writes it to the cache; when the CPU reads data, it first queries the cache. Only when the required data is not found in the cache does it read the data from main memory. The unit of data stored in the cache is called a cache line.

[0004] In the related art, when any core in the CPU initiates a write instruction to the memory, the operating system first writes the data corresponding to the write instruction into the cache line in the cache corresponding to the core, and marks the status of the cache line based on the cache consistency protocol (modified exclusive shared invalid, MESI), wherein the status of the cache line is used to indicate the consistency status of the data in the caches corresponding to multiple CPU cores and the memory. For example, if the cache line is marked as modified (modified, M), it indicates that the data in the cache line is new data and is inconsistent with the data that does not exist in other caches and is inconsistent with the data in the memory.

[0005] However, in the above method, since the data in the cache line marked as modified in this cache is inconsistent with the data in other caches and memory and only one copy is stored, the longer the data exists in the cache, the probability of bit flipping of the data will increase significantly, resulting in data errors in the cache, thereby reducing data reliability.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a cache line-based data backup method, apparatus, processor, and computing device, which can improve the reliability of stored data. The technical solution is as follows.

[0008] In a first aspect, a cache line-based data backup method is provided, the method comprising:

[0009] In response to a first data write instruction, the data in the data write instruction is written to a first cache line in the cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory.

[0010] The first data is data corresponding to the first write instruction, and the state of the first data is a modified state, which indicates that the first data is valid, exists only in the cache, and is inconsistent with the data in the memory. The first data meeting the write-back condition means that the first cache line storing the first data needs to be used to store other data or backup data of other data, that is, the data in the first cache line needs to be replaced.

[0011] In the above method, since the state of the first data is a modified state, that is, it only exists in the cache and is inconsistent with the data in the memory, therefore, storing the backup data of the first data in the cache can avoid data inconsistency problems caused by errors in the first data, and only the backup data is stored in the cache for the data in the modified state, while the backup data for the data in the exclusive state (the data is consistent with the data in the memory) and the data in the shared state (the data also exists in other caches and is consistent with the data in the memory) are not stored in the cache, which can avoid excessive occupation of the cache by redundant backup data, thereby ensuring the cache hit rate while ensuring data reliability.

[0012] Optionally, in response to a first data write instruction, writing data in the first data write instruction into a first cache line in a cache includes:

[0013] In response to a write instruction to a memory address, data in the write instruction is written into a first cache line.

[0014] Optionally, in response to a first data write instruction, writing data in the first data write instruction into a first cache line in a cache includes:

[0015] In response to a write-back instruction to the upper-level cache, data in the write-back instruction is written into the first cache line.

[0016] Optionally, the cache includes multiple groups, each group includes multiple cache lines, and storing a backup cache line of the first cache line in the cache includes:

[0017] A backup cache line of the first cache line is stored in the group where the first cache line is located.

[0018] Optionally, storing a backup cache line of the first cache line in the cache group where the first cache line is located includes:

[0019] At least one second cache line is determined in the group where the first cache line is located; and the first cache line is copied to the at least one second cache line.

[0020] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N;

[0021] Determining at least one second cache line in the group where the first cache line is located includes: determining a cache line corresponding to the first cache line in the group where the first cache line is located as the second cache line.

[0022] Optionally, determining at least one second cache line in the group where the first cache line is located includes any one of the following:

[0023] Based on a least recently used algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a first-in-first-out algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

[0024] Among them, the least recently used algorithm (LRU) is used to determine the cache line that has been least accessed in the recent period as the second cache line; the first in first out (FIFO) algorithm is used to determine the cache line with the longest existence as the second cache line; and the random replacement algorithm (RAND, rand) is used to determine the cache line determined by a random number as the second cache line.

[0025] Optionally, copying the first cache line to the at least one second cache line includes:

[0026] If the state of the second cache line is exclusive, shared or invalid, the first cache line is copied to the second cache line; if the state of the second cache line is modified, the data in the second cache line is written back to the memory and the first cache line is copied to the second cache line.

[0027] Among them, the exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in the memory, the shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in the memory, and the invalid state indicates that the data in the second cache line is invalid.

[0028] The second cache line may have stored other data before storing the first data, and the stored data may exist only in the cache, or may exist in both the cache and a memory or other cache. To avoid data loss caused by overwriting data previously stored in the second cache line when copying the first data to the second cache line, the computing device copies the first data to at least one second cache line based on the state of the data already stored in the second cache line.

[0029] Optionally, the first cache line further includes a memory mirroring flag, which is used to indicate whether data in a memory address corresponding to the first cache line has a backup in the memory. Storing a backup cache line of the first cache line in the cache includes:

[0030] If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

[0031] Optionally, the method further includes:

[0032] In response to a read instruction for the memory address, a first cache line and a backup cache line of a second cache line in the cache are respectively checked, where the first cache line is the cache line corresponding to the memory address; if both the first cache line and the backup cache line of the first cache line are successfully checked, the data in the first cache line is returned; if only one of the first cache line and the backup cache line of the first cache line is successfully checked, the data in the cache line where the check succeeds is returned, and the cache line where the check fails is restored based on the cache line where the check succeeds.

[0033] Optionally, the cache line includes a tag, status information, a memory mirroring flag, and data, the tag being used to indicate a memory address corresponding to the cache line, and the method further includes:

[0034] Error checking and correcting (ECC) is used to protect the tag, status information and memory mirror tag in the cache line respectively, and cyclic redundancy check (CRC) is used to protect the data in the cache line.

[0035] Optionally, the method further includes:

[0036] In response to a second data write instruction, the data in the second data write instruction is written into the first cache line in the cache; and the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0037] The second data write instruction may be a write instruction to a memory address or a write-back instruction to an upper-level cache.

[0038] In a second aspect, a cache line-based data backup device is provided, which includes at least one functional module, and the at least one functional module is used to execute the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0039] In a third aspect, a processor is provided, which is used to execute the cache line-based data backup method provided in the first aspect or any possible implementation of the first aspect.

[0040] In a fourth aspect, a computing device is provided, which includes a processor and a memory, the memory storing program code, and the processor being used to execute the program code, so that the computing device executes the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0041] In a fifth aspect, a storage medium is provided, which is used to store at least one section of program code, and the at least one section of program code is used to execute the cache line-based data backup method provided by the first aspect or any possible implementation of the first aspect.

[0042] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0044] FIG2 is a schematic diagram of a cache consistency architecture provided by an embodiment of the present application;

[0045] FIG3 is a flow chart of a cache line-based data backup method provided by an embodiment of the present application;

[0046] FIG4 is a flow chart of a cache line-based data backup method according to an embodiment of the present application;

[0047] 5 is a flow chart of a data reading method in a cache line-based data backup method provided by an embodiment of the present application;

[0048] 6 is a flow chart of a data writing method in a cache line-based data backup method provided by an embodiment of the present application;

[0049] FIG7 is a schematic structural diagram of a cache line-based data backup device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0051] First, the structure of a computing device provided in an embodiment of the present application is introduced.

[0052] As shown in Figure 1, Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. The computing device 100 can be a host, a server, or a personal computer, etc. The computing device 100 can be implemented by a general bus architecture.

[0053] The computing device 100 includes at least one processor 101 , a communication bus 102 , a memory 103 , and at least one communication interface 104 .

[0054] The processor 101 is, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 101 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0055] The communication bus 102 is used to transmit information between the above components. The communication bus 102 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG1 shows only one line, but this does not mean that there is only one bus or one type of bus.

[0056] The memory 103 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 103 is, for example, independent and connected to the processor 101 via the communication bus 102. The memory 103 can also be integrated with the processor 101.

[0057] The communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 104 includes a wired communication interface and may also include a wireless communication interface. The wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0058] As an embodiment, the processor 101 may include one or more CPUs.

[0059] As an embodiment, the computing device 100 may include multiple processors, each of which may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as program code).

[0060] As an embodiment, the computing device 100 may further include an output device and an input device. The output device communicates with the processor 101 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 101 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0061] In some embodiments, the memory 103 is used to store program codes for executing the solution of the present application, and the processor 101 can execute the program codes stored in the memory 103. That is, the computing device 100 can implement the cache line-based data backup method provided by the method embodiment through the processor 101 and the program codes in the memory 103.

[0062] The embodiments of the present application relate to a cache consistency architecture in a computing device. To facilitate understanding of the contents of the embodiments of the present application, several technical terms involved in the cache consistency architecture are explained below in conjunction with FIG2 .

[0063] FIG2 is a schematic diagram of a cache consistency architecture provided in an embodiment of the present application. As shown in FIG2 , the cache consistency architecture includes multiple CPU cores (core0 and core1), a cache memory, and a memory.

[0064] Cache memory (cache, also known as cache or high-speed cache) is a high-speed, small-capacity memory located between the CPU and main memory in the computer storage system hierarchy. When the CPU needs data, it first queries the cache. If the data is not found in the cache, it reads the data from main memory. Cache is divided into Level 1 (L1 cache), Level 2 (L2 cache), and Level 3 (L3 cache). The L1 cache, L2 cache, and L3 cache are located farther away from the CPU, with increasing capacity and decreasing data access speed. When the CPU needs data, it first queries the L1 cache. If the data is not found in the L1 cache, it queries the L2 cache. If the data is not found in the L2 cache, it queries the L3 cache. If the data is not found in the L3 cache, it queries main memory. In a multi-core processor, each core has its own dedicated L1 and L2 cache, while all cores share the L3 cache. Since the data required by the CPU changes over time, some of the data stored in the cache will become data that the CPU rarely accesses over time. This data that the CPU rarely accesses will be written back to the memory level by level to avoid excessive cache usage. Among them, level-by-level write-back means that when the data in the high-level cache meets the write-back condition, the data is written to the low-level cache, and when the data in the lowest-level cache meets the write-back condition, the data is written to the memory. For example, when the data in the first-level cache meets the write-back condition, the data in the first-level cache is written to the second-level cache; when the data in the second-level cache meets the write-back condition, the data in the second-level cache is written to the third-level cache; when the data in the third-level cache meets the write-back condition, the data in the third-level cache is written to the memory.

[0065] A cache line is a unit of data stored in the cache and the smallest unit of data exchange between the cache and the main memory. In some embodiments, the capacity of a cache line is limited to the amount of data that can be accessed within a single main memory (i.e., main memory) storage cycle.

[0066] Entry: In this application, it refers to an entry in the cache that contains a tag, data, and attribute fields, corresponding to a cache line. Among them, tag is used to indicate the memory address, data is used to store data, and attribute is used to store the attribute information of the cache line. For multi-core CPUs, based on the cache consistency protocol, the MESI state is used to describe the state of the data in the cache line. Correspondingly, the attribute field in the entry stores the MESI status of the cache line. The MESI status can be described in Table 1 below. For a single-core CPU, the state of a cache line is described by the value of its target bit (dirty valid). For example, a dirty valid value of 00 indicates that the data in the cache line is invalid (corresponding to the I state in MESI), a dirty valid value of 01 indicates that the data in the cache line is valid and has not been modified (corresponding to the E state in MESI), a dirty valid value of 10 indicates that the state is illegal, and a dirty valid value of 11 indicates that the data in the cache line is valid and has been modified (corresponding to the M state in MESI). Correspondingly, the attribute field in the entry stores the dirty valid value of the data. In some embodiments, the attribute field in the entry also stores a memory mirroring flag (MF), which is used to indicate whether the data in the memory address corresponding to the cache line is backed up in memory.

[0067] Table 1

[0068] Snoop filter (SF): It is part of the cache memory and is at the same level as the third-level cache. It is used to solve the problem of cache consistency. SF will snoop the write instructions of other cores and invalidate the data in the local cache when necessary to ensure the consistency of the same data in the caches corresponding to multiple cores (this process is also called the snoop process). SF records the tag of the cache line, the MESI status, and the core number where the cache line is located. Among them, snooping means that the local core sends the read / write request to other specific cores through the bus, and the core that receives the request responds to the read / write request according to the local situation.

[0069] Write back: When the CPU initiates a write instruction to the memory, it is only temporarily written to the cache and marked with a flag. The data is not written from the cache to the memory until it is evicted, actively flushed, or snooped.

[0070] Based on the cache coherence structure in the computing device described above, an embodiment of the present application provides a cache line-based data backup method, wherein, in response to a first data write instruction, data in the first data write instruction is written to a first cache line in a cache, causing the first cache line to be in a modified state, and a backup cache line of the first cache line is stored in the cache. In the method, the modified state indicates that the data in the first cache line is new, does not exist in other caches, and is inconsistent with data in a memory. Therefore, storing a backup cache line of the first cache line in the cache can avoid data inconsistencies caused by errors in the data in the first cache line. Furthermore, only backup cache lines of cache lines in a modified state are stored in the cache, while backup cache lines of cache lines in an exclusive state (data exists only in the cache and is consistent with data in the memory) or a shared state (data also exists in other caches and is consistent with data in the memory) are not stored in the cache. This method avoids excessive cache usage due to redundant backups, thereby ensuring data reliability while also maintaining a cache hit rate.

[0071] The above describes the basic process of a cache line-based data backup method provided by an embodiment of the present application. The process of this method is described in detail below. Figure 3 is a flowchart of a cache line-based data backup method provided by an embodiment of the present application. As shown in Figure 3, taking the method executed by a computing device as an example, the method includes the following steps 301 to 304.

[0072] 301. In response to a first data write instruction, the computing device writes the data in the first data write instruction to a first cache line in the cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory.

[0073] The first data write instruction may be a write instruction to a memory address. Accordingly, writing the data in the first data write instruction to the first cache line in the cache is equivalent to writing the data in the write instruction to the first cache line. The first data write instruction may also be a write-back instruction to the cache of the previous level. Accordingly, writing the data in the first data write instruction to the first cache line in the cache is equivalent to writing the data in the write-back instruction to the first cache line. The cache refers to the cache corresponding to the CPU core in the computing device that initiates the first data write instruction, including the first-level cache, second-level cache, and third-level cache corresponding to the CPU core. Correspondingly, other caches refer to other caches in the computing device other than the cache corresponding to the CPU core. Since multiple CPU cores share the third-level cache, other caches are also the first-level cache and second-level cache exclusively used by other CPU cores. The cache includes multiple cache lines, each of which stores a tag, data, and attribute information. The attribute information includes the status of the cache line and a memory mirror tag.

[0074] The computing device determines a first cache line in the cache in response to the first data write instruction, and writes the data in the first data write instruction into the determined first cache line.

[0075] The computing device determines the first cache line in the cache using a set-associative mapping approach. In this mapping mode, the cache includes multiple groups, each group includes multiple cache lines. The first character string in the memory address carried by the first data write instruction is a comparison tag, the second character string is a group index, and the third character string is an offset. The process of the computing device determining the first cache line in the cache includes: determining the group corresponding to the group index in the cache based on the group index in the memory address; comparing the comparison tag in the memory address with the tags of multiple cache lines in the determined group; if the tag of any cache line in the group matches the comparison tag (i.e., a write hit), determining the cache line as the first cache line; if the tags of all cache lines in the group do not match the comparison tag and the cache is full (i.e., a write miss and the cache is full), determining a cache line in the cache as the first cache line; if the tags of all cache lines in the group do not match the comparison tag and the cache is not full (i.e., a write miss and the cache is not full), determining any idle cache line in the group as the first cache line. In the above three cases, the process of the computing device writing the data in the first data write instruction into the first cache line is different. The process of writing the data into the first cache line in the above three cases will be introduced below.

[0076] The first case: write hit. The computing device writes the data in the first data write instruction into the first cache line based on the state of the first cache line. If the original state of the first cache line is a modified state or an exclusive state, the computing device directly overwrites the data originally stored in the first cache line with the data in the first data write instruction; if the original state of the first cache line is a shared state, the computing device will snoop (snoop) to let other cores with the same data set the state of the corresponding cache line to an invalid state, so that the state of the first cache line in this cache is an exclusive state, and then overwrite the data originally stored in the first cache line with the data in the first data write instruction. This process can be understood as the need to modify the state of the first cache line to a modified state or an exclusive state before writing data.

[0077] The second situation: the write misses and the cache is full. The computing device writes the data in the first data write instruction to the first cache line based on the state of the first cache line. If the original state of the first cache line is a modified state, the computing device first writes back the data originally stored in the first cache line, and then sets the state of the first cache line to an invalid state; if the original state of the first cache line is an exclusive state or a shared state, the computing device directly sets the state of the first cache line to an invalid state, and notifies the SF to update the state of the first cache line. For the data originally stored in the first cache line, the computing device first queries the state recorded in the SF. If there is no record in the SF, the third-level cache and memory are queried. If other caches store the same data as the first cache line in the cache, the local core uses snoop to let other cores with the same data set the state of the corresponding cache line to an invalid state, and the local core then writes the data in the first data write instruction to the first cache line.

[0078] Case 3: Write miss and cache not full. The calculation first queries the status of the record in the query SF. If there is no record in the SF, the third-level cache and memory are queried. If other caches store the same data as the first cache line in the cache, the local core uses snoop to instruct other cores with the same data to invalidate the corresponding cache line. The local core then writes the data in the first data write instruction to the first cache line.

[0079] 302. The computing device determines at least one second cache line in the group where the first cache line is located.

[0080] Among them, the second cache line is used as a backup cache line for the first cache line, and the number of second cache lines can be set according to actual needs. For example, if the reliability requirement for the data in the first cache line is higher, the number of backup cache lines for the first cache line is greater, that is, the number of second cache lines is greater; if the reliability requirement for the data in the first cache line is lower, the number of backup cache lines for the first cache line is smaller, that is, the number of second cache lines is smaller. The embodiment of the present application does not limit the number of backup cache lines for the first cache line, and thus does not limit the number of second cache lines.

[0081] The computing device determines the second cache line in the group where the first cache line is located based on a fixed strategy or a non-fixed strategy. The following describes the determination of the second cache line under the fixed strategy and the determination of the second cache line under the non-fixed strategy.

[0082] Fixed strategy: The position of the backup cache line corresponding to each cache line is fixed. The group where the first cache line is located includes 2N cache lines, where the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N; the computing device determines the cache line corresponding to the first cache line in the group where the first cache line is located as the second cache line. It should be noted that the above-mentioned cache line correspondence method is only exemplary, and the cache line correspondence method can be determined based on the number of backup cache lines. This embodiment of the present application does not limit this.

[0083] Non-fixed strategy: The position of the backup cache line corresponding to each cache line is not fixed. The process of the computing device determining at least one second cache line in the group where the first cache line is located includes any of the following methods: the first method: based on the least recently used algorithm, determining at least one second cache line in the group where the first cache line is located; the second method: based on the first-in-first-out algorithm, determining at least one second cache line in the group where the first cache line is located; the third method: based on the random replacement algorithm, determining at least one second cache line in the group where the first cache line is located. Among them, the least recently used algorithm (LRU) is used to determine the cache line that has been least accessed in the recent period as the second cache line; the first-in-first-out algorithm (FIFO) is used to determine the cache line with the longest existence time as the second cache line; the random replacement algorithm (RAND, rand) is used to determine the cache line determined according to a random number as the second cache line. It should be noted that the above three replacement algorithms are only exemplary and can be set according to actual needs. The embodiments of the present application do not limit this.

[0084] In some embodiments, the attribute information of the first cache line includes a memory mirroring flag. If the memory mirroring flag in the first cache line indicates that the data in the memory address corresponding to the first cache line has a backup in the memory, the computing device determines at least one second cache line in the group where the first cache line is located to store a backup cache line of the first cache line in the cache. In the above method, the backup of the data is stored on the cache side only when the memory side performs mirroring protection for the data in the memory address corresponding to the first data write instruction, that is, selective mirroring is performed on the cache side. This can avoid the problem of significantly reduced cache side data protection effect due to the cache side performing mirroring while the memory side does not. At the same time, selective mirroring on the cache side can increase the proportion of valid data in the cache while ensuring the reliability of the cache side data, and avoid excessive cache occupation by backup data, which leads to a decrease in cache hit rate.

[0085] 303. The computing device copies the first cache line to at least one second cache line based on a state of the at least one second cache line, so as to store a backup cache line of the first cache line in the cache.

[0086] The second cache line may have stored other data before storing the data in the first cache line, and the stored data may exist only in the cache, or may exist in the cache and in a memory or other cache.

[0087] Taking copying a first cache line to any second cache line as an example, the computing device copies the first cache line to the second cache line based on the state of the second cache line, including: if the state of the second cache line is exclusive, shared or invalid, copying the first cache line to the second cache line; if the state of the second cache line is modified, writing the data in the second cache line back to the memory, and then copying the first cache line to the second cache line.

[0088] It should be noted that the above steps 302 and 303 are one implementation method of storing the backup cache line of the first cache line in the cache. In some embodiments, this step is also implemented based on other methods, which is not limited in the embodiments of the present application.

[0089] 304. In response to the first cache line satisfying the write-back condition, the computing device writes the data in the first cache line back to the memory level by level.

[0090] Among them, the first cache line meeting the write-back condition means that the first cache line needs to be used to store other data or backup data of other data, that is, the data in the first cache line needs to be replaced. Level-by-level write-back means that when the data in the high-level cache meets the write-back condition, the data is written to the low-level cache, and when the data in the lowest-level cache meets the write-back condition, the data is written to the memory. For example, when the data in the first-level cache meets the write-back condition, the data in the first-level cache is written to the second-level cache; when the data in the second-level cache meets the write-back condition, the data in the second-level cache is written to the third-level cache; when the data in the third-level cache meets the write-back condition, the data in the third-level cache is written to the memory. After the computing device writes the first data back to the memory, it updates the record in the listening filter.

[0091] In some embodiments, in response to a first cache line satisfying a write-back condition, the computing device writes the data in the first cache line back to the memory level by level, and invalidates the backup cache lines of the first cache line. In the above method, the first cache line satisfying the write-back condition indicates that the number of CPU accesses to the data in the first cache line has decreased. Writing back the data in the first cache line while invalidating the backup cache lines of the first cache line can avoid excessive cache usage and free up space for data that is frequently accessed by the CPU.

[0092] For a computing device including a multi-core CPU, in some embodiments, if the snoop filter intercepts a read instruction from other cores for the first cache line, the core modifies the state of the first cache line in the cache to a shared state, and modifies the state of the backup cache line of the first cache line to an invalid state; in the above method, when other cores need to read the first cache line, the first cache line is set to a shared state, so that other caches can synchronize the first cache line to meet the possible read requirements of other cores for the first cache line. Other CPU cores do not need to read the first cache line from the memory, which can improve the reading efficiency of the first cache line. At the same time, setting the backup cache line of the first cache line to an invalid state can avoid excessive cache occupation. In other embodiments, if the snoop filter intercepts a write instruction from other cores for the memory address or modifies the state of the cache line corresponding to the memory address in the cache to an exclusive state, the core modifies the state of both the first cache line and the backup cache line of the first cache line in the cache to an invalid state, and writes back the data in the first cache line.

[0093] It should be noted that step 304 is an optional step. In some embodiments, step 304 may not be performed, and the embodiments of the present application do not limit this.

[0094] The following uses FIG4 as an example to illustrate the process shown in step 304 of the above step 301. FIG4 is a flow chart of a cache line-based data backup method provided by an embodiment of the present application. As shown in FIG4, data "Data_x=3" and data "Data_y=2" are stored in the memory. The memory address corresponding to "Data_x=3" is mapped to the cache line of the first group and the first way (that is, the first cache line) in the cache. The memory address corresponding to "Data_y=2" is mapped to the cache line of the first group and the third way in the cache. If the state of the cache line of the first group and the third way is invalid (I), shared (S) or exclusive (E), the process of the computing device executing the cache line-based data backup method includes: Step ①: In response to the CPU executing a write instruction (w rite), request the state of the first cache line of the first group from the snooping filter (SF), and SF returns the state E; modify the data "Data_x=3" in the first cache line of the first group to "Data_x=5", set its state to the modified state (M), and notify SF to update the record; step ②: select one cache line to store the backup cache line: taking the LRU algorithm under the non-fixed strategy as an example, determine that the least recently used cache line in the first group is the third cache line, determine the third cache line of the first group as the second cache line, and the state of the second cache line is I; step ③: copy (copy) the first cache line of the first group to the third cache line of the first group, and set the state of the third cache line of the first group to M. If the state of the 3rd cache line of the 1st group is the modified state (M), the above process is the same. The difference is that before copying the 1st cache line "Data_x=5" of the 1st cache line to the 3rd cache line of the 1st group, the computing device first writes the data in the 3rd cache line of the 1st group back to the memory. The similarities are not repeated here.

[0095] In the above method, the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with the data in the memory. Therefore, storing a backup cache line of the first cache line in the cache can avoid data inconsistency problems caused by errors in the data in the first cache line. In addition, only the backup cache line of the modified cache line is stored in the cache, while the backup cache line of the cache line in the exclusive state (the data exists only in the cache and is consistent with the data in the memory) or the shared state (the data also exists in other caches and is consistent with the data in the memory) is not stored in the cache. This can avoid excessive cache occupation by redundant backups, thereby ensuring data reliability and cache hit rate. Furthermore, the backup cache line of the first cache line is only stored in the cache when the memory side performs mirroring protection for the data at the memory address corresponding to the first write instruction, that is, selective mirroring is performed on the cache side. This can avoid the problem of significantly reduced cache data protection due to mirroring on the cache side but not on the memory side. It can also further increase the proportion of valid data in the cache and further avoid excessive cache occupation by backup cache lines, which may reduce the cache hit rate.

[0096] The above describes the process of a cache line-based data backup method provided by an embodiment of the present application. Based on steps 301 to 303 above, a first cache line and a backup cache line of the first cache line are already stored in the cache. In some embodiments, the computing device can read the data in the first cache line from the cache. The process includes: in response to a read instruction to a memory address, respectively verifying the first cache line and the backup cache line of the second cache line in the cache, where the first cache line is the cache line corresponding to the memory address; if both the first cache line and the backup cache line of the first cache line are verified successfully, the data in the first cache line is returned; if only one of the first cache line and the backup cache line of the first cache line is verified successfully, the data in the cache line that succeeds in verification is returned, and the cache line that fails in verification is restored based on the cache line that succeeds in verification.

[0097] As can be seen from step 302 above, if the computing device determines the second cache line in the group containing the first cache line based on a fixed strategy, the position of the second cache line is fixed, that is, the position of the backup cache line for the first cache line is fixed. If the computing device determines the second cache line in the group containing the first cache line based on a non-fixed strategy, the position of the second cache line is not fixed, that is, the position of the backup cache line for the first cache line is not fixed. The data reading process under a fixed strategy and the data reading process under a non-fixed strategy will be described below.

[0098] A cache line includes a tag, data, and attribute information. The tag indicates the memory address corresponding to the cache line, and the attribute information indicates the state (MESI) and memory mirror flag (MF) of the cache line. If the tag is incorrect, the computing device will not be able to hit the cache; if the data in the cache line is incorrect, the computing device will read incorrect data; if the attribute information is incorrect, the computing device will obtain an incorrect state or memory mirror flag. Therefore, before reading data from the cache, the computing device first verifies the cache line. For cache lines with backup cache lines, error checking and correcting (ECC) is used to protect the tag, state (MESI), and memory mirror flag (MF) in the cache line, and a cyclic redundancy check (CRC) is used to protect the data in the cache line. For cache lines without backup cache lines, ECC is used to protect the cache line. The computing device verifies the cache line according to the verification method corresponding to the above protection method. It should be noted that the above description of the protection method and the verification method is only exemplary. In some embodiments, other methods can also be used to protect and verify the cache line, and the embodiments of the present application do not limit this.

[0099] First, let's introduce the data reading process under a fixed strategy. The following uses the aforementioned verification method as an example to illustrate the data reading process under a fixed strategy. Under a fixed strategy, in response to a read instruction for a memory address, the computing device first verifies multiple cache lines in a target group in the cache according to the aforementioned verification method, and then reads the data based on the verification results. The target group is the group in the cache corresponding to the memory address. The data reading process under a fixed strategy includes the following two cases.

[0100] Case 1: Multiple cache lines are verified successfully. If the tag of any cache line in the multiple cache lines matches the memory address in the read instruction, the computing device returns the data in the cache line. If the tags of none of the cache lines match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next-level cache or memory. The data corresponding to the memory address is then read from the next-level cache or memory, written to the replaced cache line, and the CPU reads the data from the cache again.

[0101] The second situation: the first cache line is verified successfully, but the backup cache line of the first cache line fails to be verified. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line and then copies the first cache line to the backup cache line to restore the backup cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement policy, and writes the cache line back to the next-level cache or memory if the replaced cache line has a backup cache line. The CPU then reads the data corresponding to the memory address from the next-level cache or memory, writes the read data to the replaced cache line, and reads the data from the cache again. If there is still a cache line that fails verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful). If the backup cache lines of multiple cache lines fail verification, the computing device restores the backup cache lines respectively. The recovery process is similar to the process of restoring the backup cache line of the first cache line based on the first cache line in the second case, and will not be repeated here.

[0102] The following describes the data reading process under a non-fixed strategy. The following uses the aforementioned verification method as an example to illustrate the data reading process under a non-fixed strategy. Under a non-fixed strategy, in response to a read instruction for a memory address, the computing device first verifies multiple cache lines in a target group in the cache according to the aforementioned verification method, and reads the data in the cache lines based on the verification results. The target group is the group in the cache corresponding to the memory address. The data reading process under a non-fixed strategy includes the following four situations.

[0103] Case 1: Multiple cache lines are verified successfully. If the tag of any cache line in the multiple cache lines matches the memory address in the read instruction, the computing device returns the data in the cache line. If the tags of none of the cache lines match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next-level cache or memory. The data corresponding to the memory address is then read from the next-level cache or memory, written to the replaced cache line, and the CPU reads the data from the cache again.

[0104] The second scenario: The first cache line is successfully verified, but there is a cache line whose tag fails verification, and the computing device cannot find a backup cache line for the first cache line (that is, the first cache line is not paired). This indicates that the cache line that failed tag verification is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line and then copies the first cache line to the backup cache line to restore the backup cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the computing device writes the cache line back to the next-level cache or memory, then reads the data corresponding to the memory address from the next-level cache or memory, writes the read data to the replaced cache line, and the CPU reads the data from the cache again. If there is still a cache line that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and verification is successful).

[0105] The third scenario: If the first cache line is verified successfully, and there is a cache line with the same tag as the first cache line but with data that fails verification, then this cache line is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line and copies the first cache line to the backup cache line of the first cache line to restore the backup cache line of the first cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement policy. If the replaced cache line has a backup cache line, the computing device writes the cache line back to the next-level cache or memory. The data corresponding to the memory address is then read from the next-level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache. If there is still a cache line that fails verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and verification succeeds).

[0106] The fourth scenario: The first cache line is verified successfully, but multiple cache lines fail tag or data verification, and the computing device cannot find a backup cache line for the first cache line (i.e., the first cache line is not paired). If the tag of the first cache line matches the memory address in the read instruction, the computing device returns the data in the first cache line, and the computing device randomly determines a cache line from the multiple cache lines that failed verification as the backup cache line for the first cache line, and copies the first cache line to the determined backup cache line to restore the backup cache line for the first cache line. If the tags of multiple cache lines do not match the memory address in the read instruction, the computing device determines a cache line to be replaced from the cache based on the replacement policy, and writes the cache line back to the next-level cache or memory if the replaced cache line has a backup cache line. The data corresponding to the memory address is then read from the next-level cache or memory, and the read data is written to the replaced cache line. The CPU then reads the data from the cache. If there is still a cache line that failed verification at this time, the computing device restores the cache line based on its backup cache line (if the cache line has a backup cache line and verification succeeds). If there are multiple unpaired cache lines that originally have backup cache lines, the computing device restores the backup cache lines thereof respectively in the same manner as the first cache line, which will not be described in detail.

[0107] The data reading process described above is illustrated below using Figure 5 as an example. Figure 5 is a schematic diagram of a data reading method in a cache line-based data backup method provided by an embodiment of the present application. As shown in Figure 5, the data "Data_x=3" is stored in the memory, and the memory address corresponding to "Data_x=3" is mapped to the cache line 1 of the first group (which stores the data "Data_x=5", that is, the first cache line) and the cache line 3 of the first group (that is, the backup cache line of the first cache line). The states of the cache line 1 of the first group and the cache line 3 of the first group are both M. Among them, the computing device performs ECC check on multiple cache lines in response to a read instruction of a memory address. The ECC check of the 1st cache line of the 1st group is successful, while the data stored in the 3rd cache line of the 1st group is "Data_x=4". The ECC check of the 3rd cache line of the 1st group fails, then the computing device copies the 1st cache line of the 1st group to the 3rd cache line of the 1st group to perform cache line recovery; when the tag in the 1st cache line of the 1st group matches the memory address, the computing device returns the data in the 1st cache line of the 1st group; when the tag in the 1st cache line of the 1st group does not match the memory address, the computing device reads the data corresponding to the memory address from the next level cache or memory.

[0108] In the above method, since a backup cache line of the first cache line is stored in the cache, when reading data in the first cache line from the cache, if the backup cache line check of the first cache line fails, the data in the first cache line can be read and the backup cache line can be restored based on the first cache line. Similarly, the first cache line can be restored based on the backup cache line, thereby improving data reliability.

[0109] The above describes the process of reading data in the first cache line in the cache. In some embodiments, the computing device can also modify the data in the first cache line, that is, write new data into the first cache line. The process includes: in response to a second data write instruction, writing the data in the second data write instruction into the first cache line in the cache; overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. Before writing data into the cache, the computing device first verifies the cache line. For a cache line with a backup cache line, ECC is used to verify the tag (tag), status (MESI) and memory mirror mark (MF) in the cache line, and CRC is used to verify the data (data) in the cache line; for a cache line without a backup cache line, ECC is used to verify the cache line. It should be noted that the above description of the verification method is only exemplary. In some embodiments, other methods can also be used to verify the cache line, and the embodiments of the present application do not limit this.

[0110] As can be seen from step 302 above, if the computing device determines the second cache line in the group containing the first cache line based on a fixed policy, the position of the second cache line is fixed, i.e., the position of the backup cache line for the first cache line is fixed. If the computing device determines the second cache line in the group containing the first cache line based on a non-fixed policy, the position of the second cache line is not fixed, i.e., the position of the backup cache line for the first cache line is not fixed. The data writing process under a fixed policy and the data writing process under a non-fixed policy will be described below.

[0111] First, we will introduce the data writing process under a fixed strategy. Using the aforementioned verification method as an example, we will illustrate the data writing process under a fixed strategy. Under a fixed strategy, in response to a second data write instruction, the computing device first verifies multiple cache lines in a target group in the cache according to the aforementioned verification method, and then writes data based on the verification results. The target group is the group in the cache corresponding to the memory address. The data writing process under a fixed strategy includes the following two scenarios.

[0112] Case 1: Multiple cache lines are verified successfully. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement policy. If the replaced cache line has a backup cache line, the computing device writes the cache line back to the next-level cache or memory, and then writes the data in the second data write instruction to the determined cache line.

[0113] The second scenario: the first cache line is verified successfully, but the backup cache line of the first cache line fails to be verified. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If a cache line that fails verification still exists at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next-level cache or memory, and the data in the second data write instruction is written to the determined cache line. If a cache line that fails verification still exists at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). Among them, if the backup cache line verification of multiple cache lines fails, the computing device will restore the backup cache lines respectively. The recovery process is the same as the process of restoring the backup cache line of the first cache line based on the first cache line in the second case, and will not be repeated.

[0114] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or the MF indicates that it does not have a backup cache line), the process by which the computing device writes the data in the second data write instruction into the cache is similar to that in the embodiment shown in FIG3 above, and is not further described here. The process by which the computing device writes the data in the second data write instruction into the cache line is also similar to that in the embodiment shown in FIG3 above, and is not further described here.

[0115] The following describes the data writing process under a non-fixed strategy. Taking the above-mentioned verification method as an example, the data writing process under a non-fixed strategy is illustrated. Under a non-fixed strategy, in response to the second data write instruction, the computing device first verifies the multiple cache lines in the target group in the cache according to the above-mentioned verification method, and writes data based on the verification results. The target group is the group in the cache corresponding to the memory address. Among them, for a cache line that has a modified state and has a backup cache line in the cache (that is, the above-mentioned first cache line), the process of the computing device writing data to the first cache line based on the verification result includes the following four situations.

[0116] Case 1: Multiple cache lines are verified successfully. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, overwriting the data in the backup cache line of the first cache line with the data in the second data write instruction. If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement policy. If the replaced cache line has a backup cache line, the computing device writes the cache line back to the next-level cache or memory, and then writes the data in the second data write instruction to the determined cache line.

[0117] The second situation: the first cache line is verified successfully, but there is a cache line whose tag verification fails, and the computing device does not find the backup cache line of the first cache line (that is, the first cache line is not paired), indicating that the cache line whose tag verification fails is the backup cache line of the first cache line. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction into the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that failed the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful); if the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a replaced cache line from the cache based on the replacement strategy, and writes the cache line back to the next level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction into the determined cache line. If there is still a cache line that failed the verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification is successful).

[0118] The third scenario: The first cache line is verified successfully, and there is a cache line with the same tag as the first cache line but the data verification fails. If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If there is still a cache line that failed verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the tags of multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy. If the replaced cache line has a backup cache line, the cache line is written back to the next-level cache or memory, and then the data in the second data write instruction is written to the determined cache line. If there is still a cache line that failed verification at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds).

[0119] The fourth situation: the first cache line is verified successfully, but the tags or data of multiple cache lines fail to be verified, and the computing device cannot find a backup cache line for the first cache line (ie, the first cache line is not paired). If the tag of the first cache line matches the memory address in the second data write instruction, the computing device writes the data in the second data write instruction to the first cache line, and the computing device randomly determines a cache line from the multiple cache lines that failed verification as a backup cache line of the first cache line, and overwrites the data in the backup cache line of the first cache line with the data in the second data write instruction. If a cache line that failed verification still exists at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If the tags of the multiple cache lines do not match the memory address in the second data write instruction, the computing device determines a cache line to be replaced from the cache based on the replacement strategy, and writes the cache line back to the next-level cache or memory if the replaced cache line has a backup cache line, and then writes the data in the second data write instruction to the determined cache line. If a cache line that failed verification still exists at this time, the computing device recovers the cache line based on its backup cache line (if the cache line has a backup cache line and the verification succeeds). If there are multiple unpaired cache lines that originally have backup cache lines, the computing device restores the backup cache lines thereof respectively in the same manner as the first cache line, which will not be described in detail.

[0120] It should be noted that if the cache line hit by the memory address in the second data write instruction does not have a backup cache line (that is, the cache line is not in a modified state or the MF indicates that it does not have a backup cache line), the process by which the computing device writes the data in the second data write instruction into the cache is similar to that in the embodiment shown in FIG3 above, and is not further described here. The process by which the computing device writes the data in the second data write instruction into the cache line is also similar to that in the embodiment shown in FIG3 above, and is not further described here.

[0121] The data writing process described above is illustrated below using Figure 6 as an example. Figure 6 is a flow chart of a data writing method in a cache line-based data backup method provided by an embodiment of the present application. As shown in Figure 6, the data "Data_x=3" is stored in the memory, and the memory address corresponding to "Data_x=3" is mapped to the cache line 1 of the first group (that is, the first cache line, storing the data "Data_x=5") and the cache line 3 of the first group (that is, the backup cache line of the first cache line, storing the data "Data_x=5") in the cache. The states of the cache line 1 of the first group and the cache line 3 of the first group are both M. The process of writing data by a computing device includes: Step ①: in response to the CPU executing a second data write instruction (write) on the 1st cache line of the 1st group in the cache, the data in the 1st cache line of the 1st group is modified from "Data_x=5" to "Data_x=6"; Step ②: copying the data "Data_x=6" in the 1st cache line of the 1st group to the 3rd cache line of the 1st group to achieve backup data synchronization.

[0122] FIG7 is a schematic structural diagram of a cache line-based data backup device provided in an embodiment of the present application. The device includes a writing module 701 and a storage module 702 .

[0123] The write module 701 is configured to, in response to a first data write instruction, write data in the first data write instruction to a first cache line in a cache, so that the state of the first cache line is a modified state, wherein the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with data in a memory;

[0124] The storage module 702 is configured to store a backup cache line of the first cache line in the cache.

[0125] Optionally, the writing module 701 is used to:

[0126] In response to a write instruction to a memory address, data in the write instruction is written into a first cache line.

[0127] Optionally, the writing module 701 is configured to include:

[0128] In response to a write-back instruction to the upper-level cache, data in the write-back instruction is written into the first cache line.

[0129] Optionally, the cache includes multiple groups, each group includes multiple cache lines, and the storage module 702 includes a storage unit:

[0130] A backup cache line of the first cache line is stored in the group where the first cache line is located.

[0131] Optionally, the storage unit is used to:

[0132] At least one second cache line is determined in the group where the first cache line is located; and the first cache line is copied to the at least one second cache line.

[0133] Optionally, the group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N;

[0134] The storage unit is used to determine a cache line corresponding to the first cache line in the group where the first cache line is located as a second cache line.

[0135] Optionally, the storage unit is used for any of the following:

[0136] Based on a least recently used algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a first-in-first-out algorithm, at least one second cache line is determined in the group where the first cache line is located; based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

[0137] Optionally, the storage module 702 is configured to:

[0138] If the state of the second cache line is exclusive, shared or invalid, the first cache line is copied to the second cache line; if the state of the second cache line is modified, the data in the second cache line is written back to the memory and the first cache line is copied to the second cache line.

[0139] Optionally, the first cache line further includes a memory mirroring flag, which is used to indicate whether data in a memory address corresponding to the first cache line is backed up in the memory. The storage module 702 is used to:

[0140] If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

[0141] Optionally, the device further includes a reading module, including:

[0142] a checking unit, configured to check, in response to a read instruction for the memory address, a first cache line and a backup cache line of a second cache line in the cache, respectively, the first cache line being a cache line corresponding to the memory address;

[0143] A return unit is configured to return the data in the first cache line if both the first cache line and the backup cache line of the first cache line are successfully verified; if only one of the first cache line and the backup cache line of the first cache line is successfully verified, return the data in the successfully verified cache line, and recover the cache line that failed to be verified based on the successfully verified cache line.

[0144] Optionally, the cache line includes a tag, status information, a memory mirroring flag, and data, the tag being used to indicate a memory address corresponding to the cache line, and the method further includes:

[0145] The protection module is used to protect the tag, status information and memory mirror tag in the cache line respectively by using error checking and correction (ECC), and to protect the data in the cache line by using cyclic redundancy check (CRC).

[0146] Optionally, the writing module 701 is further configured to:

[0147] In response to a second data write instruction, the data in the second data write instruction is written into the first cache line in the cache; and the data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

[0148] The writing module 701 and the storage module 702 can be implemented by software or hardware. For example, the implementation of the writing module 701 will be described below using the writing module 701 as an example. Similarly, the implementation of the storage module 702 can refer to the implementation of the writing module 701.

[0149] As an example of a software functional unit, the write module 701 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Furthermore, the computing instance may be one or more. For example, the write module 701 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Furthermore, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including one data center or multiple geographically close data centers. Typically, a region may include multiple AZs.

[0150] Similarly, multiple hosts / virtual machines / containers running the code can be distributed within the same virtual private cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Cross-region communication between two VPCs within the same region, or between VPCs in different regions, requires a communication gateway within each VPC to interconnect the VPCs.

[0151] As an example of a hardware functional unit, the write module 701 may include at least one computing device, such as a server. Alternatively, the write module 701 may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0152] The multiple computing devices included in the write module 701 can be distributed in the same region or in different regions. The multiple computing devices included in the write module 701 can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the write module 701 can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of servers, ASICs, PLDs, CPLDs, FPGAs, GALs, and other computing devices.

[0153] It should be noted that, in other embodiments, the steps that the above modules are responsible for implementing can be specified as needed, and the above modules can respectively implement different steps in the cache line-based data backup method to achieve all the functions of the above device. That is, the cache line-based data backup device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate when implementing the cache line-based data backup method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the corresponding method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0154] An embodiment of the present application provides a processor configured to execute a cache line-based data backup method as provided in the aforementioned method embodiment or any possible implementation manner of the method embodiment.

[0155] An embodiment of the present application provides a storage medium for storing at least one segment of program code, which is used to execute a cache line-based data backup method as provided in the aforementioned method embodiment or any possible implementation of the method embodiment.

[0156] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data involved in this application were obtained with full authorization.

[0157] Those skilled in the art will appreciate that the various method steps and units described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0158] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0159] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0160] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0161] In addition, each unit in each embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software units.

[0162] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or partly contributed to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computing device (which can be a personal computer, server, or computing device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0163] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first data write instruction may be referred to as a second data write instruction, and similarly, a second data write instruction may be referred to as a first data write instruction. Both the first data write instruction and the second data write instruction may be write instructions, and in some cases, may be separate and different data write instructions.

[0164] As used herein, the term "at least one" means one or more, and the term "plurality" means two or more. For example, a plurality of cache lines refers to two or more cache lines. The terms "system" and "network" are often used interchangeably herein.

[0165] It should also be understood that the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined that..." or "if [stated condition or event] is detected" may be interpreted to mean "upon determining that..." or "in response to determining that..." or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0166] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0167] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer program instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0168] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired or wireless method. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., a digital video disc (DVD), or a semiconductor medium (e.g., a solid-state drive)), etc.

[0169] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0170] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data backup method based on a cache line, characterized in that: The method comprises: In response to a first data write instruction, write data in the first data write instruction into a first cache line in a cache, so that the state of the first cache line is a modified state, and the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with data in a memory; A backup cache line of the first cache line is stored in the cache.

2. The method according to claim 1, characterized in that The step of writing the data in the first data write instruction to a first cache line in the cache in response to the first data write instruction comprises: In response to a write instruction to a memory address, data in the write instruction is written into the first cache line.

3. The method according to claim 1, characterized in that The step of writing the data in the first data write instruction to a first cache line in the cache in response to the first data write instruction comprises: In response to a write-back instruction to the cache at an upper level, data in the write-back instruction is written into the first cache line.

4. The method according to any one of claims 1 to 3, characterized in that: The cache includes a plurality of groups, each group includes a plurality of cache lines, and a backup cache line of the first cache line is stored in the cache, including: A backup cache line of the first cache line is stored in the group where the first cache line is located.

5. The method according to claim 4, characterized in that The storing a backup cache line of the first cache line in the group where the first cache line is located comprises: determining at least one second cache line in the group where the first cache line is located; The first cache line is copied to the at least one second cache line.

6. The method according to claim 5, characterized in that The group to which the first cache line belongs includes 2N cache lines, wherein the i-th cache line corresponds to the N+i-th cache line, N is an integer greater than 1, and i is an integer greater than or equal to 0 and less than N; The step of determining at least one second cache line in the group where the first cache line is located comprises: A cache line in the group where the first cache line is located and corresponding to the first cache line is determined as the second cache line.

7. The method according to claim 5, characterized in that The determining at least one second cache line in the group where the first cache line is located includes any one of the following: Determine at least one second cache line in the group where the first cache line is located based on a least recently used algorithm; Based on a first-in-first-out algorithm, determining at least one second cache line in the group where the first cache line is located; Based on a random replacement algorithm, at least one second cache line is determined in the group where the first cache line is located.

8. The method according to claim 5, characterized in that The copying the first cache line to the at least one second cache line comprises: If the state of the second cache line is an exclusive state, a shared state or an invalid state, copying the first cache line to the second cache line, the exclusive state indicates that the data in the second cache line does not exist in other caches and is consistent with the data in the memory, the shared state indicates that the data in the second cache line also exists in other caches and is consistent with the data in the memory, and the invalid state indicates that the data in the second cache line is invalid; If the state of the second cache line is a modified state, the data in the second cache line is written back to the memory, and the first cache line is copied to the second cache line.

9. The method according to any one of claims 1 to 8, characterized in that The first cache line further includes a memory mirror mark, and the memory mirror mark is used to indicate whether data in a memory address corresponding to the first cache line is backed up in the memory, and the backup cache line storing the first cache line in the cache includes: If the memory mirror mark in the first cache line indicates that the data in the memory address corresponding to the first data write instruction has a backup in the memory, a backup cache line of the first cache line is stored in the cache.

10. The method according to claim 1, characterized in that The method further comprises: In response to a read instruction to a memory address, respectively checking a first cache line in the cache and a backup cache line of the first cache line, the first cache line being a cache line corresponding to the memory address; If both the first cache line and the backup cache line of the first cache line are verified successfully, returning the data in the first cache line; If only one of the first cache line and the backup cache line of the first cache line is successfully verified, the data in the successfully verified cache line is returned, and the cache line that failed to be verified is restored based on the successfully verified cache line.

11. The method according to claim 1, characterized in that: The cache line includes a tag, status information, a memory mirroring mark and data, the tag is used to indicate a memory address corresponding to the cache line, and the method further includes: Error checking and correction (ECC) is used to protect the tags, status information and memory mirroring tags in the cache line respectively, and cyclic redundancy check (CRC) is used to protect the data in the cache line.

12. The method according to claim 1, characterized in that The method further comprises: In response to a second data write instruction, writing data in the second data write instruction into the first cache line in the cache; The data in the backup cache line of the first cache line is overwritten with the data in the second data write instruction.

13. A data backup device based on a cache line, characterized in that: The device comprises: a writing module, configured to write data in the first data writing instruction into a first cache line in a cache in response to a first data writing instruction, so that the state of the first cache line is a modified state, wherein the modified state indicates that the data in the first cache line is new data, does not exist in other caches, and is inconsistent with data in a memory; A storage module is used to store a backup cache line of the first cache line in the cache.

14. A processor, characterized in that: The processor is used to execute the cache line-based data backup method according to any one of claims 1 to 12.

15. A computing device, characterized in that: The computing device comprises a processor and a memory, wherein the memory stores a program code, and the processor is configured to execute the program code, so that the computing device executes the cache line-based data backup method according to any one of claims 1 to 12.

16. A storage medium, characterized in that: The storage medium is used to store at least one section of program code, and the at least one section of program code is used to execute the cache line-based data backup method according to any one of claims 1 to 12.

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