Memory repair circuit and memory repair method

Abstract

The present invention provides a memory repair circuit and a memory repair method. The memory repair circuit comprises: a primary marking module (1) for determining whether a bit is in a breakdown state, and performing primary marking on a bit in a breakdown state; a flip determination module (2) for determining whether a flip bit exists in a bit group (6), the bit group (6) comprising a plurality of bits on a same bit line, and the flip bit being a bit of which data to be written is 1 and that has undergone primary marking; a secondary marking module (3) for providing a flip flag bit, which corresponds to the bit group (6) one-to-one, the flip flag bit being used to perform secondary marking on the bit group (6) having the flip bit; and a data reading module (4) for outputting data obtained by inverting data read from the flip bit that has undergone secondary marking, and outputting data read from the bit that has only undergone primarily marking and data read from a bit that has not undergone primary marking. The present invention can reduce the cost of bit repair.

Description

Memory repair circuit and memory repair method Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a memory repair circuit and a memory repair method. Background Art

[0002] Due to the immature manufacturing process of existing MRAM (non-volatile magnetic random access memory), many bits in the array may malfunction. For example, some tail bits are difficult to flip, requiring a higher write voltage than normal bits to function properly. Alternatively, some bits may have been broken down, even in an irreversible state, and thus cannot be used normally. This can severely impact the array's yield.

[0003] To use the array function normally, the problematic bits must be removed or replaced with units that can be read and written normally.

[0004] A common existing method is to use redundant cells in rows and columns for repair. However, this method can only replace bits in an entire row or column of the array at a time. Therefore, if a single-digit tailing state bit or / and irreversible breakdown bit occurs in a row or column of the array, thousands of bits in the entire row or column must be replaced, meaning thousands of normally usable bits must be replaced. This undoubtedly wastes resources, increases the cost of bit repair, and reduces bit repair efficiency.

[0005] Summary of the Invention

[0006] To solve the above problems, the memory repair circuit and memory repair method provided by the present invention reduce the cost of bit repair and improve the efficiency of bit repair by setting a primary marking module, a flip judgment module, a secondary marking module and a data reading module.

[0007] In a first aspect, the present invention provides a memory repair circuit, comprising:

[0008] A primary marking module is electrically connected to the bits on the memory, and is used to determine whether the bits are in a breakdown state and to perform a primary marking on the bits in the breakdown state;

[0009] a flip determination module electrically connected to the byte and the primary marking module, for determining whether a flipped bit exists in the byte, wherein the byte includes multiple bits on the same bit line, and the flipped bit is a bit whose data to be written is 1 and has been marked by the primary marking;

[0010] The secondary marking module is electrically connected to the flip judgment module and is used to provide a flip flag bit, the flip flag bit corresponds to the byte one-to-one, and the flip flag bit is used to perform secondary marking on the byte with the flip bit;

[0011] The data reading module is electrically connected to the bit, the primary marking module and the secondary marking module, and is used to output data that is the inversion of the data read from the flipped bit that has passed the secondary marking, and output data read from the bit that has only passed the primary marking and data read from the bit that has not passed the primary marking.

[0012] Optionally, the memory repair circuit further includes:

[0013] The write breakdown module is connected to the bit and is used to break down the burned bit and / or the tailing state bit. The tailing state bit is a bit in the memory that requires a read / write voltage greater than the normal read / write voltage used by the memory during application.

[0014] Optionally, the write breakdown module includes: a first control switch unit, a second control switch unit and a third control switch unit;

[0015] The first control switch unit is connected in series to the common bit line of the byte, the second control switch unit is connected in series to the common source line of the byte, one end of the third control switch unit is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit;

[0016] The first control switch is connected to the first control terminal, the second control switch is connected to the second control terminal, and the third control switch is connected to the third control terminal;

[0017] When a bit is broken down or in a tailing state, the first control terminal controls the first control switch to be turned off, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned on;

[0018] When using normal read and write voltages to read and write bits, the first control terminal controls the first control switch to be turned on, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned off;

[0019] When the bit is not read, written or penetrated, the third control terminal controls the third control switch to be closed.

[0020] Optionally, the first-level marking module includes: a current mirror, a first voltage-type amplifier, and a first reference resistor;

[0021] The current mirror includes a first current output terminal and a second current output terminal, wherein the current output by the first current output terminal is equal to the current output by the second current output terminal;

[0022] The first voltage-type amplifier includes: a first voltage input terminal and a second voltage input terminal;

[0023] The first current output terminal is electrically connected to one end of the bit group and the first voltage input terminal respectively, the second current output terminal is electrically connected to one end of the first reference resistor and the second voltage input terminal respectively, and the other end of the first reference resistor and the other end of the bit group have the same potential;

[0024] The resistance of the first reference resistor is greater than the resistance of the bit in the breakdown state and less than the resistance of the bit in the low resistance state;

[0025] The first voltage type amplifier is used for comparing the potentials of the first voltage input terminal and the second voltage input terminal;

[0026] The primary marking module is further configured to perform a primary marking on the bit connected to the first voltage input terminal when the potential of the first voltage input terminal is less than the potential of the second voltage input terminal.

[0027] Optionally, the first-level marking module further includes: a second voltage-type amplifier and a second reference resistor;

[0028] The second voltage-type amplifier includes: a third voltage input terminal and a fourth voltage input terminal, and the current mirror further includes: a third current output terminal, and the current output by the third current output terminal is equal to the current output by the first current output terminal;

[0029] The third current output terminal is electrically connected to one end of the second reference resistor and the third voltage input terminal respectively, the third voltage input terminal is electrically connected to the first current output terminal, and the other end of the second reference resistor and the other end of the bit group have the same potential;

[0030] The resistance of the second reference resistor is greater than the resistance of the bit in the low-resistance state and less than the resistance of the bit in the high-resistance state;

[0031] The second voltage type amplifier is used for comparing the potentials of the first voltage input terminal and the third voltage input terminal;

[0032] The primary marking module is further configured to output data read from the bit connected to the first voltage input terminal according to a comparison result of the second voltage-type amplifier.

[0033] Optionally, the primary marking module is further configured to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, so as to perform a primary marking on the bit in the breakdown state, and assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state;

[0034] The flip judgment module includes: an OR gate and multiple AND gates;

[0035] Multiple AND gates correspond one-to-one to the bits in the byte group, and one input end of each of the AND gates is electrically connected to the primary marking module to obtain the data written in the judgment bit corresponding to the corresponding bit; another input end of each of the AND gates is connected to the data writing end of the corresponding bit to obtain the data to be written corresponding to the bit;

[0036] The OR gate is electrically connected to the output ends of the plurality of AND gates; the output end of the OR gate is electrically connected to the secondary marking module to write the output value into the flip flag bit.

[0037] Optionally, the secondary marking module is further configured to vote on the values ​​read from the plurality of marking bits and output a majority of identical values ​​as a flip flag value, the flip flag value being used to distinguish whether a flip bit exists in the corresponding byte group;

[0038] The data reading module is also used to output data according to the flip flag value and the marking result of the first-level marking module.

[0039] Optionally, the data reading module includes: a bit reader, a buffer, an inverter, a logic judge and a multiplexer;

[0040] The input end of the bit reader is electrically connected to the bit, the output end of the bit reader is electrically connected to the input end of the buffer and the input end of the inverter respectively, the input end of the multiplexer is electrically connected to the output end of the buffer and the output end of the inverter respectively, the enable end of the multiplexer is electrically connected to the output end of the logic determiner, and the input end of the logic determiner is electrically connected to the secondary marking module and the primary marking module respectively;

[0041] The multi-logic judge is used to judge whether the bit connected to the bit reader is a flipped bit through the secondary marking module and the primary marking module; if so, output a first enable signal; if not, output a second enable signal;

[0042] The multiplexer is configured to be connected to the inverter when receiving a first enable signal, and to be connected to the buffer when receiving a second enable signal.

[0043] In a second aspect, the present invention provides a method for repairing a memory, comprising:

[0044] Reading the value in the judgment bit of the bit to determine whether the bit is in a breakdown state according to the value in the judgment bit, the judgment bit is used to perform a primary mark on the bit in the breakdown state;

[0045] Determine whether there is a flip bit in the byte; if so, perform a secondary marking on the byte by using a flip flag bit; wherein the byte includes multiple bits on the same bit line, and the flip bit is a bit that has the data to be written as 1 and has been marked by the primary flag;

[0046] When performing a read operation on a bit, the judgment bit and the flip flag bit corresponding to the bit are read to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, the data obtained by inverting the data read from the flipped bit that has been secondarily marked is output; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, the data read from the bit is output.

[0047] Optionally, before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the method further includes:

[0048] Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

[0049] Optionally, the determination bit marks a value of 1 for a bit in a breakdown state and a value of 0 for a bit not in a breakdown state;

[0050] The flip flag has a value of 1 for bytes marked with secondary marking and a value of 0 for bytes not marked with secondary marking.

[0051] Optionally, the step of reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes:

[0052] Equal currents are applied to the bit and a first reference resistor, respectively, and the resistance of the bit is compared with the resistance of the first reference resistor. The resistance of the first reference resistor is greater than the resistance of the bit in the breakdown state and less than the resistance of the bit in the low-resistance state. If the resistance of the bit is less than the resistance of the first reference resistor, the bit is determined to be in the breakdown state. If the resistance of the bit is greater than the resistance of the first reference resistor, the bit is determined to be not in the breakdown state.

[0053] Optionally, when performing a read operation on a bit, reading a determination bit and a flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, outputting data obtained by inverting the data read from the secondarily marked flipped bit; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, outputting the data read from the bit comprises:

[0054] Equal currents are applied to the bit and the second reference resistor, respectively, and the resistance of the bit is compared with the resistance of the second reference resistor. The resistance of the second reference resistor is greater than the resistance of the bit in the low-resistance state and less than the resistance of the bit in the high-resistance state. If the resistance of the bit is less than the resistance of the second reference resistor, the data read from the bit is determined to be 0. If the resistance of the bit is greater than the resistance of the second reference resistor, the data read from the bit is determined to be 1.

[0055] Optionally, determining whether there is a flip bit in the byte; and if so, performing a secondary marking on the byte where the bit is located by using the flip flag bit includes:

[0056] Determine whether there is a flip bit in the byte; if so, set the flip flag to 1 to mark the byte secondary through the flip flag; otherwise, set the flip flag to 0 low.

[0057] Optionally, the flip flag bit includes a plurality of mark bits;

[0058] The steps of determining whether a flip bit exists in a byte; if so, setting a flip flag to 1 to perform secondary marking on the byte by the flip flag; if not, setting the flip flag to 0, include:

[0059] Determine whether a flip bit exists in the byte; if so, set multiple flag bits to high to perform secondary marking on the byte by using multiple flip bits; if not, set multiple flip bits to 0;

[0060] When performing a read operation on a bit, the judgment bit and flip flag bit corresponding to the bit are read to determine whether the bit is in a breakdown state and whether the byte group where the bit is located has been secondary marked. This includes:

[0061] By voting on the values ​​read from multiple flag bits, the majority of the same values ​​are output as the flip flag value. The flip flag value is used to distinguish whether there is a flip bit in the corresponding byte.

[0062] The memory repair circuit and memory repair method provided by the embodiments of the present invention can accurately mark the flipped bits by setting a primary marking module, a flip judgment module, a secondary marking module and a data reading module, and flip the data originally stored in the bits when reading data. There is no need to set redundant bits to replace bits in a breakdown state, thereby reducing the cost of bit repair and improving the efficiency of bit repair. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0064] FIG1 is a schematic structural diagram of a memory repair circuit according to an embodiment of the present application;

[0065] FIG2 is a schematic structural diagram of a write breakdown module according to an embodiment of the present application;

[0066] FIG3 is a schematic structural diagram of a primary marking module according to an embodiment of the present application;

[0067] FIG4 is a schematic structural diagram of a rollover determination module according to an embodiment of the present application;

[0068] FIG5 is a schematic structural diagram of a data reading module according to an embodiment of the present application;

[0069] FIG6 is a schematic diagram of relative positions of bits according to an embodiment of the present application;

[0070] FIG7 is a schematic diagram showing the corresponding relationship between the determination bit and the bit element according to an embodiment of the present application;

[0071] FIG8 is a diagram showing the corresponding relationship between the data stored in each bit after data is written in one embodiment of the present application;

[0072] FIG9 is a diagram showing the corresponding relationship between the data stored in each bit after data is written according to an embodiment of the present application;

[0073] FIG10 is a logic diagram of inverted readout data according to an embodiment of the present application;

[0074] FIG11 is a logic diagram of normal data reading according to an embodiment of the present application;

[0075] FIG12 is a schematic flowchart of a memory repair method according to an embodiment of the present application. DETAILED DESCRIPTION

[0076] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0078] In a first aspect, an embodiment of the present invention provides a memory repair circuit. Referring to FIG1 , the memory repair circuit includes:

[0079] The primary marking module 1 is electrically connected to the bits on the memory and is used to determine whether the bits are in a breakdown state and to perform a primary marking on the bits in the breakdown state;

[0080] The flip judgment module 2 is electrically connected to the byte 6 and the primary marking module 1, and is used to determine whether there is a flipped bit in the byte 6, wherein the byte 6 includes multiple bits on the same bit line, and the flipped bit is a bit whose data to be written is 1 and has been marked by the primary marking:

[0081] The secondary marking module 3 is electrically connected to the flip judgment module 2 and is used to provide a flip flag bit, which corresponds one-to-one to the byte 6. The flip flag bit is used to perform secondary marking on the byte 6 with the flipped bit;

[0082] The data reading module 4 is electrically connected to the bit, the primary marking module 1 and the secondary marking module 3, and is used to output the data that is the inversion of the data read from the flipped bit that has passed the secondary marking, and output the data read from the bit that has only passed the primary marking and the data read from the bit that has not passed the primary marking.

[0083] By setting a primary marking module 1, a flip judgment module 2, a secondary marking module 3 and a data reading module 4, the memory repair circuit can accurately mark flipped bits and flip the data originally stored in the bits when reading data. There is no need to set redundant bits to replace bits in a breakdown state, thereby reducing the cost of bit repair and improving the efficiency of bit repair.

[0084] Furthermore, the memory repair circuit also includes a write-through module 5. This write-through module 5 is connected to the bits and is used to break down burned bits and / or tailing bits. Tailing bits are bits in the memory that require a read / write voltage greater than the normal read / write voltage used by the memory during operation. A single write-through module 5 can break down bits in one or more groups of bits, which is not specifically limited in this embodiment.

[0085] In this embodiment, write-through module 5 is used to break down burned bits and tailing bits. This prevents burned bits and tailing bits from being read or written as normal bits, thereby affecting the yield of the data storage array. Specifically, after the write-through module 5 breaks down the burned bits and tailing bits, the memory repair circuit can, when reading data, invert the data read from the bits in the broken state where the data to be written is 1, thereby ensuring the yield of the data storage array.

[0086] 2 , the write breakdown module 5 includes: a first control switch unit M1 , a second control switch unit M2 and a third control switch unit M3 .

[0087] The first control switch unit M1 is connected in series to the common bit line of byte 6, the second control switch unit M2 is connected in series to the common source line of byte 6, one end of the third control switch unit M3 is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit M1.

[0088] The first control switch is connected to the first control terminal, the second control switch is connected to the second control terminal, and the third control switch is connected to the third control terminal.

[0089] When a bit is being burned or in a tailing state, the first control terminal turns off the first control switch, the second control terminal turns on the second control switch, and the third control terminal turns on the third control switch. When reading or writing a bit using normal read / write voltages, the first control terminal turns on the first control switch, the second control terminal turns on the second control switch, and the third control terminal turns off the third control switch. When a bit is not being read or written, or when a bit is being burned, the third control terminal turns off the third control switch.

[0090] In other words, in this embodiment, the first control end controls the on and off of the first control switch by receiving the CSL1 signal, the second control end controls the on and off of the second control switch by receiving the CSL2 signal, and the third control end controls the on and off of the third control switch by receiving the Break_down_EN signal.

[0091] Specifically, when the CSL1, CSL2 and Break_down_EN signals are all low, the first control switch, the second control switch and the third control switch are all in the off state, and the bits in byte group 6 are not read or written.

[0092] When the CSL1 and CSL2 signals are both high and the Break_down_EN signal is low, the first control switch and the second control switch are both open and the third control switch is closed. At this time, normal read and write operations can be performed on the bits in byte group 6.

[0093] When the CSL1 signal is low and the CSL2 and Break_down_EN signals are both high, the first control switch is in the closed state, and the second control switch and the third control switch are both in the open state. At this time, the bit of byte group 6 can be written and destroyed. In this state, the voltage loaded across the selected MTJ can short-term breakdown of the selected MTJ, thereby realizing the write-destroy function.

[0094] 3 , the first-level marking module 1 includes: a current mirror 11 , a first voltage-type amplifier SA2 , and a first reference resistor 12 .

[0095] The current mirror 11 includes a first current output terminal and a second current output terminal, and the current output by the first current output terminal is equal to the current output by the second current output terminal; the first voltage amplifier SA2 includes a first voltage input terminal and a second voltage input terminal.

[0096] The first current output terminal is electrically connected to one end of the byte 6 and the first voltage input terminal respectively. The second current output terminal is electrically connected to one end of the first reference resistor 12 and the second voltage input terminal respectively. The other end of the first reference resistor 12 and the other end of the byte 6 have the same potential.

[0097] The resistance of the first reference resistor 12 is greater than the resistance of the bit in the breakdown state and less than the resistance of the bit in the low resistance state; the first voltage amplifier SA2 is used to compare the potential of the first voltage input terminal and the second voltage input terminal; the first marking module 1 is also used to

[0098] When the potential of the first voltage input terminal is less than the potential of the second voltage input terminal, a first-level mark is performed on the bit connected to the first voltage input terminal.

[0099] It should be noted that the other end of the first reference resistor 12 and the other end of the byte 6 can be connected to the same connection point to achieve the same potential, or they can be connected to different circuit structures to achieve the same potential. In this embodiment, when the first voltage-type amplifier SA2 is used to compare the potentials of the first voltage input terminal and the second voltage input terminal, the other end of the first reference resistor 12 and the other end of the byte 6 are both grounded.

[0100] Similarly, in addition to using the current mirror 11 to ensure that the current input to the first reference resistor 12 and the byte 6 is the same, the first reference resistor 12 and the byte 6 can also be connected in series to ensure that the current input to the two is the same. However, this method requires adjustment to the specific circuit structure of the primary marking module 1. The first voltage-type amplifier SA2 detects the voltage drop across the first reference resistor 12 and the voltage drop across the byte 6 respectively, and performs a primary marking on the bit connected to the first voltage input terminal when the voltage drop across the byte 6 is greater than the voltage drop across the first reference resistor 12. The circuit structure of this method is not described in detail in this embodiment.

[0101] In this embodiment, the current mirror 11 is used to ensure that the current input to the first reference resistor 12 and the current input to the byte 6 are the same, and the structure of the primary marking module 1 is simplified, thereby reducing the complexity of the memory repair circuit.

[0102] In an optional embodiment, the primary marking module 1 further includes: a second voltage-type amplifier SA1 and a second reference resistor 13 .

[0103] The second voltage-type amplifier SA1 includes a third voltage input terminal and a fourth voltage input terminal. The current mirror 11 also includes a third current output terminal. The current output by the third current output terminal is equal to the current output by the first current output terminal.

[0104] The third current output terminal is electrically connected to one end of a second reference resistor 13 and the third voltage input terminal, respectively. The third voltage input terminal is electrically connected to the first current output terminal. The other end of the second reference resistor 13 and the other end of the bit 6 have the same potential. The resistance of the second reference resistor 13 is greater than the resistance of the bit in the low-resistance state and less than the resistance of the bit in the high-resistance state.

[0105] The second voltage amplifier SA1 is used to compare the potentials of the first voltage input terminal and the third voltage input terminal. The primary marking module 1 is also used to output data read from the bit connected to the first voltage input terminal based on the comparison result of the second voltage amplifier SA1.

[0106] It should be noted that the other end of the second reference resistor 13 and the other end of the bit 6 can be connected to the same connection point to achieve the same potential, or they can be connected to different circuit structures to achieve the same potential. In this embodiment, when the second voltage-type amplifier SA1 is used to compare the potentials of the third voltage input terminal and the fourth voltage input terminal, the other end of the second reference resistor 13 and the other end of the bit 6 are both grounded.

[0107] Similarly, in addition to using the current mirror 11 to ensure that the current input to the second reference resistor 13 and the byte 6 is the same, the second reference resistor 13 and the byte 6 can also be connected in series to achieve the same current input to the two. However, this method requires adjustment to the specific circuit structure of the first-level marking module 1, including the second voltage-type amplifier SA1 that respectively detects the voltage drop across the second reference resistor 13 and the voltage drop across the byte 6. This embodiment does not elaborate on the circuit structure of this method.

[0108] In this embodiment, the current mirror 11 is used to ensure that the current input to the second reference resistor 13 and the current input to the byte 6 are the same, and the structure of the primary marking module 1 is simplified, thereby reducing the complexity of the memory repair circuit.

[0109] Furthermore, the first-level marking module 1 uses two voltage-type sensitive amplifiers, namely the first voltage-type amplifier SA2 and the second voltage-type amplifier SA1, the first reference resistor 12, the second reference resistor 13 and the current mirror 11 to realize the function. The working principle of the first-level marking module 1 is described in detail below.

[0110] The primary marking module 1 uses a current mirror 11 to separate the array current Iarray flowing into the byte 6, the determination bit reference current Ired flowing into the first reference resistor 12, and the array reference current Iref flowing into the second reference resistor 13. Due to the action of the current mirror 11, the three currents have the same value. The branches containing the array current Iarray and the array reference current Iref are connected to a second voltage-source amplifier SA1, while the branches containing the array current Iarray and the determination bit reference current Ired are connected to a first voltage-source amplifier SA2. The resistance of the second reference resistor 13 connected to the branch containing the array reference current Iref is lower than the resistance of the MTJ in the RAP state (high-impedance state) and higher than the resistance of the MTJ in the RP state (high-impedance state). The resistance of the first reference resistor 12 connected to the branch containing the determination bit reference current Ired is higher than the resistance of the MTJ in the break-down state (breakdown state) and lower than the reference resistance of the MTJ in the RP state. The resistance relationship is: MTJ RAP state > MTJ RP state > MTJ break-down state.

[0111] Because the resistance downstream of each branch varies, the voltage at the access point also varies. The corresponding voltage-sensing amplifier can compare the two voltages. When the voltage at the access point of the branch containing array current Iarray is higher than the voltage at the access point of the branch containing array current Iref, it indicates that the resistance in array current Iarray is greater than second reference resistor 13. In this case, the connected bit is in the RAP state, and the second voltage-sensing amplifier SA1 reads a 1. When the voltage at the access point of the branch containing array current Iarray is lower than the voltage at the access point of the branch containing array reference current Iref, it indicates that the resistance in array current Iarray is less than second reference resistor 13. In this case, the connected bit is in the RP state, and the second voltage-sensing amplifier SA1 reads a 0.

[0112] Similarly, the first voltage-source amplifier SA2 can output the comparison result between the array resistance and the judgment bit reference resistance. If the array resistance is greater than the first reference resistance 12, the connected bit is normal, and the first voltage-source amplifier SA2 outputs a 0. If the array resistance is less than the first reference resistance 12, the bit is in a breakdown state, and the first voltage-source amplifier SA2 outputs a 1. In other words, the primary marking module 1 is also used to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, thereby performing a primary marking on the bit in the breakdown state; and to assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state.

[0113] It should be noted that the judgment bit can be provided by an additional storage module, such as a register, or by the bit corresponding to the judgment bit itself. In this embodiment, the judgment bit is provided by the corresponding bit itself. It can be understood that the bit stores both the judgment bit and the data bit. In other words, the bit in the memory has three storage states, namely, 0 state, 1 state, and X state. Among them, the data bit in the bit corresponds to the bit's 0 state and 1 state; the judgment bit in the bit corresponds to the bit's X state.

[0114] The resistance of a bit in different storage states varies. The X state, also known as the short state, has a very low resistance. For example, the resistance of a bit in the 1 state is 10kOhm, the resistance of a bit in the 0 state is 3kOhm, and the resistance of a bit in the X state is only 200Ohm, but this is not limited to these values. When a bit in the breakdown state is marked at the first level, it is in the X state.

[0115] In this embodiment, the advantage of using two voltage-type sense amplifiers is that the voltage of the connected bit can be simultaneously compared with the voltages at both the first reference resistor 12 and the second reference resistor 13, and two results can be output. For example, when SA1 = 1 and SA2 = 1, the connected bit is determined to be in the rap state; when SA1 = 0 and SA2 = 1, the connected bit is determined to be in the rp state; and when SA1 = 0 and SA2 = 0, the connected bit is determined to be in the break down state. It should be noted that in this embodiment, the situation where SA1 = 1 and SA2 = 0 does not exist, and this will not be further described.

[0116] It is understood that a primary marking module 1 can perform primary marking on bits in one or more groups of bytes 6. Specifically, when the data storage array is small, a primary marking module 1 can be electrically connected to a corresponding group of bytes 6. For example, if the data storage array is 30*30 in size and has a bit width of 30 bits, the data storage array includes 30 groups of bytes and 30 primary marking modules 1. Each group of bytes is electrically connected to a primary marking module 1. In this way, each primary marking module 1 performs primary marking on the corresponding bytes.

[0117] When the data storage array is large, the first-level marking module 1 can be electrically connected to multiple groups of bytes 6. In conjunction with Figure 3, if the size of the data storage array is 1024*1024 and its bit width is 16 bits, then the data storage array includes 30 groups of bytes and 30 first-level marking modules 1, and every 64 groups of bytes are electrically connected to a first-level marking module 1. In this way, each first-level marking module 1 performs first-level marking on the corresponding 64 groups of bytes. It should be noted that in order to ensure that the first-level marking module 1 can perform first-level marking on the bits in the corresponding 64 groups of bytes in an orderly manner, the 64 groups of bytes are selectively electrically connected to the corresponding first-level marking module 1 through a multiplexer (MUX). It can be understood that in this data storage array, 64 groups of bytes correspond to one bit width. When reading the data stored in the bit, the multiplexer will connect the byte where the bit selected by the word line is located as the target byte to the first-level marking module 1.

[0118] In this embodiment, one primary tag module 1 corresponds to 64 bytes 6 as an example, but the present invention is not limited thereto.

[0119] 4 , the flip judgment module 2 includes: an OR gate and multiple AND gates.

[0120] Multiple AND gates correspond one-to-one with the bits in byte group 6. One input of each AND gate is electrically connected to the primary marking module 1 to retrieve the data written in the judgment bit corresponding to the corresponding bit. Another input of each AND gate is electrically connected to the data writing terminal of the corresponding bit to retrieve the data to be written to the corresponding bit. An OR gate is electrically connected to the output of each AND gate. The output of the OR gate is electrically connected to the secondary marking module 3 to write the output value into the flip flag bit.

[0121] In this embodiment, the flip determination module 2 corresponds one-to-one with each byte 6. An input terminal of each AND gate is electrically connected to the output terminal of the first voltage-source amplifier SA2 in the primary flag module 1. It should be noted that when the first voltage-source amplifier SA2 is electrically coupled to different bits in the byte 6, it receives different enable signals (SA_flag0, SA_flag1, SA_flag2, ..., SA_flagn) to electrically couple the first voltage-source amplifier SA2 with the corresponding AND gate, thereby transmitting the determination bit data (X DATA0, X DATA1, X DATA2, ..., X DATAn) output by the second voltage-source amplifier SA2 to the corresponding AND gate. Simultaneously, the AND gate receives the storage data to be written to the corresponding bit by the write driver.

[0122] It should be noted that n is determined by the bit width of the data storage array. For example, if the bit width of the data storage array is 16, n is 16.

[0123] By setting up a flip judgment module 2, the result of the read judgment bit is used to select the data written to the flip flag bit. Specifically, if the judgment bits in the group are all low, that is, the data stored in all the judgment bits in byte group 6 are all 0, then the flip flag bit is written to 0; if there is a high bit in the judgment bit in the group, that is, there is a judgment bit in which the data stored in all the judgment bits in byte group 6 are all 1, and the data to be written in the bit corresponding to the high-bit judgment bit is 0, then the flip flag bit is still written to 0. If there is a high bit in the judgment bit in the group, and the data to be written in the bit corresponding to the high-bit judgment bit is 1, then the flip flag bit of this group is written to 1. The reason is that the broken-down bit can only read 0. When the data to be written is 1, it is inverted by flipping the flag bit during reading, so that the purpose of repairing the broken-down bit can be achieved.

[0124] 5 , the data reading module 4 includes a bit reader 41 , a buffer 42 , an inverter 43 , a logic determiner 44 and a multiplexer 45 .

[0125] Among them, the input end of the bit reader 41 is electrically connected to the bit; the output end of the bit reader 41 is electrically connected to the input end of the buffer 42 and the input end of the inverter 43 respectively; the input end of the multiplexer 45 is electrically connected to the output end of the buffer 42 and the output end of the inverter 43 respectively; the enable end of the multiplexer 45 is electrically connected to the output end of the logic judge 44; the input end of the logic judge 44 is electrically connected to the secondary marking module 3 and the primary marking module 1 respectively; the output end of the multiplexer 45 outputs data as the output end of the data reading module 4.

[0126] Multi-logic determiner 44 is used to determine whether the bit connected to bit reader 41 is a flipped bit through secondary flag module 3 and primary flag module 1. If so, it outputs a first enable signal; if not, it outputs a second enable signal. Multiplexer 45 is used to connect to inverter 43 when it receives the first enable signal and to connect to buffer 42 when it receives the second enable signal.

[0127] A data read module 4 can read data from bits in one or more groups of bytes. In this embodiment, each data read module 4 corresponds to multiple groups of bytes, i.e., each data read module 4 corresponds to a primary tag module. The logic determiner 44 is an AND gate device. The input of the bit reader 41 is electrically coupled to the output of the second voltage-source amplifier SA1, thereby electrically connecting to the bit. The logic determiner 44 is electrically coupled to the output of the first voltage-source amplifier SA2 to determine whether the connected bit is in a breakdown state.

[0128] It can be understood that in this embodiment, the bit reader 41 is the second voltage-type amplifier SA1 .

[0129] Furthermore, the secondary marking module 3 is further configured to vote on the values ​​read from the multiple marking bits and output the value with the same majority as the flip flag value. The flip flag value is used to distinguish whether a flip bit exists in the corresponding byte group 6. The data reading module 4 is further configured to output data based on the flip flag value and the marking result of the primary marking module 1.

[0130] In this embodiment, the secondary marking module 3 outputs three sets of flip flag values ​​from a triple-modular redundant (3-bit) array in the memory's data storage array, but this is not limited to this. This triple-modular redundant array, consistent with a normal data storage array, votes through the three flip flag bits to obtain a single result (1 bit), which is output as the final flip flag. The triple-modular redundant array ensures the accuracy of the memory repair circuit's repairs and prevents erroneous data inversion errors caused by corrupted bits occupied by a single flip flag bit, which could affect read operations.

[0131] In this embodiment, with reference to FIG6 , eight array bits (Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7) are configured with three flip flags (Flag0, Flag1, Flag2), forming a data group, to illustrate the operating principle of the aforementioned memory repair circuit. The eight array bits constitute a group of byte 6; the number of array bits and determination flags can be any number and is not specifically limited in this embodiment. Array bit Data2 was tested and found to be in a tailing state.

[0132] First, a write / destroy operation is performed on array bit Data2. Specifically, array bit Data2 is selected and M1 is driven off, M2 is driven on, and M3 is driven on. This creates a path, causing the voltage applied to the MTJ to be too high, causing the MTJ (magnetic tunnel junction) in array bit Data2 to burn out. The write operation is not performed on the remaining unselected cells. At this point, the resistance of array bit Data2 drops from several thousand ohms to several hundred ohms, far less than the resistance of a normal MTJ. This completes the write / destroy operation on array bit Data2. Subsequent read and write operations on byte group 6 can then proceed normally.

[0133] Afterwards, when performing a write operation, the operation of reading the judgment bit is performed first, wherein the judgment bit read out of a normal bit is 0, and the judgment bit read out of a bit in a breakdown state is 1, as shown in FIG7 . Since the array bit Data2 was previously written out, the judgment bit corresponding to the array bit Data2 in the judgment bits read out is high. At this time, it is necessary to compare the data to be written into the array bit Data2. At this time, the data to be written corresponding to the array bit Data2 is 1. According to the corresponding logic circuit, when the judgment bit corresponding to the bit is high, and the data to be written to the bit corresponding to this judgment bit is high, the three flip flag bits of this group are all set to 1 and written, as shown in FIG8 . However, when the judgment bit is high and the data to be written to the bit corresponding to this judgment bit is low, or when the judgment bits in the group are all low, the three flip flag bits are all set to 0 and written, and the data are directly written into the corresponding array bits, as shown in FIG9 .

[0134] Finally, during a read operation, all data stored within the three flip flags and eight array bits must be read and processed, with output based on the status of the three flip flags within the group. Referring to Figure 10 , even if one of the three flip flags is damaged, resulting in Flag0 = 1, Flag1 = 1, and Flag2 = 0, the triple modular redundant array will still produce a final FLAG = 1. In this case, the read data must be inverted before output. This ensures that the actual output data is consistent with the actual written data, i.e., the data to be written, completing the memory repair.

[0135] Similarly, referring to FIG11 , when FLAG = 0, the data stored in the array bit can be directly output. It should be noted that in actual applications, the number of flag bits and data bits to be flipped can be configured based on the yield of the actual data storage array. Furthermore, the memory repair circuit can also be used in conjunction with ECC (error checking and correction) technology to improve the yield of the data storage array. This embodiment does not specifically limit this.

[0136] The memory repair circuit provided by the present invention can promptly repair the corresponding bits during each read operation, effectively solving the errors of damaged bits that occur during the life of the memory, improving the reliability of the memory, and greatly improving the repair efficiency. In addition, the memory repair circuit occupies a small area of ​​the memory, which improves the chip yield while reducing the cost of the memory.

[0137] It should be noted that the memory repair circuit can also repair multiple broken-down and burned bits and / or tailing bits in the same bit group 6. In the specific implementation process, corresponding logic selection circuits need to be added, which is not specifically limited in this embodiment.

[0138] In a second aspect, an embodiment of the present invention provides a method for repairing a memory. Referring to FIG. 12 , the method includes steps S101 to S103:

[0139] Step S101 : reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit.

[0140] The judgment bit is used to mark the bit in the breakdown state at the first level;

[0141] Step S102: Determine whether there is a flip bit in byte 6; if so, perform secondary marking on byte 6 by using the flip flag bit.

[0142] Byte 6 includes multiple bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked first. In this embodiment, the second-level marking of byte 6 by flipping the flag bit is to set the value of the flip flag bit corresponding to byte 6 to 1; if it is determined that there is no flip bit in byte 6, the value of the flip flag bit corresponding to byte 6 is set to 0.

[0143] Step S103: When performing a read operation on a bit, the determination bit and the flip flag bit corresponding to the bit are read to determine whether the bit is in a breakdown state and whether byte group 6 where the bit is located is secondarily marked. If the bit is in a breakdown state and byte group 6 where the bit is located is secondarily marked, data obtained by inverting the data read from the secondarily marked flipped bit is output. If the bit is not in a breakdown state or byte group 6 where the bit is located is not secondarily marked, the data read from the bit is output.

[0144] In an optional embodiment, before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the repair method further includes:

[0145] Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

[0146] In an optional embodiment, the determination bit marks a value of 1 for a bit in a breakdown state and a value of 0 for a bit not in a breakdown state;

[0147] The flip flag is set to 1 for byte 6 that is marked with the secondary mark and to 0 for byte 6 that is not marked with the secondary mark.

[0148] In an optional embodiment, the step of reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes:

[0149] Equal currents are applied to the bit and first reference resistor 12, respectively. The resistance of the bit is compared with the resistance of the first reference resistor 12. The resistance of the first reference resistor 12 is greater than the resistance of the bit in the breakdown state and less than the resistance of the bit in the low-resistance state. If the resistance of the bit is less than the resistance of the first reference resistor 12, the bit is determined to be in the breakdown state. If the resistance of the bit is greater than the resistance of the first reference resistor 12, the bit is determined to be not in the breakdown state.

[0150] In an optional embodiment, when performing a read operation on a bit, a determination bit and a flip flag bit corresponding to the bit are read to determine whether the bit is in a breakdown state and whether byte group 6 where the bit is located is secondarily marked; if the bit is in a breakdown state and byte group 6 where the bit is located is secondarily marked, outputting data obtained by inverting the data read from the secondarily marked flipped bit; if the bit is not in a breakdown state or byte group 6 where the bit is located is not secondarily marked, the step of outputting the data read from the bit includes:

[0151] Equal currents are applied to the bit and second reference resistor 13, respectively, and the resistance of the bit is compared with the resistance of the second reference resistor 13. The resistance of the second reference resistor 13 is greater than the resistance of the bit in the low-resistance state and less than the resistance of the bit in the high-resistance state. If the resistance of the bit is less than the resistance of the second reference resistor 13, the data read from the bit is determined to be 0. If the resistance of the bit is greater than the resistance of the second reference resistor 13, the data read from the bit is determined to be 1.

[0152] In an optional embodiment, determining whether a flip bit exists in byte 6; and if so, performing a secondary marking on byte 6 where the bit exists by using a flip flag bit includes:

[0153] Determine whether there is a flip bit in byte 6; if so, set the flip flag to 1 to perform secondary marking on byte 6 through the flip flag; if not, set the flip flag to 0 low.

[0154] In an optional embodiment, the flip flag bit includes a plurality of mark bits;

[0155] The steps of determining whether there is a flip bit in byte 6; if so, setting the flip flag to 1 to perform secondary marking on byte 6 by the flip flag; if not, setting the flip flag to 0, include:

[0156] Determine whether there is a flip bit in byte 6; if so, set multiple flag bits to high to perform secondary marking on byte 6 via multiple flip bits; if not, set multiple flip bits to 0;

[0157] When performing a read operation on a bit, the step of reading the judgment bit and the flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group 6 where the bit is located has been secondary marked includes:

[0158] By voting on the values ​​read from the multiple flag bits, the majority of the same values ​​are output as the flip flag value. The flip flag value is used to distinguish whether there is a flip bit in the corresponding byte 6.

[0159] This memory repair method takes into account the limited repair capability of redundancy repair and the wasteful area of ​​ECC repair. Therefore, a repair method that inverts the flip flag is employed. After marking the damaged bits, the data to be written is compared with the data to be written, and the flip flag is written based on the comparison result. During readout, the flip flag is used as logic to replace the bits in the damaged state bit by bit. Because the flip flag is also part of the data storage array and has a certain probability of error, a triple-module redundant flip flag function is added to prevent errors in the flip flag writing. This means that as long as no two judgment bits are simultaneously incorrect, the function will function normally.

[0160] At the same time, when the chip performs a write operation, the repair method first reads the judgment bit. When the judgment bit detects a bit in the read data group in a breakdown state, the judgment bit is high. At this time, it is determined whether the data to be written to the bit corresponding to this flag bit is 0. If so, it is written normally. If not, all three flip flag bits of this group of data are set high. When the chip performs a read operation, if at least two of the flip flag bits are high, the read data is inverted. If at least two of the flip flag bits are low, the data is read normally, thus completing the memory repair.

[0161] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0162] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A memory repair circuit, characterized in that: include: A primary marking module, electrically connected to the bit on the memory, for determining whether the bit is in a breakdown state and performing a primary marking on the bit in the breakdown state; A flip judgment module, electrically connected to the byte group and the primary marking module, for judging whether there is a flip bit in the byte group, wherein the byte group includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary marking; A secondary marking module, electrically connected to the flip judgment module, for providing a flip flag, wherein the flip flag corresponds to the byte one-to-one, and the flip flag is used to perform secondary marking on the byte with the flip bit; A data reading module is electrically connected to the bit, the primary marking module and the secondary marking module, and is used to output data that is the inversion of the data read from the flipped bit that has been secondary marked, and to output data read from the bit that has only been primary marked and data read from the bit that has not been primary marked.

2. The memory repair circuit according to claim 1, characterized in that: The memory repair circuit also includes: A write breakdown module is connected to the bit and is used to break down the burned bit and / or the tailing state bit. The tailing state bit is a bit in the memory that requires a read / write voltage greater than a normal read / write voltage used by the memory during application.

3. The memory repair circuit according to claim 2, characterized in that: The write breakdown module includes: a first control switch unit, a second control switch unit and a third control switch unit; The first control switch unit is connected in series to the common bit line of the bit group, the second control switch unit is connected in series to the common source line of the bit group, one end of the third control switch unit is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit; The first control switch is connected to a first control terminal, the second control switch is connected to a second control terminal, and the third control switch is connected to a third control terminal; When the burned bit or the tailing bit is broken down, the first control end controls the first control switch to be turned off, the second control end controls the second control switch to be turned on, and the third control end controls the third control switch to be turned on; When a normal read / write voltage is used to read and write a bit, the first control terminal controls the first control switch to be turned on, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned off; When the bit is not read, written or punctured, the third control terminal controls the third control switch to be closed.

4. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The primary marking module includes: a current mirror, a first voltage amplifier and a first reference resistor; The current mirror comprises: a first current output terminal and a second current output terminal, the current output by the first current output terminal is equal to the current output by the second current output terminal; The first voltage type amplifier comprises: a first voltage input terminal and a second voltage input terminal; The first current output terminal is electrically connected to one end of the bit group and the first voltage input terminal respectively, the second current output terminal is electrically connected to one end of the first reference resistor and the second voltage input terminal respectively, and the other end of the first reference resistor and the other end of the bit group have the same potential; The resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state; The first voltage type amplifier is used to compare the potentials of the first voltage input terminal and the second voltage input terminal; The primary marking module is further used to perform primary marking on a bit connected to the first voltage input terminal when the potential of the first voltage input terminal is less than the potential of the second voltage input terminal.

5. The memory repair circuit according to claim 4, characterized in that: The primary marking module further includes: a second voltage-type amplifier and a second reference resistor; The second voltage-type amplifier includes: a third voltage input terminal and a fourth voltage input terminal, and the current mirror also includes: a third current output terminal, and the current output by the third current output terminal is equal to the current output by the first current output terminal; The third current output terminal is electrically connected to one end of the second reference resistor and the third voltage input terminal respectively, the third voltage input terminal is electrically connected to the first current output terminal, and the other end of the second reference resistor and the other end of the bit group have the same potential; The resistance value of the second reference resistor is greater than the resistance value of the bit in the low resistance state and less than the resistance value of the bit in the high resistance state; The second voltage type amplifier is used to compare the potentials of the first voltage input terminal and the third voltage input terminal; The primary marking module is also used to output data read from the bit connected to the first voltage input terminal according to the comparison result of the second voltage-type amplifier.

6. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The primary marking module is also used to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, so as to perform a primary marking on the bit in the breakdown state, and assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state; The flip judgment module includes: an OR gate and multiple AND gates; The plurality of AND gates correspond to the bits in the byte group one by one, and one input end of the plurality of AND gates is electrically connected to the primary marking module respectively to obtain the data written in the judgment bit corresponding to the corresponding bit; the other input ends of the plurality of AND gates are connected to the data writing end of the corresponding bit respectively to obtain the data to be written corresponding to the bit; The OR gate is electrically connected to the output ends of the plurality of AND gates; the output end of the OR gate is electrically connected to the secondary marking module so as to write the output value into the flip flag bit.

7. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The secondary marking module is further used to vote on the values ​​read from the multiple marking bits and output the majority of the same values ​​as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group; The data reading module is also used to output data according to the flip flag value and the marking result of the first-level marking module.

8. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The data reading module includes: a bit reader, a buffer, an inverter, a logic judge and a multiplexer; The input end of the bit reader is electrically connected to the bit, the output end of the bit reader is electrically connected to the input end of the buffer and the input end of the inverter respectively, the input end of the multiplexer is electrically connected to the output end of the buffer and the output end of the inverter respectively, the enable end of the multiplexer is electrically connected to the output end of the logic determiner, and the input end of the logic determiner is electrically connected to the secondary marking module and the primary marking module respectively; The multi-logic determiner is used to determine whether the bit connected to the bit reader is flipped through the secondary marking module and the primary marking module; if so, output a first enable signal; if not, output a second enable signal; The multiplexer is used to communicate with the inverter when receiving a first enable signal, and to communicate with the buffer when receiving a second enable signal.

9. A method for repairing a memory, characterized in that: include: Reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit, wherein the determination bit is used to perform a primary mark on the bit in the breakdown state; Determine whether there is a flip bit in the byte; if so, perform secondary marking on the byte by using a flip flag bit; wherein the byte includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked at the primary level; When performing a read operation on a bit, read the judgment bit and the flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, output data that is the inversion of the data read from the flip bit that has been secondarily marked; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, output the data read from the bit.

10. The method according to claim 9, characterized in that Before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the method further includes: Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

11. The method according to claim 9, characterized in that The value of the judgment bit for the bit mark in the breakdown state is 1, and the value of the bit mark not in the breakdown state is 0; The flip flag has a value of 1 for byte markings that are subject to secondary marking, and a value of 0 for byte markings that are not subject to secondary marking.

12. The method according to any one of claims 9 to 11, characterized in that The step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes: Equal currents are respectively passed through the bit and the first reference resistor, and the relative sizes of the resistance value of the bit and the resistance value of the first reference resistor are compared, the resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state; if the resistance value of the bit is less than the resistance value of the first reference resistor, it is determined that the bit is in the breakdown state; if the resistance value of the bit is greater than the resistance value of the first reference resistor, it is determined that the bit is not in the breakdown state.

13. The method according to any one of claims 9 to 11, characterized in that When performing a read operation on a bit, reading the judgment bit and the flip flag bit corresponding to the bit to judge whether the bit is in a breakdown state and whether the byte group where the bit is located is secondary marked; if the bit is in a breakdown state and the byte group where the bit is located is secondary marked, outputting data obtained by inverting the data read from the flip bit that has been secondary marked; If the bit is not in a breakdown state or the byte group where the bit is located is not secondary marked, the step of outputting the data read from the bit comprises: Passing equal currents through the bit and the second reference resistor, respectively, and comparing the relative magnitudes of the resistance of the bit and the resistance of the second reference resistor, wherein the resistance of the second reference resistor is greater than the resistance of the bit in the low resistance state and less than the resistance of the bit in the high resistance state; If the resistance value of the bit is less than the resistance value of the second reference resistor, the data read from the bit is determined to be 0; if the resistance value of the bit is greater than the resistance value of the second reference resistor, the data read from the bit is determined to be 1.

14. The method according to any one of claims 9 to 11, characterized in that The determination of whether there is a flip bit in the byte; If yes, the step of performing secondary marking on the byte group where the bit is located by flipping the flag bit includes: Determine whether there is a flip bit in the byte; if so, set the flip flag to 1 to perform secondary marking on the byte through the flip flag; if not, set the flip flag to 0 low.

15. The method according to claim 14, characterized in that The flip flag bit includes a plurality of marking bits; The determining whether there is a flip bit in the byte; if so, setting the flip flag to 1 to perform secondary marking on the byte through the flip flag; If not, the step of setting the flip flag position to 0 includes: Determine whether there is a flip bit in the byte; if so, set the multiple flag bits to high to perform secondary marking on the byte through the multiple flip bits; if not, set the multiple flip bits to 0; The step of reading the determination bit and the flip flag bit corresponding to the bit when performing a read operation on the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located has been secondary marked includes: By voting on the values ​​read from the multiple mark bits, the majority of the same values ​​are output as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group.

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