Electric power conversion device

Abstract

The present invention realizes zero voltage soft switching without directly controlling a plurality of switches for zero voltage soft switching in a control device. A control device (51) sets, for each of a plurality of switching circuits (10), a second dead time period obtained by adding a prescribed time to a preset first dead time period, between a high-level period of a first control signal to a first switching element (1) and a high-level period of the first control signal to a second switching element (2). The prescribed time is determined according to a current value of a load current, the inductance of a resonance inductor (L1), and a voltage value of a regeneration capacitor (15). A signal generation circuit (52) sets the length of the high-level period of a second control signal generated for each of the plurality of switches (8) to the fixed length, and causes the start timing of the high-level period of the fixed length to follow the start timing of the second dead time period.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device capable of converting DC power into AC power.

[0002] Patent Document 1 discloses a power conversion system.

[0003] The power conversion system (power conversion device) disclosed in Patent Document 1 includes a switching means having a pair of main switching elements (first switching element and second switching element) connected in series, an auxiliary circuit for performing soft switching of each of the main switching elements, and a controller. The auxiliary circuit includes two capacitors, a coil (resonance inductor), and a plurality of auxiliary switching elements. The controller generates a control signal (first control signal) for PWM control of each of the main switching elements and outputs it to the gate of each of the main switching elements. The controller also generates a control signal (second control signal) for controlling the on / off of each of the auxiliary switching elements and outputs it to the gate of each of the auxiliary switching elements.

[0004] JP 2010-233306 A

[0005] In the power conversion system (power conversion device) disclosed in Patent Document 1, the controller needs to generate and output a plurality of first control signals and a plurality of second control signals, which increases the size of the controller. Also, the power conversion system disclosed in Patent Document 1 is configured to perform zero-current soft switching, but is not configured to support zero-voltage soft switching.

[0006] An object of the present disclosure is to provide a power conversion device that can achieve zero voltage soft switching without directly controlling a plurality of switches for zero voltage soft switching in a control device.

[0007] A power conversion device according to one aspect of the present disclosure includes a first DC terminal and a second DC terminal, a power conversion circuit, multiple AC terminals, multiple switches, multiple resonant capacitors, at least one resonant inductor, a regenerative capacitor, a control device, and a signal generating circuit. The power conversion circuit includes multiple first switching elements and multiple second switching elements. In the power conversion circuit, multiple switching circuits, each of which has the multiple first switching elements and the multiple second switching elements connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit, the multiple first switching elements are connected to the first DC terminal. In the power conversion circuit, the multiple second switching elements are connected to the second DC terminal. The multiple AC terminals correspond one-to-one to the multiple switching circuits. Each of the multiple AC terminals is connected to a connection point between the first switching element and the second switching element in a corresponding one of the multiple switching circuits, through which a load current flows. The multiple switches correspond one-to-one to the multiple switching circuits. Each of the plurality of switches has a first end and a second end, and the first end is connected to the connection point between the first switching element and the second switching element in a corresponding switching circuit among the plurality of switching circuits. The plurality of resonant capacitors correspond one-to-one to the plurality of switches. Each of the plurality of resonant capacitors is connected between the first end and the second DC terminal of a corresponding switch among the plurality of switches. The at least one resonant inductor has a third end and a fourth end. The third end of the at least one resonant inductor is connected to the second end of the corresponding switch among the plurality of switches. The regenerative capacitor has a fifth end and a sixth end. The fifth end of the regenerative capacitor is connected to the second DC terminal, and the sixth end is connected to the fourth end of the at least one resonant inductor. The control device provides each of the plurality of first switching elements and the plurality of second switching elements with a first control signal whose potential changes between a high level and a low level.The signal generating circuit provides each of the plurality of switches with a second control signal whose potential changes between a high level and a low level. The control device sets, for each of the plurality of switching circuits, a second dead time period that is obtained by adding a predetermined time to a predetermined first dead time period between a high level period of the first control signal to the first switching element and a high level period of the first control signal to the second switching element so that on periods of the first switching element and the second switching element do not overlap. The predetermined time period is determined based on the current value of the load current, the inductance of the at least one resonance inductor, and the voltage value of the regenerative capacitor. The signal generating circuit sets a fixed length of the high level period of the second control signal generated for each of the plurality of switches, and causes the start timing of the fixed length high level period to follow the start timing of the second dead time period for a corresponding switching circuit among the plurality of switching circuits.

[0008] The power conversion device of the present disclosure has an advantage that it is possible to realize zero voltage soft switching without directly controlling a plurality of switches for zero voltage soft switching in a control device.

[0009] FIG. 1 is a circuit diagram of a system including a power conversion device according to a first embodiment. FIG. 2 is a circuit block diagram of a signal generating circuit in the power conversion device according to the first embodiment. FIG. 3 is a diagram illustrating time variations in duty and load current corresponding to voltage commands for each of three phases in an AC load connected to multiple AC terminals of the power conversion device according to the first embodiment. FIG. 4 is a timing chart for explaining the operation of the power conversion device according to the first embodiment. FIG. 5 is a timing chart for explaining the operation of the power conversion device according to the first embodiment. FIG. 6 is a timing chart for explaining the operation of the power conversion device according to the first embodiment. FIG. 7 is a diagram illustrating the operation of the power conversion device according to the first embodiment when the load current of the U phase is positive. FIG. 8 is a diagram illustrating the operation of the power conversion device according to the first embodiment during a first period. FIG. 9 is a diagram illustrating the operation of the power conversion device according to the first embodiment during a second period. FIG. 10 is a diagram illustrating the operation of the power conversion device according to the first embodiment during a third period. FIG. 11 is a diagram illustrating the operation of the power conversion device according to the first embodiment when the polarity of the load current of the U phase is negative. FIG. 12 is a circuit diagram of a system including a power conversion device according to the second embodiment. FIG. 13 is a circuit block diagram of a signal generating circuit in a power conversion device according to the second embodiment. FIG. 14 is a diagram illustrating the operation of the power conversion device according to the second embodiment when the polarity of the U-phase load current is positive. FIG. 15 is a diagram illustrating the operation of the power conversion device according to the second embodiment at a high load. FIG. 16 is a diagram illustrating the operation of the power conversion device according to the second embodiment at a low load. FIG. 17 is a diagram illustrating the operation of the power conversion device according to the second embodiment at no load. FIG. 18 is a diagram illustrating the operation of the power conversion device according to the second embodiment when the polarity of the U-phase load current is negative. FIG. 19 is a circuit diagram of a system including a power conversion device according to the third embodiment. FIG. 20 is a diagram illustrating the operation of the power conversion device according to the third embodiment when the polarity of the U-phase load current is positive. FIG. 21 is a diagram illustrating the operation of the power conversion device according to the third embodiment when the polarity of the U-phase load current is negative. FIG. 22 is a circuit diagram of a system including a power conversion device according to the fourth embodiment. FIG. 23 is a diagram illustrating the operation of the power conversion device according to the fourth embodiment when the polarity of the U-phase load current is positive.Fig. 24 is a diagram illustrating the operation of the power conversion device according to the fourth embodiment when the polarity of the load current of the U phase is negative. Fig. 25 is a circuit diagram of a system including the power conversion device according to the fifth embodiment. Fig. 26 is a circuit diagram of a system including the power conversion device according to the sixth embodiment. Fig. 27 is a circuit diagram of a system including the power conversion device according to the seventh embodiment. Fig. 28 is a circuit diagram of a system including the power conversion device according to the eighth embodiment. Fig. 29 is a circuit block diagram of a signal generating circuit in the power conversion device according to the eighth embodiment. Fig. 30 is a circuit diagram of a system including the power conversion device according to the ninth embodiment. Fig. 31 is a circuit diagram of a system including the power conversion device according to the tenth embodiment. Fig. 32 is a circuit diagram of a system including the power conversion device according to the eleventh embodiment. Fig. 33 is a circuit diagram of a system including the power conversion device according to the twelfth embodiment. Fig. 34 is a circuit diagram of a system including the power conversion device according to the thirteenth embodiment.

[0010] First Embodiment A power conversion device 100 according to a first embodiment will be described below with reference to FIGS. 1 to 11. FIG.

[0011] (1) Overall Configuration of the Power Conversion Device FIG. 1 is a circuit diagram of a system including a power conversion device 100 according to the first embodiment. As shown in FIG. 1 , the power conversion device 100 includes, for example, a first DC terminal 31, a second DC terminal 32, and multiple (e.g., three) AC terminals 41. A DC power source E1 is connected between the first DC terminal 31 and the second DC terminal 32, and an AC load RA1 is connected to the multiple AC terminals 41. The AC load RA1 is, for example, a three-phase servo motor. The power conversion device 100 converts DC output from the DC power source E1 into AC power and outputs it to the AC load RA1. The DC power source E1 includes, for example, a solar cell or a fuel cell. The DC power source E1 may also include a DC-DC converter. In the power conversion device 100, when the multiple AC terminals 41 are three AC terminals 41, the AC power is, for example, three-phase AC power having a U phase, a V phase, and a W phase.

[0012] The power conversion device 100 includes a power conversion circuit 11, a plurality of (e.g., three) switches 8, a plurality of (e.g., three) resonant capacitors 9, a resonant inductor L1, a regenerative capacitor 15, a control device 51, and a signal generation circuit 52. Each of the plurality of switches 8 is, for example, a bidirectional switch. The power conversion device 100 also includes a first clamp diode 13 and a second clamp diode 14.

[0013] The power conversion circuit 11 has a plurality of (e.g., three) first switching elements 1 and a plurality of (e.g., three) second switching elements 2. In the power conversion circuit 11, a plurality of (e.g., three) switching circuits 10, each having a plurality of first switching elements 1 and a plurality of second switching elements 2 connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit 11, the plurality of first switching elements 1 are connected to first DC terminals 31, and the plurality of second switching elements 2 are connected to second DC terminals 32.

[0014] The plurality of AC terminals 41 correspond one-to-one to the plurality of switching circuits 10. Each of the plurality of AC terminals 41 is connected to a connection point 3 of the first switching element 1 and the second switching element 2 in the corresponding switching circuit 10.

[0015] The multiple switches 8 correspond one-to-one to the multiple switching circuits 10. Each of the multiple switches 8 has a first end 81 and a second end 82. The first end 81 of each of the multiple switches 8 is connected to a connection point 3 between a first switching element 1 and a second switching element 2 in a corresponding one of the multiple switching circuits 10.

[0016] The plurality of resonance capacitors 9 correspond one-to-one to the plurality of switches 8. Each of the plurality of resonance capacitors 9 is connected between the first end 81 of the corresponding switch 8 among the plurality of switches 8 and the second DC terminal 32.

[0017] The resonance inductor L1 has a third end and a fourth end. The third end of the resonance inductor L1 is connected to the second end 82 of a corresponding one of the multiple switches 8 (three switches 8 in the first embodiment).

[0018] The regenerative capacitor 15 has a fifth end 153 and a sixth end 154. In the regenerative capacitor 15, the fifth end 153 is connected to the second DC terminal 32, and the sixth end 154 is connected to the fourth end of the resonant inductor L1.

[0019] The control device 51 provides a first control signal to each of the plurality of first switching elements 1 and the plurality of second switching elements 2 .

[0020] The signal generating circuit 52 provides a second control signal to each of the plurality of switches 8 .

[0021] (2) Details of the Power Conversion Device Hereinafter, for convenience of explanation, the switching circuits 10 corresponding to the U phase, V phase, and W phase of the multiple switching circuits 10 may be referred to as switching circuit 10U, switching circuit 10V, and switching circuit 10W, respectively. Hereinafter, the first switching element 1 and the second switching element 2 of switching circuit 10U may be referred to as first switching element 1U and second switching element 2U. Hereinafter, the first switching element 1 and the second switching element 2 of switching circuit 10V may be referred to as first switching element 1V and second switching element 2V. Hereinafter, the first switching element 1 and the second switching element 2 of switching circuit 10W may be referred to as first switching element 1W and second switching element 2W. In the following, the connection point 3 between the first switching element 1U and the second switching element 2U will be referred to as connection point 3U, the connection point 3 between the first switching element 1V and the second switching element 2V will be referred to as connection point 3V, and the connection point 3 between the first switching element 1W and the second switching element 2W will be referred to as connection point 3W. In the following, the AC terminal 41 connected to connection point 3U will be referred to as AC terminal 41U, the AC terminal 41 connected to connection point 3V will be referred to as AC terminal 41V, and the AC terminal 41 connected to connection point 3W will be referred to as AC terminal 41W. In the following, the resonant capacitor 9 connected in parallel to the second switching element 2U will be referred to as resonant capacitor 9U, the resonant capacitor 9 connected in parallel to the second switching element 2V will be referred to as resonant capacitor 9V, and the resonant capacitor 9 connected in parallel to the second switching element 2W will be referred to as resonant capacitor 9W. In the following, the switch 8 connected to connection point 3U may be referred to as switch 8U, the switch 8 connected to connection point 3V may be referred to as switch 8V, and the switch 8 connected to connection point 3W may be referred to as switch 8W.

[0022] In the power conversion device 100, for example, a high-potential output terminal (positive electrode) of the DC power supply E1 is connected to the first DC terminal 31, and a low-potential output terminal (negative electrode) of the DC power supply E1 is connected to the second DC terminal 32. In addition, in the power conversion device 100, for example, a U-phase terminal, a V-phase terminal, and a W-phase terminal of the AC load RA1 are connected to three AC terminals 41U, 41V, and 41W, respectively.

[0023] In the power conversion circuit 11, each of a plurality of (three in the example of FIG. 1 ) first switching elements 1 and a plurality of (three in the example of FIG. 1 ) second switching elements 2 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the plurality of first switching elements 1 and the plurality of second switching elements 2 are connected to a control device 51. In each of the plurality of switching circuits 10 of the power conversion device 100, a first main terminal of the first switching element 1 is connected to a first DC terminal 31, a second main terminal of the first switching element 1 is connected to a first main terminal of the second switching element 2, and a second main terminal of the second switching element 2 is connected to a second DC terminal 32. In each of the plurality of switching circuits 10, the first switching element 1 is a high-side switching element (P-side switching element), and the second switching element 2 is a low-side switching element (N-side switching element). Each of the plurality of first switching elements 1 and the plurality of second switching elements 2 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Therefore, the control terminal, the first main terminal and the second main terminal of each of the plurality of first switching elements 1 and the plurality of second switching elements 2 are the gate terminal, the collector terminal and the emitter terminal, respectively.

[0024] The power conversion circuit 11 further includes a plurality of (three) first diodes 4 connected in anti-parallel to the plurality of (three) first switching elements 1 in a one-to-one relationship, and a plurality of (three) second diodes 5 connected in anti-parallel to the plurality of (three) second switching elements 2 in a one-to-one relationship. In each of the plurality of first diodes 4, the anode of the first diode 4 is connected to the second main terminal (emitter terminal) of the first switching element 1 corresponding to the first diode 4, and the cathode of the first diode 4 is connected to the first main terminal (collector terminal) of the first switching element 1 corresponding to the first diode 4. In each of the plurality of second diodes 5, the anode of the second diode 5 is connected to the second main terminal (emitter terminal) of the second switching element 2 corresponding to the second diode 5, and the cathode of the second diode 5 is connected to the first main terminal (collector terminal) of the second switching element 2 corresponding to the second diode 5.

[0025] A connection point 3U between the first switching element 1U and the second switching element 2U is connected to, for example, the U-phase terminal of the AC load RA1 via an AC terminal 41U. A connection point 3V between the first switching element 1V and the second switching element 2V is connected to, for example, the V-phase of the AC load RA1 via an AC terminal 41V. A connection point 3W between the first switching element 1W and the second switching element 2W is connected to, for example, the W-phase of the AC load RA1 via an AC terminal 41W.

[0026] The plurality of resonant capacitors 9 correspond one-to-one to the plurality of switches 8. Each of the plurality of resonant capacitors 9 is connected between the first end 81 and the second DC terminal 32 of the corresponding switch 8. The power conversion device 100 has a plurality of resonant circuits. Each of the plurality of resonant circuits includes a resonant capacitor 9 and a resonant inductor L1.

[0027] Each of the multiple switches 8 has a third switching element 6 and a fourth switching element 7. Each of the multiple (three in the example of FIG. 1 ) third switching elements 6 and the multiple (three in the example of FIG. 1 ) fourth switching elements 7 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the multiple third switching elements 6 and the multiple fourth switching elements 7 are connected to the signal generating circuit 52. Each of the multiple third switching elements 6 and the multiple fourth switching elements 7 is, for example, an IGBT. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the multiple third switching elements 6 and the multiple fourth switching elements 7 are a gate terminal, a collector terminal, and an emitter terminal, respectively. In each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 are connected in anti-series. In each of the multiple switches 8, the first main terminal (collector terminal) of the third switching element 6 and the first main terminal (collector terminal) of the fourth switching element 7 are connected. In each of the switches 8, the second main terminal (emitter terminal) of the third switching element 6 is connected to the connection point 3 of a corresponding one of the switching circuits 10, and the second main terminal (emitter terminal) of the fourth switching element 7 is connected to the resonance inductor L1. Each of the switches 8 further includes a diode 61 connected in anti-parallel to the third switching element 6 and a diode 71 connected in anti-parallel to the fourth switching element 7.

[0028] In the power conversion device 100, the switch 8U is connected to a connection point 3U between the first switching element 1U and the second switching element 2U. The switch 8V is connected to a connection point 3V between the first switching element 1V and the second switching element 2V. The switch 8W is connected to a connection point 3W between the first switching element 1W and the second switching element 2W. Hereinafter, for convenience of explanation, the third switching element 6 and the fourth switching element 7 of the switch 8U will be referred to as the third switching element 6U and the fourth switching element 7U, the third switching element 6 and the fourth switching element 7 of the switch 8V will be referred to as the third switching element 6V and the fourth switching element 7V, and the third switching element 6 and the fourth switching element 7 of the switch 8W will be referred to as the third switching element 6W and the fourth switching element 7W, respectively.

[0029] The multiple switches 8 are controlled by the signal generating circuit 52. In other words, the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W are controlled by the signal generating circuit 52.

[0030] The resonant inductor L1 has a third end and a fourth end. The third end of the resonant inductor L1 is connected to the second ends 82 of the multiple switches 8. In the first embodiment, the third end of the resonant inductor L1 is connected to a common connection point 25 to which the second ends 82 of the multiple switches 8 are connected. The fourth end of the resonant inductor L1 is connected to a sixth end 154 of the regenerative capacitor 15.

[0031] The regenerative capacitor 15 is connected between the fourth end of the resonance inductor L1 and the second DC terminal 32. The regenerative capacitor 15 is, for example, a film capacitor.

[0032] The control device 51 controls a plurality of first switching elements 1 and a plurality of second switching elements 2. The control device 51 includes a computer system. The computer system is primarily composed of a processor and a memory as hardware. The processor executes a program recorded in the memory of the computer system to realize the functions of the control device 51 in the present disclosure. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The integrated circuits, such as ICs and LSIs, are referred to by different names depending on the degree of integration, and include integrated circuits called system LSIs, very large-scale integrations (VLSIs), or ultra-large-scale integrations (ULSIs). Furthermore, field-programmable gate arrays (FPGAs), which are programmed after the LSI is manufactured, or logic devices that can reconfigure the connections within the LSI or reconfigure the circuit partitions within the LSI, can also be used as processors. The electronic circuits may be integrated into a single chip or distributed across multiple chips. The multiple chips may be integrated into one device or distributed across multiple devices. The computer system referred to here includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller is also composed of one or more electronic circuits including semiconductor integrated circuits or large-scale integrated circuits.

[0033] The control device 51 outputs first control signals SU1, SV1, and SW1 that control the on / off states of the multiple first switching elements 1U, 1V, and 1W, respectively. Each of the first control signals SU1, SV1, and SW1 is, for example, a PWM (Pulse Width Modulation) signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first switching elements 1U, 1V, and 1W are turned on when the first control signals SU1, SV1, and SW1 are at a high level, and turned off when the first control signals SU1, SV1, and SW1 are at a low level. The control device 51 also outputs first control signals SU2, SV2, and SW2 that control the on / off states of the multiple second switching elements 2U, 2V, and 2W, respectively. Each of the first control signals SU2, SV2, and SW2 is, for example, a PWM signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The second switching elements 2U, 2V, and 2W are turned on when the first control signals SU2, SV2, and SW2 are at a high level, and turned off when the first control signals SU2, SV2, and SW2 are at a low level.

[0034] The control device 51 uses a sawtooth-wave carrier signal to generate first control signals SU1, SV1, SW1 corresponding to the multiple first switching elements 1U, 1V, and 1W, respectively, and first control signals SU2, SV2, and SW2 corresponding to the multiple second switching elements 2U, 2V, and 2W, respectively. More specifically, the control device 51 generates the first control signals SU1 and SU2 to be applied to the first switching element 1U and the second switching element 2U, respectively, based on at least the carrier signal and a U-phase voltage command. The control device 51 also generates the first control signals SV1 and SV2 to be applied to the first switching element 1V and the second switching element 2V, respectively, based on at least the carrier signal and a V-phase voltage command. The control device 51 also generates the first control signals SW1 and SW2 to be applied to the first switching element 1W and the second switching element 2W, respectively, based on at least the carrier signal and a W-phase voltage command. The U-phase voltage command, V-phase voltage command, and W-phase voltage command are, for example, sinusoidal signals whose phases differ by 120°, and whose values ​​(voltage command values) change over time. Note that the waveform of the carrier signal is not limited to a sawtooth waveform and may be, for example, a triangular wave. The U-phase voltage command, V-phase voltage command, and W-phase voltage command each have the same length per cycle. The U-phase voltage command, V-phase voltage command, and W-phase voltage command each have a longer length per cycle than the carrier signal.

[0035] The duties of the first control signals SU1 and SU2 provided by the control device 51 to the first switching element 1U and the second switching element 2U, respectively, vary based on a U-phase voltage command. FIG. 3 is a diagram showing time variations in the duties corresponding to the voltage commands for each of the three phases and time variations in the load current in an AC load connected to multiple AC terminals of the power conversion device 100 according to the first embodiment. In FIG. 3, the duty of the first control signal SU1 is shown as a U-phase duty. The control device 51 (see FIG. 1) compares the U-phase voltage command with the carrier signal to generate the first control signal SU1 to be provided to the first switching element 1U. The control device 51 also inverts the first control signal SU1 provided to the first switching element 1U to generate the first control signal SU2 to be provided to the second switching element 2U. In addition, the control device 51 pre-sets a first dead time period Td1 (see Figure 4) between the high-level period of the first control signal SU1 and the high-level period of the first control signal SU2 so that the on periods of the first switching element 1U and the second switching element 2U do not overlap.

[0036] The duty of the first control signals SV1 and SV2 provided by the control device 51 to the first switching element 1V and the second switching element 2V, respectively, varies based on the V-phase voltage command. In FIG. 3, the duty of the first control signal SV1 is shown as the V-phase duty. The control device 51 (see FIG. 1) compares the V-phase voltage command with a carrier signal to generate the first control signal SV1 provided to the first switching element 1V. The control device 51 also inverts the first control signal SV1 provided to the first switching element 1V to generate the first control signal SV2 provided to the second switching element 2V. The control device 51 also sets a first dead time period Td1 (see FIG. 5) between the high-level period of the first control signal SV1 and the high-level period of the first control signal SV2 so that the on periods of the first switching element 1V and the second switching element 2V do not overlap.

[0037] The duty of the first control signals SW1 and SW2 provided by the control device 51 to the first switching element 1W and the second switching element 2W, respectively, varies based on the W-phase voltage command. In FIG. 3, the duty of the first control signal SW1 is shown as the W-phase duty. The control device 51 (see FIG. 1) compares the W-phase voltage command with a carrier signal to generate the first control signal SW1 provided to the first switching element 1W. The control device 51 also inverts the first control signal SW1 provided to the first switching element 1W to generate the first control signal SW2 provided to the second switching element 2W. The control device 51 also sets a first dead time period Td1 (see FIG. 6) between the high-level period of the first control signal SW1 and the high-level period of the first control signal SW2 so that the on periods of the first switching element 1W and the second switching element 2W do not overlap.

[0038] The U-phase voltage command, V-phase voltage command, and W-phase voltage command are, for example, sinusoidal signals whose phases are different from each other by 120°, and whose values ​​change over time. Therefore, the duty of the first control signal SU1 (U-phase duty), the duty of the first control signal SV1 (V-phase duty), and the duty of the first control signal SW1 (W-phase duty) change like sinusoidal waves whose phases are different from each other by 120°, as shown in FIG. 3 . Similarly, the duty of the first control signal SU2, the duty of the first control signal SV2, and the duty of the first control signal SW2 change like sinusoidal waves whose phases are different from each other by 120°.

[0039] The control device 51 generates the first control signals SU1, SU2, SV1, SV2, SW1, and SW2 based on the carrier signal, the voltage commands, and information about the state of the AC load RA1. For example, if the AC load RA1 is a three-phase motor, the information about the state of the AC load RA1 includes, for example, detection values ​​from a plurality of current sensors that detect output currents (hereinafter also referred to as load currents) iU, iV, and iW flowing through the U-phase, V-phase, and W-phase of the AC load RA1, respectively.

[0040] The plurality of switches 8, the resonant inductor L1, the plurality of resonant capacitors 9, and the regenerative capacitor 15 are provided to perform zero-voltage soft switching of the plurality of first switching elements 1 and the plurality of second switching elements 2.

[0041] When the third switching element 6U is in the ON state and the fourth switching element 7U is in the OFF state, the switch 8U allows a charging current to pass through the path of the regenerative capacitor 15-resonant inductor L1-switch 8U-resonant capacitor 9U. The charging current is a current that charges the resonant capacitor 9U. When the third switching element 6U is in the OFF state and the fourth switching element 7U is in the ON state, the switch 8U allows a discharging current to pass through the path of the resonant capacitor 9U-switch 8U-resonant inductor L1-regenerative capacitor 15. The discharging current is a current that discharges the charge in the resonant capacitor 9U.

[0042] When the third switching element 6V is in the ON state and the fourth switching element 7V is in the OFF state, the switch 8V allows a charging current to pass through the path of the regenerative capacitor 15-resonant inductor L1-switch 8V-resonant capacitor 9V. The charging current is a current that charges the resonant capacitor 9V. When the third switching element 6V is in the OFF state and the fourth switching element 7V is in the ON state, the switch 8V allows a discharging current to pass through the path of the resonant capacitor 9V-switch 8V-resonant inductor L1-regenerative capacitor 15. The discharging current is a current that discharges the charge of the resonant capacitor 9V.

[0043] When the third switching element 6W is in the ON state and the fourth switching element 7W is in the OFF state, the switch 8W allows a charging current to pass through the path of the regenerative capacitor 15 - resonant inductor L1 - switch 8W - resonant capacitor 9W. The charging current is a current that charges the resonant capacitor 9W. When the third switching element 6W is in the OFF state and the fourth switching element 7W is in the ON state, the switch 8W allows a discharging current to pass through the path of the resonant capacitor 9W - switch 8W - resonant inductor L1 - regenerative capacitor 15. The discharging current is a current that discharges the charge in the resonant capacitor 9W.

[0044] In this embodiment, the control device 51 sets, for each of the multiple switching circuits 10, a second dead time period Td2 determined by the first dead time period Td1 and a predetermined time (additional time Tad) between the high-level period of the first control signal to the first switching element 1 and the high-level period of the first control signal to the second switching element 2. The second dead time period Td2 includes the first dead time period Td1 and has a length obtained by adding the predetermined time to the length of the first dead time period Td1 (the total length of the first dead time period Td1 and the predetermined time). In other words, the control device 51 sets the second dead time period Td2, which is obtained by extending the first dead time period Td1 by the predetermined time, as the dead time period.

[0045] The first dead-time period Td1 is a period set for each of the multiple switching circuits 10 between the high-level period of the first control signal to the first switching element 1 and the high-level period of the first control signal to the second switching element 2. This period is a period during which both the first control signal to the first switching element 1 and the first control signal to the second switching element 2 are low so that the on-periods of the first switching element 1 and the second switching element 2 do not overlap (i.e., there is no period in which both the first switching element 1 and the second switching element 2 are on). In this embodiment, for example, the length of the resonant half cycle corresponding to each of the multiple switches 8 is designed according to the length of the first dead-time period Td1 of each of the multiple switching circuits 10. The resonant half cycle is half the resonant cycle, which is the reciprocal of the resonant frequency of the resonant circuit including the switch 8, the resonant inductor L1, and one resonant capacitor 9. Therefore, when the inductance of the resonant inductor L1 is L and the capacitance of the resonant capacitor 9 is C, the resonant half cycle is expressed as π × (L C) １／２ The length of the resonance half cycle is set to be the same as the length of the first dead time period Td1, for example.

[0046] The length of the resonant half cycle of the resonant circuit including the resonant inductor L1 and the resonant capacitor 9U is set to, for example, the length of the first dead time period Td1 (see FIG. 4) set between the high level period of the first control signal SU1 and the high level period of the first control signal SU2. The length of the resonant half cycle of the resonant circuit including the resonant inductor L1 and the resonant capacitor 9V is set to the length of the first dead time period Td1 (see FIG. 5) set between the high level period of the first control signal SV1 and the high level period of the first control signal SV2. The length of the resonant half cycle of the resonant circuit including the resonant inductor L1 and the resonant capacitor 9W is set to the length of the first dead time period Td1 (see FIG. 6) set between the high level period of the first control signal SW1 and the high level period of the first control signal SV2.

[0047] If the resonant period is Tres, Tres / 2, which is the resonant half period, is the length of the first dead time period Td1. The end of the resonant half period preferably coincides with the end of the first dead time period Td1 for the switching circuit 10 corresponding to the switch 8. FIG. 4 is a timing chart for explaining the operation of the power conversion device 100 according to the first embodiment. FIG. 4 illustrates the first control signals SU1 and SU2, the second control signals SU6 and SU7, the first dead time period Td1, the additional time Tad, and the second dead time period Td2. In the example of FIG. 4, the start and end of the first dead time period Td1 are time t12 and time t13, respectively. FIG. 5 is a timing chart for explaining the operation of the power conversion device 100 according to the first embodiment. FIG. 5 illustrates the first control signals SV1 and SV2, the second control signals SV6 and SV7, the first dead time period Td1, the additional time Tad, and the second dead time period Td2. In the example of Fig. 5, the start and end points of the first dead time period Td1 are time t22 and time t23, respectively. Fig. 6 is a timing chart for explaining the operation of the power conversion device 100 according to the first embodiment. Fig. 6 illustrates the first control signals SW1 and SW2, the second control signals SW6 and SW7, the first dead time period Td1, the additional time Tad, and the second dead time period Td2. In the example of Fig. 6, the start and end points of the first dead time period Td1 are time t32 and time t33, respectively.

[0048] The length of the resonant half cycle described above is an ideal design example, and may be 90% to 110% of the length of the first dead time period Td1. The resonant half cycle and the first dead time period Td1 may have different lengths.

[0049] The second dead time period Td2 is a period obtained by adding a predetermined time corresponding to the current value of the load current and the voltage value of the regenerative capacitor 15 to the first dead time period Td1. The predetermined time is, for example, an additional time Tad determined by the current value of the load current, the voltage value of the regenerative capacitor 15, and the inductance L of the resonant inductor L1. The current value of the load current is, for example, the load current detection result obtained by a current sensor, a signal-processed value thereof, or an estimated value of the load current iU. The load current detection result or signal-processed value thereof is a detected value at a carrier cycle in which the additional time Tad is added to the first dead time period Td1, or at a timing closest to that carrier cycle. The estimated value of the load current is, for example, a value estimated from the load current at a carrier cycle in which the additional time Tad is added to the first dead time period Td1. The inductance L of the resonant inductor L1 is a value pre-stored in the control device 51. The voltage value of the regenerative capacitor 15 is a detected value of the voltage V15 of the regenerative capacitor 15 (the potential V15 at the sixth terminal 154 of the regenerative capacitor 15). In the example of FIG. 4, the additional time Tad is a value obtained by calculating Tad = iU × (L / V15). In the example of FIG. 5, the additional time Tad is a value obtained by calculating Tad = iV × (L / V15). In the example of FIG. 6, the additional time Tad is a value obtained by calculating Tad = iW × (L / V15).

[0050] The length of the predetermined time is an ideal design example, and may be 90% or more and 110% or less of the additional time Tad.

[0051] In the power conversion device 100 , a signal generating circuit 52 separate from the control device 51 controls the multiple switches 8 .

[0052] The signal generating circuit 52 generates second control signals SU6, SU7, SV6, SV7, SW6, and SW7 that control the on / off of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively, and outputs these signals to the gate terminals of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively.

[0053] The signal generating circuit 52 generates, for each of the plurality of switches 8, a second control signal having a high-level period corresponding to the second dead-time period Td2 for the corresponding switching circuit 10 among the plurality of switching circuits 10. The signal generating circuit 52 fixes the length of the high-level period of the second control signal generated for each of the plurality of switches 8, and causes the start timing of the high-level period of the fixed length to follow the start timing of the second dead-time period Td2 for the corresponding switching circuit 10 among the plurality of switching circuits 10 for each of the plurality of switches 8. In the present disclosure, "synchronizing the start timing of the high-level period of the fixed length with the start timing of the second dead-time period Td2 for the corresponding switching circuit 10 among the plurality of switching circuits 10 for each of the plurality of switches 8" means that the start timing (start point) of the high-level period of the fixed length is between the start timing (start point) and end timing (end point) of the second dead-time period Td2, and the length of time between the start timing (start point) of the high-level period of the fixed length and the end timing (end point) of the second dead-time period Td2 is equal to or longer than the length of the first dead-time period Td1. In the first embodiment, the signal generating circuit 52 synchronizes the start timing of the high-level period of the second control signal to each of the plurality of switches 8 with the start timing of the second dead-time period Td2.

[0054] The signal generation circuit 52 generates a second control signal for each of the multiple switches 8 using one of the first control signal to the first switching element 1 and the first control signal to the second switching element 2 of the corresponding switching circuit 10 among the multiple switching circuits 10. FIG. 2 is a circuit block diagram of the signal generation circuit 52 in the power conversion device 100 according to the first embodiment. In this embodiment, the signal generation circuit 52 has, for example, multiple logic circuits 521 to 526 and multiple gate drive circuits 531 to 536, as shown in FIG. 2. In the signal generation circuit 52, the multiple logic circuits 521 to 526 correspond one-to-one to the multiple gate drive circuits 531 to 536.

[0055] The logic circuit 521 is configured to generate a second control signal SU6 using the first control signal SU2. The logic circuit 521 detects the falling edge of the first control signal SU2 to the second switching element 2U and generates a second control signal SU6 having a high-level period of a fixed length T2 (see FIG. 4). The logic circuit 521 includes, for example, a multivibrator M11. The first control signal SU2 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 521 outputs the second control signal SU6 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M11 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SU2 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of a CR time constant determined by the capacitance of a capacitor C11 and the resistance value of a resistor R11 connected to the multivibrator M11. The second control signal SU6 is supplied to the third switching element 6U via the gate drive circuit 531.

[0056] The logic circuit 522 is configured to generate a second control signal SU7 using the first control signal SU1. The logic circuit 522 detects the falling edge of the first control signal SU1 to the first switching element 1U and generates a second control signal SU7 having a high-level period of fixed length T2. The logic circuit 522 includes, for example, a multivibrator M21. The first control signal SU1 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 522 outputs the second control signal SU7 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M21 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SU1 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of the CR time constant determined by the capacitance of the capacitor C21 and the resistance value of the resistor R21 connected to the multivibrator M21. The second control signal SU7 is supplied to the fourth switching element 7U via the gate drive circuit 532.

[0057] The logic circuit 523 is configured to generate a second control signal SV6 using the first control signal SV2. The logic circuit 523 detects the falling edge of the first control signal SV2 to the second switching element 2V and generates a second control signal SV6 having a high-level period of a fixed length T2 (see FIG. 5). The logic circuit 523 includes, for example, a multivibrator M31. The first control signal SV2 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 523 outputs the second control signal SV6 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M31 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SV2 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of a CR time constant determined by the capacitance of a capacitor C31 and the resistance value of a resistor R31 connected to the multivibrator M31. The second control signal SV6 is supplied to the third switching element 6V via the gate drive circuit 533.

[0058] The logic circuit 524 is configured to generate a second control signal SV7 using the first control signal SV1. The logic circuit 524 detects the falling edge of the first control signal SV1 to the first switching element 1V and generates a second control signal SV7 having a high-level period of fixed length T2. The logic circuit 524 includes, for example, a multivibrator M41. The first control signal SV1 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 524 outputs the second control signal SV7 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M41 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SV1 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of the CR time constant determined by the capacitance of the capacitor C41 and the resistance value of the resistor R41 connected to the multivibrator M41. The second control signal SV7 is applied to the fourth switching element 7V via the gate drive circuit 534.

[0059] The logic circuit 525 is configured to generate a second control signal SW6 using the first control signal SW2. The logic circuit 525 detects the falling edge of the first control signal SW2 to the second switching element 2W and generates a second control signal SW6 having a high-level period of a fixed length T2 (see FIG. 6). The logic circuit 525 includes, for example, a multivibrator M51. The first control signal SW2 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 525 outputs the second control signal SW6 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M51 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SW2 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of a CR time constant determined by the capacitance of a capacitor C51 and the resistance value of a resistor R51 connected to the multivibrator M51. The second control signal SW6 is supplied to the third switching element 6W via the gate drive circuit 535.

[0060] The logic circuit 526 is configured to generate a second control signal SW7 using the first control signal SW1. The logic circuit 526 detects the falling edge of the first control signal SW1 to the first switching element 1W and generates a second control signal SW7 having a high-level period of fixed length T2. The logic circuit 526 includes, for example, a multivibrator M61. The first control signal SW1 output from the control device 51 is input to an inverting trigger terminal, and the logic circuit 526 outputs the second control signal SW7 from an inverting output terminal (represented by an overlined Q in FIG. 2). The multivibrator M61 is an edge-triggered monostable multivibrator that detects the falling edge of the first control signal SW1 and sets the output signal from the inverting output terminal to a high level for a fixed period (fixed length). The fixed length is the length of the CR time constant determined by the capacitance of the capacitor C61 and the resistance value of the resistor R61 connected to the multivibrator M61. The second control signal SW7 is supplied to the fourth switching element 7W via the gate drive circuit 536.

[0061] The first clamp diode 13 has an anode connected to the third end of the resonance inductor L1 and a cathode connected to the first DC terminal 31. The second clamp diode 14 has a cathode connected to the third end of the resonance inductor L1 and an anode connected to the second DC terminal 32.

[0062] (3) Operation of the Power Conversion Device In the following description, the polarity of current iL1 flowing through resonant inductor L1 will be defined as positive when flowing in the direction of the arrow in Fig. 1, and as negative when flowing in the direction opposite to the direction of the arrow in Fig. 1. Also, in the following description, the polarity of load currents iU, iV, and iW flowing through the U, V, and W phases of AC load RA1 will be defined as positive when flowing in the direction of the arrow in Fig. 1, and as negative when flowing in the direction opposite to the direction of the arrow in Fig. 1. Also, in the following description, the polarity of currents i9U, i9V, and i9W flowing through resonant capacitors 9U, 9V, and 9W will be defined as positive when flowing in the direction of the arrow in Fig. 1, and as negative when flowing in the direction opposite to the direction of the arrow in Fig. 1. Therefore, in the case of a discharge operation in which the resonant capacitors 9U, 9V, and 9W are discharged, the polarity of the currents i9U, i9V, and i9W is positive, and in the case of a charge operation in which the resonant capacitors 9U, 9V, and 9W are charged, the polarity of the currents i9U, i9V, and i9W is negative.

[0063] In the following description, the switching element (the first switching element 1 or the second switching element 2) that is the target of zero voltage soft switching will also be referred to as the target switching element.

[0064] In the power conversion device 100, the target switching element is the first switching element 1 (hereinafter also referred to as the target first switching element 1), and when the polarity of the load current flowing through the AC terminal 41 connected to the target first switching element 1 is positive, the signal generating circuit 52 turns on the third switching element 6 corresponding to the target first switching element 1. As a result, the power conversion device 100 causes the resonant inductor L1 connected to the target first switching element 1 to resonate with the resonant capacitor 9, charging the resonant capacitor 9 from the regenerative capacitor 15 and setting the voltage across the target first switching element 1 to zero. As a result, the power conversion device 100 can achieve zero-voltage soft switching of the target first switching element 1.

[0065] Furthermore, in the power conversion device 100, when the target switching element is the second switching element 2 (hereinafter also referred to as the target second switching element 2) and the polarity of the load current flowing through the AC terminal 41 connected to the target second switching element 2 is negative, the signal generating circuit 52 turns on the fourth switching element 7 corresponding to the target second switching element 2. As a result, the power conversion device 100 causes the resonant capacitor 9 and the resonant inductor L1 connected to the target second switching element 2 to resonate, discharging the resonant capacitor 9 and setting the voltage across the target second switching element 2 to zero. As a result, the power conversion device 100 can achieve zero-voltage soft switching of the target second switching element 2.

[0066] When the control device 51 sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the second switching element 2.

[0067] 7 is a diagram illustrating the operation of the power conversion device 100 according to embodiment 1 when the load current of the U phase is positive. For example, when setting the second dead time period Td2 for the switching circuit 10U, if the polarity of the load current iU is positive, as shown in FIG. 7 , the control device 51 adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal SU2 to the second switching element 2U by a predetermined time (additional time Tad).

[0068] 7 illustrates the first control signals SU1, SU2, and SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U when the target switching element is the first switching element 1U of the switching circuit 10U. Also, in FIG. 7, the voltage value of the DC power supply E1 is illustrated as Vd.

[0069] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U becomes Vd at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends. Therefore, when the first control signal SU1 changes from low level to high level at time t13, the first switching element 1U is subjected to zero-voltage soft switching. 7 , the current iL1 flowing through the resonant inductor L1 begins at time t11, when the high-level period of the second control signal SU6 begins. At time t12, a predetermined time (additional time Tad) has elapsed since time t11, the current iL1 becomes the same as the load current iU. At time t13, when the second dead time period Td2 ends, the current iL1 becomes the same as the load current iU. Finally, at time t14, when a second predetermined time Tad2, which is the same length as the predetermined time (first predetermined time), has elapsed since time t13, the current iL1 becomes zero. In the signal generating circuit 52, the second control signal SU6 changes from low to high at time t11, when the first control signal SU2 changes from high to low. The current iL1 flowing between time t12 and time t13 is a resonant current (charging current for the resonant capacitor 9U) flowing from the regenerative capacitor 15 to the resonant capacitor 9U via the resonant inductor L1.

[0070] Hereinafter, a period T01 in which the absolute value of the current iL1 increases from zero to the absolute value of the load current (load current iU in the example of FIG. 7 ) will be referred to as a first period T01, a period T02 in which the absolute value of the current iL1 is greater than the load current (load current iU in the example of FIG. 7 ) will be referred to as a second period T02, and a period T03 in which the absolute value of the current iL1 decreases from the absolute value of the load current (load current iU in the example of FIG. 7 ) to zero will be referred to as a third period T03. In the power conversion device 100, when the current iL1 increases from zero to iL1=iU in the first period, the first period T01 transitions to a second period T02, and when a resonant current flows in the second period T02 and the first control signal to the target switching element changes from low level to high level, the second period T02 transitions to a third period T03.

[0071] In FIG. 7 , the first period T01 is the period from time t11 to time t12. The length of the first period T01 is the same as the first predetermined time (additional time Tad). FIG. 8 is a diagram illustrating the operation of the power conversion device 100 according to the first embodiment during the first period T01. In FIG. 8 , the current path of the current iL1 flowing through the resonant inductor L1 during the first period T01 in FIG. 7 is indicated by a bold solid line, and the current path of the load current iU flowing during the first period T01 is indicated by a bold dashed line. During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in an OFF state, and the third switching element 6U is in an ON state. During the first period T01, the current iL1 flows through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U. During the first period T01, the load current iU flows through a path passing through the second diode 5 connected in antiparallel to the second switching element 2U, the AC terminal 41U, and the AC load RA1.

[0072] In FIG. 7 , the second period T02 is the period from time t12 to time t13. The length of the second period T02 is the same as the length of the resonant half cycle. FIG. 9 is an explanatory diagram of the operation of the power conversion device 100 according to the first embodiment during the second period T02. In FIG. 9 , the current path of the current iL1 flowing through the resonant inductor L1 during the second period T02 in FIG. 7 is indicated by a bold solid line. During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the OFF state, and the third switching element 6U is in the ON state. During the second period T02, the current iL1 flows through the regenerative capacitor 15, the resonant inductor L1, the diode 71, and the third switching element 6U, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9.

[0073] In FIG. 7, the third period T03 is the period from time t13 to time t14. The length of the third period T03 is the same as the second predetermined time Tad2. FIG. 10 is an explanatory diagram of the operation of the power conversion device 100 according to the first embodiment during the third period T03. In FIG. 10, the current path of the current iL1 flowing through the resonant inductor L1 during the third period T03 in FIG. 7 is indicated by a bold solid line, and the current path of the load current iU flowing during the third period T03 is indicated by a bold dashed line. During the third period T03, the first switching element 1U is in the ON state, the second switching element 2U is in the OFF state, the third switching element 6U is in the ON state, and the fourth switching element 7U is in the OFF state. During the third period T03, the current iL1 flows through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U. This reduces the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through a path passing through the first DC terminal 31, the first switching element 1U, the AC terminal 41U and the AC load RA1.

[0074] 7, the fixed length T2 is longer than the second dead time period Td2, but the fixed length T2 may be the same as the length of the second dead time period Td2. In this case, during the third period T03, the first switching element 1U is in the ON state, and the second switching element 2U, the third switching element 6U, and the fourth switching element 7U are each in the OFF state. During the third period T03, the current iL1 flows through the regenerative capacitor 15, the resonant inductor L1, and the first clamp diode 13. This reduces the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the path of the first DC terminal 31, the first switching element 1U, the AC terminal 41U, and the AC load RA1.

[0075] When the control device 51 sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time to the first dead time period Td1 by shortening the high-level period of the first control signal to the first switching element 1.

[0076] 11 is a diagram illustrating the operation of the power conversion device 100 according to embodiment 1 when the polarity of the U-phase load current is negative. For example, when setting the second dead time period Td2 for the switching circuit 10U, if the polarity of the load current iU is negative, as shown in FIG. 11 , the control device 51 adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal SU1 to the first switching element 1U by the predetermined time (additional time Tad).

[0077] 11 illustrates the first control signals SU1, SU2, and SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U when the target switching element is the second switching element 2U of the switching circuit 10U. Also, in FIG. 11, the voltage value of the DC power supply E1 is illustrated as Vd.

[0078] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U becomes Vd at time t43 when the second dead time period Td2 immediately before the high-level period of the first control signal SU2 ends, and the voltage V2u across the second switching element 2U becomes zero at time t43 when the second dead time period Td2 ends. Therefore, when the first control signal SU2 changes from low level to high level at time t43, the second switching element 2U is subjected to zero-voltage soft switching. 11 , the current iL1 flowing through the resonant inductor L1 begins at time t41, when the high-level period of the second control signal SU7 begins, reaches the same value as the load current iU at time t42, when the additional time Tad has elapsed, reaches the same value as the load current iU at time t43, when the second dead-time period Td2 ends, and reaches zero at time t44, when a second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t43. In the signal generating circuit 52, the second control signal SU7 changes from low to high when the first control signal SU1 changes from high to low. The current iL1 flowing between time t42 and time t43 is the resonant current (the discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0079] 11, the first period T01 is the period from time t41 to time t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the first period T01, the current iL1 flows through a path that passes through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. Also, during the first period T01, the load current iU flows through a path that passes through the AC load RA1, the AC terminal 41U, and the first diode 4 connected in anti-parallel to the first switching element 1U.

[0080] In FIG. 11 , the second period T02 is the period from time t42 to time t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is a combined current of a current flowing from the AC terminal 41U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15, and a current (resonant current) flowing from the resonant capacitor 9U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. During the second period T02, the resonant capacitor 9 is discharged.

[0081] In FIG. 11 , the third period T03 is the period from time t43 to time t44. During the third period T03, the first switching element 1U and the third switching element 6U are each in an OFF state, and the second switching element 2U and the fourth switching element 7U are each in an ON state. During the third period T03, the current iL1 flows through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. This reduces the absolute value of the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the AC terminal 41U and the second switching element 2U.

[0082] 11, the fixed length T2 is longer than the second dead time period Td2, but the fixed length T2 may be the same as the length of the second dead time period Td2. In this case, during the third period T03, the second switching element 2U is in the ON state, and the first switching element 1U, the third switching element 6U, and the fourth switching element 7U are each in the OFF state. During the third period T03, the current iL1 flows through the second clamp diode 14, the resonant inductor L1, and the regenerative capacitor 15. This reduces the absolute value of the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the AC load RA1, the AC terminal 41U, the second switching element 2U, and the second DC terminal 32.

[0083] Although an example of setting the second dead time period Td2 for the switching circuit 10U has been described above, the same applies to the switching circuit 10V and the switching circuit 10W.

[0084] (4) Advantages The power conversion device 100 according to the first embodiment includes a first DC terminal 31 and a second DC terminal 32, a power conversion circuit 11, a plurality of AC terminals 41, a plurality of switches 8, a plurality of resonant capacitors 9, a resonant inductor L1, a regenerative capacitor 15, a control device 51, and a signal generation circuit 52. The power conversion circuit 11 includes a plurality of first switching elements 1 and a plurality of second switching elements 2. In the power conversion circuit 11, a plurality of switching circuits 10 are connected in parallel, each of which includes a plurality of first switching elements 1 and a plurality of second switching elements 2 connected in series in a one-to-one relationship. The control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10 by adding a predetermined time (additional time Tad) to a predetermined first dead time period Td1 between a high-level period of the first control signal to the first switching element 1 and a high-level period of the first control signal to the second switching element 2 so that the on periods of the first switching element 1 and the second switching element 2 do not overlap. The predetermined time is determined according to the current value of the load current, the inductance of the resonance inductor L1, and the voltage value of the regenerative capacitor 15. The signal generating circuit 52 sets the length of the high-level period of the second control signal generated for each of the multiple switches 8 to a fixed length T2, and causes the start timing of the high-level period of the fixed length T2 for each of the multiple switches 8 to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0085] According to the above configuration, zero-voltage soft switching can be achieved without directly controlling the multiple switches 8 for zero-voltage soft switching in the control device 51. More specifically, the control device 51 does not need to generate a second control signal for directly controlling the multiple switches 8 for zero-voltage soft switching. Therefore, zero-voltage soft switching of each of the multiple first switching elements 1 and the multiple second switching elements 2 can be achieved without directly controlling the multiple switches 8 in the control device 51. Furthermore, according to the above configuration, the length of the high-level period of the second control signal is set to a fixed length T2, which simplifies the circuit configuration of the signal generation circuit 52. Furthermore, according to the above configuration, the control device 51 does not need to generate and output the multiple second control signals SU6, SU7, SV6, SV7, SW6, and SW7. This simplifies the control device 51. For example, this prevents an increase in the number of control ports of a microcomputer included in the control device 51, thereby preventing the control device 51 from becoming larger.

[0086] The power conversion device 100 according to the first embodiment further includes a first clamp diode 13 and a second clamp diode 14. The first clamp diode 13 has an anode connected to the third end of the resonant inductor L1 and a cathode connected to the first DC terminal 31. The second clamp diode 14 has a cathode connected to the third end of the resonant inductor L1 and an anode connected to the second DC terminal 32. When setting the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, the control device 51 adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the second switching element 2. In addition, when the control device 51 sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the first switching element 1.

[0087] According to the above configuration, it is possible to achieve zero-voltage soft switching while further reducing the dead-time loss and the dead-time error.

[0088] Furthermore, in the power conversion device 100 according to the first embodiment, the signal generating circuit 52 generates a second control signal for each of the plurality of switches 8 using one of the first control signal to the first switching element 1 and the first control signal to the second switching element 2 of the corresponding switching circuit 10 among the plurality of switching circuits 10.

[0089] According to the above configuration, it is possible to easily generate a second control signal having a high-level period corresponding to the second dead time period Td2, and it is possible to simplify the signal generation circuit 52.

[0090] Furthermore, in the power conversion device 100 according to the first embodiment, the fixed length T2 is equal to or greater than the total length of the first period T01, the second period T02, and the third period T03. The length of the first period T01 is equal to the length of a predetermined time (additional time Tad). The length of the second period T02 is half the length of the resonance period. The length of the third period T03 is equal to the length of the first period T01.

[0091] According to the above configuration, it is possible to more reliably achieve zero voltage soft switching.

[0092] (Embodiment 2) A power conversion device 100A according to embodiment 2 will be described with reference to Figures 12 to 18. Regarding the power conversion device 100A according to embodiment 2, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Figures 1 and 2) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0093] (1) Configuration Fig. 12 is a circuit diagram of a system including a power conversion device 100A according to embodiment 2. Fig. 13 is a circuit block diagram of a signal generation circuit 52A in the power conversion device 100A according to embodiment 2. As shown in Figs. 12 and 13 , the power conversion device 100A differs from the power conversion device 100 in that it includes a signal generation circuit 52A instead of the signal generation circuit 52 of the power conversion device 100.

[0094] In the power conversion device 100A, a signal generating circuit 52A controls a plurality of switches 8.

[0095] The signal generating circuit 52A generates second control signals SU6, SU7, SV6, SV7, SW6, and SW7 that control the on / off of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively, and outputs these signals to the gate terminals of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively.

[0096] The signal generating circuit 52A generates, for each of the multiple switches 8, a second control signal having a high-level period corresponding to the second dead-time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10. In the second embodiment, the signal generating circuit 52A delays the start of the high-level period of the second control signal to each of the multiple switches 8 by a specified time T1 (see FIGS. 14 to 18 ) from the start of the second dead-time period Td2, and delays the end of the high-level period of the second control signal to each of the multiple switches 8 from the end of the second dead-time period Td2. The length of the high-level period of the second control signal to each of the multiple switches 8 (fixed length T2) is longer than the length of the first dead-time period Td1.

[0097] The signal generation circuit 52A generates a second control signal for each of the multiple switches 8 using one of the first control signal to the first switching element 1 and the first control signal to the second switching element 2 of a corresponding switching circuit 10 among the multiple switching circuits 10. The signal generation circuit 52A sets the length of the high-level period of the second control signal generated for each of the multiple switches 8 to a fixed length T2, and causes the start timing of the high-level period of the fixed length T2 to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10 for each of the multiple switches 8. In this embodiment, as shown in FIG. 13 , the signal generation circuit 52A has multiple logic circuits 521A to 526A and multiple gate drive circuits 531 to 536. In the signal generation circuit 52A, the multiple logic circuits 521A to 526A correspond one-to-one to the multiple gate drive circuits 531 to 536.

[0098] The logic circuit 521A is configured to generate a second control signal SU6 using the first control signal SU2. The logic circuit 521A detects the falling edge of the first control signal SU2 to the second switching element 2U and generates a second control signal SU6 having a high-level period of a fixed length T2. The logic circuit 521A includes, for example, two multivibrators M11 and M12 connected in series. Each of the two multivibrators M11 and M12 is an edge-triggered monostable multivibrator. In the logic circuit 521A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first multivibrator M11 is connected to the inverting trigger terminal of the second multivibrator M12. In the logic circuit 521A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C11 connected to the upstream multivibrator M11 and the resistance value of the resistor R11. Also, in the logic circuit 521A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C12 connected to the downstream multivibrator M12 and the resistance value of the resistor R12. The logic circuit 521A receives a first control signal SU2 output from the control device 51 as an input to the inverting trigger terminal of the upstream multivibrator M11, and outputs a second control signal SU6 from the output terminal Q of the downstream multivibrator M12. The second control signal SU6 is applied to the third switching element 6U via the gate drive circuit 531. Figure 14 is an explanatory diagram of the operation of the power conversion device 100A according to the second embodiment when the polarity of the U-phase load current is positive. 14 shows the first control signals SU1 and SU2, the output signal from the inverting output terminal of the upstream multivibrator M11, and the second control signal SU6 for the case where the target switching element is the first switching element 1U of the switching circuit 10U. In Fig. 14, the first control signal SU2 falls from high to low at time t10, the output signal from the inverting output terminal of the upstream multivibrator M11 falls from high to low at time t11, the first control signal SU1 changes from low to high at time t13, and the second control signal SU6 changes from high to low at time t14.

[0099] The logic circuit 522A is configured to generate a second control signal SU7 using the first control signal SU1. The logic circuit 522A detects the falling edge of the first control signal SU1 to the first switching element 1U and generates a second control signal SU7 having a high-level period of a fixed length T2. The logic circuit 522A includes, for example, two multivibrators M21 and M22 connected in series. Each of the two multivibrators M21 and M22 is an edge-triggered monostable multivibrator. In the logic circuit 522A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first multivibrator M21 is connected to the inverting trigger terminal of the second multivibrator M22. In the logic circuit 522A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C21 connected to the multivibrator M21 in the preceding stage and the resistance value of the resistor R21. Also, in the logic circuit 522A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C22 connected to the multivibrator M22 in the following stage and the resistance value of the resistor R22. The logic circuit 522A receives the first control signal SU1 output from the control device 51 as an input to the inverting trigger terminal of the multivibrator M21 in the preceding stage, and outputs a second control signal SU7 from the output terminal Q of the multivibrator M22 in the following stage. The second control signal SU7 is provided to the fourth switching element 7U via the gate drive circuit 532.

[0100] The logic circuit 523A is configured to generate a second control signal SV6 using the first control signal SV2. The logic circuit 523A detects the falling edge of the first control signal SV2 to the second switching element 2V and generates the second control signal SV6 having a high-level period of a fixed length T2. The logic circuit 523A includes, for example, two multivibrators M31 and M32 connected in series. Each of the two multivibrators M31 and M32 is an edge-triggered monostable multivibrator. In the logic circuit 523A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first multivibrator M31 is connected to the inverting trigger terminal of the second multivibrator M32. In the logic circuit 523A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C31 connected to the multivibrator M31 in the preceding stage and the resistance value of the resistor R31. Also, in the logic circuit 523A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C32 connected to the multivibrator M32 in the following stage and the resistance value of the resistor R32. The logic circuit 523A receives the first control signal SV2 output from the control device 51 as an input to the inverting trigger terminal of the multivibrator M31 in the preceding stage, and outputs a second control signal SV6 from the output terminal Q of the multivibrator M32 in the following stage. The second control signal SV6 is provided to the third switching element 6V via the gate drive circuit 533.

[0101] The logic circuit 524A is configured to generate a second control signal SV7 using the first control signal SV1. The logic circuit 524A detects the falling edge of the first control signal SV1 to the first switching element 1V and generates a second control signal SV7 having a high-level period of a fixed length T2. The logic circuit 524A includes, for example, two multivibrators M41 and M42 connected in series. Each of the two multivibrators M41 and M42 is an edge-triggered monostable multivibrator. In the logic circuit 524A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first-stage multivibrator M41 is connected to the inverting trigger terminal of the second-stage multivibrator M42. In the logic circuit 524A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C41 connected to the multivibrator M41 in the preceding stage and the resistance value of the resistor R41. Also, in the logic circuit 524A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C42 connected to the multivibrator M42 in the following stage and the resistance value of the resistor R42. The logic circuit 524A receives the first control signal SV1 output from the control device 51 as an input to the inverting trigger terminal of the multivibrator M41 in the preceding stage, and outputs a second control signal SV7 from the output terminal Q of the multivibrator M42 in the following stage. The second control signal SV7 is provided to the fourth switching element 7V via the gate drive circuit 534.

[0102] The logic circuit 525A is configured to generate a second control signal SW6 using the first control signal SW2. The logic circuit 525A detects the falling edge of the first control signal SW2 to the second switching element 2W and generates a second control signal SW6 having a high-level period of a fixed length T2. The logic circuit 525A includes, for example, two multivibrators M51 and M52 connected in series. Each of the two multivibrators M51 and M52 is an edge-triggered monostable multivibrator. In the logic circuit 525A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first-stage multivibrator M51 is connected to the inverting trigger terminal of the second-stage multivibrator M52. In the logic circuit 525A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C51 connected to the multivibrator M51 in the preceding stage and the resistance value of the resistor R51. Also, in the logic circuit 525A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C52 connected to the multivibrator M52 in the following stage and the resistance value of the resistor R52. The logic circuit 525A receives the first control signal SW2 output from the control device 51 as an input to the inverting trigger terminal of the multivibrator M51 in the preceding stage, and outputs the second control signal SW6 from the output terminal of the multivibrator M52 in the following stage. The second control signal SW6 is provided to the third switching element 6W via the gate drive circuit 535.

[0103] The logic circuit 526A is configured to generate a second control signal SW7 using the first control signal SW1. The logic circuit 526A detects the falling edge of the first control signal SW1 to the first switching element 1W and generates a second control signal SW7 having a high-level period of a fixed length T2. The logic circuit 526A includes, for example, two multivibrators M61 and M62 connected in series. Each of the two multivibrators M61 and M62 is an edge-triggered monostable multivibrator. In the logic circuit 526A, the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the first-stage multivibrator M61 is connected to the inverting trigger terminal of the second-stage multivibrator M62. In the logic circuit 526A, the specified time T1 is the length of a CR time constant determined by the capacitance of the capacitor C61 connected to the upstream multivibrator M61 and the resistance value of the resistor R61. Also, in the logic circuit 526A, the fixed length T2 is the length of a CR time constant determined by the capacitance of the capacitor C62 connected to the downstream multivibrator M62 and the resistance value of the resistor R62. The logic circuit 526A receives the first control signal SW1 output from the control device 51 as an input to the inverting trigger terminal of the upstream multivibrator M61, and outputs a second control signal SW7 from the inverting output terminal (represented by an overlined Q in FIG. 13 ) of the downstream multivibrator M62. The second control signal SW7 is provided to the fourth switching element 7W via the gate drive circuit 536.

[0104] (2) Operation Fig. 15 is a diagram illustrating the operation of the power conversion device 100A according to the second embodiment at a high load. Fig. 16 is a diagram illustrating the operation of the power conversion device 100A according to the second embodiment at a low load. Fig. 17 is a diagram illustrating the operation of the power conversion device 100A according to the second embodiment at no load.

[0105] 15 illustrates the first control signals SU1 and SU2, the output signal from the output terminal Q of the multivibrator M11 in the preceding stage, the output signal from the inverting output terminal (indicated by an overlined Q in FIGS. 13 and 15) of the multivibrator M12 in the following stage, the second control signal SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U, for the case where the target switching element is the first switching element 1U of the switching circuit 10U. Also, in FIG. 15, the voltage value of the DC power supply E1 is illustrated as Vd.

[0106] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U becomes Vd at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends. Therefore, when the first control signal SU1 changes from low level to high level at time t13, the first switching element 1U is subjected to zero-voltage soft switching. 15 , the current iL1 flowing through the resonant inductor L1 begins at time t11, when the high-level period of the second control signal SU6 begins. At time t12, when a predetermined time (additional time Tad) has elapsed, the current iL1 becomes the same as the load current iU. At time t13, when the second dead-time period Td2 ends, the current iL1 becomes the same as the load current iU. Finally, at time t14, when a second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t13, the current iL1 becomes zero. In the signal generating circuit 52A, the second control signal SU6 changes from low to high at time t11, when the first control signal SU2 changes from high to low. The current iL1 flowing between time t12 and time t13 is a resonant current (charging current for the resonant capacitor 9U) flowing from the regenerative capacitor 15 to the resonant capacitor 9U via the resonant inductor L1.

[0107] During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in an OFF state, and the third switching element 6U is in an ON state. During the first period T01, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in Fig. 8. Also, during the first period T01, the load current iU flows through the path passing through the second diode 5 connected in anti-parallel to the second switching element 2U, the AC terminal 41U, and the AC load RA1, as in Fig. 8.

[0108] During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are each in an OFF state, and the third switching element 6U is in an ON state. During the second period T02, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, and the third switching element 6U, as in Fig. 9, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9U.

[0109] During the third period T03, the first switching element 1U and the third switching element 6U are each in an ON state, and the second switching element 2U and the fourth switching element 7U are each in an OFF state. During the third period T03, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in FIG. 10. This reduces the current iL1 to zero. Also, during the third period T03, the load current iU flows through the path passing through the first DC terminal 31, the first switching element 1U, the AC terminal 41U, and the AC load RA1, as in FIG. 10.

[0110] 16 and 17, similar to Fig. 15, show the first control signals SU1 and SU2, the output signal from the output terminal Q of the front-stage multivibrator M11, the output signal from the inverting output terminal (indicated by an overlined Q in Figs. 13 and 15) of the rear-stage multivibrator M12, the second control signal SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U, for the case where the target switching element is the first switching element 1U of the switching circuit 10U. Also, in Figs. 16 and 17, the voltage value of the DC power supply E1 is shown as Vd.

[0111] 15 to 17 show different current values ​​of the load current iU. Fig. 15 shows the case where the load current iU has a maximum current value at a high load, Fig. 16 shows the case where the load current iU has a smaller current value than Fig. 15 at a low load, and Fig. 17 shows the case where the load current iU has a zero current value at a low load.

[0112] As shown in FIG. 15 , the fixed length T2 is the sum of the lengths of the first period T01, the second period T02, and the third period T03 when the load current iU is at its maximum under a high load. The length of the first period T01 is the length of a predetermined time (additional time Tad). The length of the second period T02 is half the length of the resonance period. The length of the third period T03 is the second predetermined time, which is the same as the first predetermined time. In FIGS. 15 to 17 , the lengths of the first period T01 are different from each other. In FIG. 17 , the length of the first period T01 is zero. Also, in FIGS. 15 to 17 , the lengths of the second period T02 are the same from each other. Also, in FIGS. 15 to 17 , the lengths of the third period T03 are different from each other. In FIG. 17 , the length of the third period T03 is zero. Therefore, in Figures 16 and 17, the fixed length T2 is longer than the total length of the first period T01, the second period T02, and the third period T03 when the load current iU is at its maximum at high load.

[0113] Fig. 18 is an explanatory diagram of the operation of the power conversion device 100A according to the second embodiment when the polarity of the U-phase load current is negative. Fig. 18 illustrates the first control signals SU1 and SU2, the output signal from the output terminal Q of the upstream multivibrator M11, the output signal from the inverting output terminal (indicated by an overlined Q in Figs. 13 and 15 ) of the downstream multivibrator M12, the second control signal SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U, for the case where the target switching element is the second switching element 2U of the switching circuit 10U. Also, Fig. 18 illustrates the voltage value of the DC power supply E1 as Vd.

[0114] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U becomes Vd at time t43 when the second dead time period Td2 immediately before the high-level period of the first control signal SU2 ends, and the voltage V2u across the second switching element 2U becomes zero at time t43 when the second dead time period Td2 ends. Therefore, when the first control signal SU2 changes from low level to high level at time t43, the second switching element 2U is subjected to zero-voltage soft switching. 18 , the current iL1 flowing through the resonant inductor L1 begins at time t41, when the high-level period of the second control signal SU7 begins. At time t42, when a predetermined time (additional time Tad) has elapsed, the current iL1 becomes the same as the load current iU. At time t43, when the second dead-time period Td2 ends, the current iL1 becomes the same as the load current iU. Finally, at time t44, when a second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t43, the current iL1 becomes zero. In the signal generating circuit 52A, the second control signal SU7 changes from low to high when the first control signal SU1 changes from high to low. The current iL1 flowing between time t42 and time t43 is the resonant current (the discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0115] 18, the first period T01 is the period from time t41 to time t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the first period T01, the current iL1 flows through a path that passes through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. Also, during the first period T01, the load current iU flows through a path that passes through the AC load RA1, the AC terminal 41U, and the first diode 4 connected in anti-parallel to the first switching element 1U.

[0116] In FIG. 18 , the second period T02 is the period from time t42 to time t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is a combined current of a current flowing from the AC terminal 41U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15, and a current (resonant current) flowing from the resonant capacitor 9U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. During the second period T02, the resonant capacitor 9 is discharged.

[0117] In FIG. 18 , the third period T03 is the period from time t43 to time t44. During the third period T03, the second switching element 2U is in the ON state, the first switching element 1U and the third switching element 6U are in the OFF state, and the fourth switching element 7U is in the ON state. During the third period T03, the current iL1 flows through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. This reduces the absolute value of the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the AC load RA1, the AC terminal 41U, the second switching element 2U, and the second DC terminal 32.

[0118] Although an example of setting the second dead time period Td2 for the switching circuit 10U has been described above, the same applies to the switching circuit 10V and the switching circuit 10W.

[0119] (3) Advantages In the power conversion device 100A according to the second embodiment, the control device 51 sets a second dead time period Td2 for each of the multiple switching circuits 10 between the high-level period of the first control signal to the first switching element 1 and the high-level period of the first control signal to the second switching element 2. The second dead time period Td2 is set by adding a predetermined time (additional time Tad) to a predetermined first dead time period Td1 so that the on periods of the first switching element 1 and the second switching element 2 do not overlap. The predetermined time is determined based on the current value of the load current, the inductance of the resonance inductor L1, and the voltage value of the regenerative capacitor 15. The signal generation circuit 52A sets the length of the high-level period of the second control signal generated for each of the multiple switches 8 to a fixed length T2, and causes the start timing of the high-level period of the fixed length T2 for each of the multiple switches 8 to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0120] According to the above configuration, zero-voltage soft switching can be achieved without directly controlling the multiple switches 8 for zero-voltage soft switching in the control device 51. More specifically, the control device 51 does not need to generate a second control signal for directly controlling the multiple switches 8 for zero-voltage soft switching. Therefore, zero-voltage soft switching of each of the multiple first switching elements 1 and the multiple second switching elements 2 can be achieved without directly controlling the multiple switches 8 in the control device 51. Furthermore, according to the above configuration, the length of the high-level period of the second control signal is set to a fixed length T2, which simplifies the circuit configuration of the signal generation circuit 52A. Furthermore, according to the above configuration, the control device 51 does not need to generate and output the multiple second control signals SU6, SU7, SV6, SV7, SW6, and SW7. This simplifies the control device 51. For example, this prevents an increase in the number of control ports of the microcomputer included in the control device 51, thereby preventing the control device 51 from becoming larger.

[0121] A power conversion device 100B according to a third embodiment will be described with reference to Fig. 19 to Fig. 21. Regarding the power conversion device 100B according to the third embodiment, the same components as those of the power conversion device 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0122] (1) Configuration Fig. 19 is a circuit diagram of a system including a power conversion device 100B according to embodiment 3. As shown in Fig. 19, the power conversion device 100B differs from the power conversion device 100 in that it includes a control device 51B instead of the control device 51 of the power conversion device 100.

[0123] In the power conversion device 100B, the control device 51B, like the control device 51, generates first control signals SU1, SU2, SV1, SV2, SV2, SW1, and SW2 to control multiple first switching elements 1 and multiple second switching elements 2.

[0124] When the control device 51B sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the first switching element 1.

[0125] When the control device 51B sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the second switching element 2.

[0126] (2) Operation Fig. 20 is a diagram illustrating the operation of the power conversion device 100B according to the third embodiment when the polarity of the U-phase load current is positive. Fig. 20 illustrates the first control signals SU1, SU2, and SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U when the target switching element is the first switching element 1U of the switching circuit 10U. Also, Fig. 20 illustrates the voltage value of the DC power supply E1 as Vd.

[0127] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U becomes Vd at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends. Therefore, when the first control signal SU1 changes from low level to high level at time t13, the first switching element 1U is subjected to zero-voltage soft switching. 20 , the current iL1 flowing through the resonant inductor L1 begins at time t11, when the high-level period of the second control signal SU6 begins. At time t12, when a predetermined time (additional time Tad) has elapsed, the current iL1 becomes the same as the load current iU. At time t13, when the second dead-time period Td2 ends, the current iL1 becomes the same as the load current iU. Finally, at time t14, when a second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t13, the current iL1 becomes zero. In the signal generating circuit 52, the second control signal SU6 changes from low to high at time t11, when the first control signal SU2 changes from high to low. The current iL1 flowing between time t12 and time t13 is a resonant current (charging current for the resonant capacitor 9U) that flows from the regenerative capacitor 15 to the resonant capacitor 9U via the resonant inductor L1.

[0128] During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in an OFF state, and the third switching element 6U is in an ON state. During the first period T01, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in Fig. 8. Also, during the first period T01, the load current iU flows through the path passing through the second diode 5 connected in anti-parallel to the second switching element 2U, the AC terminal 41U, and the AC load RA1, as in Fig. 8.

[0129] During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are each in an OFF state, and the third switching element 6U is in an ON state. During the second period T02, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, and the third switching element 6U, as in Fig. 9, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9U.

[0130] During the third period T03, the first switching element 1U and the third switching element 6U are each in an ON state, and the second switching element 2U and the fourth switching element 7U are each in an OFF state. During the third period T03, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in FIG. 10. This reduces the current iL1 to zero. Also, during the third period T03, the load current iU flows through the path passing through the first DC terminal 31, the first switching element 1U, the AC terminal 41U, and the AC load RA1, as in FIG. 10.

[0131] Fig. 21 is a diagram illustrating the operation of the power conversion device 100B according to the third embodiment when the polarity of the U-phase load current is negative. Fig. 21 illustrates the first control signals SU1, SU2, and SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U when the target switching element is the second switching element 2U of the switching circuit 10U. Also, Fig. 21 illustrates the voltage value of the DC power supply E1 as Vd.

[0132] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U becomes Vd at time t43 when the second dead time period Td2 immediately before the high-level period of the first control signal SU2 ends, and the voltage V2u across the second switching element 2U becomes zero at time t43 when the second dead time period Td2 ends. Therefore, when the first control signal SU2 changes from low level to high level at time t43, the second switching element 2U is subjected to zero-voltage soft switching. 21 , the current iL1 flowing through the resonant inductor L1 starts at time t41, when the high-level period of the second control signal SU7 begins, reaches the same value as the load current iU at time t42, when a predetermined time (additional time Tad) has elapsed, reaches the same value as the load current iU at time t43, when the second dead time period Td2 ends, and reaches zero at time t44, when a predetermined time (additional time Tad) has elapsed from time t43. In the signal generating circuit 52, the second control signal SU7 changes from low to high when the first control signal SU1 changes from high to low. The current iL1 flowing between time t42 and time t43 is the resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0133] 21, the first period T01 is the period from time t41 to time t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the first period T01, the current iL1 flows through a path that passes through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. Also, during the first period T01, the load current iU flows through a path that passes through the AC load RA1, the AC terminal 41U, and the first diode 4 connected in anti-parallel to the first switching element 1U.

[0134] In FIG. 21 , the second period T02 is the period from time t42 to time t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is a combined current of a current flowing from the AC terminal 41U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15, and a current (resonant current) flowing from the resonant capacitor 9U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. During the second period T02, the resonant capacitor 9 is discharged.

[0135] In FIG. 21 , the third period T03 is the period from time t43 to time t44. During the third period T03, the first switching element 1U and the third switching element 6U are each in an OFF state, and the second switching element 2U and the fourth switching element 7U are each in an ON state. During the third period T03, the current iL1 flows through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. This reduces the absolute value of the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the AC terminal 41U, the second switching element 2U, and the second DC terminal 32.

[0136] Although an example of setting the second dead time period Td2 for the switching circuit 10U has been described above, the same applies to the switching circuit 10V and the switching circuit 10W.

[0137] (3) Advantages In the power conversion device 100B according to the third embodiment, the control device 51B extends, for each of the multiple switching circuits 10, a first dead time period Td1 that is preset so that the on periods of the first switching element 1 and the second switching element 2 do not overlap between the high-level period of the first control signal to the first switching element 1 and the high-level period of the first control signal to the second switching element 2, to a second dead time period Td2 that is extended by a predetermined time (additional time Tad) that corresponds to the current value of the load current and the voltage value of the regenerative capacitor 15. The signal generation circuit 52 sets the length of the high-level period of the second control signal generated for each of the multiple switches 8 to a fixed length T2, and causes the start timing of the high-level period of the fixed length T2, for each of the multiple switches 8, to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0138] According to the above configuration, it is possible to realize zero voltage soft switching without directly controlling the plurality of switches 8 for zero voltage soft switching in the control device 51B.

[0139] Furthermore, in the power conversion device 100B, when the control device 51B sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time Tad) to the first dead time period by shortening the high-level period of the first control signal to the first switching element 1, and if the polarity of the load current is negative, it adds a predetermined time (additional time Tad) to the first dead time period Td1 by shortening the high-level period of the first control signal to the second switching element 2.

[0140] According to the above configuration, it is possible to realize zero voltage soft switching.

[0141] (Fourth embodiment) A power conversion device 100C according to a fourth embodiment will be described with reference to Fig. 22 to Fig. 24. Regarding the power conversion device 100C according to the fourth embodiment, components that are the same as those of the power conversion device 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0142] (1) Configuration Fig. 22 is a circuit diagram of a system including a power conversion device 100C according to embodiment 4. As shown in Fig. 22, the power conversion device 100C differs from the power conversion device 100 in that it includes a control device 51C instead of the control device 51 of the power conversion device 100.

[0143] In the power conversion device 100C, the control device 51C, like the control device 51, generates first control signals SU1, SU2, SV1, SV2, SV2, SW1, and SW2 to control multiple first switching elements 1 and multiple second switching elements 2.

[0144] When setting the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, the control device 51C adds a predetermined time to the first dead time period Td1 by advancing the end point of the high-level period of the first control signal to the second switching element 2 and delaying the start point of the high-level period of the first control signal to the first switching element 1. If the time by which the end point of the high-level period of the first control signal to the second switching element 2 is advanced is Ta21 (see FIG. 23 ) and the time by which the start point of the high-level period of the first control signal to the first switching element 1 is delayed is Ta11 (see FIG. 23 ), then the predetermined time is Ta11 + Ta21.

[0145] When the polarity of the load current is negative, the control device 51C adds a predetermined time to the first dead time period Td1 by advancing the end point of the high-level period of the first control signal to the first switching element 1 and delaying the start point of the high-level period of the first control signal to the second switching element 2. If the time by which the end point of the high-level period of the first control signal to the first switching element 1 is advanced is Ta12 (see FIG. 24 ) and the time by which the start point of the high-level period of the first control signal to the second switching element 2 is delayed is Ta22 (see FIG. 24 ), then the predetermined time is Ta12 + Ta22.

[0146] (2) Operation Fig. 23 is a diagram illustrating the operation of the power conversion device 100C according to the fourth embodiment when the polarity of the U-phase load current is positive. Fig. 23 illustrates the first control signals SU1, SU2, and SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U when the target switching element is the first switching element 1U of the switching circuit 10U. Also, Fig. 23 illustrates the voltage value of the DC power supply E1 as Vd.

[0147] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U becomes Vd at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13 when the second dead time period Td2 immediately before the high-level period of the first control signal SU1 ends. Therefore, when the first control signal SU1 changes from low level to high level at time t13, the first switching element 1U is subjected to zero-voltage soft switching. 23 , the current iL1 flowing through the resonant inductor L1 starts at time t11, when the high-level period of the second control signal SU6 begins, reaches the same value as the load current iU at time t12, when a time period equal to the additional time Tad has elapsed, reaches the same value as the load current iU at time t13, when the second dead time period Td2 ends, and becomes zero at time t14, when the third period T03 has elapsed since time t13. In the signal generating circuit 52, the second control signal SU6 changes from low to high at time t11, when the first control signal SU2 changes from high to low. The current iL1 flowing between time t12 and time t13 is a resonant current (charging current for the resonant capacitor 9U) that flows from the regenerative capacitor 15 through the resonant inductor L1 to the resonant capacitor 9U.

[0148] During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in an OFF state, and the third switching element 6U is in an ON state. During the first period T01, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in Fig. 8. Also, during the first period T01, the load current iU flows through the path passing through the second diode 5 connected in anti-parallel to the second switching element 2U, the AC terminal 41U, and the AC load RA1, as in Fig. 8.

[0149] During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are each in an OFF state, and the third switching element 6U is in an ON state. During the second period T02, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, and the third switching element 6U, as in Fig. 9, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9U.

[0150] During the third period T03, the first switching element 1U is in the ON state, and the second switching element 2U, the third switching element 6U, and the fourth switching element 7U are each in the OFF state. During the third period T03, the current iL1 flows through the path passing through the regenerative capacitor 15, the resonant inductor L1, the diode 71, the third switching element 6U, and the AC terminal 41U, as in FIG. 10. This reduces the current iL1 to zero. Also, during the third period T03, the load current iU flows through the path passing through the first DC terminal 31, the first switching element 1U, the AC terminal 41U, and the AC load RA1, as in FIG. 10.

[0151] Fig. 24 is a diagram illustrating the operation of the power conversion device 100C according to the fourth embodiment when the polarity of the U-phase load current is negative. Fig. 24 illustrates the first control signals SU1, SU2, and SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U when the target switching element is the second switching element 2U of the switching circuit 10U. Also, Fig. 24 illustrates the voltage value of the DC power supply E1 as Vd.

[0152] In the switching circuit 10U, when the target switching element is the second switching element 2U, the voltage V1u across the first switching element 1U becomes Vd at time t43, which is the end of the second dead time period Td2 immediately before the high-level period of the first control signal SU2, and the voltage V2u across the second switching element 2U becomes zero at time t43, which is the end of the second dead time period Td2. Therefore, when the first control signal SU2 changes from low to high at time t43, the second switching element 2U is subjected to zero-voltage soft switching. In the example of FIG. 24 , the current iL1 flowing through the resonant inductor L1 begins at time t41, which is the start of the high-level period of the second control signal SU7, and becomes the same value as the load current iU at time t42, which is the same length of time as the predetermined time, at time t43, which is the end of the second dead time period Td2, and becomes zero at time t44, which is the same length of time as the predetermined time from time t43. In the signal generating circuit 52, the second control signal SU7 changes from low to high when the first control signal SU1 changes from high to low. The current iL1 flowing between time t42 and time t43 is a resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0153] 24, the first period T01 is the period from time t41 to time t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the first period T01, the current iL1 flows through a path that passes through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. Also, during the first period T01, the load current iU flows through a path that passes through the AC load RA1, the AC terminal 41U, and the first diode 4 connected in anti-parallel to the first switching element 1U.

[0154] In FIG. 24 , the second period T02 is the period from time t42 to time t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in an OFF state, and the fourth switching element 7U is in an ON state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is a combined current of a current flowing from the AC terminal 41U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15, and a current (resonant current) flowing from the resonant capacitor 9U through the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. During the second period T02, the resonant capacitor 9 is discharged.

[0155] In FIG. 24 , the third period T03 is the period from time t43 to time t44. During the third period T03, the first switching element 1U and the third switching element 6U are each in an OFF state, and the second switching element 2U and the fourth switching element 7U are each in an ON state. During the third period T03, the current iL1 flows through the AC terminal 41U, the diode 61, the fourth switching element 7U, the resonant inductor L1, and the regenerative capacitor 15. This reduces the absolute value of the current iL1 to zero. Furthermore, during the third period T03, the load current iU flows through the AC terminal 41U, the second switching element 2U, and the second DC terminal 32.

[0156] Although an example of setting the second dead time period Td2 for the switching circuit 10U has been described above, the same applies to the switching circuit 10V and the switching circuit 10W.

[0157] (3) Advantages In the power conversion device 100C according to the fourth embodiment, the control device 51C sets a second dead time period Td2 for each of the multiple switching circuits 10 between the high-level period of the first control signal to the first switching element 1 and the high-level period of the first control signal to the second switching element 2. The second dead time period Td2 is set by adding a predetermined time (additional time Tad) to a predetermined first dead time period Td1 so that the on periods of the first switching element 1 and the second switching element 2 do not overlap. The predetermined time is determined based on the current value of the load current, the inductance of the resonance inductor L1, and the voltage value of the regenerative capacitor 15. The signal generation circuit 52 sets the length of the high-level period of the second control signal generated for each of the multiple switches 8 to a fixed length T2, and causes the start timing of the high-level period of the fixed length T2 for each of the multiple switches 8 to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0158] According to the above configuration, it is possible to realize zero voltage soft switching without directly controlling the plurality of switches 8 for zero voltage soft switching in the control device 51C.

[0159] Furthermore, in the power conversion device 100C, when the control device 51C sets the second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time to the first dead time period Td1 by advancing the end point of the high level period of the first control signal to the second switching element 2 and delaying the start point of the high level period of the first control signal to the first switching element 1, and if the polarity of the load current is negative, it adds a predetermined time to the first dead time period Td1 by advancing the end point of the high level period of the first control signal to the first switching element 1 and delaying the start point of the high level period of the first control signal to the second switching element 2.

[0160] According to the above configuration, it is possible to realize zero-voltage soft switching while reducing dead-time loss and dead-time error.

[0161] (Embodiment 5) A power conversion device 100 according to embodiment 5 will be described with reference to Fig. 25. That is, Fig. 25 is a circuit diagram of a system including the power conversion device 100 according to embodiment 5. With regard to the power conversion device 100 according to embodiment 5, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0162] In the power conversion device 100 according to the fifth embodiment, the third switching element 6 and the fourth switching element 7 are connected in anti-series in each of the multiple switches 8. In the power conversion device 100 according to the fifth embodiment, in each of the multiple switches 8, the second main terminal (emitter terminal) of the third switching element 6 and the second main terminal (emitter terminal) of the fourth switching element 7 are connected, the first main terminal (collector terminal) of the third switching element 6 is connected to the connection point 3 of a corresponding one of the multiple switching circuits 10, and the first terminal (collector terminal) of the fourth switching element 7 is connected to the resonance inductor L1. Each of the multiple switches 8 further includes a diode 61 connected in anti-parallel to the third switching element 6 and a diode 71 connected in anti-parallel to the fourth switching element 7.

[0163] The power conversion device 100 according to the fifth embodiment has the same advantages as the power conversion device 100 according to the first embodiment.

[0164] In the power conversion device 100 according to the fifth embodiment, each of the third switching element 6 and the fourth switching element 7 may be replaced with a MOSFET or a bipolar transistor. In this case, the diode 61 and the diode 71 in FIG. 26 may be substituted with a parasitic diode of the replaced element, or an element built into the chip of the replaced element. Furthermore, in the power conversion device 100 according to the fifth embodiment, the diode 61 and the diode 71 are not limited to being externally connected to the third switching element 6 and the fourth switching element 7, but may also be built into the chip.

[0165] Sixth Embodiment A power conversion device 100 according to a sixth embodiment will be described with reference to Fig. 26. That is, Fig. 26 is a circuit diagram of a system including the power conversion device 100 according to the sixth embodiment. With respect to the power conversion device 100 according to the sixth embodiment, components that are the same as those of the power conversion device 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0166] In the power conversion device 100 according to the sixth embodiment, in each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 are each a MOSFET, and the third switching element 6 and the fourth switching element 7 are connected in anti-series. In the power conversion device 100 according to the sixth embodiment, in each of the multiple switches 8, a first main terminal (drain terminal) of the third switching element 6 is connected to a first main terminal (drain terminal) of the fourth switching element 7. Each of the multiple switches 8 further includes a diode 61 connected in anti-parallel to the third switching element 6 and a diode 71 connected in anti-parallel to the fourth switching element 7. In each of the multiple switches 8, a second main terminal (source terminal) of the fourth switching element 7 is connected to a resonance inductor L1. In each of the multiple switches 8, a second main terminal (source terminal) of the third switching element 6 is connected to a connection point 3 of a switching circuit 10 corresponding to the switch 8 having the third switching element 6.

[0167] The power conversion device 100 according to the sixth embodiment has the same advantages as the power conversion device 100 according to the first embodiment.

[0168] (Seventh embodiment) A power conversion device 100 according to a seventh embodiment will be described with reference to Fig. 27. That is, Fig. 27 is a circuit diagram of a system including the power conversion device 100 according to the seventh embodiment. With regard to the power conversion device 100 according to the seventh embodiment, components that are the same as those of the power conversion device 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0169] In the power conversion device 100 according to the seventh embodiment, in each of the plurality of switches 8, the third switching element 6 and the fourth switching element 7 are each a MOSFET, a diode 63 is connected in series to the third switching element 6, and a diode 73 is connected in series to the fourth switching element 7. In the power conversion device 100 according to the seventh embodiment, in each of the plurality of switches 8, a series circuit of the third switching element 6 and the diode 63 and a series circuit of the fourth switching element 7 and the diode 73 are connected in anti-parallel.

[0170] The power conversion device 100 according to the seventh embodiment has the same advantages as the power conversion device 100 according to the first embodiment.

[0171] Eighth Embodiment A power conversion device 100D according to an eighth embodiment will be described with reference to Fig. 28 and Fig. 29. That is, Fig. 28 is a circuit diagram of a system including the power conversion device 100D according to the eighth embodiment. Fig. 29 is a circuit block diagram of a signal generation circuit 52D in the power conversion device 100D according to the eighth embodiment.

[0172] Regarding the power conversion device 100D according to the eighth embodiment, the same components as those of the power conversion device 100A according to the second embodiment (see FIG. 12) are denoted by the same reference numerals and description thereof will be omitted.

[0173] In the power conversion device 100D according to the eighth embodiment, each of the multiple switches 8 includes one MOSFET 80, a diode 83 connected in anti-parallel to the MOSFET 80, a series circuit of two diodes 84 and 85 connected in anti-parallel to the MOSFET 80, and a series circuit of two diodes 86 and 87 connected in anti-parallel to the MOSFET 80. In each of the multiple switches 8, a connection point between the diode 84 and the diode 85 in the switch 8 (a first end 81 of the switch 8) is connected to a connection point 3 of a corresponding switching circuit 10 among the multiple switching circuits 10, and a connection point between the diode 86 and the diode 87 (a second end 82 of the switch 8) is connected to the common connection point 25. In each of the switches 8, when the MOSFET 80 is in an on state, the switch 8 is in an on state, and when the MOSFET 80 is in an off state, the switch 8 is in an off state.

[0174] The power conversion device 100D according to the eighth embodiment includes a signal generation circuit 52D instead of the signal generation circuit 52A (see FIGS. 12 and 13) of the power conversion device 100A according to the second embodiment.

[0175] The MOSFETs 80 of the multiple switches 8 are controlled by a signal generation circuit 52D. The signal generation circuit 52D outputs a second control signal SU8 that controls the on / off state of the MOSFET 80 of the switch 8U, a second control signal SV8 that controls the on / off state of the MOSFET 80 of the switch 8V, and a second control signal SW8 that controls the on / off state of the MOSFET 80 of the switch 8W. As shown in FIG. 29 , for example, the signal generation circuit 52D generates the second control signal SU8 using the first control signals SU1 and SU2. The signal generation circuit 52D also generates the second control signal SV8 using the first control signals SV1 and SV2. The signal generation circuit 52D also generates the second control signal SW8 using the first control signals SW1 and SW2.

[0176] The signal generation circuit 52D has substantially the same configuration as the signal generation circuit 52A, but differs from the signal generation circuit 52A in that it further includes three OR circuits 541 to 543. The OR circuit 541 is a two-input, one-output OR circuit that receives the output signal of the gate drive circuit 531 (corresponding to the second control signal SU6 in the signal generation circuit 52A) and the output signal of the gate drive circuit 532 (corresponding to the second control signal SU7 in the signal generation circuit 52A) and outputs a second control signal SU8. The OR circuit 542 is a two-input, one-output OR circuit that receives the output signal of the gate drive circuit 533 (corresponding to the second control signal SV6 in the signal generation circuit 52A) and the output signal of the gate drive circuit 534 (corresponding to the second control signal SV7 in the signal generation circuit 52A) and outputs a second control signal SV8. The logical sum circuit 543 is a two-input, one-output logical sum circuit, which receives the output signal of the gate drive circuit 535 (corresponding to the second control signal SW6 in the signal generation circuit 52A) and the output signal of the gate drive circuit 536 (corresponding to the second control signal SW7 in the signal generation circuit 52A), and outputs a second control signal SV8.

[0177] In the switch 8, when the MOSFET 80 is in the on state, a resonant current flows due to a resonant circuit including the resonant inductor L1 and the resonant capacitor 9. In the power conversion device 100D according to the eighth embodiment, when one of the multiple switches 8 is in the on state, a charging current including the resonant current flows through the path of the regenerative capacitor 15, the resonant inductor L1, the diode 86, the MOSFET 80, the diode 85, and the resonant capacitor 9. In addition, in the power conversion device 100D according to the eighth embodiment, when one of the multiple switches 8 is in the on state, a discharging current including the resonant current flows through the path of the resonant capacitor 9, the diode 84, the MOSFET 80, the diode 87, the resonant inductor L1, and the regenerative capacitor 15.

[0178] The power conversion device 100D according to the eighth embodiment has the same advantages as the power conversion device 100A according to the second embodiment.

[0179] In the power conversion device 100D according to the eighth embodiment, each of the plurality of MOSFETs 80 may be replaced with an IGBT. Furthermore, in the power conversion device 100D according to the eighth embodiment, each of the plurality of switches 8 may have, instead of the MOSFET 80, a bipolar transistor or a GaN-based GIT (Gate Injection Transistor), for example.

[0180] (Embodiment 9) A power conversion device 100 according to embodiment 9 will be described with reference to Fig. 30. That is, Fig. 30 is a circuit diagram of a system including the power conversion device 100 according to embodiment 9. Regarding the power conversion device 100 according to embodiment 9, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0181] In the power conversion device 100 according to the ninth embodiment, each of the multiple switches 8 is a dual-gate GaN-based GIT having a first source terminal, a first gate terminal, a second gate terminal, and a second source terminal. In the power conversion device 100 according to the ninth embodiment, a second control signal SU6 is applied between the first gate terminal and the first source terminal of the dual-gate GaN-based GIT constituting the switch 8U, and a second control signal SU7 is applied between the second gate terminal and the second source terminal of the dual-gate GaN-based GIT constituting the switch 8V. A second control signal SV6 is applied between the first gate terminal and the first source terminal of the dual-gate GaN-based GIT constituting the switch 8V, and a second control signal SV7 is applied between the second gate terminal and the second source terminal of the dual-gate GaN-based GIT constituting the switch 8W. A second control signal SW6 is applied between the first gate terminal and the first source terminal of the dual-gate GaN-based GIT, and a second control signal SW7 is applied between the second gate terminal and the second source terminal of the dual-gate GaN-based GIT constituting the switch 8W.

[0182] The power conversion device 100 according to the ninth embodiment has the same advantages as the power conversion device 100 according to the first embodiment.

[0183] (Embodiment 10) A power conversion device 100E according to embodiment 10 will be described with reference to Fig. 31. That is, Fig. 30 is a circuit diagram of a system including the power conversion device 100E according to embodiment 10. With regard to the power conversion device 100E according to embodiment 10, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0184] (1) Configuration The power conversion device 100E differs from the power conversion device 100 in that it further includes a regenerative capacitor 16 (hereinafter also referred to as the second regenerative capacitor 16) connected between the sixth end 154 of the regenerative capacitor 15 (hereinafter also referred to as the first regenerative capacitor 15) and the first DC terminal 31.

[0185] The second regenerative capacitor 16 is connected in series to the first regenerative capacitor 15. Therefore, in the power conversion device 100E, a series circuit of the second regenerative capacitor 16 and the first regenerative capacitor 15 is connected between the first DC terminal 31 and the second DC terminal 32. In the power conversion device 100E, a plurality of resonant inductors L1 are connected to a path between the first regenerative capacitor 15 and the second regenerative capacitor 16. The capacitance of the second regenerative capacitor 16 is the same as the capacitance of the first regenerative capacitor 15. The phrase "the capacitance of the second regenerative capacitor 16 is the same as the capacitance of the first regenerative capacitor 15" does not necessarily mean that the capacitance of the second regenerative capacitor 16 exactly matches the capacitance of the first regenerative capacitor 15, but may mean that the capacitance of the second regenerative capacitor 16 is within a range of 95% to 105% of the capacitance of the first regenerative capacitor 15.

[0186] In the power conversion device 100E according to the tenth embodiment, the voltage V15 of the first regeneration capacitor 15 (the potential at the sixth terminal 154 of the first regeneration capacitor 15) is equal to the value obtained by dividing the voltage Vd of the DC power supply E1 between the second regeneration capacitor 16 and the first regeneration capacitor 15. Therefore, the voltage V15 of the first regeneration capacitor 15 is approximately Vd / 2. In the power conversion device 100E according to the tenth embodiment, the control device 51 may store the value of the voltage V15 of the first regeneration capacitor 15 in advance.

[0187] (2) Advantages The operation of the control device 51 and the signal generating circuit 52 of the power conversion device 100E according to the tenth embodiment is similar to the operation of the control device 51 and the signal generating circuit 52 of the power conversion device 100 according to the first embodiment. Therefore, like the power conversion device 100 according to the first embodiment, the power conversion device 100E according to the tenth embodiment can achieve zero voltage soft switching without directly controlling the multiple switches 8 for zero voltage soft switching in the control device 51.

[0188] (Embodiment 11) A power conversion device 100F according to embodiment 11 will be described with reference to Fig. 32. That is, Fig. 32 is a circuit diagram of a system including the power conversion device 100F according to embodiment 11. With regard to the power conversion device 100F according to embodiment 11, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0189] (1) Configuration The power conversion device 100F differs from the power conversion device 100 in that the sixth end 154 of the regenerative capacitor 15 is connected to the first DC terminal 31.

[0190] (2) Operation The operation of the control device 51 and the signal generating circuit 52 of the power conversion device 100F according to the eleventh embodiment is similar to the operation of the control device 51 and the signal generating circuit 52 of the power conversion device 100 according to the first embodiment.

[0191] (3) Advantages Like the power conversion device 100 according to the first embodiment, the power conversion device 100F according to the eleventh embodiment can realize zero voltage soft switching without directly controlling the multiple switches 8 for zero voltage soft switching in the control device 51.

[0192] (Twelfth Embodiment) A power conversion device 100G according to a twelfth embodiment will be described with reference to Fig. 33. That is, Fig. 33 is a circuit diagram of a system including a power conversion device 100G according to a thirteenth embodiment. With respect to the power conversion device 100G according to the thirteenth embodiment, components similar to those of the power conversion device 100A according to the second embodiment (see Fig. 12) are denoted by the same reference numerals, and description thereof will be omitted.

[0193] (1) Configuration The power conversion device 100G differs from the power conversion device 100A according to the second embodiment in that the power conversion device 100G includes a plurality of resonance inductors L1 (three in the example of FIG. 33).

[0194] The fourth ends of the multiple resonant inductors L1 are connected to the sixth end 154 of the regenerative capacitor 15. The multiple resonant inductors L1 have the same inductance. That is, the three resonant inductors L1 have the same inductance. "The inductances of the three resonant inductors L1 are the same" does not necessarily mean that the inductance of each of two of the three resonant inductors L1 is completely the same as the inductance of the remaining resonant inductor L1, but may mean that the inductance of each of the two resonant inductors L1 is within a range of 95% to 105% of the inductance of the remaining resonant inductor L1.

[0195] (2) Operation The operation of the power conversion device 100G according to the twelfth embodiment is similar to the operation of the power conversion device 100A according to the second embodiment, and therefore a description thereof will be omitted.

[0196] (3) Advantages Like the power conversion device 100A according to the second embodiment, the power conversion device 100G according to the twelfth embodiment can achieve zero voltage soft switching without directly controlling the multiple switches 8 in the control device 51.

[0197] (Embodiment 13) A power conversion device 100H according to embodiment 13 will be described with reference to Fig. 34. That is, Fig. 34 is a circuit diagram of a system including the power conversion device 100H according to embodiment 13. With respect to the power conversion device 100H according to embodiment 13, components that are the same as those of the power conversion device 100 according to embodiment 1 (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0198] (1) Configuration The power conversion device 100H differs from the power conversion device 100 according to the first embodiment in that it includes a plurality of (three in the example of FIG. 34 ) resonance inductors L1. The power conversion device 100H also differs from the power conversion device 100 according to the first embodiment in that it includes a plurality of (three in the example of FIG. 34 ) first clamp diodes 13 and a plurality of (three in the example of FIG. 34 ) second clamp diodes 14.

[0199] The fourth ends of the multiple resonant inductors L1 are connected to the sixth end 154 of the regenerative capacitor 15. The multiple resonant inductors L1 have the same inductance. That is, the three resonant inductors L1 have the same inductance. "The inductances of the three resonant inductors L1 are the same" does not necessarily mean that the inductance of each of two of the three resonant inductors L1 is completely the same as the inductance of the remaining resonant inductor L1, but may mean that the inductance of each of the two resonant inductors L1 is within a range of 95% to 105% of the inductance of the remaining resonant inductor L1.

[0200] The first clamp diodes 13 correspond one-to-one to the resonance inductors L1. Each of the first clamp diodes 13 has an anode connected to the third end of a corresponding one of the resonance inductors L1 and a cathode connected to the first DC terminal 31.

[0201] The second clamp diodes 14 correspond one-to-one to the resonance inductors L1. Each of the second clamp diodes 14 has a cathode connected to the third end of a corresponding one of the resonance inductors L1 and an anode connected to the second DC terminal 32.

[0202] (2) Operation The operation of the power conversion device 100H according to the thirteenth embodiment is similar to the operation of the power conversion device 100 according to the first embodiment, and therefore a description thereof will be omitted. In the power conversion device 100H according to the thirteenth embodiment, when the load current is positive, the current iL1 of the resonant inductor L1 can be caused to flow through the first clamp diode 13 during the third period T03. In the power conversion device 100H according to the thirteenth embodiment, when the load current is negative, the current iL1 of the resonant inductor L1 can also be caused to flow through the second clamp diode 14 during the third period T03.

[0203] (3) Advantages Like the power conversion device 100 according to the first embodiment, the power conversion device 100H according to the thirteenth embodiment can realize zero voltage soft switching without directly controlling the multiple switches 8 for zero voltage soft switching in the control device 51.

[0204] (Modifications) The above-described embodiments 1 to 13 are merely examples of various embodiments of the present disclosure. The above-described embodiments 1 to 13 can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0205] For example, the signal generating circuits 52, 52A, 52D may be configured to generate a second control signal for each of the plurality of switches 8 using at least one of a first control signal to the first switching element 1 and a first control signal to the second switching element 2 of a corresponding one of the plurality of switching circuits 10.

[0206] In the power conversion device 100 according to the first embodiment, the diode 61 and the diode 71 are not limited to being externally attached to the third switching element 6 and the fourth switching element 7, respectively, but may also be elements built into one chip.

[0207] In addition, in the power conversion devices 100A to 100C according to embodiments 2 to 4, the configuration of the switch 8 is the same as the configuration of the switch 8 in the power conversion device 100 according to embodiment 1, but may be the same as the configuration of the switch 8 in any of embodiments 5 to 9.

[0208] Furthermore, in the power conversion devices 100, 100A to 100H, if the capacitance of each of the multiple resonant capacitors 9 is relatively small, instead of attaching the multiple resonant capacitors 9 externally, the parasitic capacitance between both ends of the multiple second switching elements 2 may also serve as the multiple resonant capacitors 9.

[0209] Furthermore, the length of the first dead time period Td1 is set to be the same as the resonance half cycle, but may be set to a length different from the resonance half cycle.

[0210] Furthermore, the power conversion devices 100, 100A to 100H are not limited to a configuration that outputs three-phase AC, but may be configured to output polyphase AC with three or more phases.

[0211] (Aspects) The following aspects are disclosed in this specification.

[0212] A power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a first aspect includes a first DC terminal (31), a second DC terminal (32), a power conversion circuit (11), a plurality of AC terminals (41), a plurality of switches (8), a plurality of resonant capacitors (9), at least one resonant inductor (L1), a regenerative capacitor (15), a control device (51; 51B; 51C), and a signal generation circuit (52; 52A; 52D). The power conversion circuit (11) has a plurality of first switching elements (1) and a plurality of second switching elements (2). In the power conversion circuit (11), a plurality of switching circuits (10), each including a plurality of first switching elements (1) and a plurality of second switching elements (2) connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit (11), a plurality of first switching elements (1) are connected to a first DC terminal (31). In the power conversion circuit (11), a plurality of second switching elements (2) are connected to a second DC terminal (32). A plurality of AC terminals (41) correspond one-to-one to the plurality of switching circuits (10). Each of the plurality of AC terminals (41) is connected to a connection point (3) between the first switching element (1) and the second switching element (2) in a corresponding one of the plurality of switching circuits (10), through which a load current flows. A plurality of switches (8) correspond one-to-one to the plurality of switching circuits (10). Each of the plurality of switches (8) has a first end (81) and a second end (82), and the first end (81) is connected to the connection point (3) between the first switching element (1) and the second switching element (2) in the corresponding one of the plurality of switching circuits (10). The plurality of resonant capacitors (9) correspond one-to-one to the plurality of switches (8). Each of the plurality of resonant capacitors (9) is connected between a first end (81) of a corresponding switch (8) among the plurality of switches (8) and a second DC terminal (32). At least one resonant inductor (L1) has a third end and a fourth end. The third end of the at least one resonant inductor (L1) is connected to a second end (82) of the corresponding switch (8) among the plurality of switches (8).The regenerative capacitor (15) has a fifth terminal (153) and a sixth terminal (154). The fifth terminal (153) of the regenerative capacitor (15) is connected to the second DC terminal (32), and the sixth terminal (154) is connected to the fourth terminal of at least one resonant inductor (L1). The control device (51; 51B; 51C) provides a first control signal, the potential of which changes between a high level and a low level, to each of the plurality of first switching elements (1) and the plurality of second switching elements (2). The signal generating circuit (52; 52A; 52E) provides a second control signal, the potential of which changes between a high level and a low level, to each of the plurality of switches (8). The control device (51; 51B; 51C) sets a second dead time period (Td2) for each of the multiple switching circuits (10) by adding a predetermined time (additional time Tad) to a predetermined first dead time period (Td1) between a high-level period of a first control signal to a first switching element (1) and a high-level period of a first control signal to a second switching element (2) so that the on periods of the first switching element (1) and the second switching element (2) do not overlap. The predetermined time (additional time Tad) is determined based on the current value of the load current, the inductance of the resonance inductor (L1), and the voltage value of the regenerative capacitor (15). The signal generating circuit (52; 52A; 52D) generates, for each of the multiple switches (8), a second control signal having a high-level period corresponding to the second dead time period (Td2) for a corresponding switching circuit (10) among the multiple switching circuits (10). The signal generating circuit (52; 52A; 52D) sets the length of the high-level period of the second control signal generated for each of the plurality of switches (8) to a fixed length (T2), and makes the start timing of the high-level period of the fixed length (T2) follow the start timing of the second dead time period (Td2) for the corresponding switching circuit (10) among the plurality of switching circuits (10) for each of the plurality of switches (8).

[0213] According to this aspect, it is possible to realize zero voltage soft switching without directly controlling the plurality of switches 8 in the control device (51; 51B; 51C).

[0214] A power conversion device (100; 100A; 100D; 100E; 100F; 100H) according to a second aspect is the same as the first aspect, but further includes a first clamp diode (13) and a second clamp diode (14). The first clamp diode (13) has an anode connected to a third end of at least one resonant inductor (L1) and a cathode connected to the first DC terminal (31). The second clamp diode (14) has a cathode connected to the third end of at least one resonant inductor (L1) and an anode connected to the second DC terminal (32). When setting the second dead time period (Td2) for each of the multiple switching circuits (10), the control device (51) adds a predetermined time (additional time Tad) to the first dead time period (Td1) by shortening the high-level period of the first control signal to the second switching element (2) when the polarity of the load current is positive, and adds a predetermined time (additional time Tad) to the first dead time period (Td1) by shortening the high-level period of the first control signal to the first switching element (1) when the polarity of the load current is negative.

[0215] According to this aspect, it is possible to achieve zero-voltage soft switching while further reducing the dead-time loss and the dead-time error.

[0216] In the power conversion device (100C) according to the third aspect, in the first aspect, when the control device (51C) sets the second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is positive, the control device (51C) advances the end point of the high-level period of the first control signal to the second switching element (2) and delays the start point of the high-level period of the first control signal to the first switching element (1), thereby adding a predetermined time (Ta11+Ta21) to the first dead time period (Td1), and if the polarity of the load current is negative, the control device (51C) advances the end point of the high-level period of the first control signal to the first switching element (1) and delays the start point of the high-level period of the first control signal to the second switching element (2), thereby adding a predetermined time (Ta12+Ta22) to the first dead time period (Td1).

[0217] According to this aspect, it is possible to achieve zero voltage soft switching while reducing dead time loss and dead time error.

[0218] In the power conversion device (100B) according to the fourth aspect, in the first aspect, when the control device (51B) sets the second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is positive, it adds a predetermined time (additional time Tad) to the first dead time period (Td1) by shortening the high-level period of the first control signal to the first switching element (1), and if the polarity of the load current is negative, it adds a predetermined time (additional time Tad) to the first dead time period (Td1) by shortening the high-level period of the first control signal to the second switching element (2).

[0219] According to this embodiment, it is possible to realize zero-voltage soft switching.

[0220] In a power conversion device (100A; 100G) according to a fifth aspect, in any one of the first to fourth aspects, the start of a high-level period of a second control signal generated for each of a plurality of switches (8) in a signal generating circuit (52A; 52D) is delayed by a specified time (T1) from the start of a second dead time period (Td2).

[0221] In a power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a sixth aspect, in any one of the first to fifth aspects, the signal generation circuit (52; 52A; 52D) generates a second control signal for each of the plurality of switches (8) using at least one of a first control signal to a first switching element (1) and a first control signal to a second switching element (2) of a corresponding switching circuit (10) among a plurality of switching circuits (10).

[0222] According to this aspect, it is possible to simplify the signal generating circuit (52; 52A; 52D).

[0223] In the power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to the seventh aspect, in the sixth aspect, the signal generating circuit (52; 52A; 52D) detects the falling edge of either the first control signal to the first switching element (1) or the first control signal to the second switching element (2) of a corresponding switching circuit (10) among a plurality of switching circuits (10) for each of the plurality of switches (8), and generates a second control signal of a fixed length (T2).

[0224] According to this aspect, it is possible to simplify the configuration of the signal generating circuit (52; 52A; 52D).

[0225] In a power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to an eighth aspect, the signal generation circuit (52; 52A; 52D) has a plurality of logic circuits (521-526; 521A-526A) that each generate a second control signal different from one another. Each of the plurality of logic circuits (521-526; 521A-526A) includes a multivibrator (M11-M61; M12-M62) that generates a second control signal having a high-level period of a fixed length (T2).

[0226] According to this aspect, it is possible to simplify the configuration of the signal generating circuit (52; 52A; 52D).

[0227] In a power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H) according to a ninth aspect, in any one of the first to eighth aspects, the fixed length (T2) is equal to or greater than the total length of the first period (T01), the second period (T02), and the third period (T03). The length of the first period (T01) is the length of a predetermined time (additional time Tad). The length of the second period (T02) is half the length of the resonance period (Tres) of a resonance circuit including at least one resonance inductor (L1) and one resonance capacitor (9) among a plurality of resonance capacitors (9). The length of the third period (T03) is the same as the length of the first period (T01).

[0228] According to this embodiment, it is possible to more reliably achieve zero voltage soft switching.

[0229] In a power conversion device (100; 100A; 100B; 100C; 100D; 100E; 100F) according to a tenth aspect, in any one of the first to ninth aspects, the at least one resonant inductor (L1) is a single resonant inductor (L1). Second ends (82) of the multiple switches (8) are commonly connected to the single resonant inductor (L1).

[0230] According to this aspect, the number of resonance inductors (L1) can be reduced to one, making it possible to achieve miniaturization.

[0231] The power conversion device of the present disclosure can achieve zero voltage soft switching without directly controlling multiple switches for zero voltage soft switching in a control device, making the power conversion device of the present disclosure industrially useful.

[0232] 1 First switching element 2 Second switching element 3 Connection point 4 First diode 5 Second diode 6 Third switching element 7 Fourth switching element 8 Switch 81 First terminal 82 Second terminal 9 Resonant capacitor 10 Switching circuit 13 First clamp diode 14 Second clamp diode 11 Power conversion circuit 15 Regenerative capacitor 153 Fifth terminal 154 Sixth terminal 31 First DC terminal 32 Second DC terminal 41 AC terminal 51, 51B, 51C Control device 52, 52A, 52D Signal generating circuit 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H Power conversion device iU, iV, iW Output current (load current) L1 Resonant inductor RA1 AC load SU1, SU2, SV1, SV2, SW1, SW2 First control signal SU6, SU7, SU8, SV6, SV7, SV8, SW6, SW7, SW8 Second control signal T01 First period T02 Second period T03 Third period Ta11 Time Ta12 Time Ta21 Time Ta22 Time Tad Additional time Td1 First dead time period Td2 Second dead time period Tres Resonance period V15 Voltage

Claims

a power conversion circuit having a first DC terminal and a second DC terminal, the power conversion circuit including a plurality of first switching elements and a plurality of second switching elements, the plurality of first switching elements being connected in series in a one-to-one relationship to each other, the plurality of first switching elements being connected to the first DC terminal, and the plurality of second switching elements being connected to the second DC terminal; a plurality of AC terminals corresponding one-to-one to the plurality of switching circuits, each connected to a connection point of the first switching elements and the second switching elements in the corresponding switching circuit, through which a load current flows; a plurality of switches corresponding one-to-one to the plurality of switching circuits, each having a first end and a second end, the first end of which is connected to the connection point of the first switching elements and the second switching elements in the corresponding switching circuit; a plurality of resonant capacitors corresponding one-to-one to the plurality of switches, each connected between the first end and the second DC terminal of the corresponding switch; and at least one resonant inductor having a third end and a fourth end, the third end being connected to the second end of the corresponding switch of the plurality of switches. a regenerative capacitor having a fifth end and a sixth end, the fifth end being connected to the second DC terminal and the sixth end being connected to the fourth end of the at least one resonant inductor; a control device that provides a first control signal, the potential of which changes between a high level and a low level, to each of the plurality of first switching elements and the plurality of second switching elements; and a signal generating circuit that provides a second control signal, the potential of which changes between a high level and a low level, to each of the plurality of switches, wherein the control device sets a second dead time period, which is a predetermined amount of time added to a first dead time period that is preset so that on periods of the first switching element and the second switching element do not overlap, between a high level period of the first control signal to the first switching element and a high level period of the first control signal to the second switching element for each of the plurality of switching circuits,a start timing of the high level period of the fixed length for each of the plurality of switches, the start timing of the high level period of the fixed length for each of the plurality of switches being in accordance with a start timing of the second dead time period for a corresponding one of the plurality of switching circuits, the signal generating circuit generating a high level period of the second control signal for each of the plurality of switches being in accordance with a current value of the load current, an inductance of the at least one resonant inductor, and a voltage value of the regenerative capacitor.

2. The power conversion device according to claim 1, further comprising: a first clamp diode having an anode connected to the third end of the at least one resonant inductor and a cathode connected to the first DC terminal; and a second clamp diode having a cathode connected to the third end of the at least one resonant inductor and an anode connected to the second DC terminal, wherein when setting the second dead time period for each of the multiple switching circuits, the control device adds the predetermined time to the first dead time period by shortening a high level period of the first control signal to the second switching element when the polarity of the load current is positive, and adds the predetermined time to the first dead time period by shortening a high level period of the first control signal to the first switching element when the polarity of the load current is negative.

3. The power conversion device according to claim 1, wherein, when setting the second dead-time period for each of the plurality of switching circuits, the control device adds the predetermined time to the first dead-time period by advancing an end point of a high-level period of the first control signal to the second switching element and delaying a start point of the high-level period of the first control signal to the first switching element when the polarity of the load current is positive, and adds the predetermined time to the first dead-time period by advancing the end point of the high-level period of the first control signal to the first switching element and delaying the start point of the high-level period of the first control signal to the second switching element when the polarity of the load current is negative.

4. The power conversion device of claim 1, wherein, when setting the second dead time period for each of the plurality of switching circuits, the control device adds the predetermined time to the first dead time period by shortening a high level period of the first control signal to the first switching element when the polarity of the load current is positive, and adds the predetermined time to the first dead time period by shortening a high level period of the first control signal to the second switching element when the polarity of the load current is negative.

5. A power conversion device according to any one of claims 1 to 4, wherein a start point of a high level period of the second control signal generated for each of the plurality of switches in the signal generating circuit is delayed by a specified time from a start point of the second dead time period.

6. A power conversion device as claimed in any one of claims 1 to 5, wherein the signal generating circuit generates the second control signal for each of the plurality of switches using at least one of the first control signal to the first switching element of a corresponding one of the plurality of switching circuits and the first control signal to the second switching element.

7. The power conversion device according to claim 6, wherein the signal generating circuit detects, for each of the plurality of switches, a falling edge of either the first control signal to the first switching element of a corresponding one of the plurality of switching circuits or the first control signal to the second switching element, and generates the second control signal of the fixed length.

8. The power conversion device according to claim 6, wherein the signal generating circuit has a plurality of logic circuits each generating the second control signal different from one another, and each of the plurality of logic circuits includes a multivibrator that generates the second control signal having a high-level period of the fixed length.

9. A power conversion device as claimed in any one of claims 1 to 8, wherein the fixed length is equal to or greater than the sum of the lengths of a first period, a second period, and a third period, the length of the first period being the predetermined time, the length of the second period being half the length of a resonance period of a resonance circuit including the at least one resonance inductor and one of the plurality of resonance capacitors, and the length of the third period being the same as the length of the first period.

10. A power conversion device according to any one of claims 1 to 9, wherein the at least one resonant inductor is a single resonant inductor, and the second ends of the multiple switches are commonly connected to the single resonant inductor.

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