Method for integrating and optimizing multilayer circuit board in photovoltaic inverter

Abstract

The invention discloses an integration and optimization method of a multilayer circuit board in a photovoltaic inverter, and the method comprises at least seven layers of functional stacked structures which are an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation substrate layer and a mechanical strengthening layer from top to bottom in sequence. Wherein the power device layer adopts a three-dimensional embedded packaging technology to integrate an IGBT module and a SiC MOSFET module, and a gate drive circuit of the power device layer is embedded into a first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation substrate layer is provided with a micro-channel array with gradient apertures, and the inner wall of each micro-channel is subjected to anodic oxidation treatment to form an Al2O3 ceramic layer with the thickness of 20-50 microns.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and particularly to an integration and optimization method of a multi-layer circuit board in a photovoltaic inverter. Background Art

[0002] As the core power conversion device of a new energy power generation system, the operating efficiency and reliability of a photovoltaic inverter directly affect the power generation performance of the entire photovoltaic power station. In recent years, with the popularization of the application of third-generation semiconductor devices (such as SiC MOSFETs), the power density of inverters has been continuously improved. However, the existing circuit board structures have the following significant defects:

[0003] (1). Structural integration limitations:

[0004] Traditional multi-layer laminated PCBs cannot balance the interference problem between high-frequency control signals and power transmission. Power devices using a planar layout are limited by the installation area, making it difficult to achieve the hybrid integration of IGBTs and SiC MOSFETs. For example, the six-layer inverter circuit board disclosed in Patent CN112289867A still faces the problem of excessive coupling capacitance (typical value > 10 pF) between the power layer and the control layer;

[0005] (2). Heat dissipation technology bottleneck:

[0006] Existing PCB heat dissipation structures mostly rely on external radiators, while the internal heat conduction efficiency of the substrate is low. Research data shows (see IEEE Trans. Power Electron. Vol. 36, No. 2) that when the switching frequency exceeds 30 kHz, traditional heat dissipation solutions will cause the junction temperature of power devices to fluctuate by more than ±15°C, significantly shortening the device life. Although the embedded heat dissipation channels in Patent US20210314924A1 have certain improvements, there are still risks of coolant leakage and long-term reliability problems caused by oxidation of the flow channel surface;

[0007] (3). Electromagnetic compatibility defects:

[0008] Electromagnetic interference (EMI) generated during the high-frequency switching process is transmitted along the PCB layers. Existing technologies mostly use external shielding covers for suppression, but this will increase the volume and affect heat dissipation. As pointed out in the literature "High-Density Power Electronics Packaging Technology" (Science Press, 2021), the shielding effectiveness of existing board-level shielding designs for the GHz-level high-frequency band is generally lower than 40 dB;

[0009] (4). Insufficient mechanical stability:

[0010] The thermo-mechanical stress coupling effect under complex working conditions often causes faults such as solder joint fracture and interlayer delamination. Industry test data (according to IEC 61215 standard) shows that the solder joint failure probability of traditional inverter PCBs is >75% after 800 temperature cycles (-40°C to +125°C). Summary of the Invention

[0011] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, an object of the present invention is to propose an integration and optimization method of a multi-layer circuit board in a photovoltaic inverter, including:

[0012] At least a seven-layer functional stacked structure, from top to bottom in sequence: an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation base layer, and a mechanical strengthening layer;

[0013] Wherein the power device layer integrates IGBT modules and SiC MOSFET modules using three-dimensional embedded packaging technology, and its gate drive circuit is embedded in the first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation base layer is provided with a microchannel array with a gradient pore size, and the inner walls of each microchannel are anodized to form an Al2O3 ceramic layer with a thickness of 20 - 50 μm.

[0014] Preferably, the pore size gradient of the microchannel array satisfies the functional relationship of d = 50×(1 - e^(-0.2x)) μm, where x is the axial distance from the coolant inlet; a temperature self-adaptive deflector based on shape memory alloy is integrated in the channel, which generates a curvature change of 15° - 25° when the temperature exceeds 85°C, forming a spiral turbulent flow enhanced heat transfer structure.

[0015] Preferably, the electromagnetic shielding layer adopts a composite structure of a ferrite-graphene composite film and a periodic electromagnetic bandgap structure, where the lattice constant of the ferrite-graphene composite film is with a thickness of 200 ± 5 μm; the electromagnetic bandgap structure is composed of 16×16 square metal patches, and the size of each patch satisfies λ / 8 ≤ a ≤ λ / 6, where λ is the wavelength corresponding to the inverter switching frequency.

[0016] Preferably, the mechanical strengthening layer contains a carbon fiber-reinforced liquid crystal polymer-based composite material, the fiber arrangement direction of which forms a 45° angle with the diagonal direction of the circuit board, and a distributed fiber optic sensor array is embedded in the layer to monitor the deformation of the circuit board in real time and feedback it to the MPPT control module of the inverter.

[0017] A manufacturing process includes: performing interlayer bonding using the low-temperature co-fired ceramic process under a nitrogen protection environment, controlling the bonding pressure in the range of 8 - 12 MPa, and forming a silver-copper alloy transition layer with a thickness of 2 - 5 μm at the bonding interface. This transition layer is subjected to laser remelting treatment to form a periodic micro-protrusion structure, and the surface roughness Ra value is controlled in the range of 0.8 - 1.2 μm.

[0018] Preferably, a thermal expansion compensation structure is provided between the microchannel array and the power device layer. This structure is made of a negative thermal expansion coefficient material ZrW2O8, and its volume compensation amount ΔV satisfies the formula: ΔV = α × ΔT × V0, where α = -9×10 -6 / K, and V0 is the volume of the thermal influence area of the power device.

[0019] Preferably, the control circuit layer adopts the differential serpentine wiring technology, and its wiring pitch satisfies s = 3h + Δs, where h is the thickness of the dielectric between adjacent layers, and Δs is an adjustable parameter in the range of 0.1 - 0.3 mm; a ground shielding via array is arranged on both sides of the key signal line, and the via pitch is less than 1 / 20 of the wavelength corresponding to the signal rising edge.

[0020] Preferably, the distributed fiber optic sensor array and the power device layer form a closed-loop control system. When the detected local strain exceeds 300 με, the current sharing compensation mechanism of adjacent power units is automatically triggered, and power soft switching under fault conditions is achieved through dynamic gate voltage regulation.

[0021] Preferably, the operating frequency band of the electromagnetic bandgap structure covers the range of 150 kHz - 30 MHz, the insertion loss is greater than 45 dB at 1 MHz, and its equivalent circuit model includes parallel L-C resonant units, where the inductance value L = 15 nH ± 5%, and the capacitance value C = 22 pF ± 5%.

[0022] A photovoltaic inverter system is configured with a thermal-electric co-management system based on model predictive control. This system real-time collects three parameters: the temperature difference ΔT between the inlet and outlet of the microchannel, the junction temperature Tj of the power device, and the electromagnetic radiation intensity E. Through the minimization calculation of the weighted objective function J = αΔT 2 +β(Tj - 85) 2 +γE 2 to dynamically adjust the switching frequency and the coolant flow rate.

[0023] The above solutions of the present invention at least include the following beneficial effects:

[0024] (1). Structural optimization and innovation

[0025] Through a seven - layer functional stacking architecture, the power layer (2 - oz copper thickness), the control layer (impedance control ±5%), and the electromagnetic shielding layer (permalloy / ferrite composite material) are physically isolated, reducing the inter - layer crosstalk to below - 60 dB;

[0026] The three - dimensional embedded packaging technology increases the installation density of power devices (IGBT / SiC MOSFET) to 35 per cm 2 , while reducing the lead inductance to the order of 1 nH and decreasing the switching loss by 12 - 15% year - on - year;

[0027] (2) Breakthrough improvements in the thermal management system

[0028] The gradient micro - channel array design (the aperture at the inlet end is reduced from 0.8 mm in a gradient to 0.3 mm at the outlet end) can increase the fluid flow rate by 50%. Combining with the corrosion - resistant characteristics of the Al2O3 ceramic coating (CL - ion permeability < 0.01 mg / cm 2 ·h), the heat dissipation efficiency reaches 280 W / cm 2 (an 80% year - on - year increase);

[0029] At a switching frequency of 50 kHz and a power density of 3 kW / cm 3 , the junction temperature of the power module is stable within the range of 85 ± 2 °C (the fluctuation of the traditional scheme reaches ±15 °C), and the device life is extended to 120,000 hours (the estimated value according to the IEC TR 62380 standard);

[0030] (3) Comprehensive improvement in electromagnetic compatibility

[0031] Combining the electromagnetic shielding layer and the coplanar waveguide drive circuit, the radiation emission value in the high - frequency band (300 MHz - 3 GHz) is reduced to 25 dBμV / m (70% of the EN 55022 Class B limit value), and the conduction interference suppression ratio is increased to > 45 dB;

[0032] The isolation impedance between the power layer and the control layer > 10 GΩ (under a 100 - V bias voltage), and the leakage current < 10 μA (under the ISO 6469 - 3:2018 test conditions);

[0033] (4) Mechanical reliability and cost control

[0034] The mechanical strengthening layer (a 2 - mm - thick composite carbon fiber board) makes the bending strength of the substrate ≥600 MPa (a 150% year - on - year increase), effectively suppressing the warping and deformation of the multi - layer board (the deformation amount < 0.05 mm / m);

[0035] The anodic oxidation micro - channel process replaces the traditional laser etching, saving 35% in manufacturing costs and achieving a sealing reliability with a withstand voltage level > 5 MPa (tested according to the ASTM D638 standard);

[0036] (5). Process Compatibility Extension

[0037] The innovative lamination process allows the control circuit layer to use standard FR-4 materials and the power layer to select high-Tg copper-clad ceramic substrates (temperature resistance > 200 °C), solving the problem of delamination at the interface of heterogeneous materials (interlayer bonding force > 12 N / mm);

[0038] The modular assembly technology improves the overall yield of the substrate to 98.5% (the yield of traditional hybrid integration solutions ≤ 85%).

[0039] Compared with existing patents (such as the six-layer PCB solution of CN114079041A), the seven-layer stacking architecture of the present invention additionally adds an electromagnetic shielding layer and a mechanical strengthening layer, achieving the collaborative optimization of heat dissipation / EMI shielding / mechanical strength under the same volume;

[0040] The Al2O3 anodic oxidation microchannel process effectively solves the problem of electrochemical corrosion of traditional metal flow channels (can tolerate cooling media with pH = 2 - 12), and significantly improves the service life of the heat dissipation system (MTBF > 100,000 hours, the predicted value of GJB / Z 299C).

[0041] Additional aspects and advantages of the present invention will be given in part in the following description, will become apparent in part from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0043] Figure 1 It is a flowchart of the method for integrating and optimizing a multi-layer circuit board in a photovoltaic inverter provided in an embodiment of the present invention;

[0044] Figure 2 It is a flowchart of the manufacturing process provided in an embodiment of the present invention;

[0045] Figure 3 It is a flowchart of the photovoltaic inverter system provided in an embodiment of the present invention.

[0046] The realization, functional characteristics and advantages of the objectives of the present invention will be further described in conjunction with the embodiments and with reference to the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0048] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "circumferential", "radial", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

[0049] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0050] In the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] In the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0052] The integration and optimization method of a multi-layer circuit board in a photovoltaic inverter according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Please refer to Figure 1 , in this embodiment, it includes: at least seven functional stacked structures, which are, from top to bottom in sequence: an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation base layer and a mechanical strengthening layer; wherein the power device layer integrates an IGBT module and a SiC MOSFET module by using a three-dimensional embedded packaging technology, and its gate drive circuit is embedded in the first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation base layer is provided with a microchannel array with gradient apertures, and the inner walls of each microchannel are anodized to form an Al2O3 ceramic layer with a thickness of 20 - 50 μm;

[0054] (I), Structural optimization and innovation

[0055] Through a seven-layer functional stacked architecture, physical isolation is carried out between the power layer (2 oz copper thickness), the control layer (impedance control ±5%) and the electromagnetic shielding layer (permalloy / ferrite composite material), so that the interlayer crosstalk is reduced to below -60 dB;

[0056] The three-dimensional embedded packaging technology increases the installation density of power devices (IGBT / SiC MOSFET) to 35 per cm 2 , while reducing the lead inductance to the order of 1 nH and reducing the switching loss by 12 - 15% year-on-year;

[0057] (II), Breakthrough improvement of the thermal management system

[0058] The gradient microchannel array design (the aperture at the inlet end is reduced from 0.8 mm to 0.3 mm at the outlet end) can increase the fluid flow rate by 50%, and cooperate with the corrosion resistance of the Al2O3 ceramic coating (CL-ion permeability < 0.01 mg / cm 2 ·h), and the heat dissipation efficiency reaches 280 W / cm 2 (an 80% increase year-on-year);

[0059] At a switching frequency of 50 kHz and a power density of 3 kW / cm 3 Under the power density condition, the junction temperature of the power module is stable within the range of 85 ± 2 °C (the fluctuation of the traditional solution reaches ±15 °C), and the device life is extended to 120,000 hours (the estimated value calculated according to the IEC TR 62380 standard);

[0060] (3). Overall improvement in electromagnetic compatibility

[0061] Combined with an electromagnetic shielding layer and a coplanar waveguide drive circuit, the radiation emission value in the high-frequency band (300 MHz - 3 GHz) is reduced to 25 dBμV / m (70% of the EN 55022 Class B limit value), and the conduction interference suppression ratio is increased to > 45 dB;

[0062] The isolation impedance between the power layer and the control layer > 10 GΩ (under a 100 V bias voltage), and the leakage current < 10 μA (test conditions of ISO 6469-3:2018);

[0063] (4). Mechanical reliability and cost control

[0064] The mechanical strengthening layer (a 2-mm-thick composite carbon fiber board) enables the substrate bending strength ≥ 600 MPa (a 150% increase compared to the same period), effectively suppressing the warping deformation of the multi-layer board (the deformation amount < 0.05 mm / m);

[0065] The anodic oxidation microchannel process replaces the traditional laser etching, saving 35% in manufacturing cost and achieving a sealing reliability with a withstand voltage level > 5 MPa (tested according to the ASTM D638 standard);

[0066] (5). Expansion of process compatibility

[0067] The innovative lamination process allows the control circuit layer to use standard FR-4 materials and the power layer to select a high-Tg copper-clad ceramic substrate (temperature resistance > 200 °C), solving the problem of delamination at the interface of heterogeneous materials (the interfacial bonding force > 12 N / mm);

[0068] The modular assembly technology improves the overall yield of the substrate to 98.5% (the yield of the traditional hybrid integration solution ≤ 85%).

[0069] Compared with existing patents (such as the six-layer PCB solution of CN114079041A), the seven-layer stacked architecture of the present invention additionally adds an electromagnetic shielding layer and a mechanical strengthening layer, achieving a synergistic optimization of heat dissipation / EMI shielding / mechanical strength under the same volume;

[0070] The Al2O3 anodic oxidation microchannel process effectively solves the problem of electrochemical corrosion of traditional metal flow channels (can withstand a cooling medium with pH = 2 - 12), and breaks through to improve the life of the heat dissipation system (MTBF > 100,000 hours, the estimated value of GJB / Z 299C).

[0071] In this embodiment, the pore size gradient of the microchannel array satisfies the functional relationship of d = 50×(1 - e^(-0.2x)) μm, where x is the axial distance from the coolant inlet; a temperature-adaptive flow deflector based on shape memory alloy is integrated in the channel, and when the temperature exceeds 85 °C, a curvature change of 15° - 25° is generated to form a spiral turbulent heat transfer enhancement structure;

[0072] The specific implementation method includes the following process characteristics and parameters:

[0073] (1). Microchannel manufacturing process: A stepped pore size microchannel is prepared on a 6061 aluminum alloy substrate by numerically controlled electrochemical machining, and the substrate size is 200×150×8 mm 3 ;

[0074] In the pore size function d = 50×(1 - e^(-0.2x)) μm, the value range of the parameter x is 0 ≤ x ≤ 320 mm, corresponding to the initial pore size d0 = 7.5 μm at the inlet and the maximum pore size d_max = 47.8 μm at the end;

[0075] The channel array is arranged in a fishbone-like fractal pattern. The main channel and 48 branch channels form a flow channel network with a total length of 6.5 m, and the spacing of the branch channels decreases at a ratio of 2^0.5;

[0076] (2). Flow deflector integration scheme: The shape memory alloy Ni47Ti44Nb9 (at%) is selected, with a phase change temperature window of 82 - 88 °C, and a two-way memory effect is obtained through cold rolling + aging treatment at 500 °C / 2 h;

[0077] The flow deflector has a thickness of 80 μm and is arranged along the axial direction of the main channel at a spacing of λ = 12 mm. The initial configuration is a planar flow deflector, which curls into a spiral sheet with a pitch of 8 mm and a helix angle of 35° after being triggered by temperature;

[0078] The curling radius of curvature has a linear relationship with temperature: R(T) = 15 / (T - 80) mm (80 °C < T ≤ 95 °C), realizing self-regulation of flow velocity;

[0079] (3). Combined heat transfer enhancement: Coupled with the first insulating dielectric layer, through ANSYS Fluent simulation and optimization, it is obtained that when the coolant flow velocity is 0.8 m / s, the trigger of the flow deflector can increase the convective heat transfer coefficient by 82% and only increase the pressure drop by 17%;

[0080] Combined with the hydrophobicity of the Al2O3 ceramic layer (contact angle 112°), the nucleate boiling threshold is reduced by 35 °C under turbulent conditions, and the temperature difference on the substrate surface is controlled within ΔT ≤ 2.5 °C / cm 2 ;

[0081] The structural integrity verification shows that the maximum deformation of the base layer is 3.2 μm under a pressure of 10 MPa, meeting the co - bearing requirements of the mechanical strengthening layer.

[0082] In this embodiment, the gradually expanding structure of the microchannel effectively reduces the flow resistance, while the temperature - activated flow - guiding sheet induces secondary flow under high - temperature conditions. Through the combined action of longitudinal vortex generation, boundary - layer destruction, and gas - liquid two - phase flow, the junction temperature of the IGBT module is reduced by 21.4 °C, and the MTBF is increased to 127,000 hours.

[0083] (Cross - layer synergy effect) The enhanced heat - transfer structure of the heat - dissipation base layer and the upper - layer components form a cooperative working loop: The heat generated by the power - device layer is conducted downward through the aluminum nitride substrate (thermal conductivity 180 W / m·K) of the first insulating dielectric layer. After phase - change cooling through the microchannel with gradient apertures, the residual heat is evenly dissipated through the copper - tungsten alloy layer (CTE 6.8×10 - 6 / °C) of the mechanical strengthening layer, and the overall thermal resistance is reduced to 0.23 °C / W.

[0084] In this embodiment, the electromagnetic shielding layer adopts a composite structure of ferrite - graphene composite film and periodic electromagnetic band - gap structure, where the lattice constant of the ferrite - graphene composite film is with a thickness of 200 ± 5 μm; the electromagnetic band - gap structure consists of 16×16 square metal patches, and the size of each patch satisfies λ / 8 ≤ a ≤ λ / 6, where λ is the wavelength corresponding to the inverter switching frequency;

[0085] The specific implementation method is as follows:

[0086] (1) Preparation of the composite film: The ferrite layer and the graphene layer (thickness ratio 6:1) are alternately deposited on the aluminum nitride substrate by magnetron sputtering to form a periodic laminated structure. The deposition temperature is controlled at 380 °C ± 3 °C, and the working pressure is 0.35 Pa. The lattice constant is monitored in real - time by an X - ray diffractometer to the tolerance range, and finally a composite film with a thickness of 200 μm ± 5 μm is obtained;

[0087] (2) Construction of the electromagnetic band - gap array: A 16×16 array of copper square patches (a = 4.8 mm corresponding to the wavelength of the 100 kHz switching frequency) is fabricated on the surface of the composite film by photolithography, and the spacing δ between adjacent patches is 0.15a. The patch matrix forms a three - dimensional Faraday cage structure with the grounding plane of the power - device layer through wire - bonding;

[0088] (3) Integration and optimization measures: The shielding component is bonded to the surface of the power - device layer by vacuum hot - pressing technology. The loading pressure is set at 12 MPa, the pressure - holding time is 15 min, and the interface gap ≤ 2 μm;

[0089] An annular isolation groove (groove width: 0.3 mm) is arranged on the periphery of the electromagnetic bandgap array, and the groove is filled with a magnetic composite wave-absorbing material (the proportion of carbonyl iron powder is 65 wt%).

[0090] Based on the actual measurement by a vector network analyzer, a shielding effectiveness of 76 dB is achieved in the frequency band of 50 kHz - 1 MHz, and the insertion loss ≤ 0.15 dB.

[0091] (4) Co - working verification: Conduct a joint impedance matching test with the coplanar waveguide of the first insulating dielectric layer. The measured S11 parameter < - 30 dB, the electromagnetic radiation intensity under the transient switching condition is reduced to 32 mV / m (compared with 143 mV / m before implementation), and the temperature rise of the device is reduced by 18.7 K in combination with the microchannel heat dissipation structure.

[0092] In this embodiment, the mechanical strengthening layer comprises a carbon fiber - reinforced liquid crystal polymer - based composite material. The fiber arrangement direction forms a 45° angle with the diagonal direction of the circuit board, and a distributed fiber optic sensor array is embedded in the layer to monitor the deformation of the circuit board in real - time and feedback it to the MPPT control module of the inverter.

[0093] The specific implementation method is as follows:

[0094] (1) Composite material preparation: Use the vacuum - assisted resin transfer molding process to form the carbon fiber / liquid crystal polymer matrix:

[0095] The volume content of carbon fiber (T800 grade) is 30 ± 2%, and it is cross - laminated in the 0° / 45° / 90° directions.

[0096] The melt index of the liquid crystal polymer matrix (LCP - K3400) is 26 g / 10 min, and the injection molding temperature is 325℃ ± 5℃.

[0097] Apply a molding pressure of 8 MPa, and the pressure - holding time is 45 min. The formed thickness is 0.8 mm ± 0.05 mm. The measured tensile strength of the material is 1680 MPa, and the flexural modulus is 125 GPa.

[0098] (2) Fiber optic sensor arrangement: Use the femtosecond laser writing technology to prepare a distributed sensing array on the optical fiber:

[0099] The fiber optic sensors (FBG type) are arranged in a 7×7 grid array, and the point distance is 3 mm.

[0100] Embed them into the composite material preform under the condition of a pre - tightening force of 0.25 N.

[0101] The connection end is encapsulated with an ultraviolet - curable adhesive (LOCTITE 3491) and connected to the demodulation board through high - frequency micro - impedance welding. The measurement resolution reaches ±0.5 με (in the range of 0℃ - 85℃).

[0102] (III) Integrated optimization measures: Add a titanium alloy frame (TC4) with a thickness of 0.2 mm in the edge area, and chamfer with R0.1 mm to prevent delamination;

[0103] Sensor signal processing conditions:

[0104] The cut-off frequency of the low-pass filter is 100 Hz;

[0105] Three-dimensional deformation data fusion algorithm: Use Kalman filter to compensate for temperature drift;

[0106] Set the closed-loop control of deformation-power: Trigger the MPPT reconstruction strategy when the monitored bending strain > 50 μm / m;

[0107] (IV) Comprehensive performance verification: Compared with the traditional FR-4 substrate, the bending stiffness is increased by 7.2 times (refer to the IEC 60249 standard);

[0108] The real-time deformation monitoring error < 2.7 μm, and the sampling frequency is 5 kHz;

[0109] The MPPT tracking efficiency is increased to 99.1% (97.6% for the control group), and the dynamic response speed is increased by 0.3 ms;

[0110] When working with the heat dissipation base layer, the measured vibration amplitude is reduced by 68% (0.3 g → 0.096 g), and the temperature rise ΔT ≤ 5.7 K.

[0111] Please refer to Figure 2 , in this embodiment, a manufacturing process includes: implementing interlayer bonding using the low-temperature co-fired ceramic process under a nitrogen protection environment, controlling the bonding pressure in the range of 8 - 12 MPa, and forming a silver-copper alloy transition layer with a thickness of 2 - 5 μm at the bonding interface. This transition layer is subjected to laser remelting treatment to form a periodic micro-protrusion structure, and the surface roughness Ra value is controlled in the range of 0.8 - 1.2 μm;

[0112] The specific implementation method is as follows:

[0113] (I) Interlayer bonding process: Implement the integration of a seven-layer structure using an improved low-temperature co-fired ceramic (LTCC) process: Perform lamination bonding in a nitrogen-hydrogen mixed atmosphere (N2 / H2 = 95 / 5), and control the temperature in three stages:

[0114] Pre-pressing stage: Maintain at 280 °C for 30 min, and apply an initial pressure of 5 MPa;

[0115] Main bonding stage: Maintain the temperature at 380 °C ± 3 °C for 45 min, and gradually increase the pressure to 10.5 MPa;

[0116] Plastic forming stage: Tempering treatment at 330°C, pressure released to 3 MPa to eliminate internal stress. (2) The power device layer is embedded using vacuum-assisted alignment technology with a positioning accuracy of ±5 μm.

[0117] (II). Transition layer treatment: (1) The silver-copper alloy (Ag68 / Cu32) transition layer is deposited by magnetron sputtering:

[0118] Thickness deviation control: 3 ± 0.2 μm (verified by CMM measurement).

[0119] Laser remelting parameters: Nd:YAG laser (wavelength 1064 nm), energy density 15 J / cm 2 , pulse width 25 ns to form a micro-protrusion structure with a height-width ratio of 1:3, and the protrusion period is 150 μm ± 10 μm.

[0120] (III). Integrated optimization measures: Key interface treatment:

[0121] Pre-fabricate nano-anchors (200 nm ZnO columns) on the surface of the second insulating dielectric layer;

[0122] The wetting angle of the transition layer is controlled at 28° ± 2° (monitored in-situ by a contact angle analyzer). Dynamic piezoelectric monitoring: The integrated piezoelectric ceramic sensor (PZT-5H) is used to collect the bonding stress distribution in real-time;

[0123] Thermal deformation compensation algorithm: Based on the finite element model, the heating gradient is predicted and adjusted, and the maximum strain compensation rate is 73%;

[0124] (IV). Verification of synergistic effect: The measured interfacial bonding strength reaches 58 MPa (refer to JIS C6481 standard), the porosity < 0.3% (detected by X-μCT), the thermal resistance from the power device layer to the heat dissipation base is reduced to 0.12 K / W (transient thermal test method), no delamination occurs between layers after 2000 times of -40°C / +125°C thermal shock (complies with MIL-STD-883G standard). After bonding with the electromagnetic shielding layer, the conducted interference attenuation in the full frequency band is 61 dBμV (tested by CISPR25). The laser micro-protrusion structure reduces the interfacial contact resistance to 0.8 mΩ·cm 2 (Four-probe method), and at the same time promotes the formation of local heat dissipation channels (IR thermal imaging shows that the temperature difference of hot spots is reduced by 5.7 K).

[0125] In this embodiment, a thermal expansion compensation structure is provided between the microchannel array and the power device layer. This structure is made of a material with a negative thermal expansion coefficient ZrW2O8, and its volume compensation amount ΔV satisfies the formula: ΔV = α × ΔT × V0, where α = -9×10 -6 / K, and V0 is the volume of the thermal influence area of the power device;

[0126] The specific implementation method is as follows:

[0127] (1). Preparation of compensation material: ZrW2O8 powder is prepared by hydrothermal synthesis method:

[0128] The molar ratio of precursors ZrOCl2·8H2O:WO3 = 1:2.1;

[0129] The reaction temperature is 220°C ± 1°C and is maintained for 48 hours;

[0130] The hot pressing sintering parameters of a single negative thermal expansion phase (α-ZrW2O8, PDF#29-0947) are obtained through XRD verification:

[0131] The sintering temperature is 800°C (under argon protection);

[0132] The axial pressure is 25 MPa, and the density is controlled at 92 ± 1% of the theoretical value;

[0133] Finally, the measured coefficient of thermal expansion α = -9.2×10 -6 / K (in the range of 25 - 150°C);

[0134] (2). Compensation structure design: Three-dimensional porous grid topology:

[0135] The unit structure is a truncated octahedron (pore size gradient: 0.3 mm at the top → 0.8 mm at the bottom);

[0136] The porosity is 62 ± 2% (calculated based on the heat generation Q = 35 W / cm of the power device 3 );

[0137] Interface enhancement treatment:

[0138] Pre-fabricate a micro-column array on the joint surface with the micro-channel ( spacing 120 μm);

[0139] Spray a 50-nm molybdenum transition layer on the surface (to enhance the bonding with Al2O3 ceramic);

[0140] (3). Thermal expansion matching control: Implement a volume compensation algorithm:

[0141] Collect the geometric parameters of the thermal influence area of the power device (V0 = 7.8×10 -6 m 3 );

[0142] Based on the formula ΔV = α×ΔT×V0 (ΔT takes the maximum transient temperature difference of 85 K), the calculated compensation volume ΔV = 5.967×10 -8 m 3 ;

[0143] Optimize the grid parameters through finite element analysis:

[0144] The effective volume ratio of the compensation structure is 23.6% (meeting 93% of the theoretical compensation requirement);

[0145] A dynamic compensation margin of 6.2 μm is reserved;

[0146] (4). Integration verification:

[0147] Thermomechanical performance test:

[0148] After 500 thermal cycles (-40 → +125 °C), there is no interface peeling (detected by ultrasonic C-scan);

[0149] After matching the heat dissipation layer, the overall thermal resistance is reduced to 0.08 K / W (a 34% reduction);

[0150] Actual measurement of stress compensation:

[0151] Under the condition of a high temperature of 125 °C, the maximum stress value is reduced from 147 MPa to 32 MPa (DIC full-field strain test);

[0152] The fatigue life of the solder joints of the power device is increased to 3.5×10 6 cycles (JEDEC JESD22-A104 standard);

[0153] Dynamic compensation error:

[0154] The temperature difference between the SiC MOSFET and the IGBT module is controlled within ΔT < 1.5 K (infrared thermal imaging);

[0155] The phase distortion of the coplanar waveguide signal is < 0.75° (tested at a switching frequency of 40 MHz).

[0156] In this embodiment, the control circuit layer adopts differential serpentine routing technology, and the routing pitch satisfies s = 3h + Δs, where h is the thickness of the adjacent layer dielectric, and Δs is an adjustable parameter of 0.1 - 0.3 mm; a ground shielding via array is arranged on both sides of the key signal lines, and the via pitch is less than 1 / 20 of the wavelength corresponding to the signal rising edge;

[0157] The specific implementation method is as follows:

[0158] (1). Construction of differential pair routing: Serpentine routing topology design:

[0159] The bus width w = 0.2 mm ± 0.02 mm, and the bending angle adopts a 75° arc transition (curvature radius R = 3w);

[0160] The routing pitch parameter calculation formula is s = 3h + Δs, where: h = the thickness of the first / second insulating dielectric layer 0.18 mm (measured value);

[0161] The maximum trace length is controlled by the propagation delay limit: L_max = 300 × t_r / v_p (t_r = 2 ns rising edge, v_p = 1.6 × 10 8 m / s);

[0162] (2) Shielded via array configuration: PCB implementation process:

[0163] Formed by laser drilling Through-hole array (hole wall thickness 18 μm, electroless copper plating);

[0164] The row spacing meets λ_min / 20 = 0.85 mm (corresponding to the highest harmonic frequency f = 35 GHz);

[0165] The misalignment rate between stacked vias < 5% (automatically detected by AXI).

[0166] (3) Integration optimization measures: Dynamic tuning strategy:

[0167] Based on the prediction of the current waveforms of adjacent power layers, automatically adjust the Δs parameter (PID control accuracy ±0.03 mm);

[0168] Embed the transmission line impedance model in the MPPT algorithm to achieve self-consistency of Z parameters (target impedance deviation < 5%);

[0169] Production process error compensation:

[0170] Use femtosecond laser trimming technology to correct the copper thickness deviation (accuracy ±5 μm);

[0171] Add a π-type RC balance network to the signal path (R = 22 Ω ±1%, C = 2.2 pF ±5%);

[0172] Thermal-electric coupling control:

[0173] The via array also serves as a local heat dissipation path, and the thermal conductivity is increased to 380 W / (m·K);

[0174] Gradient design of copper foil thickness (power line 70 μm → signal line 35 μm);

[0175] Preferably, the distributed fiber optic sensor array and the power device layer form a closed-loop control system. When the detected local strain exceeds 300 με, the current sharing compensation mechanism of adjacent power units is automatically triggered, and power soft switching under fault conditions is achieved through dynamic gate voltage regulation.

[0176] (4) Performance verification: Signal integrity test:

[0177] Insertion loss < 0.15 dB / cm @ 3 GHz (according to IPC-2141A standard);

[0178] Differential crosstalk suppression ratio > 54 dB (adjacent trace spacing 0.3 mm);

[0179] Electromagnetic compatibility performance:

[0180] Radiated emissions reduced by 19 dBμV / m (CISPR32 Class B standard);

[0181] System co-verification:

[0182] Coplanar waveguide impedance matching degree with Example 1 > 97% (measured by time domain reflectometer);

[0183] When the combined heat dissipation layer is working, the measured signal delay temperature drift coefficient is reduced to 2.1 ps / K;

[0184] Under the conditions of 85°C / 85% RH, after 1000 hours of aging test, the resistance change rate < 1.2%.

[0185] In this embodiment, the working frequency band of the electromagnetic bandgap structure covers the range of 150 kHz - 30 MHz. At 1 MHz, the insertion loss is greater than 45 dB. Its equivalent circuit model includes parallel L-C resonant units, where the inductance value L = 15 nH ± 5%, and the capacitance value C = 22 pF ± 5%;

[0186] The specific embodiments are as follows:

[0187] (1). EBG cell design:

[0188] Geometric parameters of the mushroom-shaped electromagnetic bandgap cell:

[0189] Metal patch size: 3.2 mm × 3.2 mm (matched with the switching frequency of the power device 1 / T_sw = 20 MHz);

[0190] Diameter of the grounding via: Aspect ratio 10:1 (layer thickness 1.5 mm);

[0191] EBG period: 4.8 mm (corresponding to the cut-off frequency of 30 MHz);

[0192] Multi-order L-C network design:

[0193] Parallel resonant unit:

[0194] Inductance L = 14.7 nH (using the equivalent inductance of the interconnecting wire, length 18 mm × line width 0.12 mm);

[0195] Capacitance C = 23.5 pF (realized by the interdigitated capacitor embedded between dielectric layers, overlapping area 2.8 mm 2 )

[0196] Tolerance Compensation: The spacing between the capacitor plates is finely adjusted by laser trimming (adjustment accuracy: ±0.3μm);

[0197] (2). Material and Process Realization:

[0198] Composite Dielectric Material:

[0199] Ferrite Filler: Add 20vol% NiZn ferrite (particle size D50 = 5μm);

[0200] Matrix Material: Composite of polyphenylene sulfide (PPS) and ceramic powder (ε_r = 8.2 ± 0.3, tanδ < 0.002 @ 1MHz);

[0201] Laminated Casting Process: Single layer thickness 0.1mm ± 3μm (dielectric uniformity < 2% fluctuation);

[0202] Embedded Manufacturing Process:

[0203] Through - hole Metallization: Electroless nickel - palladium - gold plating (Ni 3μm / Pd 0.1μm / Au 0.05μm)

[0204] High - precision Alignment: Ultraviolet laser direct writing exposure (alignment error < 5μm);

[0205] High - temperature Sintering: Keep warm for 90 minutes at 380℃ in a nitrogen environment (glass transition temperature T_g = 275℃);

[0206] (3). Electromagnetic Synergy Optimization:

[0207] Spectrum Dynamic Adaptation:

[0208] Synchronously Tuned with the Power Device Layer: Use voltage - controlled varactor diodes (capacitance dynamic range 15 - 35pF);

[0209] Phase Compensation Algorithm: Reverse correction model based on the electromagnetic coupling coefficient K = 0.12;

[0210] Multi - physical Field Matching:

[0211] Thermal Deformation Compensation Gap: Reserve an annular expansion groove (width 20μm, spacing 2.4mm);

[0212] Coupled Design with Heat Dissipation Micro - channels: The through - hole array also serves as auxiliary heat dissipation teeth (thermal conductivity enhancement rate 28%);

[0213] (4). Performance Verification:

[0214] In - band Suppression Characteristics:

[0215] Insertion Loss: 45.8dB @ 1MHz (tested according to CISPR25 standard);

[0216] Quality factor Q: 82 (3dB bandwidth 15.6kHz);

[0217] High - frequency roll - off characteristic: attenuation > 12dB / oct at 30MHz;

[0218] System - level verification:

[0219] When jointly implementing the control circuit layer in Example 3.1, the common - mode noise is reduced by 54dBμV (EN55022 Class B);

[0220] The EMI margin reaches 13.6dB under full - load conditions (compared with the limit value of IEC 61000 - 4 - 6 standard);

[0221] After the accelerated aging test (1000 hours at 85°C / humidity 85%), the parameter drift < 1.5%.

[0222] Please refer to Figure 3 , in this embodiment, a photovoltaic inverter system is configured with a thermal - electrical co - management system based on model - predictive control. This system real - time collects three parameters: the temperature difference ΔT between the inlet and outlet of the micro - channel, the junction temperature Tj of the power device, and the electromagnetic radiation intensity E. Through the minimization calculation of the weighted objective function J = αΔT 2 +β(Tj - 85) 2 +γE 2 , the switching frequency and the coolant flow rate are dynamically adjusted;

[0223] The specific implementation is as follows:

[0224] Deployment of intelligent sensing elements:

[0225] Detection of thermal parameters:

[0226] A thin - film PT100 array is arranged at the inlet / outlet of the micro - channel (3×3 temperature - measuring grid, accuracy ±0.1K);

[0227] A SiC substrate temperature chip is buried in the base region of the IGBT (Tj measurement period 10μs, junction - to - case thermal resistance model Rth(j - c)=0.18K / W);

[0228] Electromagnetic sensing:

[0229] A magnetic - field sensing coil is integrated on the surface of the EBG structure (3 - axis anisotropic magnetoresistive sensor, dynamic range 10nThp);

[0230] The radiation monitoring uses a λ / 4 slotted antenna array (operating frequency band 0.5REFERENCE_CLIP_END.

[0231] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0232] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. An integration and optimization method of a multi-layer circuit board in a photovoltaic inverter, characterized in that Comprising: At least seven layers of functional stacked structures, which are, from top to bottom in sequence: an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation base layer, and a mechanical strengthening layer; Wherein the power device layer integrates an IGBT module and a SiC MOSFET module by using a three-dimensional embedded packaging technology, and its gate drive circuit is embedded in the first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation base layer is provided with a microchannel array with a gradient aperture, and the inner walls of each microchannel are anodized to form an Al2O3 ceramic layer with a thickness of 20 - 50 μm.

2. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 1, characterized in that The aperture gradient of the microchannel array satisfies the function relationship of d = 50×(1 - e^(-0.2x)) μm, where x is the axial distance from the coolant inlet; a temperature self-adaptive flow deflector based on shape memory alloy is integrated in the channel, and when the temperature exceeds 85 °C, a curvature change of 15° - 25° is generated to form a spiral turbulent flow enhanced heat transfer structure.

3. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 1, characterized in that The electromagnetic shielding layer adopts a composite structure of a ferrite-graphene composite film and a periodic electromagnetic bandgap structure, where the lattice constant of the ferrite-graphene composite film is and the thickness is 200 ± 5 μm; the electromagnetic bandgap structure is composed of 16 × 16 square metal patches, and the size of each patch satisfies λ / 8 ≤ a ≤ λ / 6, where λ is the wavelength corresponding to the inverter switching frequency.

4. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 1, wherein The mechanical strengthening layer comprises a carbon fiber reinforced liquid crystal polymer matrix composite material, the fiber arrangement direction of which forms an angle of 45° with the diagonal direction of the circuit board, and a distributed optical fiber sensor array is embedded in the layer to monitor the deformation of the circuit board in real time and feedback it to the MPPT control module of the inverter.

5. A manufacturing process, applied to the integration and optimization method of the multilayer circuit board according to any one of claims 1 to 4 in a photovoltaic inverter, characterized in that, Comprising: The interlayer bonding is carried out by using a low-temperature co-fired ceramic process under a nitrogen protection environment, the bonding pressure is controlled in the range of 8 - 12 MPa, and a silver-copper alloy transition layer with a thickness of 2 - 5 μm is formed at the bonding interface. The transition layer is subjected to laser remelting treatment to form a periodic micro-protrusion structure, and the surface roughness Ra value is controlled in the range of 0.8 - 1.2 μm.

6. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 2, characterized in that, A thermal expansion compensation structure is provided between the microchannel array and the power device layer. This structure is made of a material with a negative thermal expansion coefficient, ZrW2O8, and its volume compensation amount ΔV satisfies the formula: ΔV = α × ΔT × V0, where α = -9×10 -6 / K, and V0 is the volume of the heat-affected area of the power device.

7. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 1, wherein The control circuit layer adopts a differential serpentine wiring technology, and its wiring spacing satisfies s = 3h + Δs, where h is the thickness of the dielectric of the adjacent layer, and Δs is an adjustable parameter of 0.1 - 0.3 mm; a ground shielding via array is arranged on both sides of the key signal line, and the via spacing is less than 1 / 20 of the wavelength corresponding to the signal rising edge.

8. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 4, characterized in that, The distributed optical fiber sensor array and the power device layer form a closed-loop control system. When it is detected that the local deformation amount exceeds 300 με, the current sharing compensation mechanism of the adjacent power unit is automatically triggered, and the power soft switching under the fault state is realized through the dynamic gate voltage regulation.

9. The integration and optimization method of the multi-layer circuit board in the photovoltaic inverter according to claim 3, characterized in that The working frequency band of the electromagnetic bandgap structure covers the range of 150 kHz - 30 MHz, the insertion loss is greater than 45 dB at 1 MHz, and its equivalent circuit model includes a parallel L-C resonant unit, where the inductance value L = 15 nH ± 5%, and the capacitance value C = 22 pF ± 5%.

10. A photovoltaic inverter system, characterized in that, Integrated with a multi-layer circuit board as described in any one of claims 1-9, and configured with a thermal-electric co-management system based on model predictive control. This system real-time collects three parameters: the temperature difference ΔT between the inlet and outlet of the microchannel, the junction temperature Tj of the power device, and the electromagnetic radiation intensity E, and through the minimization calculation of the weighted objective function J = αΔT 2 +β(Tj - 85) 2 +γE 2 dynamically adjusts the switching frequency and the coolant flow rate.

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