Parallel half-bridge power module with double-end power supply and double-face heat dissipation packaging

Abstract

The invention relates to the technical field of packaging, in particular to a double-end power supply and double-face heat dissipation packaged parallel half-bridge power module, which is characterized in that a SiC MOSFET chip and a diode chip are arranged between an upper DBC board and a lower DBC board, the bottom ends of the SiC MOSFET chip and the diode chip are connected with the lower DBC board through solder layers, and the lower DBC board is connected with the lower DBC board through solder layers. The top end of the SiC MOSFET chip and the top end of the diode chip are respectively connected with a conducting strip through a solder layer, and the conducting strip is connected with the upper DBC board through the solder layer. According to the invention, the two DBC boards and the buffer conducting strip realize electrical connection of all parts in the module, so that the whole packaging structure of the module is simplified; two-sided heat dissipation of the SiC MOSFET and the diode chip is realized through the copper-clad layers arranged on the surfaces of the two DBC boards, the problem of heat flow concentration of the SiC chip under the high-frequency working condition is effectively solved, and the problem of'heat-electric stress' coupling of the module under the high-frequency working condition is solved through system coupling current balance and two-sided heat dissipation capability, so that the module has multi-unit self-current-sharing, and the service life of the module is prolonged. The high-frequency switch stress is inhibited and balanced; and the power density is improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging. Background Technology

[0002] SiC MOSFETs, with their high switching frequency, high voltage withstand capability, and low loss characteristics, have become ideal devices for high-frequency power electronics applications. However, due to limitations in semiconductor technology, cost, and thermal and mechanical factors, the current-carrying capacity of a single chip is limited. To improve the current rating of SiC power modules, multiple chips need to be connected in parallel. However, traditional multi-module parallel connection methods not only introduce large parasitic inductance but also significantly impact the switching speed and dynamic balancing of the devices. Therefore, developing multi-chip parallel packaged power modules is necessary. However, its high-frequency operation (tens of kHz to MHz) presents three major challenges: deeply coupled parasitic parameters, electromagnetic interference (EMI), and heat dissipation. The stray inductance of the power circuit, under the influence of high dv / dt and high di / dt, excites strong EMI and voltage spikes, while increasing switching losses. The high-frequency cumulative loss density, combined with the chip heat flow concentration effect, greatly increases the risk of local overheating. Reducing the switching speed to alleviate the above problems exacerbates the heat dissipation pressure, forming a mutual constraint. Furthermore, the parasitic parameter differences in the parallel circuits lead to uneven current distribution, causing local thermal runaway and dynamic voltage equalization failure. Some devices are subjected to overcurrent and high voltage spikes and reverse recovery impacts, which significantly increase losses and worsen output harmonics. Ultimately, the system power density and reliability are constrained by the weakest link. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging to solve the above problems.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging, including an upper DBC board and a lower DBC board. A SiC MOSFET chip and a diode chip are disposed between the upper DBC board and the lower DBC board. The bottom ends of the SiC MOSFET chip and the diode chip are respectively connected to the lower DBC board through solder layers, and the top ends of the SiC MOSFET chip and the diode chip are respectively connected to a conductive sheet through solder layers. The conductive sheet is connected to the upper DBC board through solder layers.

[0005] As a further embodiment of the present invention, both the upper DBC board and the lower DBC board are copper-clad ceramic boards. The upper DBC board includes an upper copper layer, an intermediate insulating layer, and a lower copper layer. The lower DBC board includes an upper copper layer, an intermediate insulating layer, and a lower copper layer.

[0006] As a further embodiment of the present invention, the middle insulating layer of the upper DBC board and the middle insulating layer of the lower DBC board are both aluminum nitride ceramic or alumina ceramic.

[0007] As a further embodiment of the present invention, the copper cladding layer of the upper DBC board is provided with a first region and a second region, and the copper cladding layer of the lower DBC board is provided with a third region, a fourth region and a fifth region.

[0008] As a further embodiment of the present invention, the third region and the fourth region are of equal size and are symmetrically distributed along the center of the lower DBC plate.

[0009] As a further embodiment of the present invention, the first region is connected to an AC power terminal, the second region is connected to a gate drive terminal; the left and right ends of the third region are symmetrically connected to a first DC negative power terminal and a second DC negative power terminal, the left and right ends of the fourth region are symmetrically connected to a first DC positive power terminal and a second DC positive power terminal, and the fifth region is connected to a gate drive terminal.

[0010] As a further embodiment of the present invention, the first DC positive power terminal, the second DC positive power terminal, the first DC negative power terminal, the second DC negative power terminal, the AC power terminal, and the gate drive terminal are all made of copper; the first DC positive power terminal and the second DC positive power terminal, and the first DC negative power terminal and the second DC negative power terminal are symmetrically distributed on both sides of the lower DBC board.

[0011] As a further embodiment of the present invention, the conductive sheet includes a first conductive sheet, a second conductive sheet, a third conductive sheet, and a fourth conductive sheet; the first conductive sheet, the second conductive sheet, and the third conductive sheet are all molybdenum sheets, and the fourth conductive sheet is a copper sheet.

[0012] As a further embodiment of the present invention, a first conductive sheet and a second conductive sheet are respectively connected to one side of the first region via solder layers. The first conductive sheet is connected to the source of the SiC MOSFET chip via a first solder layer, and the second conductive sheet is connected to the anode of the diode chip via a second solder layer. On the other side of the first region, a first conductive sheet and a second conductive sheet are respectively connected to the first conductive sheet via solder layers. The first conductive sheet is connected to the drain of the SiC MOSFET chip via a first solder layer, and the second conductive sheet is connected to the cathode of the diode chip via a second solder layer. The second region is located directly in front of the SiC MOSFET chip. The gate of the SiC MOSFET chip is connected to the third conductive sheet via a fourth conductive sheet, and the third conductive sheet is connected to the gate drive terminal via a fifth region.

[0013] As a further aspect of the present invention, there are 6 groups of SiC MOSFET chips and diode cores in the first region, which are arranged alternately and at equal intervals.

[0014] As a further embodiment of the present invention, the third region is connected to a first conductive sheet and a second conductive sheet via solder layers. The first conductive sheet is connected to the drain of the SiC MOSFET chip via a first solder layer, and the second conductive sheet is connected to the cathode of the diode chip via a second solder layer. The fourth region is connected to a first conductive sheet and a second conductive sheet via solder layers. The first conductive sheet is connected to the source of the SiC MOSFET chip via a first solder layer, and the second conductive sheet is connected to the anode of the diode chip via a second solder layer. The second region is located directly in front of the SiC MOSFET chip. The gate of the SiC MOSFET chip is connected to the third conductive sheet via the fourth conductive sheet, and the third conductive sheet is connected to the gate drive terminal via the fifth region.

[0015] As a further embodiment of the present invention, there are 6 groups of SiC MOSFET chips and diode cores on the third and fourth regions, which are arranged alternately and at equal intervals.

[0016] Because the present invention adopts the above technical solution, the advantages and positive effects of the present invention are as follows: 1. By using dual-end power supply on both sides, the distance between the conductive loops of each parallel bridge arm is equal, which balances the parasitic inductance of each upper and lower bridge arm loop and achieves dynamic current balance. Combined with the copper-clad layer design of two DBC boards, the low-inductance interconnection technology of electrical connection of each part of the module significantly suppresses the parasitic inductance effect of the power loop, and simultaneously eliminates the local overcurrent, thermal runaway and dynamic voltage stress imbalance caused by parameter mismatch in traditional modules, thereby improving electrical symmetry and EMI performance.

[0017] 2. By using two DBC boards and a buffer conductive sheet to realize the electrical connection of each part inside the module, the overall packaging structure of the module is simplified; at the same time, the copper-clad layer on the surface of the two DBC boards realizes double-sided heat dissipation of SiC MOSFET and diode chips, effectively solving the problem of heat flow concentration of SiC chips under high-frequency operating conditions.

[0018] 3. This design solves the "thermal-electric stress" coupling problem of SiC MOSFET three-level power modules under high-frequency operation by balancing the system coupling current and the dual-sided heat dissipation capability, giving the module the advantages of multi-unit self-current sharing, high-frequency switching stress suppression and balancing, and improved power density. Attached Figure Description

[0019] Figure 1 This is an equivalent circuit topology diagram of a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging according to the present invention.

[0020] Figure 2 This is an exploded view of a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging according to the present invention.

[0021] Figure 3 This is a schematic diagram of the upper DBC board.

[0022] Figure 4 This is a front view of a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging according to the present invention.

[0023] Figure 5 This is a comparison diagram of the parasitic inductance of each parallel power circuit in a parallel half-bridge power module with dual-end power supply and double-sided heat dissipation packaging according to the present invention.

[0024] Figure 6 This is a comparison diagram of the parasitic inductance of each parallel power circuit in the parallel half-bridge power module of the present invention, which removes the second DC positive power terminal and the second DC negative power terminal for single-end power supply and double-sided heat dissipation packaging.

[0025] Figure 7 This is a schematic diagram of the temperature distribution on the front side of a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging according to the present invention.

[0026] Figure 8 This is a schematic diagram of the temperature distribution on the reverse side of a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging according to the present invention.

[0027] In the diagram: 1 is the first DC positive power terminal, 2 is the first DC negative power terminal, 3 is the second DC positive power terminal, 4 is the second DC negative power terminal, 5 is the gate drive terminal, 6 is the third region copper layer, 7 is the fourth region copper layer, 8 is the fifth region copper layer, 9 is the first conductive sheet, 10 is the second conductive sheet, 11 is the third conductive sheet, 12 is the fourth conductive sheet, 13 is the SiC MOSFET chip, 14 is the diode chip, 15 is the solder layer, 151 is the first solder layer, 152 is the second solder layer, 16 is the AC power terminal, 17 is the first region copper layer, 18 is the second region copper layer, 19 is the upper DBC board, and 20 is the lower DBC board. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0029] like Figures 1-4As shown, the present invention discloses a parallel half-bridge power module with dual-end power supply and dual-sided heat dissipation packaging, characterized in that it includes an upper DBC board 19 and a lower DBC board 20. A SiC MOSFET chip 13 and a diode chip 14 are disposed between the upper DBC board 19 and the lower DBC board 20. The bottom ends of the SiC MOSFET chip 13 and the diode chip 14 are respectively connected to the lower DBC board 20 through a solder layer 15. The top ends of the SiC MOSFET chip 13 and the diode chip 14 are respectively connected to a conductive sheet through a solder layer 15. The conductive sheet is connected to the upper DBC board 19 through a solder layer 15.

[0030] Furthermore, in this invention, both the upper DBC board 19 and the lower DBC board 20 are copper-clad ceramic boards. The upper DBC board 19 includes an upper upper copper layer, an upper DBC board intermediate insulating layer, and an upper DBC board lower copper layer. The lower DBC board 20 includes a lower DBC board upper copper layer, a lower DBC board intermediate insulating layer, and a lower DBC board lower copper layer. The SiC MOSFET chip 13 and diode chip 14 are electrically connected through conductive sheets and the copper-clad layers of the DBC boards. The low-inductance interconnection technology achieved by using the copper-clad layers of two DBC boards significantly suppresses the parasitic inductance effect of the power circuit. Simultaneously, double-sided heat dissipation is achieved, effectively solving the problem of heat concentration in SiC chips under high-frequency operating conditions.

[0031] Furthermore, in this invention, the intermediate insulating layer of the upper DBC board and the intermediate insulating layer of the lower DBC board are both aluminum nitride ceramic or alumina ceramic.

[0032] Furthermore, the copper cladding layer of the upper DBC board 19 is provided with a first region 17 and a second region 18, and the copper cladding layer of the lower DBC board 20 is provided with a third region 6, a fourth region 7 and a fifth region 8.

[0033] Furthermore, the third region 6 and the fourth region 7 are of equal size and are symmetrically distributed along the center of the lower DBC plate 20.

[0034] Furthermore, in this invention, the first region 17 is connected to an AC power terminal 16, the second region 18 is connected to a gate drive terminal 5; the third region 6 is symmetrically connected to a first DC negative power terminal 2 and a second DC negative power terminal 4 at its left and right ends, the fourth region 7 is symmetrically connected to a first DC positive power terminal 1 and a second DC positive power terminal 3 at its left and right ends, and the fifth region 8 is connected to a gate drive terminal 5.

[0035] Furthermore, the first DC positive power terminal 1, the second DC positive power terminal 3, the first DC negative power terminal 2, the second DC negative power terminal 4, the AC power terminal 16, and the gate drive terminal 5 are all made of copper. The first DC positive power terminal 1 and the second DC positive power terminal 3, and the first DC negative power terminal 2 and the second DC negative power terminal 4 are symmetrically distributed on both sides of the lower DBC board 20. The symmetrical distribution of the first DC positive power terminal 1 and the second DC positive power terminal 3, and the first DC negative power terminal 2 and the second DC negative power terminal 4 on both sides, along with the alternating and equidistant distribution of SiC MOSFET chips and diode chips, ensures that the overall paths of the three parallel power circuits in the upper and lower bridge arms are the same, balancing the parasitic inductance of each branch, achieving dynamic current balance, eliminating local overcurrent and thermal runaway problems caused by parasitic parameter mismatch, and improving electrical symmetry and EMI performance.

[0036] Furthermore, the conductive sheet of the present invention includes a first conductive sheet 9, a second conductive sheet 10, a third conductive sheet 11, and a fourth conductive sheet 12; the first conductive sheet 9, the second conductive sheet 10, and the third conductive sheet 11 are all molybdenum sheets, and the fourth conductive sheet 12 is a copper sheet.

[0037] Furthermore, on one side of the first region 17, a first conductive sheet 9 and a second conductive sheet 10 are respectively connected by a solder layer 15. The first conductive sheet 9 is connected to the source of the SiC MOSFET chip 13 through a first solder layer 151, and the second conductive sheet 10 is connected to the anode of the diode chip 14 through a second solder layer 152. On the other side of the first region 17, a first conductive sheet 9 and a second conductive sheet 10 are respectively connected by a solder layer 15. The first conductive sheet 9 is connected to the drain of the SiC MOSFET chip 13 through a first solder layer 151, and the second conductive sheet 10 is connected to the cathode of the diode chip 14 through a second solder layer 152. The second region 18 is located directly in front of the SiC MOSFET chip 13. The gate of the SiC MOSFET chip 13 is connected to the third conductive sheet 11 through a fourth conductive sheet 12, and the third conductive sheet 11 is connected to the gate driving terminal 5 through a fifth region 8.

[0038] Furthermore, the present invention provides that there are 6 groups of SiC MOSFET chips 13 and diode chips 14 on the first region 17, which are arranged alternately and at equal intervals.

[0039] Furthermore, in this invention, the third region 6 is connected to a first conductive sheet 9 and a second conductive sheet 10 via a solder layer 15. The first conductive sheet 9 is connected to the drain of the SiC MOSFET chip 13 via a first solder layer 151, and the second conductive sheet 10 is connected to the cathode of the diode chip 14 via a second solder layer 152. The fourth region 7 is connected to the first conductive sheet 9 and the second conductive sheet 10 via a solder layer 15. The first conductive sheet 9 is connected to the source of the SiC MOSFET chip 13 via a first solder layer 151, and the second conductive sheet 10 is connected to the anode of the diode chip 14 via a second solder layer 152. The second region 18 is located directly in front of the SiC MOSFET chip 13. The gate of the SiC MOSFET chip 13 is connected to the third conductive sheet 11 via a fourth conductive sheet 12, and the third conductive sheet 11 is connected to the gate drive terminal 5 via a fifth region 8.

[0040] Furthermore, the SiC MOSFET chip 13 and diode chip 14 on the third region 6 and the fourth region 7 are in 6 groups, and are arranged alternately and at equal intervals.

[0041] according to Figure 5 and Figure 6 Compared to parallel modules with single-ended power supply, the dual-ended power supply design of this invention makes the parasitic inductance distribution of each branch more uniform.

[0042] according to Figure 7 and Figure 8 The heat source for the six chips is set to 50W. The heat dissipation boundary conditions are located on the upper and lower surfaces of the power module. The heat convection coefficient is set to 200W / (m2·℃). The highest temperature is 82.385℃. The higher temperatures are distributed on the upper and lower DBC boards and the left and right sides respectively.

[0043] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention. The scope of protection of the present invention is defined only by the appended claims.

Claims

1. A parallel half-bridge power module with dual-ended power supply and double-sided heat dissipation packaging, characterized in that: The system includes an upper DBC board (19) and a lower DBC board (20). A SiC MOSFET chip (13) and a diode chip (14) are disposed between the upper DBC board (19) and the lower DBC board (20). The bottom ends of the SiC MOSFET chip (13) and the diode chip (14) are connected to the lower DBC board (20) through solder layers (15), respectively. The top ends of the SiC MOSFET chip (13) and the diode chip (14) are connected to conductive sheets through solder layers (15), respectively. The conductive sheets are connected to the upper DBC board (19) through solder layers (15).

2. The parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: Both the upper DBC board (19) and the lower DBC board (20) are copper-clad ceramic boards. The upper DBC board (19) includes an upper copper layer, an upper DBC board middle insulating layer, and an upper DBC board lower copper layer. The lower DBC board (20) includes a lower DBC board upper copper layer, a lower DBC board middle insulating layer, and a lower DBC board lower copper layer. The upper DBC board middle insulating layer and the lower DBC board middle insulating layer are both aluminum nitride ceramic or alumina ceramic.

3. The parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: The upper DBC board (19) has a first region (17) and a second region (18) on its copper cladding layer, and the lower DBC board (20) has a third region (6), a fourth region (7) and a fifth region (8) on its copper cladding layer; the third region (6) and the fourth region (7) are of equal size and are symmetrically distributed along the center of the lower DBC board (20).

4. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging as described in claim 3, characterized in that: The first region (17) is connected to an AC power terminal (16), the second region (18) is connected to a gate drive terminal (5); the third region (6) is symmetrically connected to a first DC negative power terminal (2) and a second DC negative power terminal (4) at its left and right ends, the fourth region (7) is symmetrically connected to a first DC positive power terminal (1) and a second DC positive power terminal (3) at its left and right ends, and the fifth region (8) is connected to a gate drive terminal (5).

5. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: The first DC positive power terminal (1), the second DC positive power terminal (3), the first DC negative power terminal (2), the second DC negative power terminal (4), the AC power terminal (16), and the gate drive terminal (5) are all made of copper. The first DC positive power terminal (1) and the second DC positive power terminal (3), the first DC negative power terminal (2) and the second DC negative power terminal (4) are symmetrically distributed on both sides of the lower DBC board (20).

6. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: The conductive sheet includes a first conductive sheet (9), a second conductive sheet (10), a third conductive sheet (11), and a fourth conductive sheet (12); the first conductive sheet (9), the second conductive sheet (10), and the third conductive sheet (11) are all molybdenum sheets, and the fourth conductive sheet (12) is a copper sheet.

7. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: On one side of the first region (17), a first conductive sheet (9) and a second conductive sheet (10) are connected via solder layers (15). The first conductive sheet (9) is connected to the source of the SiC MOSFET chip (13) via a first solder layer (151), and the second conductive sheet (10) is connected to the anode of the diode chip (14) via a second solder layer (152). On the other side of the first region (17), a first conductive sheet (9) and a second conductive sheet (10) are connected via solder layers (15). The first conductive sheet (9) is connected to the drain of the SiC MOSFET chip (13) via a first solder layer (151), and the second conductive sheet (10) is connected to the cathode of the diode chip (14) via a second solder layer (152). The second region (18) is located directly in front of the SiC MOSFET chip (13). The gate of the MOSFET chip (13) is connected to the third conductive sheet (11) through the fourth conductive sheet (12), and the third conductive sheet (11) is connected to the gate drive terminal (5) through the fifth region (8).

8. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 7, characterized in that: There are 6 groups of SiC MOSFET chips (13) and diode cores (14) on the first region (17), which are arranged alternately and at equal intervals.

9. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 1, characterized in that: The third region (6) is connected to the first conductive sheet (9) and the second conductive sheet (10) through the solder layer (15). The first conductive sheet (9) is connected to the drain of the SiC MOSFET chip (13) through the first solder layer (151), and the second conductive sheet (10) is connected to the cathode of the diode chip (14) through the second solder layer (152). The fourth region (7) is connected to the first conductive sheet (9) and the second conductive sheet (10) through the solder layer (15). The first conductive sheet (9) is connected to the source of the SiC MOSFET chip (13) through the first solder layer (151), and the second conductive sheet (10) is connected to the anode of the diode chip (14) through the second solder layer (152). The second region (18) is located in front of the SiC MOSFET chip (13). The gate of the SiC MOSFET chip (13) is connected to the third conductive sheet (11) through the fourth conductive sheet (12), and the third conductive sheet (11) is connected to the gate driving terminal (5) through the fifth region (8).

10. A parallel half-bridge power module with dual-ended power supply and dual-sided heat dissipation packaging according to claim 9, characterized in that: There are 6 groups of SiC MOSFET chips (13) and diode cores (14) on the third region (6) and the fourth region (7), which are arranged alternately and at equal intervals.

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