Memory circuit and memory processing method

Abstract

The present invention enables further reduction in power consumption and area of an entire circuit for outputting a pulse output signal for use in stochastic computing.　Provided is a stochastic memory SM for outputting a pulse output signal Vout the probability of which of being a state 1 is a probability p, the stochastic memory SM comprising: a bistable circuit 1 which outputs a pulse output signal Vout on the basis of a bistable characteristic with a single peak structure as a relationship between voltage and potential of the pulse output signal Vout and to which the pulse output signal Vout is fed back; an offset circuit 2 which includes a floating gate transistor FG, and which superimposes, on the pulse output signal Vout, an offset signal Vvf obtained by offsetting a noise signal Vnoise the state of which changes randomly; and a voltage control circuit 5 which controls the direction and amount of the offset in accordance with the probability p by controlling a floating gate voltage Vfg of the floating gate transistor FG in accordance with the probability p.

Description

Memory circuit and memory processing method

[0001] The present invention relates to the technical field of memory circuits and memory processing methods, and more particularly to memory circuits used in learning devices using artificial intelligence (so-called AI) and stochastic computing (hereinafter simply referred to as "SC"), and memory processing methods on such memory circuits.

[0002] In recent years, with the expansion of the so-called "Internet of Things," research and development into so-called edge computing, for example, in wearable devices worn by people, has been active.

[0003] Meanwhile, in parallel with the Internet, research and development into artificial intelligence (AI) has also been actively conducted in recent years. However, in the research and development of AI, the cost of product-sum operations as AI (the "cost" of the product-sum operations refers to, for example, the high speed required of the processing unit that handles the AI ​​processing, the amount of memory required for the processing, etc.) has increased dramatically. For this reason, the cost poses a significant barrier when attempting to apply AI integrated circuits to edge computing, which is particularly subject to significant limitations on the area and power consumption of the integrated circuit itself. Therefore, when applying AI integrated circuits to edge computing, it is necessary to maximize the power efficiency of the circuit.

[0004] Therefore, when considering the application of various architectures to edge computing from the above perspective, the inventors of the present invention focused on SC, which has a history of over 50 years. SC is a computational technique that significantly reduces circuit area by using probability. Originally, SC is characterized by variability in computation results due to the nature of probability. However, in recent years, SC has shown potential for application in various applications where a certain degree of error in computation results is acceptable, such as image processing and deep learning. Furthermore, because a certain degree of error is also acceptable in AI integrated circuits in edge computing, the introduction of SC to edge computing is expected to result in reduced area and power consumption. An example of a component technology for realizing an AI integrated circuit in edge computing using SC is the true random number generator for digital circuits described in Patent Document 1 below.

[0005] Special Publication No. 2006-509286

[0006] However, prior art, including the technology described in Patent Document 1, often requires a decoder, an encoder, and a memory circuit for its configuration, which poses the problem that the power consumption and area required for a probabilistic computer compatible with SC are not sufficient.

[0007] The present invention has been made in consideration of the above-mentioned demands and problems, and one example of the object of the present invention is to provide a memory circuit and a memory processing method executed in the memory circuit that enable further reduction in power consumption and area of ​​the entire circuit for outputting pulse output signals used in the SC itself and in AI integrated circuits that use the SC.

[0008] In order to solve the above-mentioned problems, the invention of claim 1 provides a memory circuit that outputs a pulse output signal that transitions between a LOW state and a HIGH state that is higher than the LOW state, and the probability that the state is the HIGH state is p, and the pulse output signal has a bistable characteristic having a single mountain-shaped structure as a relationship between voltage and potential, and the balanced states include a first stable state as the single mountain-shaped structure corresponding to the LOW state and a first power supply voltage, a second stable state as the single mountain-shaped structure corresponding to the HIGH state and a second power supply voltage higher than the first power supply voltage, and a second stable state as the first stable state and the The device is equipped with: a bistable circuit that outputs the pulse output signal based on bistable characteristics including an unstable state corresponding to the top of the single mountain-shaped structure between a first stable state and a second stable state, which is an unstable state corresponding to ground potential, and to which the output pulse output signal is fed back; an offset circuit that includes a non-volatile memory type transistor and superimposes an offset signal obtained by offsetting a random signal whose state randomly changes between a HIGH state and a LOW state on the fed-back pulse output signal; and a control circuit that controls the direction and amount of the offset in accordance with the probability p by controlling the memory value of the transistor in accordance with the probability p.

[0009] In order to solve the above-mentioned problems, the invention of claim 7 provides a memory circuit that outputs a pulse output signal that transitions between a LOW state and a HIGH state that is higher than the LOW state, and the probability that the HIGH state is the HIGH state is p, and the memory circuit includes a bistable circuit, an offset circuit including a nonvolatile memory type transistor and connected to the bistable circuit, and a control circuit. The memory circuit is a memory processing method executed in the memory circuit, wherein the pulse output signal has a bistable characteristic having a single-mountain structure as a relationship between voltage and potential, and the balanced state includes a first stable state as the single-mountain structure corresponding to the LOW state and a first power supply voltage, and a second stable state corresponding to the HIGH state and a second power supply voltage higher than the first power supply voltage, and an output / feedback step of outputting the pulse output signal from the bistable circuit based on bistable characteristics including a second stable state as the single mountain-shaped structure and an unstable state corresponding to the top of the single mountain-shaped structure between the first stable state and the second stable state and corresponding to ground potential, and feeding back the output pulse output within the bistable circuit; an offset step of superimposing an offset signal, which is obtained by offsetting a random signal whose state randomly changes between a HIGH state and a LOW state, on the fed-back pulse output signal by the offset circuit; and a control step of controlling the memory value of the transistor by the control circuit in correspondence with the probability p, thereby controlling the direction and amount of the offset in correspondence with the probability p.

[0010] According to the invention of claim 1 or claim 7, when outputting a pulse output signal which transitions between a HIGH state and a LOW state and the probability that the state will be a HIGH state is p, the direction and amount of offset of a random signal superimposed on the pulse output signal which is fed back in a bistable circuit having bistable characteristics of a single mountain-shaped structure including a first stable state, a second stable state, and an unstable state are controlled in accordance with the probability p. Therefore, since the pulse output signal which will be a HIGH state with the probability p can be generated using a small number of elements, it is possible to reduce the power consumption and area of ​​the entire circuit for outputting the pulse output signal.

[0011] Furthermore, the bistable circuit has a bistable characteristic of a single mountain-shaped structure, and the random signal superimposed on the feedback pulse output signal is offset while maintaining the bistable characteristic constant, thereby enabling the above-mentioned lower power consumption and smaller area compared to the case where a double well structure, which has been conventionally used to realize bistable characteristics, is used.

[0012] In order to solve the above problem, the invention described in claim 2 is a memory circuit described in claim 1, wherein the transistor is a floating gate transistor, the stored value is the amount of charge in the floating gate transistor controlled by the floating gate voltage of the floating gate transistor, and the control circuit is a voltage control circuit that controls the floating gate voltage in accordance with the probability p, thereby controlling the direction and amount of the offset in accordance with the probability p.

[0013] According to the invention of claim 2, in addition to the effects of the invention of claim 1, the nonvolatile memory type transistor is a floating gate transistor, the stored value is the amount of charge in the floating gate transistor controlled by the floating gate voltage of the floating gate transistor, and by controlling the floating gate voltage in accordance with the probability p, the direction and amount of offset in the offset signal are controlled in accordance with the probability p, so that by using a simple configuration, it is possible to further reduce the power consumption and area of ​​the entire memory circuit.

[0014] In order to solve the above problem, the invention of claim 3 is the memory circuit of claim 2, further comprising a switch circuit that controls on / off the superposition of the offset signal onto the fed-back pulse output signal, wherein the offset circuit that outputs the offset signal comprises a first operational amplifier having the floating gate transistor at its positive terminal and having the random signal input to its gate terminal, and having the offset signal fed back to its negative terminal, and the bistable circuit is configured to comprise a capacitor connected between the output terminal of the pulse output signal and the first power supply voltage, and a second operational amplifier having the offset signal, with the pulse output signal fed back as feedback, input to its positive terminal and having its negative terminal grounded.

[0015] According to the third aspect of the present invention, in addition to the effects of the second aspect, the superposition of an offset signal on the pulse output signal is controlled on / off by a switch circuit, and the offset circuit comprises a first operational amplifier having a floating gate transistor at its positive terminal to which a random signal is input and to which the offset signal is fed back to its negative terminal. The bistable circuit comprises a capacitor connected between the output terminal of the pulse output signal and the first power supply voltage, and a second operational amplifier having a positive terminal to which the offset signal, to which the pulse output signal is fed back, and a grounded negative terminal. This allows for a simpler configuration of the memory circuit, and further reduces power consumption and area.

[0016] In order to solve the above problem, the invention described in claim 4 is a memory circuit described in any one of claims 1 to 3, in which the application of each of the random signals used in multiple memory circuits is controlled by the output of any of the stages in an inverter delay circuit consisting of multiple stages of inverter circuits connected in series.

[0017] According to the fourth aspect of the present invention, in addition to the effects of any one of the first to third aspects of the present invention, the application of each random signal used in a plurality of memory circuits is controlled by the output of one of the stages in an inverter delay circuit formed by connecting multiple stages of inverter circuits in series, so that each memory circuit is driven by a random signal that is independent of the others, and therefore a pulse output signal whose probability of being in a HIGH state is p can be accurately output with a simple circuit configuration.

[0018] In order to solve the above problem, the invention described in claim 5 is a memory circuit described in any one of claims 1 to 4, further comprising an input section such as a voltage control circuit to which an increase signal and a decrease signal corresponding to the weighting in the processing are input, the increase signal and the decrease signal being output from a learning device that performs artificial intelligence processing using the pulse output signal output from the bistable circuit, and the control circuit is configured to control the stored value in correspondence with the probability p based on the input increase signal and decrease signal.

[0019] According to the invention of claim 5, in addition to the effects of the invention of any one of claims 1 to 4, the memory value of the transistor is controlled in correspondence with probability p based on an increase signal and a decrease signal that are output from a learning device that performs artificial intelligence processing using a pulse output signal and that correspond to the weighting in the processing. Therefore, low power consumption and a small area can be achieved when a pulse output signal whose HIGH state probability is probability p is used in a learning device.

[0020] In order to solve the above problem, the invention described in claim 6 is a memory circuit described in any one of claims 1 to 4, wherein the memory circuit is included in a probabilistic computer having a processing unit that performs storage processing using the pulse output signal output from the bistable circuit, and the control circuit is configured to control the storage value in correspondence with the probability p based on the storage value signal output from the processing unit.

[0021] According to the sixth aspect of the present invention, in addition to the effects of any one of the first to fourth aspects of the present invention, the memory circuit is included in a probabilistic computer, and the memory value of the transistor is controlled in accordance with the probability p based on the memory value signal output from the processing unit of the probabilistic computer. Therefore, it is possible to reduce power consumption and area when a pulse output signal whose HIGH state probability is p is used in a probabilistic computer.

[0022] According to the present invention, when a pulse output signal is output whose state transitions between a HIGH state and a LOW state and the probability that the state will be a HIGH state is p, the direction and amount of offset of a random signal superimposed on the pulse output signal fed back in a bistable circuit having bistable characteristics of a single mountain-shaped structure including a first stable state, a second stable state, and an unstable state are controlled in accordance with the probability p.

[0023] Therefore, since a pulse output signal whose HIGH state probability is p can be generated using a small number of elements, it is possible to reduce the power consumption and area of ​​the entire circuit for outputting the pulse output signal.

[0024] Furthermore, the bistable circuit has a bistable characteristic of a single mountain-shaped structure, and the random signal superimposed on the pulse output signal is offset while maintaining the bistable characteristic constant, thereby enabling the above-mentioned lower power consumption and smaller area compared to when a double well structure, which has been conventionally used to achieve bistable characteristics, is used.

[0025] FIG. 11 is a diagram (I) explaining the principle of the present invention, where (a) is a waveform diagram showing an example of a pulse output signal of the present invention, and (b) is a diagram showing the bistable characteristic of the present invention. FIG. 12 is a diagram (II) explaining the principle of the present invention, where (a) is a diagram showing the relationship between the voltage and potential of a pulse output signal in the bistable characteristic of the present invention, and (b) is a diagram showing the relationship between time and the voltage of the pulse output signal in the bistable characteristic. FIG. 13 is a diagram (III) explaining the principle of the present invention, where (a) is a diagram (i) showing the relationship between the bistable characteristic of the present invention and the floating gate voltage, (b) is a diagram showing said relationship, and (c) is a diagram showing said relationship. FIG. 14 is a diagram showing the general configuration of a stochastic memory of an embodiment, where (a) is a diagram showing said general configuration, and (b) is a diagram showing the configuration of a floating gate transistor of an embodiment. FIG. 15 is a diagram showing the operation of the stochastic memory of an embodiment, where (a) is a diagram showing the relationship between the voltage and potential of a pulse output signal as the operation, and (b) is a flowchart showing a memory processing method using the stochastic memory. FIG. 16 is a diagram showing the relationship between time and the voltage of each part in the operation of the stochastic memory of an embodiment. 1 is a diagram showing the relationship between time and the voltage of each part when the floating gate voltage changes in the operation of the stochastic memory of the embodiment. FIG. 2 is a circuit diagram showing the configuration of a noise signal application circuit corresponding to the stochastic memory of the embodiment. FIG. 3 is a diagram showing the temporal changes of a pulse output signal in the operation of the stochastic memory of the embodiment, where (a) is a diagram showing the temporal changes, and (b) is a diagram illustrating the relationship between the floating gate voltage and probability in the pulse output signal. FIG. 4 is a diagram showing the general configuration of a modified stochastic memory.

[0026] Next, the principle of the present invention and embodiments for implementing the present invention using the principle will be described with reference to the drawings. The embodiments and modified embodiments of the present invention described below along with the principle are embodiments in which the present invention is applied to a stochastic memory that outputs a pulse output signal in which a state transitions between state 1 and state 0, and the probability that the state is state 1 is p (0≦p≦1). In this case, in the stochastic memory of the embodiment, the probability p of the pulse output signal can be variably controlled by the present invention. The stochastic memory of the embodiment corresponds to an example of a "memory circuit" of the present invention.

[0027] (I) Principle of the Present Invention First, before describing specific embodiments, the principle of the present invention will be described with reference to Figures 1 to 3. Figures 1 to 3 are diagrams for explaining the principle, respectively.

[0028] As described above and shown in FIG. 1A, the probabilistic memory of the embodiment generates a pulse output signal V that transitions between state 1 and state 0 and has a probability of being state 1 of “p”. ｏｕｔ More specifically, first, the pulse output signal V ｏｕｔ In this case, the state is randomly repeated between state 1 and state 0, for example, at a preset period (sampling period). If, for example, there are 500 periods out of 1000 such periods in which the state is 1, then the pulse output signal V ｏｕｔ The probability p of this is 500 / 1000 = 0.5. For example, if the cycle is five times and the state is 1 twice in a row and 0 the remaining three times, the probability p in this case is 2 / 5 = 0.4.

[0029] In order to achieve low power consumption and a small area in the above-mentioned probabilistic memory, the inventors of the present invention considered applying the bistable characteristics of a single-mountain structure in a bistable circuit (hereinafter simply referred to as the "bistable characteristics of the embodiment").

[0030] In this case, the bistable characteristic of the embodiment applied to the present invention is, for example, a pulse output signal V corresponding to the above state as shown in FIG. ｏｕｔ The bistable characteristic MV has a "single-mountain structure" as a relationship between the voltage of the pulse output signal V and the potential corresponding to the voltage. In the case illustrated in FIG. 1(b), the bistable characteristic MV has a "single-mountain structure" as a relationship between the voltage of the pulse output signal V and the potential corresponding to the voltage. ｏｕｔ The power supply voltage V ＳＳ is the first stable state of the potential corresponding to state 0, and the power supply voltage V ＤＤ becomes a second stable state of potential corresponding to state 1. On the other hand, when the voltage is just before or after the ground potential GND, the voltage and the corresponding potential become unstable. By providing the above three states, the bistable characteristic of the embodiment is realized. In the stochastic memory of the embodiment, as illustrated in FIG. 1B, the noise signal V of the embodiment is a random signal that fluctuates within a range including the ground potential GND. ｎｏｉｓｅ is applied to the bistable characteristic MV from the outside, and the noise signal V ｎｏｉｓｅ The initial value of the noise signal V (the initial value as a voltage indicated by the white circles in FIGS. 1(b) to 3) is controlled in accordance with the probability p, as will be described later. ｎｏｉｓｅ The initial value of is usually a voltage corresponding to the ground potential GND. As a result, the stochastic memory of the embodiment outputs the pulse output signal V whose probability of being in state 1 is the probability p. ｏｕｔ will be output.

[0031] When the bistable characteristic of the embodiment having such a single-mountain structure is realized as an actual circuit, it can be realized by an extremely simple circuit including one operational amplifier and one capacitor, as will be described later. Because it can be realized by this extremely simple circuit, the bistable characteristic of the embodiment is a stable bistable characteristic that is less susceptible to the influence of circuit constants, for example, when a bistable characteristic is realized using multiple drive elements.

[0032] More specifically, as illustrated in FIG. 2A, a noise signal V is applied to the bistable characteristic MV of the embodiment.ｎｏｉｓｅ If the initial value of is set to a value higher than the ground potential GND, then the pulse output signal V ｏｕｔ The voltage of the pulse output signal V ｏｕｔ The power supply voltage V corresponding to state 1 as ＤＤ (see ● in Figure 2), and the power supply voltage V ＤＤ On the other hand, although not shown in the figure, the noise signal V applied to the bistable characteristic MV of the embodiment ｎｏｉｓｅ If the initial value of is set to a value lower than the ground potential GND, then the pulse output signal V ｏｕｔ The voltage of the pulse output signal V ｏｕｔ The power supply voltage V corresponding to the state 0 as ＳＳ and the power supply voltage V ＳＳ In the bistable characteristic of the embodiment, the pulse output signal V ｏｕｔ The change in state as shown in FIG. 2(b) is the change in the noise signal V ｎｏｉｓｅ In response to the change in the power supply voltage V ＤＤ State 1 and power supply voltage V ＳＳ The noise signal V ｎｏｉｓｅ The voltage of the pulse output signal V is set to a voltage that can transition from state 1 to state 0 beyond the ground potential GND (or a voltage that can transition from state 0 to state 1 beyond the ground potential GND). ｏｕｔ The voltage of the noise signal V ｎｏｉｓｅ It can be considered that the noise signal V stochastically changes between two states, state 1 and state 0, across the ground potential GND, depending on the initial value of V . ｎｏｉｓｅ The pulse output signal V as a stochastic memory corresponding to the voltage of ｏｕｔ corresponds to a stochastic transition between state 0 and state 1.

[0033] Therefore, in the bistable characteristic of the embodiment, the noise signal V ｎｏｉｓｅThe initial value of ρ is changed in accordance with the desired probability p of the stochastic memory of the embodiment. Therefore, in the stochastic memory of the embodiment, the floating gate voltage V ｆｇ is controlled in accordance with the desired probability p, a pulse output signal V that corresponds to the amount of charge and becomes state 1 with the desired probability p is generated. ｏｕｔ More specifically, as shown in FIG. 3A, when the initial value is not controlled (changed), the pulse output signal V ｏｕｔ is the power supply voltage V ＤＤ (corresponding to state 1) Stability p and power supply voltage V ＳＳ The probability p of stabilizing in state 0 is 0.5. In contrast, if the desired probability p is less than 0.5, the floating gate voltage V ｆｇ is controlled to be a negative value, the pulse output signal V ｏｕｔ is the power supply voltage V ＤＤ The probability p of stabilizing at this state approaches state 0 (in other words, the pulse output signal V ｏｕｔ is the power supply voltage V ＳＳ (The probability p of stabilizing at state 1 approaches state 1.) Furthermore, if the desired probability p is greater than 0.5, the floating gate voltage V ｆｇ is controlled to be a positive value, the pulse output signal V ｏｕｔ is the power supply voltage V ＤＤ The probability p of stabilizing at this state approaches state 1 (in other words, the pulse output signal V ｏｕｔ is the power supply voltage V ＳＳ The probability p of stabilizing at this state approaches state 0).

[0034] As described above, in the probabilistic memory of the embodiment having the bistable characteristic MV of the embodiment, as illustrated in FIGS. 1 to 3, the noise signal V ｎｏｉｓｅ By controlling the initial value of the stochastic memory, the pulse output signal V ｏｕｔ The probability p as .times. ...

[0035] (II) Embodiments Next, the configuration and operation of a stochastic memory according to an embodiment of the present invention based on the above-described principles will be specifically described with reference to Figures 4 to 9. Note that Figure 4 is a diagram showing the general configuration of the stochastic memory, Figure 5 is a diagram showing the operation of the stochastic memory, and Figure 6 is a diagram showing the relationship between time and the voltage of each component during operation of the stochastic memory. Also, Figure 7 is a diagram showing the relationship between time and the voltage of each component when the floating gate voltage changes during operation of the stochastic memory, Figure 8 is a circuit diagram showing the configuration of a noise signal application circuit constituting the stochastic memory, and Figure 9 is a diagram showing the temporal changes in the pulse output signal during operation of the stochastic memory according to the embodiment.

[0036] As shown in Fig. 4(a), the stochastic memory SM of the embodiment is configured to include a bistable circuit 1, an offset circuit 2, an analog switch circuit 3, a noise signal application circuit 4, a voltage control circuit 5, and a switch control circuit 6. In this case, the noise signal application circuit 4 applies the noise signal V of the embodiment to only one stochastic memory SM. ｎｏｉｓｅ Alternatively, the noise signal application circuit 4 may be shared by multiple stochastic memories SM. The bistable circuit 1 is configured by connecting an operational amplifier 1A and a capacitor C as shown in FIG. 4(a). The offset circuit 2 is configured by connecting an operational amplifier 2A having a floating gate transistor FG shown in FIG. 4(b) in its positive terminal with the noise signal application circuit 4 and a voltage control circuit 5 as shown in FIG. 4(a). In this case, the operational amplifier 1A corresponds to an example of the "second operational amplifier" of the present invention, the operational amplifier 2A corresponds to an example of the "first operational amplifier" of the present invention, and the floating gate transistor FG corresponds to an example of the "transistor" (non-volatile memory type transistor) of the present invention.

[0037] In the stochastic memory SM having the above configuration, the bistable circuit 1 is a bistable circuit having the bistable characteristic MV of the above embodiment, and outputs the pulse output signal V as the stochastic memory SM from its output terminal. ｏｕｔ and outputs the pulse output signal V ｏｕｔis superimposed on the output of the switch circuit 3 and fed back to the positive terminal of the operational amplifier 1A. The negative terminal of the operational amplifier 1A is grounded. Furthermore, the output terminal of the operational amplifier 1A (pulse output signal V ｏｕｔ output terminal) and power supply voltage V ｓｓ The capacitor C is connected between the switch circuit 3 and the control signal V ｃｏｎ The on / off is controlled by

[0038] On the other hand, in the operational amplifier 2A constituting the offset circuit 2, the noise signal V applied from the noise signal application circuit 4 ｎｏｉｓｅ is input to the gate terminal of the internal floating gate transistor FG via its positive terminal as shown in FIG. 4(b). Also, a floating gate voltage V ｆｇ is input to the floating gate of the floating gate transistor FG as shown in FIG. ｆｇ Examples of the input signal IN input to the voltage control circuit 5 to control the voltage V include the following: (A) When the stochastic memory SM of the embodiment is used for AI learning such as online learning or batch learning, the input signal IN is an increase signal and a decrease signal of the weight (w) output from the AI-based learning device. This is because updating the weight W requires an operation such as "W(t+1) = W(t) ± ΔW" to "save a new value that is slightly increased or decreased from the stored value." (B) When the stochastic memory SM of the embodiment is used as a storage device for a computer (including a processing unit such as a CPU) using the SC, the input signal IN is a stored value signal (e.g., a stored value signal output from the processing unit) having the value of the probability p to be stored in the stochastic memory SM. This is because the computer needs to store the results of various calculations such as "A × B" and "C + D." With the above configuration, the noise signal V ｎｏｉｓｅ The offset corresponding to the control of the initial value of the noise signal V ｎｏｉｓｅ The offset signal Vｖｆ is output to the bistable circuit 1 in response to the on / off state of the switch circuit 3, and is also fed back to the negative terminal of the operational amplifier 2A.

[0039] In the probabilistic memory SM having the above configuration, as shown in FIG. 5, the pulse output signal V corresponding to the probability p is ｏｕｔ As an “initialization” operation in the operation of outputting the control signal V ｃｏｎ The switch circuit 3 is turned on based on the initial value of the floating gate voltage V ｆｇ (i.e., offset by the offset circuit 2) ｎｏｉｓｅ is the offset signal V ｖｆ The offset signal V is input to the positive terminal of the operational amplifier 1A of the bistable circuit 1 via the switch circuit 3. ｖｆ , the pulse output signal V ｏｕｔ Next, when time has passed after the initialization, the pulse output signal V corresponding to the probability p is fed back. ｏｕｔ As a "binarization" operation in the operation of outputting the control signal V ｃｏｎ , the switch circuit 3 is turned off, and then the offset signal V that was input at the timing when the previous switch circuit 3 was turned on is ｖｆ The floating gate voltage V ｆｇ The offset amount corresponding to the power supply voltage VDD (V ｆｇ >0 (see FIG. 3(c)) or power supply voltage V ＳＳ (V ｆｇ < 0 (see FIG. 3(b)). After that, the noise signal V ｎｏｉｓｅ A pulse output signal V (with a probability of being in state 1 p) corresponding to the voltage of ｏｕｔ The output continues.

[0040] Next, the initialization and binarization operations shown in Fig. 5(a) will be explained together with reference to Fig. 5(b). That is, the initialization and binarization operations are repeated as a loop process a desired number of times N (times) corresponding to the application of the stochastic memory SM (steps S1 and S10). Then, as the initialization operation, the offset circuit 2 outputs the noise signal V ｎｏｉｓｅ to the floating gate voltage V ｆｇ is added to the offset signal V ｖｆ is generated (step S2), and at that point the control signal V ｃｏｎ If the value is "1 (the switch circuit 3 is on)" (step S3, step S3: NO), the offset signal V ｖｆ The voltage of the pulse output signal V ｏｕｔ (Step S4), and then the process returns to Step S2 and the above-described process is repeated. ｃｏｎ is "0 (the switch circuit 3 is off)" (step S3, step S3: YES), the pulse output signal V ｏｕｔ The voltage of the offset signal V ｖｆ (Step S5), and then the pulse output signal V ｏｕｔ It is determined whether the voltage of the pulse output signal V is equal to or greater than the ground voltage (i.e., 0 volts) (step S6). ｏｕｔ If the voltage of is 0 volts or more (step S6: YES), the pulse output signal V ｏｕｔ The voltage is the power supply voltage V ＤＤ On the other hand, the pulse output signal V ｏｕｔ If the voltage of is less than 0 volts (step S6: NO), the pulse output signal V ｏｕｔ The voltage is the power supply voltage V ＳＳ The signal is amplified to the value 0 and output (step S7). Thereafter, the parameter i indicating the number of times of the loop is incremented by "1" (step S9), and the operations of steps S1 to S8 are repeated N times, thereby completing the initialization and binarization operations.

[0041] Next, the initialization and binarization operations described with reference to Fig. 5 will be described with reference to Fig. 6 as a relationship between time and voltage. As shown in Fig. 6, the control signal V ｃｏｎ is set to "1", and at other times the control signal V ｃｏｎ In this state, when the initialization and binarization shown in FIG. 5 are repeated, first, at timing T1, the offset signal V ｖｆ Due to the influence of the pulse output signal V ｏｕｔ Since the voltage of is higher than the ground potential GND (see step S6 in FIG. 6: YES), the pulse output signal V ｏｕｔ The power supply voltage V ＤＤ Then, between timing T2 and timing T3, the control signal V ｃｏｎ is set to "1" (see step S3 in FIG. 6: NO), the offset signal V ｖｆ A pulse output signal V having a voltage equal to the voltage of ｏｕｔ is output (see step S4 in FIG. 6). Next, the control signal V ｃｏｎ At timing T3 when the offset signal V ｖｆ Due to the influence of the pulse output signal V ｏｕｔ Since the voltage of is lower than the ground potential GND (see step S6 in FIG. 6: NO), the pulse output signal V ｏｕｔ The power supply voltage V ＳＳ , and stabilizes (see step S7 in FIG. 6). Furthermore, between timing T4 and timing T5, the control signal V ｃｏｎ is set to "1" (see step S3 in FIG. 6: NO), the offset signal V ｖｆ A pulse output signal V having a voltage equal to the voltage of ｏｕｔ is output (see step S4 in FIG. 6). ｃｏｎ At timing T5 when the offset signal V ｖｆ Due to the influence of the pulse output signal V ｏｕｔSince the voltage of is lower than the ground potential GND (see step S6 in FIG. 6: NO), the pulse output signal V ｏｕｔ After timing T5, the power supply voltage V ＳＳ and the voltage is stabilized (see step S7 in FIG. 6).

[0042] At this time, the floating gate voltage V ｆｇ is less than 0 volts, the original noise signal V ｎｏｉｓｅ The voltage of the control signal V ｃｏｎ Even if the potential is higher than the ground potential GND at the time of switching, the pulse output signal V ｏｕｔ The voltage is the power supply voltage V ＳＳ It may be stabilized at

[0043] Next, the noise signal V ｎｏｉｓｅ Regarding the specific configuration of the noise signal application circuit 4 that generates the noise signal V, ｎｏｉｓｅ The noise signal application circuit 4 that outputs (supplies) the above will be described with reference to Fig. 8. Fig. 8 is a circuit diagram showing the configuration of the noise signal application circuit 4 that corresponds to the stochastic memory SM of the embodiment.

[0044] The noise signal application circuit 4 of the embodiment is configured to apply independent noise signals V ｎｏｉｓｅ As long as it can output a noise signal V, it is possible to use, for example, a conventional distributed constant circuit (for example, a distributed constant circuit described on the Internet at "https: / / zawa2.com / ZZsim / doc_microstrip.html"), or a conventional linear feedback shift register (for example, a linear feedback shift register described on the Internet at "https: / / www.semanticscholar.org / paper / Compact-and-accurate-stochastic-circuits-with-Ichihara-Ishii / a62be61c4fe614a968d468aaf49f405bd7d873fb"). In this case, in the former distributed constant circuit, a phase delay occurs due to the inductors and capacitors that make up the circuit, so the output for each phase is converted into a noise signal V. ｎｏｉｓｅBy doing so, independent noise signals V ｎｏｉｓｅ In the latter linear feedback shift register, the output from each stage of the linear feedback shift register and the random number are shifted in synchronization with the clock signal, and the shifted output is then fed to the noise signal V ｎｏｉｓｅ By doing so, independent noise signals V ｎｏｉｓｅ can be supplied.

[0045] On the other hand, as another example, as illustrated in FIG. 8, a plurality of inverters t ｄ Each inverter t in the inverter delay circuit DD in which ｄ The input and output signals of the control signal V ｃｏｎ and this control signal V ｃｏｎ Thus, the noise signal V output from one noise signal application circuit 4 ｎｏｉｓｅ may be configured to supply each of the noise signals V to each of the stochastic memories SM with different delay times. ｎｏｉｓｅ to the offset circuit 2 are applied with control signals V ｃｏｎ As a result, the plurality of stochastic memories SM can be controlled in a time-division manner (while varying the delay time). ｎｏｉｓｅ This will enable us to supply

[0046] Finally, the inventors of the present invention have determined that the floating gate voltage V ｆｇ and pulse output signal V ｏｕｔ We performed simulations of the change in the noise signal V and the corresponding change in the probability p as a probabilistic memory SM. ｎｏｉｓｅ The stochastic stable operation (transition (movement) operation to stable state 0 or state 1) that occurs when the input is repeated 100 times to generate a pulse output signal V ｏｕｔ The change in state 1 is checked, and the pulse output signal V ｏｕｔCalculating the probability p of ｆｇ The results are shown in Figure 9.

[0047] First, as shown in FIG. 9(a), the pulse output signal V ｏｕｔ When the voltage of V changes with time, the probability p is ｆｇ 9B. From the simulation results shown in FIG. 9, it was confirmed that the floating gate voltage V ｆｇ By controlling the amount of charge in the floating gate transistor FG of the embodiment, the pulse output signal V ｏｕｔ It was confirmed that the probability p of the pulse output signal V ｏｕｔ As a result, it has become clear that the probability p can be stored as a probabilistic memory SM.

[0048] As described above, according to the configuration of the probabilistic memory SM of the embodiment, a pulse output signal V ｏｕｔ When outputting the pulse output signal V, the bistable circuit 1 has a bistable characteristic MV of a single-mountain structure embodiment including two stable states and one unstable state. ｏｕｔ The noise signal V superimposed on ｎｏｉｓｅ The direction and amount of the offset of the pulse output signal V whose probability of being in state 1 is p is controlled in accordance with the probability p (see FIGS. 1 to 3). ｏｕｔ Since the pulse output signal V can be generated using a small number of elements, ｏｕｔ Therefore, it is possible to reduce the power consumption and area of ​​the entire circuit for outputting the signal.

[0049] Furthermore, the bistable circuit 1 has the bistable characteristic MV of the embodiment with a single mountain-shaped structure, and the pulse output signal V is fed back while keeping the bistable characteristic MV of the embodiment constant. ｏｕｔ The noise signal V superimposed on ｎｏｉｓｅare offset and superimposed (see FIGS. 1 to 3), the above-mentioned reduction in power consumption and area is possible compared to the case where a double well structure, which has been conventionally used to realize the bistable characteristic MV of the embodiment, is used.

[0050] Furthermore, the pulse output signal V ｏｕｔ Offset signal V ｖｆ The switch circuit 3 controls the on / off of the superposition of the noise signal V ｎｏｉｓｅ A floating gate transistor FG is provided at its positive terminal, and an offset signal V ｖｆ The bistable circuit 1 is configured with an operational amplifier 2A having a negative terminal fed back to the negative terminal (see FIG. 4). ｏｕｔ output terminal and power supply voltage V ｓｓ and a capacitor C connected between the pulse output signal V ｏｕｔ The offset signal V ｖｆ is input to the positive terminal and the negative terminal is grounded. Therefore, the probabilistic memory SM can have a simpler configuration.

[0051] Furthermore, each noise signal V used in the plurality of stochastic memories SM ｎｏｉｓｅ The application of the inverter circuit t ｄ The delay circuit DD is controlled by the output of one of the stages in the inverter delay circuit DD, which is made up of serially connected inverters (see FIG. 8). As a result, each stochastic memory SM generates a noise signal V ｎｏｉｓｅ , the probability of being in state 1 is p. ｏｕｔ can be accurately output with a simple circuit configuration.

[0052] In addition, the pulse output signal V ｏｕｔ The floating gate voltage V is calculated based on the increase and decrease signals output from the learning device that performs AI processing using the ｆｇ is controlled in accordance with the probability p, the pulse output signal V ｏｕｔ When used in a learning device, it is possible to reduce power consumption and area.

[0053] Furthermore, a probabilistic memory SM is included in the probabilistic computer, and a floating gate voltage V is calculated based on a stored value signal output from a processing unit of the probabilistic computer. ｆｇ is controlled in accordance with the probability p, the pulse output signal V ｏｕｔ This allows for lower power consumption and smaller area when used in a probabilistic computer.

[0054] (III) Modifications Next, several modifications of the present invention will be described.

[0055] First, a first modified embodiment of the present invention will be described with reference to Fig. 10. Fig. 10 is a diagram showing the general configuration of the probabilistic memory of the first modified embodiment. In Fig. 10, the same components as those in the probabilistic memory SM of the embodiment are designated by the same component numbers, and detailed descriptions thereof will be omitted.

[0056] In the stochastic memory SM of the above-described embodiment, the operation of the stochastic memory SM is realized using the bistable characteristic MV of the bistable circuit 1. However, in addition to this, in the stochastic memory of a first modified embodiment described below, the operation of the stochastic memory is realized by a simpler configuration such as a sample-and-hold circuit.

[0057] That is, as shown in FIG. 10, the probabilistic memory SMM of the first modified embodiment has a bistable circuit having one end connected to a power supply voltage V ＳＳ The other end is connected to the switch circuit 3, and the sample and hold signal V ｓｈ and a capacitor C1 that outputs a control signal V ｃｏｎ The sample and hold signal V ｓｈ is input and driven by transistor 11 and transistor 13 to generate a pulse output signal V ｏｕｔ In this configuration, the sample-and-hold circuit of the first modified embodiment realized by the switch circuit 3 and the capacitor C1 receives the control signal V ｃｏｎ When the offset signal Vｖｆ A sample and hold signal V of a voltage equal to the voltage of ｓｈ and outputs the control signal V ｃｏｎ When the value of the sample-and-hold signal V is set to "0", a predetermined constant voltage is generated. ｓｈ Then, the inverter 12 outputs the control signal V ｃｏｎ When the sample hold signal V ｓｈ When the voltage is 0 volts or higher, the power supply voltage V ＳＳ The pulse output signal V ｏｕｔ and outputs the sample-and-hold signal V ｓｈ When the voltage is less than 0 volts, the power supply voltage V ＤＤ The pulse output signal V ｏｕｔ In other words, the inverter 12 outputs the sample-and-hold signal V ｓｈ In response to the voltage of the control signal V, the inverter 12 performs a binarization operation similar to that of the bistable circuit 1 in the stochastic memory SM of the embodiment. ｃｏｎ It will not operate when set to "1".

[0058] According to the configuration and operation of the stochastic memory of the first modified embodiment described above, the stochastic memory can be realized with a simpler configuration, which makes it possible to further reduce the power consumption and area of ​​the entire stochastic memory.

[0059] Next, a second modified embodiment of the present invention will be described. In the second modified embodiment described below, the same components as those in the probabilistic memory SM of the embodiment will be assigned the same component numbers and detailed descriptions will be omitted.

[0060] In the above-described embodiment of the stochastic memory SM, the stochastic memory SM has been described as having a floating gate transistor FG, which corresponds to an example of the "transistor" (non-volatile memory type transistor) of the present invention. At this time, in the floating gate transistor FG, the floating gate voltage V ｆｇThe amount of charge in the floating gate transistor FG, which corresponds to an example of the "storage value" of the present invention, is controlled by the floating gate voltage V ｆｇ is controlled by a voltage control circuit 5. However, other examples that correspond to the "transistor" of the present invention include at least a conventional spin FET (Field Effect Transistor) or a ferroelectric FET (also called a "ferroelectric gate FET").

[0061] In this case, the spin FET is a FET used in a conventional spin transfer torque random access memory (Spin Transfer Torque Random Access Memory), and is a current-controlled FET. In this spin FET, it is the spin reversal rate that is controlled in response to the probability p of the present invention. This reversal rate corresponds to another example of the "memory value" of the present invention. By controlling this reversal rate in response to the probability p under current control, the spin FET of the second modified form can be made to exhibit the same function as the floating gate transistor FG of the embodiment according to the present invention.

[0062] On the other hand, the ferroelectric FET is a FET including a ferroelectric layer in a part of the gate insulator, and is a time-controlled FET. In this ferroelectric FET, what is controlled in response to the probability p of the present invention is the polarizability of the ferroelectric material constituting the gate insulator. This polarizability corresponds to another example of the "memorized value" of the present invention. Then, by controlling this polarizability in response to the probability p under time control, the ferroelectric FET of the second modified embodiment can exhibit the function of the present invention equivalent to that of the floating gate transistor FG of the embodiment.

[0063] The stochastic memory of the second modified form, which includes each FET (non-volatile memory type transistor) of the second modified form having the configuration and operation described above, can also achieve the same effects as the stochastic memory SM of the embodiment.

[0064] As explained above, the present invention can be used in the field of stochastic memories, and particularly when applied to stochastic memories that require low power consumption and a small area, a particularly significant effect can be obtained.

[0065] REFERENCE SIGNS LIST 1 Bistable circuit 1A Operational amplifier 2 Offset circuit 2A Operational amplifier 3 Switch circuit 4 Noise signal application circuit 5 Voltage control circuit 6 Switch control circuit 10 Sampling buffer circuit 11, 13 Transistor 12, t ｄ Inverter MV Bistable characteristics SM, SMM Stochastic memory C, C1 Capacitor FG Floating gate transistor DD Inverter delay circuit V ｆｇ Floating gate voltage V ｏｕｔ Pulse output signal V ｎｏｉｓｅ Noise signal IN Input signal

Claims

1. A memory circuit that outputs a pulse output signal whose state transitions between a LOW state and a HIGH state higher than the LOW state, with a probability p of the state being the HIGH state, the bistable circuit outputting the pulse output signal based on a bistable characteristic having a single-peak structure as a relationship between the voltage and potential of the pulse output signal, the bistable characteristic including, as equilibrium states, a first stable state of the single-peak structure corresponding to the LOW state and a first power supply voltage, a second stable state of the single-peak structure corresponding to the HIGH state and a second power supply voltage higher than the first power supply voltage, and an unstable state corresponding to the top of the single-peak structure between the first and second stable states and corresponding to ground potential, and the output pulse output signal being fed back; an offset circuit that includes a non-volatile memory type transistor and superimposes an offset signal obtained by offsetting a random signal whose state randomly changes between a HIGH state and a LOW state, on the fed-back pulse output signal; a control circuit that controls a stored value of the transistor in accordance with the probability p, thereby controlling a direction and amount of the offset in accordance with the probability p.

2. A memory circuit as claimed in claim 1, characterized in that: the transistor is a floating gate transistor; the stored value is an amount of charge in the floating gate transistor controlled by a floating gate voltage of the floating gate transistor; and the control circuit is a voltage control circuit which controls the floating gate voltage in correspondence with the probability p, thereby controlling the direction and amount of the offset in correspondence with the probability p.

3. A memory circuit as claimed in claim 2, further comprising a switch circuit for controlling on / off the superposition of the offset signal onto the fed-back pulse output signal, wherein the offset circuit for outputting the offset signal comprises a first operational amplifier having a floating gate transistor at its positive terminal, the gate terminal of which receives the random signal, and the offset signal is fed back to its negative terminal, and wherein the bistable circuit comprises a capacitor connected between the output terminal of the pulse output signal and the first power supply voltage, and a second operational amplifier having a positive terminal to which the offset signal, with the pulse output signal fed back thereto, is input and whose negative terminal is grounded.

4. A memory circuit as claimed in any one of claims 1 to 3, characterized in that the application of each of the random signals used in a plurality of the memory circuits is controlled by the output of any one of the stages in an inverter delay circuit consisting of multiple stages of inverter circuits connected in series.

5. A memory circuit as claimed in any one of claims 1 to 4, further comprising an input section to which an increase signal and a decrease signal corresponding to a weighting in an artificial intelligence process output from a learning device that uses the pulse output signal output from the bistable circuit are input, and the control circuit controls the stored value in correspondence with the probability p based on the input increase signal and decrease signal.

6. A memory circuit as claimed in any one of claims 1 to 4, characterized in that the memory circuit is included in a probabilistic computer having a processing unit which performs storage processing using the pulse output signal output from the bistable circuit, and the control circuit controls the stored value in correspondence with the probability p based on the stored value signal output from the processing unit.

7. A memory processing method executed in a memory circuit that outputs a pulse output signal whose state transitions between a LOW state and a HIGH state higher than the LOW state, with a probability p of the state being the HIGH state, the memory circuit comprising a bistable circuit, an offset circuit including a non-volatile memory type transistor and connected to the bistable circuit, and a control circuit, the method comprising: an output / feedback step of outputting the pulse output signal from the bistable circuit based on a bistable characteristic having a single-ridge structure as a relationship between the voltage and potential of the pulse output signal, the bistable characteristic including, as an equilibrium state, a first stable state as the single-ridge structure corresponding to the LOW state and a first power supply voltage, respectively, a second stable state as the single-ridge structure corresponding to the HIGH state and a second power supply voltage higher than the first power supply voltage, respectively, and an unstable state corresponding to the top of the single-ridge structure between the first and second stable states and corresponding to ground potential, and feeding back the output pulse output within the bistable circuit; 1. A memory processing method comprising: an offset process in which an offset signal obtained by offsetting a random signal whose state randomly changes between a HIGH state and a LOW state is superimposed on the fed-back pulse output signal by the offset circuit; and a control process in which a direction and amount of the offset are controlled in correspondence with the probability p by controlling a stored value of the transistor by the control circuit in correspondence with the probability p.

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