High-capacity memory module with high command-bandwidth utilization and consistent latency

Abstract

A memory module includes data and command buffers that intermediate between a host and collections of memory packages. The data buffer has a host-side data port for receiving write data and memory-side data ports connected to respective memory packages. The command buffer converts host-side commands to pairs of memory-side commands that control the data buffer and alternative groups of the memory packages. The memory buffer reduces the bit rate of the write data from the host and directs the reduced-rate write data into alternating pairs of the memory packages.

Description

High-Capacity Memory Module with High Command-Bandwidth Utilization and Consistent LatencyFIELD OF THE INVENTION

[0001] The subject matter presented herein relates to computer memory.BACKGROUND

[0002] Computers include processors for processing data and memory for storing that data. Memory is often disposed on a "memory module," usually a small circuit board supporting and interconnecting a series of dynamic random-access memory (DRAM) dies. Memory modules come in different sizes and capacities, measured in bytes, and support varying levels of speed performance. Other figures of merit for memory modules include latency (the time a module takes to start delivering data after a request is made), cost, and energy efficiency. There is ever a demand for better and less expensive memory modules and systems.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0004] Figure 1 depicts a memory system 100 in which a host 105 (e.g. a memory controller) issues command and address (CA) signals via a primary CA port PCA to write to and read from a memory module 110 via ten byte- wide primary data ports DQ, one of which is shown.

[0005] Figure 2 is a timing diagram 200 illustrating a sequence of write transactions for memory system 100 of Figure 1.

[0006] Figure 3 depicts an embodiment of memory data buffer 120 of Figure 1. A horizontal dashed line divides buffer 120 into host- and memory-side clock domains.

[0007] Figure 4 details embodiments of read and write FIFOs 325 and 330 of Figure 3.

[0008] Figure 5 depicts a memory system 100 of Figure 1 with all ten slices 115, eight for data and two for error-correcting code (ECC), distributed onto 2 channels (_0 / _l), one left and on right of the RCD, that can be considered data in the context of this disclosure.

[0009] Figure 6 depicts a memory system 600 like memory system 100 of Figure 1 but with a memory module 610 with a different arrangement of memory link groups MD00, MD01, MD10, and MD11.

[0010] Figure 7 depicts a memory system 700 similar to memory system 100 of Figure 1, like-identified elements being the same or similar.DETAILED DESCRIPTION

[0011] Figure 1 depicts a memory system 100 in which a host 105 (e.g. a memory controller) issues command and address (CA) signals via a primary CA port PCA to write to and read from a memory module 110 via ten byte- wide primary data ports DQ, only one of which is shown. Module 110 is a Memory Rank Dual Inline Memory Module (MRDIMM ) in this example, a “rank” referring to a set of memory devices that can be accessed independently. By using multiple ranks, MRDIMMs can increase the amount of memory available and improve performance by allowing more data to be accessed simultaneously. Module 110 employs memory packages PK with multiple dies D to increase the amount of available memory. Data and command buffers 120 and 125 manage overlapping access to ranks of memory dies in a manner that allows host 105 to take full advantage of the bandwidths offered by the primary CA and DQ ports while delivering consistent access latency.

[0012] Data signals are conveyed to a module connector 112 in byte- wide bursts of e.g. sixteen bits timed to a strobe signal on a primary strobe port DQS. Memory module 110 includes ten parallel data slices 115, one of which is shown, to service commands from host 105. (Ten slices 115 are illustrated together in Figure 5.) Each slice 115 includes four memory packages PK00, PK01, PK10, and PK11 with a memory data buffer (MDB) 120 to control the flow of data signals between the memory packages and host 105. The four packages are divided into respective anterior first and second packages PK00 and PK01 and respective posterior third and fourth packages PK10 and PK11, where “anterior” and “posterior” refer to two sides of memory module 110. A CA buffer 125, alternatively called a registered clock driver (RCD), registers and re-drives signals from host 105 to access the memory dies and includes logic to manage read and write access to the memory packages responsive to commands from host 105. In one embodiment, data and CA buffers 120 and 125 allow host 105 to access a large amount of memory with consistent access latency and quadruple the effective data bandwidth, while fully exploiting available CA bandwidth.

[0013] Data buffer 120 has a host-side data port (DQ / DQS) to communicate read and write data to and from host 105. First, second, third, and fourth memory-side data ports, identified using memory link groups MD00, MD01, MD10, and MD11, are connected to respectivepackages PKOO, PK01, PK1O, and PK11. CA buffer 125 separates the incoming DCA(0:13) into a pair of CA buses QACA[0:13] and QBCA[0:13] to independently control the bottom and top rows of memory packages. As detailed below, lowermost packages PKOO and PK10 in all ten slices 115 are collectively termed a first "pseudo channel" PCI and uppermost packages PK01 and PK11 a second pseudo channel PC2. In this context, the term "channel" refers to the entire set of signal paths and component interfaces between host 105 and module 110 that services individual host commands. The term "pseudo channel," in contrast, refers to a subset of signal paths and components controlled separately to service individual host commands. Data buffer 120, under direction of CA buffer 125 via a buffer-command bus BCOM, combines data on both pseudo channels PCI and PC2 to service commands from host 105. Pseudo channels PCI and PC2 communicate data at one fourth the bit rate of the channel servicing host 105 but together have four times the data width. Data buffer 120 interleaves pseudo-channel accesses and handles the rate conversion, and thus supports a 4x module bandwidth extension and increased capacity with minimal or no changes to legacy memory devices.

[0014] Each memory package PK includes a number of memory devices D, two dynamic random-access memory (DRAM) dies in this example. First package PKOO includes first and second memory dies D000 and D001, second package PK01 includes third and fourth memory dies DO 10 and D011, third package PK10 includes fifth and sixth memory dies DI 00 and D 101, and fourth package PK11 includes seventh and eighth memory dies DI 10 and Di l l. On the host side, data buffer 120 includes a byte-wide host interface 130 operating at a host-channel bit rate indicated by a clock rate CLK. On the memory side, data buffer 120 includes a 32-bit pseudochannel interface 135 connected to each package and die and operating at a memory bit rate one quarter the host clock rate (CLK / 4).

[0015] Figure 2 is a timing diagram 200 illustrating a sequence of write transactions for memory system 100 of Figure 1. Signal names on the vertical axis correspond to like-identified nodes in Figure 1. (In general, signals and their corresponding signal paths are similarly identified. Whether a given reference is to a signal or signal path will be clear in context.) The lower portion of diagram 200 is a continuation of the upper portion with a pair of ellipses representing a temporal gap that is unnecessary for understanding the signal flow.

[0016] On the host side, Command / Address signals DCA are timed to the clock signal CLK. The data signals DQ communicated over the host interface are timed to the DQS signal. In this example CLK and DQS have the same frequency, so CLK represents the bit rate of the DQ.Column commands to the DRAM in this example are packaged commands scheduled over two CLK cycles. The host schedules two column-access commands as clockwise-interleaved pairs to be scheduled for simultaneous access to memory packages and dies on both pseudo channels PCI and PC2. Three pairs of CA commands, distinguished by shading, illustrate the host CA links operating at full bandwidth.

[0017] CA buffer 125 interprets each controller command and conveys corresponding commands to the memory packages and dies via secondary buses QACA and QBCA. Interleaved pairs of host commands are presented concurrently on both secondary buses QACA and QBCA timed to memory clock signal MCLK, which operates at one quarter the host clock rate. The signals for secondary busses QACA and QBCA are specific to the installed memory dies, and the timing, format, and other parameters of those signals are specified for commercially available memory devices in a manner well understood by those of skill in the art.

[0018] Being that these are write transactions, each of the six column-access commands is followed by a corresponding burst of data bits, sixteen bits in this example, accompanied by a strobe signal DQS. System 100 is a double-data-rate (DDR) system, meaning that data bits are communicated on both rising and falling clock edges. Memory Data Buffer 120 de-interleaves DQ DDR bursts to communicate parallel memory-side bursts. The data DQ associated with the first two commands on buses QACA and QBCA are de-interleaved and presented as parallel sixteen-bit bursts on memory link groups MD00 and MD01. Both pseudo channels PCI and PC2 are thus employed in parallel and simultaneously to meet the bandwidth demands of host 105.

[0019] Each memory link group is of width eight, the same as link group DQ from host 105, but operates at a quarter the bit rate and thus requires twice as long as the host channel to communicate the same quantity of data. Accesses to different die groups within pseudo channels PSI and PS2 are interleaved to maintain the memory-side data bandwidth. The data DQ associated with the second two commands on buses QACA and QBCA are de-interleaved and presented as parallel sixteen-bit bursts on memory link groups MD10 and MD11 before the bursts on link groups MD00 and MD01 are completed, halfway through the prior bursts in this example. The data DQ associated with the third pair of commands are likewise de-interleaved and presented as parallel sixteen-bit bursts before the bursts on link groups MD10 and MD11 are completed. By then, however, the first pair of data bursts are finished so the third pair is conveyed via memory link groups MD00 and MD01. Slice 115, and likewise the remaining slices, thus accommodates the full write bandwidth of host 105 and does so while providingconsistent write-access latency. Read transactions are managed likewise in the opposite direction so a detailed discussion is omitted.

[0020] Figure 3 depicts an embodiment of memory data buffer 120 of Figure 1. A horizontal dashed line divides buffer 120 into host- and memory-side clock domains. The lower region comprises channel interface 130, data nodes 300 that each connect to one of eight DQ links to host 105. The upper region comprises pseudo-channel interface 135, memory nodes 305 that connect to designated links within memory link groups MD00, MD01, MD10, and MD11.Buffer 120 is functionally divided into eight sections 310[0:7] , one for each host node 300. Each section 310 communicates between a host node 300 and a corresponding memory node 305 in each of the four link groups MD00, MD01, MD10, and MD11. Only section 310[0] is detailed — the one associated with host node 300 for host link DQ[0]; the other seven sections 310[l :7] are functionally identical.

[0021] On the host side, section 310[0] includes a DDR transmitter 315 and a DDR receiver 320 that communicate with respective read and write FIFOs 325 and 330. On the memory side, section 310[0] includes four transmitters 335 and four receivers 340 paired to communicate read and write data between the lowest-order memory node 305 of each memory link group and FIFOs 325 and 330.

[0022] Each FIFO (First-In-First-Out) includes an array of registers, each capable of holding 16 bits (per pin data of each access). In this example the write FIFO also performs the deserialization function. Alternatively, a de-serializer could also be preceding each write FIFO. Write FIFO 330 includes two pointers, a host pointer DQin (in the faster CLK domain) and a memory pointer MDout (in the slower MCLK=CLK / 4 domain) to manage data inflow and outflow. Control logic (not shown) in section 310 manages the pointers to produce the timing illustrated in Figure 2. FIFO 325 works similarly to move data in the opposite direction but from the slower to the faster clock domain. The read FIFO analogously performs the serialization function in the DQout pointer domain.

[0023] Figure 4 details embodiments of read and write FIFOs 325 and 330 of Figure 3. Write pointer DQin separates each incoming bit into either an even or odd 16b register stage, depending on what DQS edge the respective bit is associated with. After the completion of the data burst, the content of the two registers is then transferred to a register of the corresponding DRAM group via demultiplexer 410. Data out pointers MDout 0 / 1 (generated in the CLK / 4domain), then transfer the data out of the write FIFO. Read FIFO 325 operates similarly, in the opposite direction, using multiplexers 405 in lieu of demultiplexers 410.

[0024] Figure 5 depicts a memory system 100 of Figure 1 with all ten slices 115, eight for data and two for error-correcting code (ECC), distributed onto 2 channels (_0 / _l), one left and on right of the RCD. Data and ECC can be considered data in the context of this disclosure. Each slice 115 communicates byte- wide data with host 105 in sixteen-bit bursts. The ten slices 115 thus cumulatively give an access granularity of 8x10x16=1,280 bits. On the memory side of buffers 125 and 120, each package PK communicates byte- wide data in sixteen-bit bursts, as does the host-side interface, but does so at one quarter the host bit rate. Each data buffer 120 combines data to and from four packages PK to match the access granularity and data bandwidth of the host side.

[0025] Analogous to a standard DDR5 DIMM, module 110 includes two independent channels featuring command / address ports DCA_0[0:13]_0 and DCA_l[0:13]_l and respective data ports DQ 0[0:31 / ECC ()[ 0:7 ] and DQ 1 [0:31 ] / ECC I [0:7] for independent channel access. CA buffer 125 issues separate control signals to the left- and right-side slices 115 (signals terminating in "_0" and "_1" respectively) responsive to host-side commands on respective DCA ports.

[0026] Figure 6 depicts a memory system 600 like memory system 100 of Figure 1 but with a memory module 610 with a different arrangement of memory link groups MD00, MD01, MD10, and MD11. As in the prior example, data buffer 120 has four memory-side data ports, identified using memory link groups MD00, MD01, MD10, and MD11. Rather than having each link group connect to a respective package PK, however, in module 610 each four- link group is divided to provide simultaneous access to a pair of packages. For example, memory link group MD00 in module 610 includes links MD00[0:3] to die DI 10 in posterior package PK11 and links MD00[4:7J to die D000 in anterior package PK00. The sequence of write transactions illustrated in timing diagram 200 of Figure 2 applies equally to system 600.

[0027] Figure 7 depicts a memory system 700 similar to memory system 100 of Figure 1, like-identified elements being the same or similar. Memory system 700 differs from system 100 in that system 700 includes a host 705 and module 710 that communicate via a host channel with double the number of data nodes. Module 710 includes ten slices 715, the same number of slices as in the prior example, but a module connector 720 connects to two byte-wide lanes DQ[0:7] and DQ[8:15] in lieu of just one. A data buffer 725 includes a pseudo-channel interface 135, asdetailed previously, but the host-side interface 730 operates at half the bit rate as in the prior example. Data buffer 725 transfers incoming data signals from the host clock domain to a memory clock domain that operates as half the bitrate. Memory modules in other embodiments include data buffers that support different host- and memory-side data widths and bit rates.

[0028] While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, memory data buffers in accordance with other embodiments can support more or fewer memory packages or dies, and clock domains other than 4: 1 can be used. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.

Claims

CLAIMSWhat is claimed is:

1. A memory module comprising: first, second, third, and fourth memory packages; a data buffer having: a host-side data port to receive write data from a host; and first, second, third, and fourth memory- side data ports connected respectively to the first, second, third, and fourth memory packages; and a command buffer having: a host-side command port to receive a sequence of host commands from the host, the sequence of host commands including first, second, third, and fourth host commands; a first memory-side command port connected to the first and third memory packages; and a second memory- side command port connected to the second and fourth memory packages; the command buffer to: derive respective first, second, third, and fourth memory- side commands from the first, second, third, and fourth host commands; issue the first and second memory-side commands simultaneously to the respective first and second memory packages; and issue the third and fourth memory-side command simultaneously to the respective third and fourth memory packages; the command buffer to issue the first and second memory-side commands overlapping and offset in time with respect to the third and fourth memory-side commands.

2. The memory module of claim 1, the command buffer to issue the first and second memory- side commands over a number of clock cycles and the third and fourth memory- side commands over the number of clock cycles after a delay of a fraction of the number of clock cycles.

3. The memory module of claim 2, wherein the fraction is one half.

4. The memory module of claim 1, wherein each packing includes first and second dies connected in parallel to the respective one of the first, second, third, and fourth memory-side data ports.

5. The memory module of claim 4, wherein the dies comprise dynamic, random-access memory.

6. A memory module comprising: a module connector to connect to a host; a first memory package having a first memory die and a second memory die; a second memory package having a third memory die and a fourth memory die; a third memory package having a fifth memory die and a sixth memory die; a fourth memory package having a seventh memory die and an eighth memory die; and a data buffer having: a channel interface coupled to the module connector to receive a burst of write data from the host; and a pseudo-channel interface coupled to the first and second memory packages, the pseudo-channel interface having: a first memory interface connected to the first memory package, the first memory interface to write first and second subsets of the write data into the respective first and second memory dies in parallel; a second memory interface connected to the second memory package, the second memory interface to write third and fourth subsets of the write data into the respective third and fourth memory dies in parallel with the first and second subsets of the write data; a third memory interface connected to the third memory package, the third memory interface to write fifth and sixth subsets of the write data into the respective fifth and sixth memory dies in parallel; and a fourth memory interface connected to the fourth memory package, the fourth memory interface to write seventh and eighth subsets of the write data into the respective seventh and eighth memory dies in parallel with the fifth and sixth subsets of the write data.

7. The memory module of claim 6, wherein the first memory interface communicates the first and second subsets of the write data over a first series of clock cycles and the third memory interface communicates the fifth and sixth subsets of the write data as a second write burst over a second series of the clock cycles overlapping the first series of clock cycles.

8. The memory module of claim 7, wherein the second series of the clock cycles overlaps half of the first series of clock cycles.

9. The memory module of claim 6, the channel interface to receive the burst of write data at a first bit rate, wherein the first memory interface conveys the first and second subsets of the write data at a second bit rate one quarter the first bit rate.

10. The memory module of claim 6, wherein the memory packages comprise dynamic, random-access memory.

11. The memory module of claim 6, further comprising an address buffer connected to the module connector to receive module commands from the host, the address buffer including a first memory- side command bus connected to the first and third memory packages and a second memory- side command bus connected to the second and fourth memory packages.

12. The memory module of claim 11, wherein the module commands include interleaved first and second module commands, the address buffer derives first and second memory-side commands from the first and second module commands, and the address buffer conveys the first and second memory-side commands in parallel to the first memory package and the second memory package.

13. The memory module of claim 12, wherein the address buffer conveys the first and second memory-side commands simultaneously.

14. The memory module of claim 12, wherein the address buffer receives the module commands at a first bit rate and conveys the first and second memory-side commands at a second bit rate lower than the first bit rate.

15. The memory module of claim 14, wherein the second bit rate is one quarter the first bit rate.

16. The memory module of claim 6, wherein the first memory interface connects to the first memory die via a first set of data lines and to the second memory die via a second set of data lines.

17. A memory buffer comprising: a channel interface to receive a burst of write data from a host; and a first memory interface to communicate first and second subsets of the write data in parallel; a second memory interface to communicate third and fourth subsets of the write data in parallel with and timed to the first and second subsets of the write data; a third memory interface to communicate fifth and sixth subsets of the write data in parallel and temporally offset from the first, second, third, and fourth subsets of the write data; and a fourth memory interface to communicate seventh and eighth subsets of the write data in parallel with and timed to the fifth and sixth subsets of the write data.

18. The memory buffer of claim 17, wherein the first memory interface communicates the first and second subsets of the write data over a first series of clock cycles and the third memory interface communicates the fifth and sixth subsets of the write data as a second write burst over a second series of the clock cycles overlapping the first series of clock cycles.

19. The memory buffer of claim 18, wherein the second series of the clock cycles overlaps half of the first series of clock cycles.

20. The memory buffer of claim 17, the channel interface to receive the burst of write data at a first bit rate, wherein the first memory interface conveys the first and second subsets of the write data at a second bit rate one quarter the first bit rate.

Images