Power amplifier circuit, and transmission circuit and communication device equipped with same

Abstract

This power amplifier circuit includes an input terminal, amplifiers (141, 142A-142C), phase shifters (143A, 143B, 155), a conversion circuit, and an output terminal. The conversion circuit converts a pair of balanced lines into an unbalanced line. The output terminal is connected to the unbalanced line. The conversion circuit includes balanced terminals (TB1, TB2) respectively connected to the pair of balanced lines. The phase shifter (143A) is connected between the output of the amplifier (141) and the output of the amplifier (142A). The phase shifter (143B) is connected between the output of the amplifier (142B) and the output of the amplifier (142C). The phase shifter (155) is connected between the output of the amplifier (142A) and the balanced terminal (TB1). The output of the amplifier (142B) is connected to the balanced terminal (TB2). The driving state of the amplifiers (142A-142C) is switched according to the power level of an input signal.

Description

Power amplifier circuit, and transmission circuit and communication device incorporating the same

[0001] The present disclosure relates to a power amplifier circuit, and a transmission circuit and a communication device incorporating the same, and more particularly to a technique for improving efficiency in a power amplifier circuit.

[0002] Japanese Patent Laid-Open Publication No. 2018-137566 (Patent Document 1) discloses an amplifier circuit including a first differential amplifier (carrier amplifier) ​​and a second differential amplifier (peak amplifier) ​​that amplify signals distributed from an input signal, and transformers (first transformer, second transformer) individually provided for each differential amplifier. The first differential amplifier operates in a range where the power level of the input signal is equal to or higher than a first level, and the second differential amplifier operates in a range where the power level of the input signal is equal to or higher than a second level that is higher than the first level. The first transformer and the second transformer receive and combine the signals output from the first differential amplifier and the second differential amplifier, respectively, and output the combined output signal to a load.

[0003] Japanese Patent Application Laid-Open No. 2018-137566

[0004] By applying digital envelope tracking (ET) to the power supply voltage of a power amplifier circuit configured as described in Patent Document 1, it is possible to improve the efficiency in the back-off region from the high output region where both the carrier amplifier and peak amplifier are in an operating state to the low output state where only the carrier amplifier is in an operating state.

[0005] In the configuration of Patent Document 1 and a typical Doherty amplifier, a back-off amount of 6 dB can generally be achieved. However, the back-off amount required for a power amplifier circuit can vary depending on, for example, the modulation method, the set voltage of the digital ET, and / or the target frequency bandwidth. Therefore, depending on the specifications required for the device to which the power amplifier circuit is applied, a back-off amount greater than 6 dB may be required.

[0006] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a power amplifier circuit that can ensure a back-off amount of 6 dB or more.

[0007] A power amplifier circuit according to the present disclosure includes an input terminal, first to fourth amplifiers, first to third phase shifters, a conversion circuit, and an output terminal. Each of the first to fourth amplifiers amplifies an input signal, which is a high-frequency signal received at the input terminal. The conversion circuit converts a pair of balanced lines to an unbalanced line. The output terminal is connected to the unbalanced lines. The conversion circuit includes a first balanced terminal and a second balanced terminal connected to the pair of balanced lines, respectively. The first phase shifter is connected between the output of the first amplifier and the output of the second amplifier. The second phase shifter is connected between the output of the third amplifier and the output of the fourth amplifier. The third phase shifter is connected between the output of the second amplifier and the first balanced terminal. The output of the third amplifier is connected to the second balanced terminal. The drive states of the second amplifier, the third amplifier, and the fourth amplifier are switched depending on the power level of the input signal.

[0008] The power amplifier circuit according to the present disclosure includes a Doherty circuit that operates a first amplifier as a carrier amplifier and second to fourth amplifiers as peak amplifiers, and switches the drive states of the second to fourth amplifiers according to the power level of the input signal. The drive states of the second to fourth amplifiers allow the impedance of the amplifiers in operation to be changed, allowing the back-off amount to be set in multiple stages. This allows the power amplifier circuit to ensure a back-off amount of 6 dB or more.

[0009] FIG. 1 is a schematic configuration diagram of a communication device to which a power amplifier circuit according to a first embodiment is applied. FIG. 2 is a diagram showing detailed configurations of the transmission circuit and power supply circuit of FIG. 1. FIG. 3 is a diagram for explaining an envelope tracking mode in a power supply circuit. FIG. 4 is a diagram for explaining the operation of a Doherty amplifier. FIG. 5 is a diagram for explaining impedance in a power amplifier circuit in a first operating state. FIG. 6 is a diagram for explaining impedance in a power amplifier circuit in a second operating state. FIG. 7 is a diagram for explaining impedance in a power amplifier circuit in a third operating state. FIG. 8 is a diagram for explaining the relationship between output power and efficiency of the power amplifier circuit of FIG. 1. FIG. 9 is a partial circuit diagram of a power amplifier circuit according to a second embodiment. FIG. 10 is a partial circuit diagram of a power amplifier circuit according to a third embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0011] 1 is a schematic configuration diagram of a communication device 1 to which a power amplifier circuit 100 according to embodiment 1 is applied. The communication device 1 is, for example, a mobile terminal such as a mobile phone, a smartphone, or a tablet, or a personal computer with a communication function.

[0012] 1 , the communication device 1 includes an antenna ANT, a transmission circuit 10, a baseband integrated circuit (BBIC) 20 constituting a baseband signal processing circuit, a radio frequency integrated circuit (RFIC) 30, and a power supply circuit 40. The transmission circuit 10 includes input terminals T1, T3, and T4, an output terminal T2, a power amplifier circuit 100, and a bias control circuit 105. In general, the communication device 1 upconverts an intermediate frequency (IF) signal transmitted from the BBIC 20 to a high frequency (radio frequency: RF) signal by the RFIC 30, amplifies the high frequency signal by the power amplifier circuit 100, and emits the signal from the antenna ANT.

[0013] The RFIC 30 is an example of a signal processing circuit that processes a high-frequency signal. The RFIC 30 up-converts the intermediate frequency signal transmitted from the BBIC 20 into a high-frequency signal and outputs the generated high-frequency signal to the transmission circuit 10 via the input terminal T1.

[0014] Furthermore, the RFIC 30 generates a control signal CON for controlling the power amplifier circuit 100 based on the information transmitted from the BBIC 20. The generated control signal CON is transmitted to the bias control circuit 105 via the input terminal T3.

[0015] The bias control circuit 105 generates a bias signal BS for controlling the magnitude and supply timing of the bias current of the amplifier included in the power amplifier circuit 100 based on the control signal CON, and outputs the bias signal BS to the power amplifier circuit 100 .

[0016] The power supply circuit 40 generates a power supply voltage Vcc to be supplied to the power amplifier circuit 100 based on information transmitted from the BBIC 20. The generated power supply voltage Vcc is supplied to the power amplifier circuit 100 via an input terminal T4.

[0017] The power amplifier circuit 100 amplifies an input signal Pin received from the RFIC 30 via an input terminal T1, and generates an output signal Pout.

[0018] The antenna ANT is connected to the output terminal T2 of the transmission circuit 10. The antenna ANT emits an output signal Pout, which is a high-frequency signal output from the transmission circuit 10, as a radio wave.

[0019] (Detailed Configuration of Power Conversion Circuit) Next, the detailed configuration of the power amplifier circuit 100 and the power supply circuit 40 in the transmission circuit 10 will be described with reference to FIG.

[0020] The power supply circuit 40 is an example of a so-called digital tracker, and can supply power supply voltages Vcc of a plurality of different voltage levels to the power amplifier circuit 100. The power supply circuit 40 includes a multilevel power converter (MPC) 410, a power supply selection circuit 420, and a digital envelope tracker (digital ET) 430.

[0021] The MPC 410 includes a plurality of DC / DC converters, which are not shown in Fig. 2. The MPC 410 converts the battery voltage VB supplied from an external battery into a plurality of different voltage levels and supplies the voltages to the power supply selection circuit 420.

[0022] The digital ET 430 receives the I and Q waveform signals of the transmit signal from the BBIC 20 and tracks the envelope of the transmit signal in the digital ET mode. The digital ET 430 generates a selection signal SEL corresponding to the voltage level of the envelope of the transmit signal and outputs it to the power supply selection circuit 420.

[0023] The power supply selection circuit 420 selects a voltage corresponding to the selection signal SEL from the plurality of voltage levels supplied from the MPC 410 and supplies it to the power amplifier circuit 100 as the power supply voltage Vcc.

[0024] The power amplifier circuit 100 includes an input terminal T10, an output terminal T20, a divider 110, a power amplifier stage 140, transmission line transformers (TLTs) 150A and 150B, a phase shifter 155, and a conversion circuit 160. The power amplifier stage 140 includes a carrier amplifier 141 and peak amplifiers 142A, 142B, and 142C.

[0025] The power amplifier circuit 100 receives an input signal Pin from the RFIC 30 at an input terminal T10, amplifies the input signal Pin, and outputs an output signal Pout from an output terminal T20 to the antenna ANT.

[0026] The bias control circuit 105 includes a phase shift circuit (PS) 120, preamplifiers 131, 132, and 133 for driving the amplifiers of the power amplifier stage 140, transformers TR1, TR2, and TR3, and a phase shifter .

[0027] The phase-shift circuit 120 converts the phase of the input signal Pin received at the input terminal T10 and distributes the converted signal to three paths. More specifically, the phase-shift circuit 120 distributes the input signal Pin, whose phase is advanced by 180° relative to the reference, to a first path connected to the preamplifier 131. The phase-shift circuit 120 distributes the input signal Pin, whose phase is advanced by 90° relative to the reference, to a second path connected to the preamplifier 132. The phase-shift circuit 120 distributes the input signal Pin, whose phase is advanced by 270° relative to the reference, to a third path connected to the preamplifier 133. The preamplifiers 131, 132, and 133 amplify the distributed input signal Pin by a predetermined gain and transmit the amplified signal to the transformers TR1, TR2, and TR3, respectively.

[0028] The preamplifier 131 is an amplifier for driving the carrier amplifier 141. The preamplifier 132 is an amplifier for driving the peak amplifiers 142A and 142B. The preamplifier 133 is an amplifier for driving the peak amplifier 142C.

[0029] One end of the primary winding of the transformer TR1 is connected to the output terminal of the preamplifier 131. The other end of the primary winding of the transformer TR1 is supplied with the power supply voltage Vcc. A capacitor C1 is connected between the supply terminal of the transformer TR1 for the power supply voltage Vcc and the ground potential GND. The capacitor C1 is a so-called bypass capacitor, and suppresses voltage fluctuations in the power supply voltage Vcc.

[0030] One end of the secondary winding of the transformer TR1 is connected to the carrier amplifier 141. The other end of the secondary winding of the transformer TR1 is connected to the ground potential GND. A signal in phase with the signal output from the preamplifier 131 is supplied to the carrier amplifier 141.

[0031] One end of the primary winding of the transformer TR2 is connected to the output terminal of the preamplifier 132. The other end of the primary winding of the transformer TR2 is supplied with the power supply voltage Vcc. A capacitor C2, which is a bypass capacitor, is connected between the supply terminal of the transformer TR2 for the power supply voltage Vcc and the ground potential GND.

[0032] One end of the secondary winding of transformer TR2 is connected to peak amplifier 142A. The other end of the secondary winding of transformer TR2 is connected to peak amplifier 142B via phase shifter 134. Phase shifter 134 is, for example, a quarter-wave line, and delays the phase of the signal transmitted to the other end of the secondary winding of transformer TR2 by 90°. With this configuration, a signal in phase with the signal output from preamplifier 132 is supplied to peak amplifier 142B, and a signal whose phase is 90° ahead of the signal output from preamplifier 132 is supplied to peak amplifier 142C.

[0033] One end of the primary winding of the transformer TR3 is connected to the output terminal of the preamplifier 133. The other end of the primary winding of the transformer TR3 is supplied with the power supply voltage Vcc. In the circuit of FIG. 2, the other end of the primary winding of the transformer TR3 is connected to the other end of the primary winding of the transformer TR2.

[0034] One end of the secondary winding of the transformer TR3 is connected to the peak amplifier 142C. The other end of the secondary winding of the transformer TR3 is connected to the ground potential GND. A signal in phase with the signal output from the preamplifier 133 is supplied to the peak amplifier 142C.

[0035] By the distributor 110 configured as described above, a signal that is 90° ahead in phase with respect to the signal supplied to the peak amplifier 142A is supplied to the carrier amplifier 141 and the peak amplifier 142B, and a signal that is 180° ahead in phase with respect to the signal supplied to the peak amplifier 142A is supplied to the peak amplifier 142C.

[0036] The power amplifier stage 140 includes phase shifters 143A and 143B in addition to the carrier amplifier 141 and peak amplifiers 142A, 142B, and 142C.

[0037] The output terminal of carrier amplifier 141 is connected to the output terminal of peak amplifier 142A via phase shifter 143A. The output terminal of peak amplifier 142C is connected to the output terminal of peak amplifier 142B via phase shifter 143B. Carrier amplifier 141 and peak amplifiers 142A to 143C each amplify the input high-frequency signal with a predetermined gain and output the amplified signal.

[0038] Phase shifters 143A and 143B are, for example, quarter-wave lines, and can delay the phases of the signals amplified by carrier amplifier 141 and peak amplifier 142C by 90°. As a result, at connection node N1 between peak amplifier 142A and phase shifter 143A, the signal output from carrier amplifier 141 and the signal output from peak amplifier 142A are combined in phase. Similarly, at connection node N2 between peak amplifier 142B and phase shifter 143B, the signal output from peak amplifier 142B and the signal output from peak amplifier 142C are combined in phase.

[0039] Furthermore, the phase shifters 143A and 143B can rotate the load impedance by 180° on the Smith chart, that is, the phase shifters 143A and 143B also function as impedance inverters.

[0040] In this specification, the term "connection node" does not refer to a specific point on a path, and different positions on the circuit are also treated as the "connection node" as long as they are electrically identical (at the same potential). For example, in Figure 2, if the line connecting the output end of peak amplifier 142A and phase shifter 143A is located at a different position from the point indicated as "N1" on the circuit, it corresponds to "connection node N1."

[0041] The power amplifier stage 140 functions as a Doherty amplifier as a whole. In the Doherty amplifier, the carrier amplifier 141 is always in operation, and the peak amplifiers 142A, 142B, and 142C are sequentially operated as the voltage level of the input signal increases. A class A or class AB amplifier, which has relatively little distortion, is used as the carrier amplifier 141. On the other hand, class C amplifiers are used as the peak amplifiers 142A, 142B, and 142C. By using a class C amplifier, the peak amplifiers 142A, 142B, and 142C stop amplifying when the voltage level of the input signal falls below a predetermined level.

[0042] A TLT 150A is connected to a connection node N1 between the phase shifter 143A and the peak amplifier 142A, i.e., the output terminal of the peak amplifier 142A. A TLT 150B is connected to a connection node N2 between the phase shifter 143B and the peak amplifier 142B, i.e., the output terminal of the peak amplifier 142B.

[0043] Each of the TLTs 150A and 150B is an impedance converter made up of three parallel lines having line lengths of 1 / 8 wavelength to 1 / 4 wavelength.

[0044] The TLT 150A includes a first line 151A, a second line 152A, and a third line 153A. One end of the first line 151A is connected to a connection node N1 of the power amplifier stage 140. The other end of the first line 151A is connected to one end of the second line 152A.

[0045] The other end of the second line 152A is connected to the balanced terminal TB1 (first balanced terminal) of the conversion circuit 160 via a phase shifter 155 and a capacitor C4. The capacitor C4 removes the DC component from the signal that has passed through the TLT 150A. The phase shifter 155 is, for example, a quarter-wave line, and delays the phase of the high-frequency signal that has passed through the TLT 150A by 90°.

[0046] One end of the third line 153A is supplied with the power supply voltage Vcc, and the other end of the third line 153A is connected to the connection node N1. The power supply voltage Vcc is used as a drive power supply for the carrier amplifier 141 and the peak amplifier 142A via the third line 153A. A capacitor C3 is connected between the supply terminal of the power supply voltage Vcc and the ground potential GND. The capacitor C3 is a bypass capacitor that suppresses voltage fluctuations of the power supply voltage Vcc.

[0047] The first line 151A, the second line 152A, and the third line 153A are arranged in parallel so that currents flow in the same direction. The third line 153A is arranged so as to be coupled to the first line 151A and the second line 152A. By arranging the three lines in this way, the TLT 150A functions as an impedance converter.

[0048] Similarly, the TLT 150B includes a first line 151B, a second line 152B, and a third line 153B. One end of the first line 151B is connected to a connection node N2 of the power amplifier stage 140. The other end of the first line 151B is connected to one end of the second line 152B. The other end of the second line 152B is connected to a balanced terminal TB2 (second balanced terminal) of the conversion circuit 160 via a capacitor C5. The capacitor C5 removes DC components from the signal that has passed through the TLT 150B.

[0049] One end of the third line 153B is supplied with the power supply voltage Vcc, and the other end of the third line 153B is connected to the connection node N2. The power supply voltage Vcc is supplied via the third line 153B as a drive power supply for the peak amplifiers 142B and 142C. In the example of the power amplifier circuit 100 in FIG. 2, the third line 153A of the TLT 150A and the third line 153B of the TLT 150B are connected to a common power supply terminal.

[0050] The first line 151B, the second line 152B, and the third line 153B are arranged in parallel so that currents flow in the same direction. The third line 153B is arranged so as to be coupled to the first line 151B and the second line 152B. By arranging the three lines in this way, the TLT 150B functions as an impedance converter.

[0051] The conversion circuit 160 is a circuit for converting a balanced line into an unbalanced line. The conversion circuit 160 includes a magnetic coupled transformer (MCT) TR4. One end of a primary winding of the magnetic coupling transformer TR4 is connected to a balanced terminal TB1, and the other end is connected to a balanced terminal TB2. One end of a secondary winding of the magnetic coupling transformer TR4 is connected to the antenna ANT via an output terminal T20, and the other end of the secondary winding is connected to the ground potential GND.

[0052] As described above, the phase of the signal output from peak amplifier 142B leads the phase of the signal output from peak amplifier 142A by 90°. Therefore, the phase of the signal that has passed through TLT 150B also leads the phase of the signal that has passed through TLT 150A by 90°. The phase of the signal that has passed through TLT 150A is delayed by 90° by phase shifter 155, and as a result, the signal input to balanced terminal TB1 is in opposite phase to the signal input to balanced terminal TB2. Therefore, the output signal Pout output from output terminal T20 by magnetic field coupling transformer TR4 is a signal obtained by combining the signals from TLT 150A and TLT 150B in phase.

[0053] In the power amplifier circuit 100 of the first embodiment, a Doherty amplifier is configured by a pair of the carrier amplifier 141 and the peak amplifier 142A, and a Doherty amplifier is also configured by a pair of the peak amplifier 142B and the peak amplifier 142C. Furthermore, in the above two Doherty amplifiers, a Doherty amplifier is configured by the carrier amplifier 141 when the peak amplifier 142A is in a non-driven state, the peak amplifier 142C when the peak amplifier 142B is in a non-driven state, and the phase shifter 155. In other words, the power amplifier circuit 100 can also be considered as a two-stage Doherty amplifier.

[0054] Therefore, in the power amplifier circuit 100 of the first embodiment, by appropriately switching the drive states of the peak amplifiers 142A to 143C in accordance with the power level of the input signal Pin, it is possible to make the power amplifier circuit 100 function as a two-stage Doherty amplifier, thereby enabling highly efficient signal amplification.

[0055] (Response to Increased Backoff Amount) In wireless communication devices, new communication standards such as 6G are being developed to achieve high-capacity, high-speed communication. Such new communication standards may employ signals in even higher frequency bands than conventional standards. Generally, signals in higher frequency bands tend to be more susceptible to attenuation than signals in lower frequency bands. Therefore, there is a need for even higher efficiency in power amplifier circuits. Furthermore, there is also a trend toward wider frequency bandwidths being used. To meet these demands, a different control method for power amplifier circuits than conventional methods is required.

[0056] (1) Regarding Tracking Modes Several tracking modes are known for adjusting the power supply voltage level in a power amplifier for a signal to be transmitted. Generally, tracking modes are broadly classified into envelope tracking mode and average power tracking (APT) mode. Furthermore, envelope tracking mode is classified into "digital envelope tracking mode (digital ET mode)" and "analog envelope tracking mode (analog ET mode)." Envelope tracking mode is a mode in which the power supply voltage level is set based on an envelope signal that indicates the envelope of the input signal. On the other hand, APT mode is a mode in which the power supply voltage level is set based on the average output power over a predetermined period, rather than the envelope signal.

[0057] FIG. 3 is a diagram for explaining an overview of each tracking mode. In FIG. 3, the upper row (A) shows a graph illustrating an example of the transition of the power supply voltage in analog ET mode. The middle row (B) shows a graph illustrating an example of the transition of the power supply voltage in APT mode, and the lower row (C) shows a graph illustrating an example of the transition of the power supply voltage in digital ET mode. In each graph, the horizontal axis represents time and the vertical axis represents voltage. The thick solid lines Vcc1 to Vcc3 represent the power supply voltage in each mode, and the thin solid lines WV1 to WV3 represent the output signal Pout, which is a modulated high-frequency signal.

[0058] In the analog ET mode (top row (A)), a power supply voltage that changes continuously is set to follow the envelope of the input signal Pin. The power supply voltage waveform in the analog ET mode is an analog waveform, not a digital waveform.

[0059] The analog ET mode provides the most efficient tracking because it always supplies a power supply voltage that corresponds to the amplitude fluctuation of the input signal Pin. However, because the power supply voltage must be changed continuously, if the amplitude fluctuation of the input signal is large or if the modulation bandwidth is wide, the power supply voltage may not be able to track the envelope of the modulated high-frequency signal.

[0060] Next, in the APT mode shown in the middle (B), a power supply voltage of a different voltage level is set for each predetermined frame unit. The power supply voltage has a digital waveform and forms a square wave. Here, a frame refers to the unit that constitutes the modulated high-frequency signal. In one example, the frame length is 10 ms.

[0061] Specifically, in APT mode, the voltage level of the power supply voltage is determined based on the average output power, not the envelope signal. In this case, it is not necessary to quickly change the power supply voltage in accordance with the input signal Pin. However, since a voltage corresponding to the peak voltage of the input signal Pin is set over each frame, there is room for improvement in terms of power saving and efficiency.

[0062] In the digital ET mode (lower row (C)), a power supply voltage of a plurality of discrete different voltage levels is set within one frame. The power supply voltage has a digital waveform and forms a rectangular wave. Specifically, in the digital ET mode, a voltage level corresponding to the voltage of the input signal Pin in a target section within the frame is selected from a plurality of different voltage levels based on an envelope signal. At this time, the voltage level is selected so as to track the envelope of the carrier wave modulated based on the transmission information. More specifically, a voltage level corresponding to the envelope value of each symbol is selected by referring to the range of envelope values ​​associated with each of the plurality of different voltage levels.

[0063] In order to make the power supply voltage follow the changes in the input signal with a high frequency and a wide modulation bandwidth, the analog ET mode is insufficient to keep up with the changes, and it is necessary to adopt the digital ET mode.

[0064] (2) Doherty Amplifier A Doherty amplifier is known as a configuration that improves the amplification efficiency of a power amplifier circuit. A Doherty amplifier is generally configured such that a carrier amplifier and a peak amplifier are connected in parallel between an input terminal and an output terminal, and a phase shifter functioning as an impedance inverter is disposed between the carrier amplifier and a combining node. When the output power is small, only the carrier amplifier operates, and when the output power exceeds a predetermined value, both the carrier amplifier and the peak amplifier operate.

[0065] 4 is a diagram for schematically explaining the operation of a Doherty amplifier. In FIG. 4, the upper part shows the circuit state and load impedance when the peak amplifier 220 is operating (right diagram) and when it is not operating (left diagram), and the lower part shows the relationship between the output power and efficiency of the Doherty amplifier in comparison with that of a class AB amplifier. In the lower part, the solid line LN10 shows the efficiency in the case of the Doherty amplifier, and the dashed line LN11 shows the efficiency in the case of a class AB amplifier.

[0066] When both the carrier amplifier 210 and the peak amplifier 220 are operating (top right diagram), the load impedance seen from each of the carrier amplifier 210 and the peak amplifier 220 is RL, and the load impedance at the combining point (output terminal) is RL / 2. On the other hand, when the peak amplifier 220 is off (top left diagram), the load impedance seen from the carrier amplifier 210 becomes 2RL due to the phase shifter 230 functioning as an impedance inverter.

[0067] Generally, amplifiers have a tendency for their efficiency to increase as the load impedance increases. Therefore, as shown in the graph at the bottom, by using a Doherty amplifier, the efficiency of the carrier amplifier 210 can be improved by increasing the load impedance in region AR1 where the peak amplifier 220 is off, compared to a class AB amplifier that can output the same peak power. Furthermore, in region AR2 where the peak amplifier 220 is on, the efficiency can be improved by the parallel operation of the carrier amplifier 210 and the peak amplifier 220.

[0068] A typical Doherty amplifier configuration can achieve a back-off of approximately 6 dB. However, the back-off required for a power amplifier circuit can vary depending on, for example, the modulation scheme, the digital ET setting voltage, and / or the target bandwidth. Therefore, depending on the specifications required for the equipment to which the power amplifier circuit is applied, a back-off greater than 6 dB may be required.

[0069] Therefore, in the power amplifier circuit of the first embodiment, a Doherty amplifier using one carrier amplifier and three peak amplifiers is used, and the number of peak amplifiers used is changed according to the power level of the input signal. More specifically, as will be described in detail below, a two-stage Doherty amplifier is configured by switching the peak amplifier according to the power level of the input signal, thereby achieving a back-off amount of 12 dB.

[0070] (Operation of Power Amplifier Circuit) Next, the operation of the power amplifier circuit 100 will be described using FIGS. 5 to 8. FIGS. 5 to 7 are diagrams for explaining the impedance within the circuit in different operating states of the power amplifier circuit 100 of the first embodiment. The operating state changes depending on the power supply voltage Vcc. In the example of the first embodiment, the power supply voltage Vcc is switched between three levels: 5.2 V, 2.0 V, and 0.8 V, by the digital ET. A first operating state is when Vcc=5.2 V, a second operating state is when Vcc=2.0 V, and a third operating state is when Vcc=0.8 V.

[0071] The first operating state (FIG. 5) corresponds to a state where the power level of the input signal Pin is greater than the first power value. In the first operating state, since a large amount of power is required, all of the peak amplifiers 142A, 142B, and 142C are driven, and amplification is performed using four amplifiers in total, including the carrier amplifier 141.

[0072] The second operating state (FIG. 6) corresponds to a state in which the power level of the input signal Pin is a second power value that is smaller than the first power value. In the second operating state, the peak amplifiers 142A and 142B are in a non-operating state, and the peak amplifier 142C is in an operating state. That is, amplification is performed by the carrier amplifier 141 and the peak amplifier 142C.

[0073] The second operating state (FIG. 6) corresponds to a state where the power level of the input signal P in is a third power value that is even lower than the second power value. In the second operating state, the peak amplifiers 142A, 142B, and 142C are in a non-driven state, and amplification is performed only by the carrier amplifier 141.

[0074] FIG. 5 is a diagram for explaining the impedance within the power amplifier circuit 100 in the first operating state.

[0075] In the following description, the load impedance of the antenna ANT is R Ｌ The impedance conversion ratio of the TLTs 150A and 150B is 1:n, and the impedance conversion ratio of the conversion circuit 160 is 1:m. The voltages of the signals supplied to the balanced terminals TB1 and TB2 of the conversion circuit 160 are V0 and -V0, respectively, the voltage of the primary winding is V1, and the voltage of the secondary winding is V2. The current flowing through the primary winding of the conversion circuit 160 is i1, and the current flowing through the secondary winding is i2.

[0076] At this time, V2 = mV1 = 2 mV0, and i2 = i1 / m, so the load impedance R Ｌ can be expressed as the following equation (1) using V0 and i1.

[0077] R Ｌ =V2 / i2=2mV0 / (i1 / m)=2m ２V0 / i1 Equation (1) The impedance when looking at the load side from the input terminal of the conversion circuit 160 is expressed as V0 / i1, so by rearranging equation (1), R Ｌ / 2m ２ This becomes:

[0078] The impedance of the phase shifter 155 is the impedance (R Ｌ / 2m ２ ), the impedance at the output terminals of the TLTs 150A and 150B is R Ｌ / 2m ２ Therefore, the impedance when looking at the load side from the input terminals (i.e., connection nodes N1 and N2) of the TLTs 150A and 150B is (R Ｌ / 2m ２ ) × (1 / n).

[0079] At the connection node N1, the output signal from the carrier amplifier 141 and the output signal from the peak amplifier 142A are combined, so the impedance Zc when looking at the load side from the output end of the carrier amplifier 141 and the impedance Zpa when looking at the load side from the output end of the peak amplifier 142A are (R Ｌ / m ２ ) × (1 / n).

[0080] Similarly, the impedance Zpb when looking at the load side from the output terminal of the peak amplifier 142B, and the impedance Zpc when looking at the load side from the output terminal of the peak amplifier 142C are expressed as follows: (R Ｌ / m ２ ) × (1 / n). The impedance of the phase shifters 143A and 143B is (R Ｌ / m ２ ) × (1 / n).

[0081] 6 is a diagram illustrating the impedance within the power amplifier circuit 100 in the second operating state. In the second operating state, the peak amplifiers 142A and 142B are in a non-driven state. That is, the impedance Zpa when looking toward the load from the output terminal of the peak amplifier 142A and the impedance Zpb when looking toward the load from the output terminal of the peak amplifier 142B are in an open state.

[0082] Here, the impedance of the phase shifters 143A and 143B is (R Ｌ / m ２ ) × (1 / n), the impedance Zc when the load side is seen from the output terminal of the carrier amplifier 141 and the impedance Zpc when the load side is seen from the output terminal of the peak amplifier 142C are set to (2R Ｌ / m ２ )×(1 / n). That is, in the second operating state, the impedance when looking at the load side from the output end of the amplifier in the driving state is twice the impedance in the first operating state.

[0083] In the second operating state, the number of amplifiers is halved and the load impedance is doubled in each of the Doherty amplifiers consisting of carrier amplifier 141 and peak amplifier 142A, and the Doherty amplifiers consisting of peak amplifier 142B and peak amplifier 142C, so that a back-off amount of 6 dB is obtained in both the first operating state and the second operating state.

[0084] 7 is a diagram illustrating the impedance within the power amplifier circuit 100 in the third operating state. In the third operating state, the peak amplifiers 142A, 142B, and 142C are in a non-driven state. That is, the impedance Zpa when looking at the load side from the output terminal of the peak amplifier 142A, the impedance Zpb when looking at the load side from the output terminal of the peak amplifier 142B, and the impedance Zpc when looking at the load side from the output terminal of the peak amplifier 142C are in an open state.

[0085] At this time, the connection node N2 is short-circuited by the phase shifter 143B. As a result, the impedance of the balanced terminal TB2 of the conversion circuit 160 is also short-circuited, and the impedance when looking at the load side from the balanced terminal TB1 is R Ｌ / m ２ This becomes:

[0086] The impedance of the phase shifter 155 is R Ｌ / 2m ２ Therefore, the load impedance at the output terminal of the TLT150A is R Ｌ / 4m ２ The load impedance at the connection node N1 is (R Ｌ / 4m ２ ) / (1 / n). Therefore, the impedance Zc when looking at the load side from the output terminal of the carrier amplifier 141 is (4R Ｌ / m ２ ) / (1 / n). That is, in the third operating state, the impedance Zc when looking from the output end of the carrier amplifier 141 to the load side is four times that of the first operating state and twice that of the second operating state.

[0087] In the third operating state, in the Doherty circuit consisting of carrier amplifier 141, peak amplifier 142C, and phase shifter 155, the number of amplifiers is halved and the load impedance is doubled compared to the second operating state, so that a back-off of 6 dB can be obtained in both the second and third operating states.

[0088] In this way, in the power amplifier circuit 100, a back-off amount of 6 dB can be obtained by the Doherty amplifier configured by the carrier amplifier 141 and the peak amplifier 142A and the Doherty amplifier configured by the peak amplifier 142B and the peak amplifier 142C, and a further back-off amount of 6 dB can be obtained by the Doherty amplifier configured by the carrier amplifier 141 and the peak amplifier 142C. Therefore, the power amplifier circuit 100 as a whole can ensure a back-off amount of 12 dB.

[0089] 8 is a diagram for explaining the relationship between the output power and efficiency of the power amplifier circuit 100. In Fig. 8, the horizontal axis represents the power level of the output signal Pout output from the output terminal T20 to the antenna ANT, and the vertical axis represents the efficiency of the power amplifier circuit 100.

[0090] In Fig. 8, dashed line LN32 represents a graph showing the case where four class AB amplifiers corresponding to the carrier amplifier 141 and the peak amplifiers 142A, 142B, and 142C are driven in APT mode. Dashed-dotted line LN33 represents a graph showing the case where the carrier amplifier 141 and the peak amplifier 142C are driven and the peak amplifiers 142A and 142B are dedriven (i.e., the second operating state) and the first operating state are switched to each other. Solid line LN34 represents a graph showing the case where only the carrier amplifier 141 is driven and the peak amplifiers 142A, 142B, and 142C are dedriven (i.e., the third operating state) and the first operating state are switched to each other. Dashed line LN31 represents a graph showing the case where the first, second, and third operating states are switched to each other according to the power level of the output signal Pout, as in the first embodiment.

[0091] The region until the amplifier reaches saturation in the third operating state is designated as RG3, the region until the amplifier reaches saturation in the second operating state is designated as RG2, and the region until the amplifier reaches saturation in the first operating state is designated as RG1. The power supply voltage Vcc in the first operating state is set to 5.2 V, the power supply voltage Vcc in the second operating state is set to 2.0 V, and the power supply voltage Vcc in the third operating state is set to 0.8 V.

[0092] When the power level of the input signal Pin decreases from the first power value to the second power value, as described in FIG. 6 , the impedance of the carrier amplifier 141 and the peak amplifier 142C in the driven state increases due to the Doherty amplifier consisting of the carrier amplifier 141 and the peak amplifier 142A, and the Doherty amplifier consisting of the peak amplifiers 142B and 142C. As a result, the efficiency is higher than when the peak amplifiers 142A and 142B are driven.

[0093] Furthermore, when the power level of the input signal Pin drops from the second power value to the third power value, the Doherty amplifier configured with the carrier amplifier 141 and the peak amplifier 142C further increases the carrier amplifier 141 in the driven state, as described in Fig. 7. This results in higher efficiency than when the carrier amplifier 141 and the peak amplifier 142C are driven.

[0094] Therefore, when the power level of the input signal Pin changes from a low state to a high state, the power supply voltage Vcc is changed in accordance with the power level, and the number of peak amplifiers used is changed, thereby increasing the efficiency of the power amplifier circuit 100 in the low output range. Also, by gradually switching the peak amplifiers to a non-driven state, the power difference between the output power when the peak amplifiers 142A, 142B, and 142C are in a driven state (first operating state) and the output power when the peak amplifiers 142A, 142B, and 142C are in a non-driven state (third operating state), i.e., the back-off amount, can be made greater than 6 dB.

[0095] The "carrier amplifier 141," "peak amplifier 142A," "peak amplifier 142B," and "peak amplifier 142C" in the first embodiment correspond to the "first amplifier" to the "fourth amplifier" in the present disclosure, respectively. The "phase shifter 143A," "phase shifter 143B," and "phase shifter 155" in the first embodiment correspond to the "first phase shifter" to the "third phase shifter" in the present disclosure, respectively. The "TLT 150A" and "TLT 150B" in the first embodiment correspond to the "first transmission line transformer" and the "second transmission line transformer" in the present disclosure, respectively. The "first line 151A" to the "third line 153A" in the TLT 150A in the first embodiment correspond to the "fourth line" to the "sixth line" in the present disclosure, respectively. The "first line 151B" to the "third line 153B" in the TLT 150B of the first embodiment correspond to the "seventh line" to the "ninth line" in the present disclosure, respectively. The "bias control circuit 105" in the present disclosure corresponds to the "control circuit" in the present disclosure.

[0096] Second Embodiment In a second embodiment, another configuration of the conversion circuit will be described.

[0097] Fig. 9 is a partial circuit diagram of a transmission circuit 10A according to embodiment 2. Fig. 6 shows the circuits subsequent to the power amplifier stage 140 of a power amplifier circuit 100A in the transmission circuit 10A. The power amplifier circuit 100A has a configuration in which the conversion circuit 160 in the power amplifier circuit 100 of Fig. 1 is replaced with a conversion circuit 160A.

[0098] The conversion circuit 160A is a so-called Marchand balun, and is composed of lines 161 and 162 each having a length of λ / 4 and a line 163 having a length of λ / 2.

[0099] One end of line 161 is connected to the output terminal of TLT 150A via capacitor C4 and phase shifter 155, and the other end of line 161 is connected to ground potential GND. Similarly, one end of line 162 is connected to the output terminal of TLT 150B via capacitor C5, and the other end of line 162 is connected to ground potential GND.

[0100] The line 163 includes partial lines 1631 and 1632, one end of which is connected to each other. The other end of the partial line 1631 is connected to the antenna ANT via the output terminal T20. The other end of the partial line 1632 is an open end. The partial line 1631 is coupled to the line 161, and the partial line 1632 is coupled to the line 162.

[0101] The lines 161 and 162 are arranged so that the direction of the current flowing through the line 163 is opposite to that of the current flowing through the line 163. As a result, the high-frequency signals from the TLTs 150A and 150B, which have a phase difference of 180°, are combined and output from the line 163.

[0102] When a Marchand balun is used as a circuit for converting a balanced line to an unbalanced line, the area on the substrate for forming the line becomes somewhat larger, but the insertion loss can be reduced compared to when an MCT such as that of the power amplifier circuit 100 is used. Therefore, the circuit efficiency of the power amplifier circuit can be further improved.

[0103] The "line 161" to "line 163" in the second embodiment correspond to the "first line" to "third line" in the present disclosure, respectively.

[0104] Third Embodiment In a third embodiment, a high-frequency termination circuit for removing harmonics of a high-frequency signal will be described.

[0105] Fig. 10 is a partial circuit diagram of a transmission circuit 10B according to embodiment 3. In a power amplifier circuit 100B of the transmission circuit 10B, in addition to the configuration of the power amplifier circuit 100 shown in Fig. 1, capacitor circuits 170A and 170B are added between the third line 153A of the TLT 150A and the output terminal of the peak amplifier 142A, and between the third line 153B of the TLT 150B and the output terminal of the peak amplifier 142B, respectively.

[0106] Each of the capacitor circuits 170A and 170B includes at least one capacitor and a switching circuit for switching the capacitor. In the example of the power amplifier circuit 100B, each of the capacitor circuits 170A and 170B includes three capacitors and three switching elements provided corresponding to the respective capacitors.

[0107] In the capacitor circuit 170A, a set of a series-connected capacitor and a switching element is connected in parallel between the third line 153A of the TLT 150A and the output terminal of the peak amplifier 142A. In the capacitor circuit 170B, a set of a series-connected capacitor and a switching element is connected in parallel between the third line 153B of the TLT 150B and the output terminal of the peak amplifier 142B.

[0108] The switching elements included in the capacitor circuit 170A are collectively referred to as a switching circuit 171A, and the switching elements included in the capacitor circuit 170B are collectively referred to as a switching circuit 171B.

[0109] In each capacitor circuit, by turning on any one of the switching elements, an LC parallel resonant circuit is formed by the capacitor connected to that switching element and the third line of the corresponding TLT.

[0110] Generally, an LC parallel resonant circuit has a characteristic that, in a frequency range higher than the resonant frequency, the capacitance increases and the admittance increases as the frequency increases. Therefore, by appropriately setting the resonant frequency of the LC parallel resonant circuit, the output impedance of the peak amplifier can be shorted in the second and third harmonic bands of the high-frequency signal to be transmitted, thereby ensuring attenuation in the corresponding harmonic bands. This prevents leakage of the high-frequency signal in the target frequency band to the power line, improving circuit efficiency and suppressing the harmonics of the high-frequency signal.

[0111] Furthermore, when power is supplied to each amplifier in the power amplifier stage 140 via a TLT, the line length of the TLT may not be set to a quarter wavelength. In this case, the power line may not appear to be in an open state when viewed from the output terminal of the amplifier. Even in such a case, by forming an LC parallel resonant circuit using the capacitor included in the capacitor circuit and the third line of the TLT, it is possible to adjust the power line to an open state with respect to the fundamental wave of the high-frequency signal to be transmitted.

[0112] It should be noted that each capacitor circuit does not necessarily need to include multiple capacitors, but in the case of a dual-band type transmission circuit that switches between and transmits signals in multiple frequency bands, for example, the characteristics can be improved in multiple frequency bands by providing capacitors corresponding to each frequency band used.

[0113] The "capacitor circuit 170A" and the "capacitor circuit 170B" in the third embodiment correspond to the "first capacitor circuit" and the "second capacitor circuit" in the present disclosure, respectively.

[0114] Fourth Embodiment In a fourth embodiment, a high-frequency termination circuit for removing the second harmonic of a high-frequency signal will be described.

[0115] Fig. 11 is a partial circuit diagram of a transmission circuit 10C according to embodiment 4. In a power amplifier circuit 100C of the transmission circuit 10C, in addition to the configuration of the power amplifier circuit 100 shown in Fig. 1, resonator circuits 180A and 180B including at least one LC series resonant circuit are added between the output terminals of peak amplifiers 142A and 142B and ground potential GND, respectively.

[0116] The resonator circuits 180A and 180B each include at least one LC series resonant circuit and a switching circuit 181A or 181B for switching between the resonators. Each switching circuit has a switching element connected in series to at least one LC series resonant circuit. By turning on one of the switching elements in the resonator circuits 180A and 180B, the corresponding LC series resonant circuit functions as a band-stop filter. In other words, it is possible to remove components of high-frequency signals that correspond to the resonant frequency of the LC series resonant circuit.

[0117] Therefore, by setting the resonant frequency of the LC series resonant circuit to the frequency of the second harmonic of the high frequency signal to be transmitted, the second harmonic component of the high frequency signal can be removed.

[0118] The "resonator circuit 180A" and the "resonator circuit 180B" in the fourth embodiment correspond to the "first resonator circuit" and the "second resonator circuit" in the present disclosure, respectively.

[0119] Aspects It will be understood by those skilled in the art that the exemplary embodiments described above are examples of the following aspects.

[0120] (Item 1) A power amplifier circuit according to one aspect includes an input terminal, first to fourth amplifiers, first to third phase shifters, a conversion circuit, and an output terminal. Each of the first to fourth amplifiers amplifies an input signal, which is a high-frequency signal received at the input terminal. The conversion circuit converts the signal from a pair of balanced lines to an unbalanced line. The output terminal is connected to the unbalanced lines. The conversion circuit includes a first balanced terminal and a second balanced terminal connected to the pair of balanced lines, respectively. The first phase shifter is connected between the output of the first amplifier and the output of the second amplifier. The second phase shifter is connected between the output of the third amplifier and the output of the fourth amplifier. The third phase shifter is connected between the output of the second amplifier and the first balanced terminal. The output of the third amplifier is connected to the second balanced terminal. The drive states of the second amplifier, the third amplifier, and the fourth amplifier are switched depending on the power level of the input signal.

[0121] (Item 2) In the power amplifier circuit described in item 1, when the power level of the input signal is in a first range, the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier are in a driven state. When the power level of the input signal is in a second range lower than the first range, the first amplifier and the fourth amplifier are in a driven state, and the second amplifier and the third amplifier are in a non-driven state. When the power level of the input signal is in a third range lower than the second range, the first amplifier is in a driven state, and the second amplifier, the third amplifier, and the fourth amplifier are in a non-driven state.

[0122] (Clause 3) The power amplifier circuit described in clause 2 further includes a divider connected to the input terminal for distributing an input signal received at the input terminal to a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier with a predetermined phase difference. The phases of the signals input to the first amplifier and the third amplifier lead by 90° the phase of the signal input to the second amplifier. The phase of the signal input to the fourth amplifier leads by 180° the phase of the signal input to the second amplifier.

[0123] (4) In the power amplifier circuit according to either of the second or third paragraphs, the conversion circuit is a magnetic coupling transformer.

[0124] (5) In the power amplifier circuit according to either of the second or third paragraphs, the conversion circuit is a Marchand balun.

[0125] (Item 6) In the power amplifier circuit described in Item 5, the Marchand balun includes a first line, a second line, and a third line coupled to the first line and the second line. One end of the first line is connected to the first balanced terminal, and the other end is connected to ground potential. One end of the second line is connected to the second balanced terminal, and the other end is connected to ground potential. One end of the third line is connected to the output terminal, and the other end is an open end. When the wavelength of the high-frequency signal to be transmitted is λ, the first line and the second line have a line length of λ / 4, and the third line has a line length of λ / 2.

[0126] (Item 7) The power amplifier circuit described in any one of Items 2 to 6 further includes a first transmission line transformer connected between the output of the second amplifier and the third phase shifter, and a second transmission line transformer connected between the output of the third amplifier and the second balanced terminal.

[0127] (Item 8) In the power amplifier circuit described in item 7, the first transmission line transformer includes fourth and fifth lines connected in series between the third phase shifter and the output of the second amplifier, and a sixth line coupled to the fourth and fifth lines. The second transmission line transformer includes seventh and eighth lines connected in series between the second balanced terminal and the output of the third amplifier, and a ninth line coupled to the seventh and eighth lines.

[0128] (Item 9) In the power amplifier circuit described in item 8, one end of the sixth line is connected to the output of the second amplifier. One end of the ninth line is connected to the output of the third amplifier. A power supply voltage is supplied to the other end of the sixth line and the other end of the ninth line. The power amplifier circuit further includes a first capacitor circuit and a second capacitor circuit. The first capacitor circuit is connected between the other end of the sixth line and the output of the second amplifier. The second capacitor circuit is connected between the other end of the ninth line and the output of the third amplifier. The first capacitor circuit includes a plurality of capacitors connected in parallel between the other end of the sixth line and the output of the second amplifier. The second capacitor circuit includes a plurality of capacitors connected in parallel between the other end of the ninth line and the output of the third amplifier. Each of the first capacitor circuit and the second capacitor circuit further includes a switching circuit for switching the corresponding plurality of capacitors.

[0129] (Item 10) In the power amplifier circuit described in item 8, one end of the sixth line is connected to the output of the second amplifier. One end of the ninth line is connected to the output of the third amplifier. A power supply voltage is supplied to the other end of the sixth line and the other end of the ninth line. The power amplifier circuit further includes a first resonator circuit and a second resonator circuit. The first resonator circuit is connected between the other end of the sixth line and ground potential. The second resonator circuit is connected between the other end of the ninth line and ground potential. The first resonator circuit includes a plurality of LC series resonators connected in parallel between the other end of the sixth line and ground potential. The second resonator circuit includes a plurality of LC series resonators connected in parallel between the other end of the ninth line and ground potential. Each of the first resonator circuit and the second resonator circuit further includes a switching circuit for switching the corresponding plurality of LC series resonators.

[0130] (Item 11) In the power amplifier circuit according to any one of items 2 to 10, a Doherty amplifier is configured by a pair of the first amplifier and the second amplifier and a pair of the third amplifier and the fourth amplifier. The first amplifier and the fourth amplifier operate as carrier amplifiers. The second amplifier and the third amplifier operate as peak amplifiers.

[0131] (12) In the power amplifier circuit according to any one of paragraphs 2 to 11, the first to fourth amplifiers form a Doherty amplifier. The first amplifier operates as a carrier amplifier. The second to fourth amplifiers operate as peak amplifiers.

[0132] (Item 13) A transmission circuit according to one aspect includes the power amplifier circuit according to any one of items 2 to 12 and a control circuit. The control circuit is configured to switch the drive states of the first to fourth amplifiers in accordance with the power level of an input signal.

[0133] (Item 14) A communication device according to one aspect includes the transmitter circuit according to item 13, a power supply circuit, a signal processing circuit, and a radiating element connected to an output terminal. The power supply circuit adjusts a power supply voltage for driving the first to fourth amplifiers in accordance with the power level of an input signal. The signal processing circuit generates a high-frequency signal and supplies it to the power amplifier circuit.

[0134] (Item 15) In the communication device described in item 14, the power supply circuit adjusts the power supply voltage to a plurality of discrete voltage levels according to the envelope of the high frequency signal.

[0135] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0136] 1 Communication device, 10, 10A to 10C Transmission circuit, 20 BBIC, 30 RFIC, 40 Power supply circuit, 100, 100A to 100C Power amplifier circuit, 105 Bias control circuit, 110 Distributor, 120 Phase shift circuit, 131 to 133 Preamplifier, 140 Power amplifier stage, 141, 210 Carrier amplifier, 142A to 142C, 220 Peak amplifier, 134, 143A, 143B, 155, 230 Phase shifter, 150A, 150B TLT, 151A to 153A, 151B to 153B, 161 to 163 Line, 160, 160A Conversion circuit, 170A, 170B Capacitor circuit, 171A, 171B, 181A, 181B Switching circuit, 180A, 180B resonator circuit, 410 MPC, 420 power supply selection circuit, 430 digital ET, 1631, 1632 partial line, ANT antenna, BS bias signal, C1 to C5 capacitors, CON control signal, GND ground potential, N1, N2 connection node, Pin input signal, Pout output signal, SEL selection signal, T1, T3, T4, T10 input terminal, T2, T20 output terminal, TB1, TB2 balanced terminal, TR1 to TR3 transformer, TR4 magnetic field coupling transformer, VB battery voltage, Vcc power supply voltage, Zc, Zpa, Zpb, Zpc impedance.

Claims

1. A power amplifier circuit comprising: an input terminal; a first amplifier, a second amplifier, a third amplifier and a fourth amplifier which amplify an input signal which is a high frequency signal received at the input terminal; a first phase shifter, a second phase shifter and a third phase shifter; a conversion circuit which converts a pair of balanced lines to unbalanced lines; and an output terminal connected to the unbalanced lines, wherein the conversion circuit includes a first balanced terminal and a second balanced terminal respectively connected to the pair of balanced lines, the first phase shifter is connected between an output of the first amplifier and an output of the second amplifier, the second phase shifter is connected between an output of the third amplifier and an output of the fourth amplifier, the third phase shifter is connected between the output of the second amplifier and the first balanced terminal, and the output of the third amplifier is connected to the second balanced terminal, and the drive states of the second amplifier, the third amplifier and the fourth amplifier are switched according to the power level of the input signal.

2. The power amplifier circuit of claim 1, wherein when the power level of the input signal is in a first range, the first amplifier, the second amplifier, the third amplifier and the fourth amplifier are in a driven state; when the power level of the input signal is in a second range smaller than the first range, the first amplifier and the fourth amplifier are in a driven state and the second amplifier and the third amplifier are in a non-driven state; and when the power level of the input signal is in a third range smaller than the second range, the first amplifier is in a driven state and the second amplifier, the third amplifier and the fourth amplifier are in a non-driven state.

3. The power amplifier circuit of claim 2, further comprising a distributor connected to said input terminal for distributing the input signal received at said input terminal to said first amplifier, said second amplifier, said third amplifier and said fourth amplifier with a predetermined phase difference, wherein the phase of the signal input to said first amplifier and said third amplifier leads the phase of the signal input to said second amplifier by 90°, and the phase of the signal input to said fourth amplifier leads the phase of the signal input to said second amplifier by 180°.

4. The power amplifier circuit according to claim 2 or 3, wherein the conversion circuit is a magnetic coupling transformer.

5. The power amplifier circuit according to claim 2 or 3, wherein the conversion circuit is a Marchand balun.

6. The power amplifier circuit according to claim 5, wherein the Marchand balun includes: a first line and a second line; and a third line coupled to the first line and the second line, one end of the first line being connected to the first balanced terminal and the other end being connected to a ground potential, one end of the second line being connected to the second balanced terminal and the other end being connected to a ground potential, one end of the third line being connected to the output terminal and the other end being an open end, wherein, when the wavelength of the high frequency signal to be transmitted is λ, the first line and the second line have a line length of λ / 4, and the third line has a line length of λ / 2.

7. A power amplifier circuit as claimed in any one of claims 2 to 6, further comprising: a first transmission line transformer connected between the output of said second amplifier and said third phase shifter; and a second transmission line transformer connected between the output of said third amplifier and said second balanced terminal.

8. The power amplifier circuit according to claim 7, wherein the first transmission line transformer includes a fourth line and a fifth line connected in series between the third phase shifter and the output of the second amplifier, and a sixth line coupled to the fourth line and the fifth line, and the second transmission line transformer includes a seventh line and an eighth line connected in series between the second balanced terminal and the output of the third amplifier, and a ninth line coupled to the seventh line and the eighth line.

9. The power amplifier circuit according to claim 8, wherein one end of the sixth line is connected to the output of the second amplifier, one end of the ninth line is connected to the output of the third amplifier, a power supply voltage is supplied to the other end of the sixth line and the other end of the ninth line, and the power amplifier circuit further comprises: a first capacitor circuit connected between the other end of the sixth line and the output of the second amplifier, and a second capacitor circuit connected between the other end of the ninth line and the output of the third amplifier, the first capacitor circuit includes a plurality of capacitors connected in parallel between the other end of the sixth line and the output of the second amplifier, the second capacitor circuit includes a plurality of capacitors connected in parallel between the other end of the ninth line and the output of the third amplifier, and each of the first capacitor circuit and the second capacitor circuit further includes a switching circuit for switching a corresponding plurality of capacitors.

10. The power amplifier circuit according to claim 8, wherein one end of the sixth line is connected to an output of the second amplifier, one end of the ninth line is connected to an output of the third amplifier, a power supply voltage is supplied to the other end of the sixth line and the other end of the ninth line, the power amplifier circuit further comprises: a first resonator circuit connected between the other end of the sixth line and a ground potential; and a second resonator circuit connected between the other end of the ninth line and a ground potential, the first resonator circuit includes a plurality of LC series resonators connected in parallel between the other end of the sixth line and a ground potential, the second resonator circuit includes a plurality of LC series resonators connected in parallel between the other end of the ninth line and a ground potential, and each of the first resonator circuit and the second resonator circuit further includes a switching circuit for switching the corresponding plurality of LC series resonators.

11. A power amplifier circuit according to any one of claims 2 to 10, wherein a Doherty amplifier is configured by a set of the first amplifier and the second amplifier and a set of the third amplifier and the fourth amplifier, the first amplifier and the fourth amplifier operate as a carrier amplifier, and the second amplifier and the third amplifier operate as a peak amplifier.

12. A power amplifier circuit as claimed in any one of claims 2 to 11, wherein the first amplifier, the second amplifier, the third amplifier and the fourth amplifier constitute a Doherty amplifier, the first amplifier operates as a carrier amplifier, and the second amplifier, the third amplifier and the fourth amplifier operate as peak amplifiers.

13. A transmission circuit comprising: a power amplifier circuit according to any one of claims 2 to 12; and a control circuit configured to switch the drive states of the first amplifier, the second amplifier, the third amplifier and the fourth amplifier in response to the power level of the input signal.

14. A communication device comprising: a transmission circuit as claimed in claim 13; a power supply circuit which adjusts a power supply voltage for driving the first amplifier, the second amplifier, the third amplifier and the fourth amplifier in accordance with the power level of the input signal; a signal processing circuit which generates the high frequency signal and supplies it to the power amplifier circuit; and a radiating element connected to the output terminal.

15. The communications device according to claim 14, wherein said power supply circuit adjusts said power supply voltage to a plurality of discrete voltage levels in response to an envelope of said high frequency signal.

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